CN220108614U

CN220108614U - Semiconductor device

Info

Publication number: CN220108614U
Application number: CN202321492569.5U
Authority: CN
Inventors: 冯立伟
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-06-13
Filing date: 2023-06-13
Publication date: 2023-11-28
Anticipated expiration: 2033-06-13

Abstract

The utility model discloses a semiconductor device, comprising: a substrate including a storage region and a peripheral region; a plurality of storage node pads disposed on the substrate and located within the storage region; a capacitor structure disposed on the storage node pad, including a plurality of bottom electrodes respectively contacting the storage node pad; and the supporting structure is arranged between the bottom electrodes and is in physical contact with the bottom electrodes, the supporting structure comprises a first supporting layer and a second supporting layer which are sequentially arranged from bottom to top, the second supporting layer has a first thickness and a second thickness, the second thickness is larger than the first thickness, the second supporting layer with the first thickness is arranged in the storage area, and the second supporting layer with the second thickness is arranged between the storage area and the peripheral area.

Description

Semiconductor device

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor devices must meet the requirements of high integration and high density. For the DRAM (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the DRAM with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of capacitor structure. In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to form an array region for storing information, and each memory cell may be formed by a transistor element and a capacitor element connected in series to receive voltage information from Word Lines (WL) and Bit Lines (BL). In response to the product requirement, the density of the memory cells in the array region must be continuously increased, which causes the difficulty and complexity of the related manufacturing process and design to be continuously increased, resulting in the reduction of the performance and reliability of the related memory device.

Disclosure of Invention

One of the objectives of the present utility model is to provide a semiconductor device for solving the technical problems of the related memory device that the memory cell density is required to be continuously increased, resulting in the continuous increase of the difficulty and complexity of the related manufacturing process and design, and the reduction of the performance and reliability of the related memory device.

To achieve the above object, one embodiment of the present utility model provides a semiconductor device including a substrate, a storage node pad, a capacitor structure, and a support structure. A substrate including a storage region and a peripheral region; a plurality of storage node pads disposed on the substrate and located within the storage region; a capacitor structure disposed on the storage node pad, including a plurality of bottom electrodes respectively contacting the storage node pad; and the support structure is arranged between the bottom electrodes and is in physical contact with the bottom electrodes, the support structure comprises a first support layer and a second support layer which are sequentially arranged from bottom to top, the second support layer has a first thickness and a second thickness, the second thickness is larger than the first thickness, the second support layer with the first thickness is arranged in the storage area, and the second support layer with the second thickness is arranged between the storage area and the peripheral area.

Advantageous effects

Compared with the prior art, the beneficial effects of the embodiment of the disclosure at least comprise: by forming a support structure with larger local thickness between the storage region and the peripheral region, more optimized structural support is provided for the capacitor structure, thereby greatly improving the efficiency and reliability of the semiconductor device.

Drawings

The accompanying drawings provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 6 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a first embodiment of the present utility model, wherein:

fig. 1 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a stacked layer structure;

FIG. 2 is a schematic cross-sectional view of a semiconductor device of the present utility model after patterning a mask layer;

fig. 3 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a via;

Fig. 4 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a mask pattern;

fig. 5 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a bottom electrode; and

fig. 6 is a schematic cross-sectional view of the semiconductor device of the present utility model after formation of the capacitor structure and plug.

Fig. 7 to 8 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a second embodiment of the present utility model, wherein:

fig. 7 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a via; and

fig. 8 is a schematic cross-sectional view of a semiconductor device of the present utility model after formation of a capacitor structure and plug.

Fig. 9 to 10 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a third embodiment of the present utility model, wherein:

fig. 9 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a mask pattern; and

fig. 10 is a schematic cross-sectional view of a semiconductor device of the present utility model after formation of a capacitor structure and plug.

Fig. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the utility model.

Wherein reference numerals are as follows:

Detailed Description

The following description sets forth the preferred embodiments of the present utility model and, together with the accompanying drawings, provides a further understanding of the utility model, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the utility model pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the utility model to accomplish other embodiments.

It will be noted that when an element is referred to as being "fixed" or "disposed on" another element, it can be directly or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are directions or positions based on the drawings, and are merely for convenience of description and are not to be construed as limiting the present technical solution.

Referring to fig. 1 to 6, a schematic diagram of steps of a method for fabricating a semiconductor device 10 according to an embodiment of the utility model is shown.

First, as shown in fig. 1, a substrate 100 is provided, and the substrate 100 may be any of a silicon substrate, a silicon-containing substrate (such as SiC, siGe, etc.), a silicon-on-insulator (SOI) substrate, etc., and the substrate 100 further includes a region where the component integration is relatively high, such as a memory region (cell region) 100a, and another region where the component integration is relatively low, such as a peripheral region (peripheral region) 100b. The storage area 100a and the peripheral area 100b may be disposed adjacently, and preferably, the peripheral area 100b may surround the outside of the storage area 100a from a top view (not shown), but not limited thereto.

At least one insulating region, such as a shallow trench isolation (shallow trench isolation, STI) 112, is formed in the substrate 100, and a plurality of Active Areas (AA) 110 are defined in the substrate 100, such that the shallow trench isolation 112 surrounds all of the active areas 110 from the top view. In one embodiment, the shallow trench isolation 112 may be formed by etching a plurality of trenches (not shown) in the substrate 100, and then filling at least one insulating material (such as silicon oxide or silicon oxynitride) into each of the trenches to form a plurality of shallow trench isolation 112 with a surface flush with the top surface of the substrate 100, but is not limited thereto.

Then, a plurality of gates, preferably buried gates 120, are formed within the substrate 100. The buried gate 120 is basically formed in the memory region 100a, and in this embodiment, is preferably formed in the memory region 100a and a portion of the peripheral region 100b adjacent to the memory region 100a, as shown in fig. 1. The process of fabricating the buried gate 120 includes, but is not limited to, the following steps. First, a plurality of trenches (not shown) extending parallel to each other are formed in the substrate 100, and then a dielectric layer 122 covering the entire surface of each of the trenches, a gate dielectric layer 124 covering the lower half surface of each of the trenches, a gate 126 filling the lower half of each of the trenches, and a cap layer 128 filling the upper half of each of the trenches are formed in each of the trenches. In this manner, the surface of the cap layer 128 may be level with the top surface of the substrate 100 such that the buried gate 120 located within the substrate 100 may serve as a Buried Word Line (BWL) for the semiconductor device 10.

Then, a plurality of Bit Lines (BL) and a plurality of storage node plugs (storage node contact, SNC) 132 are formed on the substrate 100. In this embodiment, the bit lines and the storage node plugs 132 are also preferably formed in the storage region 100a and a part of the peripheral region 100b adjacent to the storage region 100 a. Although the bit lines are not specifically shown in the drawings in this embodiment, it should be readily understood by those skilled in the art that each of the bit lines extends parallel to each other, is electrically isolated from the buried gate 120 in the substrate 100 by an insulating layer (not shown, for example, including a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100, and extends into the active region 110 to electrically connect to the substrate 100 by a Bit Line Contact (BLC) correspondingly formed under each of the bit lines. It will be further understood by those skilled in the art that, if the extension directions of the active region 110, the buried gate 120 and the bit lines are different from each other in the top view, the extension direction of the bit lines should be perpendicular to the extension direction of the buried gate 120 and cross the active region 110 and the buried gate 120, and each storage node plug 132 is disposed between the bit lines.

The storage node plugs 132 physically contact the active regions 110, over which the storage node pads 134 are respectively disposed. Wherein adjacent storage node plugs 132 and adjacent storage node pads 134 are isolated from each other by insulating sidewalls (storage node contact isolation, SCISO) 136 disposed directly above the respective buried gates 120. As such, the storage node plug 132 may be electrically connected to the substrate 100 to receive and transmit voltage signals from the substrate 100 (e.g., transistor elements within the substrate 100). In an embodiment, the material of the storage node plug 132 may include an epitaxial material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and the material of the storage node pad 134 may include a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but is not limited thereto. Those skilled in the art should readily understand that the storage node pads 134 may also be formed integrally with the storage node plugs 132 based on the same conductive material, but is not limited thereto.

On the other hand, at least one gate structure 140 and a plurality of plugs 154 are formed on the substrate 100 in the peripheral region 100 b. It should be noted that the gate structure 140 may be fabricated by a similar process to that of the bit line, such that the gate structure 140 has a structure and material similar to that of the bit line, for example, a gate dielectric layer 142 (including the same material as the insulating layer, such as a silicon oxide-silicon nitride-silicon oxide structure), a semiconductor layer 144 (including polysilicon), a barrier layer 146 (including titanium and/or titanium nitride), a conductive layer 148 (including low-resistance metal such as tungsten, aluminum or copper), and a cap layer 150 (including silicon oxide, silicon nitride or silicon oxynitride), which are sequentially stacked on the top surface of the substrate 100, and a spacer 152 on the sidewall of the gate structure 140 may be formed together with a bit line spacer (not shown), wherein the spacer 152 and the spacer may include the same dielectric material, but are not limited thereto. In addition, the process of fabricating the plugs 154 may be similar to that of the storage node plugs 132 and the storage node pads 134, such that each plug 154 includes sequentially stacked epitaxial materials 154a (which may be made of silicon, silicon-phosphorus, silicon-germanium, or germanium, etc.) and low-resistance metal materials 154b (which may be made of aluminum, titanium, copper, tungsten, etc.). Plugs 154 are formed in the dielectric layer 156 on opposite sides of the gate structure 140 and electrically connect to the substrate 100.

As further shown in fig. 1, the support layer structure 160 and the mask layer structure 170 are further formed on the substrate 100, wherein the support layer structure 160 and the mask layer structure 170 integrally cover the storage region 100a and the peripheral region 100b of the substrate 100. Specifically, the support layer structure 160 may include at least one oxide layer and at least one nitride layer alternately stacked. In this embodiment, the support layer structure 160 may include, but is not limited to, a first support material layer 162 (made of silicon oxide, for example), a second support material layer 164 (made of silicon nitride, silicon carbonitride, for example), a third support material layer 166 (made of silicon oxide, for example), and a fourth support material layer 168 (made of silicon nitride, silicon carbonitride, for example) stacked in order from bottom to top. Preferably, the oxide layer (e.g., including the first support material layer 162 and the third support material layer 166) may have a relatively large thickness, e.g., the oxide layer has a thickness 5 times to 10 times or more than that of the nitride layer (e.g., including the second support material layer 164 or the fourth support material layer 168). Also, the thickness t11 of the nitride layer (e.g., the fourth support material layer 168) disposed away from the substrate 100 is preferably greater than the thickness of the nitride layer (e.g., the second support material layer 164) disposed adjacent to the substrate 100, as shown in fig. 1, but is not limited thereto. Thus, the thickness of the entire supporting layer 160 is about 1600 angstroms (angstrom) to about 2000 angstroms, but is not limited thereto. It should be understood by those skilled in the art that the specific stacking number of the oxide layer and the nitride layer is not limited to that shown in fig. 1, and may be adjusted to other layers according to practical requirements. The mask layer structure 170 is formed on the support layer structure 160 and preferably has a composite structure. In the present embodiment, the mask layer structure 170 may include an organic bottom layer 172, a silicon hard mask bottom anti-reflective coating 174, a photoresist layer 176, and the like, which are stacked in order, but not limited thereto.

As shown in fig. 2, a photolithography process is performed. The photolithographic fabrication process includes, but is not limited to, the following steps. First, a photomask (not shown) is provided, and the pattern of the photomask is transferred to the photoresist layer 176, and then the photoresist layer 176 shown in fig. 1 is patterned. Next, the pattern of the patterned photoresist layer 176 is transferred to the underlying silicon hard mask bottom anti-reflective coating 174 and organic underlayer 172, forming the silicon hard mask bottom anti-reflective coating 174 and organic underlayer 172 as shown in fig. 2. It should be noted that, since the pattern of the photomask is mainly located in the memory region 100a, and the peripheral region 100b is entirely covered by the mask layer structure 170, the difference of the pattern integration in the two regions (the memory region 100a and the peripheral region 100 b) causes the etching load effect (micro-loading effect). Thus, during pattern transfer, the silicon hard mask bottom anti-reflective coating 174 in the memory region 100a has a reduced thickness t22 after the photolithography process is performed, while the silicon hard mask bottom anti-reflective coating 174 in the peripheral region 100b maintains the original thickness t21 under the influence of the photolithography process. That is, after the photolithography process is performed, the top surface of the silicon hard mask bottom anti-reflection coating 174 located in the peripheral region 100b and the top surface of the silicon hard mask bottom anti-reflection coating 174 located in the memory region 100a are not coplanar with each other, as shown in fig. 2.

Then, an etching process, such as a dry etching process, is performed on the silicon hard mask bottom anti-reflective coating 174 and the organic bottom layer 172 shown in fig. 2, so as to sequentially penetrate the fourth support material layer 168, the third support material layer 166, the second support material layer 164 and the first support material layer 162, and form a plurality of through holes 160a in the support layer structure 160, as shown in fig. 3. Each perforation 160a is aligned with each storage node pad 134 below, such that the top surface of each storage node pad 1340 is exposed from each perforation 160a, respectively. The silicon hard mask bottom anti-reflective coating 174 and the organic bottom layer 172 as shown in fig. 2 are either consumed simultaneously when the etching process is performed or removed completely after the etching process is performed. It should also be noted that, due to the etching loading effect caused by the difference of the pattern densities of the bottom anti-reflective coating 174 of the silicon hard mask in the two regions (the storage region 100a and the peripheral region 100 b), the fourth support material layer 168a in the storage region 100a is partially consumed during the etching process, and accordingly has the same reduced thickness t12, while the fourth support material layer 168b in the peripheral region 100b still maintains the original thickness t11. That is, after the etching process, the top surface of the fourth support material layer 168b located in the peripheral region 100b and the top surface of the fourth support material layer 168a located in the memory region 100a are not coplanar with each other, as shown in fig. 3.

As shown in fig. 4, a deposition and etch back process is performed to form a plurality of bottom electrode layers 178 within the support layer structure 160, and a mask layer structure 190 is formed over the support layer structure 160 and the bottom electrode layers 178. In one embodiment, the fabrication process of the bottom electrode layer 178 includes, but is not limited to, the following steps. First, an electrode material layer, for example, a low-resistance metal material including aluminum, titanium, copper, or tungsten, is formed on the support layer structure 160, and preferably, the metal material may include titanium. A portion of the electrode material layer is formed inside each perforation 160a and conformally covers the inside surface of each perforation 160a, and another portion is formed outside each perforation 160a and covers the top surface of the support layer structure 160. Then, the electrode material layer formed outside each of the through holes 160a is removed, and a plurality of bottom electrode layers 178 each having a U-shaped structure are formed and located inside each of the through holes 160 a. It should be noted that, since the fourth support material layer 168a located in the memory region 100a and the fourth support material layer 168b located in the peripheral region 100b have a thickness difference (t 12/t 11), the bottom electrode layer 178b formed at the boundary between the memory region 100a and the peripheral region 100b has two sidewalls with different heights. The sidewall of bottom electrode layer 178b adjacent peripheral region 100b has a relatively high top surface, and the sidewall of bottom electrode layer 178b adjacent storage region 100a has a relatively low top surface and is of equal height to the top surface of fourth support material layer 168a within storage region 100a, but is of an asymmetric configuration. The bottom electrode layer 178a formed in the storage region 100a has two sidewalls with the same height, and the sidewalls are both the same height as the fourth support material layer 168a in the storage region 100a, so as to have a symmetrical structure.

As further shown in fig. 4, the mask layer structure 190 also has a composite structure, for example, but not limited to, an organic underlayer 180, a silicon hard mask bottom anti-reflective coating 182, a photoresist layer 184, and a plurality of mask patterns 186, which are stacked in sequence. Wherein each mask pattern 186 covers the support layer structure 160 in the storage region 100a in such a way as to cover two adjacent bottom electrode layers 178a at the same time and to partially cover one bottom electrode layer 178a at both sides of the two adjacent bottom electrode layers 178 a. In addition, one of the mask patterns 186 also covers both a portion of the memory region 100a and a portion of the peripheral region 100b to completely cover the bottom electrode layer 178b formed at the interface between the memory region 100a and the peripheral region 100 b.

Then, at least one etching process, such as a first dry etching process, is performed on the support layer structure 160 through the mask pattern 186 shown in fig. 4, a portion of the photoresist layer 184, a portion of the silicon hard mask bottom anti-reflective coating 182, a portion of the organic underlayer 180, a portion of the fourth support material layer 168a, and a portion of the third support material layer 166 are removed, and then a first wet etching process is performed, and an etchant such as tetramethylammonium hydroxide (tetramethylammonium hydroxide, TMAH) is introduced to remove the remaining portion of the third support material layer 166. Then, another etching process, such as a second dry etching process, is performed to remove a portion of the second support material layer 164 and a portion of the first support material layer 162, and then a second wet etching process is performed to remove the remaining portion of the first support material layer 162 by introducing an etchant such as tetramethyl ammonium hydroxide. That is, the mask layer structure 190 and the support layer structure 160 formed in the peripheral region 100b have been completely removed, and then the remaining portion of the mask layer structure 190 is completely removed.

Note that, as shown in fig. 4, the mask pattern 186 and the bottom electrode layer 178a in the storage region 100a may be consumed simultaneously when the first dry etching process and/or the first wet etching process are performed, so that not only the mask pattern 186 is removed, but also a single side wall of the bottom electrode layer 178a in the storage region is shortened. In this operation, as shown in fig. 5, a plurality of bottom electrodes 278 are formed on the storage node plug structure 130, including a bottom electrode 278a having a symmetrical U-shaped electrode structure and disposed in the storage region 100a, a bottom electrode 278b having an asymmetrical U-shaped electrode structure and disposed at the boundary between the storage region 100a and the peripheral region 100b, and a bottom electrode 278c having an asymmetrical U-shaped electrode structure and disposed in the storage region 100a, wherein one side wall of the bottom electrode 278b is at the same height as both side walls of the bottom electrode 278a, and the other side wall of the bottom electrode 278b is higher than both side walls of the bottom electrode 278a, and one side wall of the bottom electrode 278c is also at the same height as both side walls of the bottom electrode 278a, and the other side wall of the bottom electrode 278c is lower than both side walls of the bottom electrode 278a, so that a space between portions of the bottom electrode 278 (e.g. between the bottom electrodes 278a and 278 c) in the storage region 100a is additionally pulled apart, so as to facilitate the subsequent deposition process.

On the other hand, the remaining fourth support material layers 168a, 168b and the remaining second support material layer 164 form second support layers 264a, 264b and the first support layer 262, respectively, which are sequentially disposed from top to bottom, together forming a support structure 260 disposed on the storage node pad 134. The support structures 260 are disposed between the bottom electrodes 278, physically contacting the sidewalls of at least one side of each bottom electrode 278 and providing corresponding structural support. In detail, as shown in fig. 5, the second support layer 264a disposed in the memory region 100a has a relatively small first thickness t12, and a top surface thereof is coplanar with a top surface of the bottom electrode 278a in the memory region 100 a. Wherein the second supporting layer 264b disposed in the peripheral region 100b has a relatively larger second thickness t11, and its highest top surface is higher than the top surface of the second supporting layer 264a and coplanar with the top surface of the sidewall on the side where the bottom electrode 278b is higher, and its bottom surface is coplanar with the bottom surface of the second supporting layer 264 a. That is, the height of the second support layer 264b with respect to the top surface of the substrate 100 is greater than the height of the second support layer 264a with respect to the top surface of the substrate 100. In this manner, the structural support of the bottom electrode 278b disposed at the interface of the storage region 100a and the peripheral region 100b is further optimized by the provision of the second support layer 264 b.

As shown in fig. 6, at least one deposition process is performed on the support structure 260 to sequentially form a capacitor dielectric layer 280 and a top electrode layer 282. A capacitor dielectric layer 280 conformally covers each bottom electrode 278 and the exposed surfaces of the support structure 260, and a top electrode layer 282 covers the capacitor dielectric layer 280 and fills the remaining space between the bottom electrodes 278. Wherein a portion of the capacitive dielectric layer 280 and the topThe electrode layer 282 may be further formed in a space between the second support layer 264 and the first support layer 262, and at the same time, in a space between the first support layer 262 and the storage node pad 134 to increase a contact area and increase a capacitance value. In one embodiment, the capacitor dielectric layer 280 may comprise a high-k dielectric material, such as hafnium oxide (HfO) ₂ ) Hafnium silicate oxide (hafnium silicon oxide, hfSiO), hafnium silicate oxynitride (hafnium silicon oxynitride, hfSiON), aluminum oxide (Al) ₂ O ₃ ) Lanthanum oxide (LaO), lanthanum aluminate (lanthanum aluminum oxide, laAlO), tantalum oxide (Ta) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Yttrium oxide (Y) ₂ O ₃ ) Zirconium oxide, zrO ₂ ) Zirconium silicate oxide (zirconium silicon oxide, zrSiO) ₄ ) Hafnium zirconate (hafnium zirconium oxide, hfZrO), strontium bismuth tantalum oxide (strontium bismuth tantalate, srBi) ₂ Ta ₂ O ₉ SBT), lead zirconate titanate (Lead zirconate titanate, pbZrxTi _1- _x O ₃ PZT) or barium strontium titanate (Barium Strontium Titanate, baxSr) _1-x TiO ₃ BST), etc., preferably comprising zirconia-alumina-zirconia (ZAZ), the top electrode layer 282 may comprise a low-resistance metal material such as aluminum, titanium, copper or tungsten, etc., preferably titanium, but not limited thereto.

Then, a patterning process is performed to remove the top electrode layer 280 and the capacitor dielectric layer 280 outside the memory region 100a, thereby forming the capacitor structure 284. Thus, the fabrication process of the capacitor structure 284 is completed. The capacitor structure 284 is composed of a bottom electrode 278, a capacitor dielectric layer 280 and a top electrode layer 282 stacked in sequence, and includes a plurality of vertically extending capacitors as Storage Nodes (SN) of the semiconductor device 10, wherein each of the capacitors is electrically connected to a transistor element (not shown) in the substrate 100 through the storage node plug 132. With this arrangement, the semiconductor device 10 of the present embodiment can form a dynamic random access memory (dynamic random access memory, DRAM) device, which is a memory cell (memory cell) with a minimum composition in a DRAM array formed by at least one of the transistor elements and at least one of the capacitors, for receiving voltage information from the bit line and the buried word line (buried gate 120).

Subsequently, as further shown in fig. 6, an interlayer dielectric layer 286 is formed on the substrate 100 to cover the capacitor structure 284 in the storage region 100a and the gate structure 140 in the peripheral region 100b, and at least one plug 290 electrically connecting the capacitor structure 284 and the gate structure 140 is formed in the interlayer dielectric layer 286. Specifically, a plug 290a electrically connected to the capacitor structure 284 is formed in the memory region 100a and physically contacts the capacitor structure 284. The plug 290b electrically connected to the gate structure 140 is formed in the peripheral region 100b, has a relatively large aspect ratio, and physically contacts the plug 154. In an embodiment, each of the plugs 290a, 290b includes a barrier layer 292, 296 and a conductive layer 294, 298 sequentially stacked, wherein the barrier layer 292, 296 may be made of titanium, tantalum, titanium nitride or tantalum nitride, and the conductive layer 294, 298 may be made of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, preferably tungsten, but not limited thereto.

Thus, the manufacturing process of the semiconductor device 10 of the present embodiment is completed. Subsequently, the capacitor structure 284 formed in the memory region 100a and the gate structure 140 formed in the peripheral region 100b may be further connected to an external circuit through the plug 290 and the metal interconnection line formed later, respectively. It should be readily understood by those skilled in the art that the specific line configuration and number of the metal interconnection lines may be adjusted according to the actual device requirements, such as the conductive lines 302 and 304 including at least the electrical connection plugs 290a and 290b and the dielectric layer 306 surrounding the conductive lines 302 and 304, as shown in fig. 6, but not limited thereto.

According to the method of fabricating the semiconductor device 10 of the first embodiment of the present utility model, the support structure 260 with a larger local thickness is formed at the boundary between the memory region 100a and the peripheral region 100 b. For example, the second supporting layer 264a disposed in the memory region 100a has a relatively smaller first thickness t12, and the second supporting layer 264b disposed at the interface between the memory region 100a and the peripheral region 100b has a relatively larger second thickness t11. Thus, when the bottom electrode 278 is formed, the bottom electrode 278b formed at the boundary between the memory region 100a and the peripheral region 100b has two sidewalls with different heights, respectively. Wherein the sidewall of the bottom electrode 278b adjacent to the peripheral region 100b physically contacts the second supporting layer 264b and has a relatively higher top surface, and the sidewall of the bottom electrode 278b adjacent to the storage region 100a has a relatively lower top surface and has the same height as the top surface of the second supporting layer 264a, such that the bottom electrode 278b has an overall asymmetric structure. In this operation, the fabrication method of the present embodiment can be performed by forming the bottom electrode 278 with asymmetric local structure (e.g. between the bottom electrodes 278b and 278 c) to pull the space between the adjacent bottom electrodes 278 in the storage region 100a, so as to facilitate the subsequent deposition process. In addition, the manufacturing method of the present embodiment can further strengthen the structural support of the bottom electrode 278 at the junction between the storage region 100a and the peripheral region 100b by forming the support structure 260 with a larger local thickness. In addition, the subsequently formed capacitor dielectric layer 280 further encapsulates the second supporting layer 264b, such that the sidewall and the surface of the second supporting layer 264b physically contact the bottom electrode 278b or the capacitor dielectric layer 280, respectively, and the contact area between the capacitor dielectric layer 280, the top electrode layer 282 and the second supporting layer 264b is increased to increase the physical support. Therefore, the manufacturing method of the semiconductor device 10 of the present embodiment can effectively improve the structural reliability of the semiconductor device 10 and optimize the functions and performances of the semiconductor device 10 on the premise that the density of the memory cells is continuously increased and the complexity of the manufacturing process is gradually increased.

According to the semiconductor device 10 of the first embodiment of the present utility model, the support structure 260 with a larger local thickness is disposed at the junction between the storage region 100a and the peripheral region 100b, so as to strengthen the structural support of the bottom electrode 278 at the junction between the storage region 100a and the peripheral region 100b, and increase the contact area between the capacitor dielectric layer 280, the top electrode layer 282 and the second support layer 264b to increase the physical support. In addition, the semiconductor device 10 of the present embodiment further includes bottom electrodes 278 (such as bottom electrodes 278b and 278 c) with asymmetric local structures, so as to effectively pull the space between adjacent bottom electrodes 278 in the storage region 100a, so as to facilitate the subsequent deposition process. Thus, the semiconductor device 10 of the present embodiment can maintain the structural reliability of the semiconductor device 10 and achieve the optimized functions and performances under the premise of continuously increasing the density of the memory cells.

It should be readily understood by those skilled in the art that other aspects of the semiconductor device and the method for manufacturing the same are possible in order to meet the actual product requirements, and are not limited to the foregoing. Further embodiments or variations of the semiconductor device and method of making the same in the present utility model are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present utility model are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 7 to 8, schematic steps of a method for fabricating a semiconductor device 20 according to a second embodiment of the utility model are shown. The manufacturing steps of the semiconductor device 20 in this embodiment are substantially the same as those of the semiconductor device 10 in the foregoing first embodiment, and the details thereof will not be repeated. The main difference between the manufacturing method of this embodiment and the manufacturing method of the foregoing first embodiment is that, due to the effect of the foregoing etching load, a portion of the thickness t21 (as shown in fig. 2) of the bottom anti-reflective coating 174 of the silicon hard mask located in the peripheral region 100b is also reduced during the pattern transfer, and the underlying fourth support material layer 168b is also partially etched during the subsequent etching process, and finally the notch R1 is formed on the fourth support material layer 168 c.

In detail, as shown in fig. 7, in the present embodiment, the fourth support material layer 168a formed in the memory region 100a is partially consumed in performing the etching process, and accordingly has the same reduced thickness t12. The fourth support material layer 168b within the peripheral region 100b is fully protected by the silicon hard mask bottom anti-reflective coating 174 (original thickness t 21) and the organic underlayer 172 as shown in fig. 2, while maintaining the original thickness t11. The fourth support material layer 168c located at the junction between the memory region 100a and the peripheral region 100b is partially consumed during the etching process, so that the portion adjacent to the memory region 100a has a reduced thickness t12, and the portion adjacent to the peripheral region 100b maintains the original thickness t11, so that the whole structure is in a step-like structure.

Then, as shown in fig. 8, the manufacturing steps of fig. 4 to 6 in the first embodiment are continued, and the bottom electrode 378, the support structure 260, the capacitor dielectric layer 380 and the top electrode layer 282 are sequentially formed, and the bottom electrode 378, the capacitor dielectric layer 380 and the top electrode layer 282 are sequentially stacked to form the capacitor structure 384 of the present embodiment. It should be noted that, since the second supporting layer 264c formed at the junction of the storage region 100a and the peripheral region 100b has a portion with a relatively larger second thickness t11 and a portion with a relatively smaller first thickness t12, the bottom electrode 378b formed at the junction of the storage region 100a and the peripheral region 100b has two side walls with equal height, and has a symmetrical structure, and both side walls of the bottom electrode 378b are equal in height to both side walls of the bottom electrode 378a in the storage region 100 a. The bottom electrode 378 formed in the memory region 100a also has a bottom electrode 378a with symmetrical structure and a bottom electrode 378c with asymmetrical structure, so as to facilitate the subsequent deposition process. Thus, the manufacturing process of the semiconductor device 20 of the present embodiment is completed. The semiconductor device 20 of the present embodiment may also form a dynamic random access memory device, which includes a plurality of capacitors extending vertically as storage nodes of the semiconductor device 20 and electrically connected to transistor elements (not shown) in the substrate 100 through the storage node plugs 132.

According to the method for fabricating the semiconductor device 20 of the second embodiment of the present utility model, the second supporting layer 264c having a stepped structure is formed at the junction between the memory region 100a and the peripheral region 100b, such that the bottom electrode 378 having an asymmetric local structure (such as the bottom electrode 378 c) is formed only in the memory region 100a, and the bottom electrode 378b formed at the junction between the memory region 100a and the peripheral region 100b has a symmetrical U-shaped electrode structure. In this operation, the manufacturing method of the present embodiment can also pull the space between adjacent bottom electrodes 378 in the storage area 100a by forming the bottom electrodes 378 (e.g., bottom electrodes 378 c) with asymmetric local structures, so as to facilitate the subsequent deposition process. In addition, in the manufacturing method of the present embodiment, the support structure 260 with a larger local thickness is formed to strengthen the structural support of the bottom electrode 378 at the junction between the storage region 100a and the peripheral region 100b, for example, the second support layer 264c with a stepped structure is formed at the junction between the storage region 100a and the peripheral region 100b, so that a larger contact area between the subsequently formed capacitor dielectric layer 380 and the top electrode layer 282 and the second support layer 264c is obtained, thereby increasing the physical support. Therefore, the manufacturing method of the semiconductor device 20 of the present embodiment can effectively improve the structural reliability of the semiconductor device 20 and optimize the functions and performances of the semiconductor device 20 on the premise that the density of the memory cells is continuously increased and the complexity of the manufacturing process is gradually increased.

According to the semiconductor device 20 of the second embodiment of the present utility model, the second supporting layer 264c with a larger local thickness is disposed at the junction between the memory region 100a and the peripheral region 100b, so as to strengthen the structural support of the bottom electrode 378 at the junction between the memory region 100a and the peripheral region 100 b. In addition, the semiconductor device 20 of the present embodiment further includes a bottom electrode 378 (e.g., bottom electrode 378 c) with an asymmetric local structure, so as to effectively pull the space between adjacent bottom electrodes 378 in the storage region 100a, thereby facilitating the subsequent deposition process. Thus, the semiconductor device 20 of the present embodiment can maintain the structural reliability of the semiconductor device 20 and achieve the optimized functions and performances under the premise of continuously increasing the density of the memory cells.

Referring to fig. 9 to 10, schematic steps of a method for fabricating a semiconductor device 30 according to a third embodiment of the utility model are shown. The manufacturing steps of the semiconductor device 30 in this embodiment are substantially the same as those of the semiconductor device 10 in the foregoing first embodiment, and the details thereof will not be repeated. The main difference between the manufacturing method of the present embodiment and the manufacturing method of the first embodiment is that the present embodiment forms a plurality of columnar bottom electrodes 478.

In detail, as shown in fig. 9, a deposition and etch back process is performed to form a bottom electrode 478 within the support layer structure 170. The bottom electrode 478a formed in the memory region 100a has an overall flush top surface and exhibits a symmetrical pillar-shaped electrode structure, while the bottom electrode 478b formed at the interface between the memory region 100a and the peripheral region 100b has a stepped top surface and exhibits an asymmetrical pillar-shaped electrode structure.

Then, as shown in fig. 10, the manufacturing steps of fig. 4 to 6 in the first embodiment are continued, and the supporting structure 260, the capacitor dielectric layer 480 and the top electrode layer 482 are sequentially formed, and the capacitor structure 484 of the present embodiment is formed by sequentially stacking the bottom electrode 478, the capacitor dielectric layer 480 and the top electrode layer 482 together. It should be noted that, since the second supporting layer 264b formed at the junction of the memory region 100a and the peripheral region 100b has the relatively larger second thickness t11, the bottom electrode 478b formed at the junction of the memory region 100a and the peripheral region 100b has a stepped top surface and has an asymmetric columnar structure. On the other hand, the bottom electrodes 478a and 478c formed in the storage region 100a have symmetrical or asymmetrical pillar-shaped electrode structures, respectively, so as to facilitate the subsequent deposition process. Thus, the manufacturing process of the semiconductor device 30 of the present embodiment is completed. The semiconductor device 30 of the present embodiment may also form a dynamic random access memory device, which includes a plurality of capacitors extending vertically as storage nodes of the semiconductor device 30 and electrically connected to transistor elements (not shown) in the substrate 100 through the storage node plugs 132.

In the method for fabricating the semiconductor device 30 according to the third embodiment of the utility model, the support structure 260 with a larger local thickness is formed at the boundary between the memory region 100a and the peripheral region 100b, so that the bottom electrode 478b formed at the boundary between the memory region 100a and the peripheral region 100b has two sidewalls with different heights when the bottom electrode 478 is formed. The sidewall of the bottom electrode 478b adjacent to the peripheral region 100b physically contacts the second supporting layer 264b and has a relatively higher top surface, and the sidewall of the bottom electrode 478b adjacent to the storage region 100a has a relatively lower top surface and is equal in height to the top surface of the second supporting layer 264a, so that the bottom electrode 478b has an asymmetric columnar electrode structure as a whole. In this operation, the fabrication method of the present embodiment can be performed by forming the bottom electrode 478 (e.g., between the bottom electrodes 478b and 478 c) with asymmetric local structure to pull the space between the adjacent bottom electrodes 478 in the storage region 100a, so as to facilitate the subsequent deposition process. In addition, the manufacturing method of the present embodiment can further strengthen the structural support of the bottom electrode 478 at the junction between the storage region 100a and the peripheral region 100b by forming the support structure 260 with a larger local thickness. The second supporting layer 264b is further covered by the subsequently formed capacitor dielectric layer 480, so that the contact area among the capacitor dielectric layer 480, the top electrode layer 482 and the second supporting layer 264b is increased to increase the physical support. Therefore, the manufacturing method of the semiconductor device 30 of the present embodiment can effectively improve the structural reliability of the semiconductor device 30 and optimize the functions and performances of the semiconductor device 30 on the premise that the density of the memory cells is continuously increased and the complexity of the manufacturing process is gradually increased.

According to the semiconductor device 30 of the third embodiment of the present utility model, a support structure 260 with a larger local thickness is disposed at the junction between the storage region 100a and the peripheral region 100b, so as to strengthen the structural support of the bottom electrode 478 at the junction between the storage region 100a and the peripheral region 100 b. In addition, the semiconductor device 30 of the present embodiment further provides the bottom electrode 478 (e.g., bottom electrodes 478b and 478 c) with asymmetric local structure, so as to effectively pull the space between adjacent bottom electrodes 478 in the storage region 100a, so as to facilitate the subsequent deposition process. Therefore, the semiconductor device 30 of the present embodiment can maintain the structural reliability of the semiconductor device 30 and achieve the optimized function and performance under the premise of continuously increasing the density of the memory cells.

Referring to fig. 11, a cross-sectional view of a semiconductor device 40 according to a fourth embodiment of the utility model is shown. The structure of the semiconductor device 40 in this embodiment is substantially the same as that of the semiconductor device 10 in the foregoing first embodiment, and the details thereof will not be repeated. The main difference between the semiconductor device 40 of this embodiment and the semiconductor device 10 of the foregoing first embodiment is that the etching selectivity is controlled to partially consume the remaining portion of the fourth support material layer 168a when the second dry etching process and/or the second wet etching process is performed, or the etching selectivity ratio of the electrode material layer to the fourth support material layer 168 is adjusted to reduce the thickness of the remaining portion of the fourth support material layer 168a, 168b to be flush with or lower than the top surface of the bottom electrode 278a when forming each bottom electrode layer 178 as shown in fig. 4.

In detail, as shown in fig. 11, the second support layer 364a disposed in the memory region 100a has a relatively small first thickness t14, and a top surface thereof is lower than that of the bottom electrode 278a disposed in the memory region 100 a. On the other hand, the second support layer 364b disposed in the peripheral region 100b has a second thickness t13 greater than the first thickness t14, and has a highest top surface higher than the top surface of the second support layer 364a, and a highest top surface lower than the top surface of the bottom electrode 278b located at the junction between the memory region 100a and the peripheral region 100b, and a bottom surface coplanar with the bottom surface of the second support layer 364 a. Then, the capacitor dielectric layer 580 and the top electrode layer 582 are further formed, and the bottom electrode 278, the capacitor dielectric layer 580 and the top electrode layer 582 are sequentially stacked to form a capacitor structure 584 of the present embodiment. It should be noted that the subsequently formed capacitor dielectric layer 580 further encapsulates the second supporting layer 364b, such that the sidewalls and the surface of the second supporting layer 364b physically contact the bottom electrode 278b or the capacitor dielectric layer 580, respectively, and the structural support of the second supporting layer 364b to the bottom electrode 278b is optimized. Although the second support layer 364b between the memory region 100a and the peripheral region 100b is not shown in the drawings, it should be understood that the second support layer 364b may also have a step-like structure like the second support layer 264c shown in fig. 8, but is not limited thereto.

Thus, the semiconductor device 40 of the present embodiment can also form a dynamic random access memory device, which includes a plurality of capacitors extending vertically as storage nodes of the semiconductor device 40 and electrically connected to transistor elements (not shown) in the substrate 100 through the storage node plugs 132.

In the semiconductor device 40 according to the fourth embodiment of the present utility model, a support structure 260 with a larger local thickness is disposed at the junction between the memory region 100a and the peripheral region 100b to strengthen the structural support of the bottom electrode 278 at the junction between the memory region 100a and the peripheral region 100 b. In addition, the semiconductor device 40 of the present embodiment further provides the bottom electrode 278 (such as bottom electrodes 278b and 278 c) with an asymmetric local structure, so as to effectively pull the space between adjacent bottom electrodes 278 in the storage area 100a, so as to facilitate the subsequent deposition process. Thus, the semiconductor device 40 of the present embodiment can maintain the structural reliability of the semiconductor device 40 and achieve the optimized functions and performances under the premise of continuously increasing the density of the memory cells.

In summary, according to the semiconductor device and the manufacturing method thereof of the present utility model, a supporting structure with larger local thickness is formed between the storage region and the peripheral region to improve the structural support provided by the supporting structure to the capacitor structure, and simultaneously, the subsequently formed bottom electrode correspondingly has a locally asymmetric structure, thereby pulling the space between adjacent bottom electrodes in the storage region, and facilitating the proceeding of the subsequent deposition process. Therefore, the semiconductor device can maintain the structural reliability of the semiconductor device and achieve the optimized function and efficiency on the premise that the density of the storage unit is continuously improved.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A semiconductor device characterized by comprising:

a substrate including a storage region and a peripheral region;

a plurality of storage node pads disposed on the substrate and located within the storage region;

A capacitor structure disposed on the storage node pad, including a plurality of bottom electrodes respectively contacting the storage node pad; and

the support structure is arranged on the storage node bonding pad, the support structure is arranged between the bottom electrodes and physically contacts with the bottom electrodes, the support structure comprises a first support layer and a second support layer which are sequentially arranged from bottom to top, the second support layer has a first thickness and a second thickness, the second thickness is larger than the first thickness, the second support layer with the first thickness is arranged on the storage area, and the second support layer with the second thickness is arranged between the storage area and the peripheral area.

2. The semiconductor device of claim 1, wherein a top surface of the second support layer having the first thickness is coplanar with a top surface of the bottom electrode, a highest top surface of the second support layer having the second thickness being higher than a top surface of the second support layer having the first thickness.

3. The semiconductor device of claim 2, wherein a bottom surface of the second support layer having the second thickness is coplanar with a bottom surface of the second support layer having the first thickness.

4. The semiconductor device of claim 2, wherein the capacitive structure further comprises a capacitive dielectric layer and a top electrode layer stacked in sequence, a sidewall of the second support layer having the second thickness physically contacting the capacitive dielectric layer and the bottom electrode simultaneously.

5. The semiconductor device of claim 4, wherein two opposite sidewalls of the second support layer having the second thickness are respectively adjacent to/away from the storage region, sidewalls adjacent to the storage region physically contact the bottom electrode, and sidewalls remote from the storage region physically contact the capacitor dielectric layer.

6. The semiconductor device of claim 1, wherein a height of the second support layer having the second thickness relative to the top surface of the substrate is greater than a height of the second support layer having the first thickness relative to the top surface of the substrate.

7. The semiconductor device according to claim 1, wherein the second support layer has a stepped structure between the memory region and the peripheral region.

8. The semiconductor device of claim 1, wherein a highest top surface of the second support layer having the second thickness is coplanar with a top surface of any of the bottom electrodes, the top surface of the second support layer having the first thickness being lower than the top surface of the bottom electrode.

9. The semiconductor device of claim 8, wherein a bottom surface of the second support layer having the second thickness is coplanar with a bottom surface of the second support layer having the first thickness.

10. The semiconductor device according to claim 8, wherein the second support layer having the second thickness has a stepped structure between the memory region and the peripheral region.

11. The semiconductor device of claim 1, wherein the capacitor structure further comprises a capacitor dielectric layer and a top electrode layer stacked in sequence while overlying the second support layer having the second thickness, the second support layer having the first thickness, and the bottom electrode, the capacitor dielectric layer being in simultaneous physical contact with two opposing sidewalls of the second support layer having the second thickness.

12. The semiconductor device according to claim 1, wherein each of the bottom electrodes has a U-shaped electrode structure or a columnar electrode structure.