CN114121962A

CN114121962A - Dynamic random access memory device and forming method thereof

Info

Publication number: CN114121962A
Application number: CN202111452104.2A
Authority: CN
Inventors: 颜逸飞
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2022-03-01

Abstract

The invention discloses a dynamic random access memory device and a forming method thereof. The bit lines are arranged on the substrate and comprise a plurality of first bit lines and at least one second bit line. Contacts are disposed on the substrate and are alternately and separately disposed from the bit lines. A dielectric layer covers the contacts and the bit lines. The storage node pads are disposed in the dielectric layer and contact the contacts, respectively. The capacitor structure is arranged on the storage node bonding pad and comprises a plurality of first capacitors and at least one second capacitor positioned above at least one second bit line. Therefore, the dynamic random access memory device can achieve more optimized element performance.

Description

Dynamic random access memory device and forming method thereof

Technical Field

The present invention relates to a semiconductor memory device and a method for forming the same, and more particularly, to a semiconductor memory device including a dynamic random access memory and a method for forming the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For a Dynamic Random Access Memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of a capacitor structure, under the current mainstream development trend, it has gradually replaced a DRAM with a planar gate structure.

Generally, a dram having a recessed gate structure is formed by a large number of memory cells (memory cells) grouped to form an array region for storing information, and each memory cell may be composed of a transistor device and a capacitor device connected in series to receive voltage information from a Word Line (WL) and a Bit Line (BL). In response to product requirements, the density of memory cells in the array region needs to be continuously increased, which results in increasing difficulty and complexity in the related fabrication process and design. Therefore, further improvements are needed in the art to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

An objective of the present invention is to provide a dynamic random access memory device and a method for forming the same, in which a storage node pad is formed on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process. Thus, the capacitor structure formed subsequently can include at least a portion of the capacitor located on the dummy bit line to form a dummy capacitor. Under the arrangement, the DRAM device can be formed on the premise of simplifying the manufacturing process, and is isolated from surrounding active elements through the arrangement of the virtual capacitor, so that the effect of optimizing the efficiency of the whole device is achieved.

To achieve the above objective, one embodiment of the present invention provides a dynamic random access memory device, which includes a substrate, a plurality of bit lines, a plurality of contacts, a dielectric layer, a plurality of storage node pads, and a capacitor structure. The bit lines are arranged on the substrate and comprise a plurality of first bit lines and at least one second bit line, and the at least one second bit line is arranged on the outer sides of all the first bit lines. The contacts are disposed on the substrate and are alternately and separately disposed from the bit lines. The dielectric layer covers the contacts and the bit lines. The storage node pads are disposed in the dielectric layer and contact the contacts, respectively. The capacitor structure is arranged on the storage node bonding pad and comprises a plurality of first capacitors which are respectively positioned on the storage node bonding pad in a paired mode, and at least one second capacitor is positioned above the at least one second bit line.

To achieve the above objective, an embodiment of the present invention provides a method for forming a dynamic random access memory device, which includes the following steps. Firstly, a substrate is provided, a plurality of bit lines are formed on the substrate, the bit lines comprise a plurality of first bit lines and at least one second bit line, and the at least one second bit line is formed on the outer side of all the first bit lines. Then, a plurality of contacts are formed on the substrate, the bit lines and the contacts are alternately arranged, and a dielectric layer is formed above the contacts and the bit lines to cover the contacts and the bit lines. Then, a plurality of storage node pads are formed in the dielectric layer, and the storage node pads are respectively opposite to the contacts. And forming a capacitor structure on the storage node bonding pad, wherein the capacitor structure comprises a plurality of first capacitors which are respectively positioned on the storage node bonding pad in a pair mode, and at least one second capacitor is positioned above the at least one second bit line.

Drawings

Fig. 1 to 9 are schematic views illustrating steps of a method for forming a semiconductor memory device according to a first embodiment of the present invention, wherein:

FIG. 1 is a top view of a semiconductor memory device after bit lines are formed;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a top view of a semiconductor memory device after a self-aligned double patterning process;

FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 5 is a cross-sectional view of a semiconductor memory device after formation of a storage node pad;

FIG. 6 is a cross-sectional view of a semiconductor memory device after forming a stacked structure;

FIG. 7 is a cross-sectional view of a semiconductor memory device after forming a bottom electrode layer;

FIG. 8 is a cross-sectional view of a semiconductor memory device after forming a top electrode layer; and

FIG. 9 is another cross-sectional view of a semiconductor memory device after forming a top electrode layer.

FIG. 10 is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.

Wherein the reference numerals are as follows:

300. 400, 500, 600 semiconductor memory device

100 substrate

101 insulating region

103 active region

130 dielectric layer

131 oxide layer

133 nitride layer

135 oxide layer

160 bit line

160a bit line contact

161 semiconductor layer

162 first bit line

163 barrier layer

164 second bit line

165 conductive layer

167 a cap layer

170 spacer structure

171 first spacer

173 second spacer

175 third spacer

180 contact

182 first contact

184 second contact

210 metal layer

211 storage node pad

221. 223 patterned mask

230 dielectric layer

240 supporting layer structure

241 first supporting layer

242 first opening

243 second support layer

244 third opening

245 third support layer

246 second opening

247 fourth support layer

250. 450, 550, 650 capacitor structure

250a, 650a first capacitance

250b, 450b, 550b, 650b second capacitance

250c, 650c third capacitance

251 bottom electrode layer

253 capacitor dielectric layer

255 top electrode layer

D1 first direction

D2 second direction

Third direction D3

W1 and W2 line widths

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below to explain the present invention and its intended effects. Those skilled in the art to which the invention relates will appreciate that the features of the various embodiments can be interchanged, recombined, mixed and modified to achieve other embodiments without departing from the spirit of the invention as defined by the appended claims.

Referring to fig. 1 to 8, steps of a method for forming a semiconductor memory device 300 according to a first embodiment of the present invention are illustrated. First, as shown in fig. 1, a substrate 100, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, is provided, at least one insulating region 101, such as a Shallow Trench Isolation (STI), is further formed in the substrate 100, and a plurality of Active Areas (AA) 103 are defined on the substrate 100. Preferably, the active regions 103 extend along the first direction D1 in parallel and spaced apart from each other and are disposed alternately, wherein the first direction D1 is, for example, intersecting and not perpendicular to the y-direction or the x-direction, as shown in fig. 1. In an embodiment, the insulating region 101 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

In addition, a plurality of buried gates (not shown) may be formed in the substrate 100, for example, the buried gates may extend parallel to each other along a direction (e.g., y direction) and cross the active region 103 to serve as buried word lines (BWLs, not shown) of the semiconductor memory device 300. A plurality of bit lines 160 and a plurality of contacts 180 (not shown in fig. 1) may be formed over the substrate 100, wherein the bit lines 160 extend in another direction (e.g., x direction) perpendicular to the direction and are interleaved with the active regions 103. Although the buried gates are not specifically shown in the drawings of the present embodiment, it should be understood that the bit lines 160 extending in the x direction are perpendicular to the buried gates extending in the y direction and are interleaved with the active regions 103 and the buried gates if viewed from a top view.

As shown in fig. 1, the bit lines 160 further include a plurality of first bit lines 162 and at least one second bit line 164, the first bit lines 162 and the second bit lines 164 are respectively disposed in a memory cell region (not shown) and a peripheral region (not shown) of the semiconductor memory device 300, and can be used as general Bit Lines (BLs) and dummy bit lines (dummy BLs), respectively, wherein the second bit lines 164 can be disposed at one side of all the first bit lines 162, but not limited thereto. It should be readily understood by those skilled in the art that the memory region and the peripheral region may have other configurations such that the first bit lines and the second bit lines have other configurations or the second bit lines have other numbers. For example, in one embodiment, the semiconductor memory device preferably includes two second bit lines respectively disposed on two opposite sides (i.e., upper and lower sides) of all the first bit lines 162 to isolate other external devices. In addition, in the present embodiment, a line width (e.g., a width in the y direction) W2 of each second bit line 164 is preferably greater than a line width W1 of each first bit line 162, but not limited thereto. In another embodiment, the second bit line and the first bit line may have the same line width selectively.

In detail, as shown in fig. 2, each bit line 160 is formed on the substrate 100 separately and includes a semiconductor layer (e.g., including polysilicon) 161, a barrier layer 163 (e.g., including titanium and/or titanium nitride), a conductive layer 165 (e.g., including low-resistance metal such as tungsten, aluminum or copper), and a cap layer 167 (e.g., including silicon oxide, silicon nitride or silicon oxynitride), which are stacked in sequence, but not limited thereto. It is noted that a portion of the first bit line 162 is formed on the dielectric layer 130 over the substrate 100, wherein the dielectric layer 130 preferably has a composite structure, such as, but not limited to, an oxide-nitride-oxide (ONO) structure including an oxide layer 131-a nitride layer 133-an oxide layer 135; another portion of the first bit lines 162 is further formed with Bit Line Contacts (BLC) 160a below it, extending into the substrate 100 and directly contacting the underlying substrate 100 (active region 103). The bit line contact 160a is formed integrally with the semiconductor layer 161 of the other part of the first bit line 162, for example, as shown in fig. 2. On the other hand, the contacts 180 are similarly formed on the substrate 100 so as to be spaced apart from each other, and are alternately arranged with the bit lines 160. The contacts 180 and the bit lines 160 are insulated from each other by spacer structures 170. In one embodiment, the spacer structure 170 may alternatively have a single layer structure or a composite layer structure as shown in fig. 2, which includes, for example, but not limited to, a first spacer 171 (e.g., comprising silicon nitride), a second spacer 173 (e.g., comprising silicon oxide), and a third spacer 173 (e.g., comprising silicon nitride) stacked in sequence. In addition, the contact 180 further includes a plurality of first contacts 182 and a plurality of second contacts 184 alternately arranged with each other, which are disposed in the memory region of the semiconductor memory device 300 and directly contact the underlying substrate 100 (including the active region 103 and the insulating region 101) to serve as Storage Node Contacts (SNCs) of the semiconductor memory device 300. In one embodiment, the contact 180 includes a low resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W).

Next, a plurality of storage node pads (SN pads) 211 are formed on the substrate 100. The storage node pads 211 are formed through a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but not limited thereto. Referring to fig. 3 and 4, a metal layer 210, such as a low-resistance metal material including aluminum, titanium, copper or tungsten, is formed above the contact 180 and the bit line 160, and preferably includes a metal material different from the contact 180, but not limited thereto; then, sequentially performing at least two self-aligned double patterning processes, forming a plurality of patterned masks 221 extending parallel to each other along the second direction D2 and a plurality of patterned masks 223 extending parallel to each other along the second direction D3 on the metal layer 210, wherein the second direction D2 and the second direction D3 intersect each other and are not perpendicular to the y-direction or the x-direction, respectively, for example, an included angle between the second direction D2 or the second direction D3 and the y-direction or the x-direction is about 60 to 120 degrees, as shown in fig. 3, but not limited thereto; then, the storage node pad 211 is formed by defining the relative position of the storage node pad 211 through the overlapping portion of the patterned mask 221 and the patterned mask 223, and performing an etching process using the formed mask as an etching mask to pattern the underlying metal layer 210, as shown in fig. 5. Note that in this embodiment, the storage node pads 211 are formed above the contacts 180 and the bit lines 160 by controlling the overlapping portions of the patterned

masks

221 and 223, and selectively located only on the first contacts 182. In other words, the storage node pads 211 are not formed above the respective second contacts 184.

Subsequently, the capacitor structure 250 may be formed over the storage node pad 211 to directly contact and electrically connect the underlying storage node pad 211. In one embodiment, the process for fabricating the capacitor structure 250 includes, but is not limited to, the following steps. First, as shown in fig. 6, a dielectric layer 230 and a support layer structure 240 are formed over the substrate 100, the dielectric layer 230 covers the contacts 180 (including the first contact 182 and the second contact 184) and the bit lines 160, and the thickness of the dielectric layer 230 is preferably greater than the thickness of the storage node pads 211, so that the storage node pads 211 can be located in the dielectric layer 230. The support layer structure 240 includes, for example, at least one oxide layer and at least one nitride layer that are alternately stacked. In the present embodiment, the support layer structure 240 includes, for example, a first support layer 241 (for example, including silicon oxide), a second support layer 243 (for example, including silicon nitride or silicon carbonitride), a third support layer 245 (for example, including silicon oxide), and a fourth support layer 247 (for example, including silicon nitride or silicon carbonitride), which are stacked from bottom to top in sequence, but not limited thereto. Preferably, the first support layer 241 and the third support layer 245 may have a relatively large thickness, for example, about 5 times to 10 times or more of the other support layers (the second support layer 243 or the fourth support layer 247), but not limited thereto. Therefore, the thickness of the supporting layer structure 240 can reach about 1600 angstroms (angstroms) to about 2000 angstroms, but not limited thereto. It should be understood by those skilled in the art that the specific stacking number of the oxide layer (e.g., the first support layer 241 or the third support layer 245) and the nitride layer (e.g., the second support layer 243 or the fourth support layer 247) is not limited to the above number, and can be adjusted according to the actual requirement, such as 3 layers, 4 layers or other numbers. Then, a plurality of first openings 242, at least one second opening 246, and a plurality of third openings 244 are formed in the support layer structure 240, and sequentially penetrate through the fourth support layer 247, the third support layer 245, the second support layer 243, the first support layer 241, and a portion of the dielectric layer 230. The first openings 242 and the third openings 244 are alternately disposed in the storage region, wherein the first openings 242 respectively face the storage node pads 211 (and the first contacts 182) located therebelow, so that the top surfaces of the storage node pads 211 can be exposed from the first openings 242; the third openings 244 are respectively aligned with the lower second contacts 184, but the bottom surfaces of the third openings 244 are lower than the top surface of the dielectric layer 230 but do not penetrate through the dielectric layer 230, so that only a portion of the dielectric layer 230 is exposed from the third openings 244. The second openings 246 are disposed outside all of the first openings 242 and all of the third openings 244, and for the second bit lines 164 located in the peripheral region, the second openings 246 do not penetrate through the dielectric layer 230, and only a portion of the dielectric layer 230 is exposed, as shown in fig. 6.

Next, as shown in fig. 7, a bottom electrode layer 251 is formed to fill the first opening 242, the third opening 244 and the second opening 246, wherein the bottom electrode layer 251 is made of a low-resistance metal material, such as aluminum, titanium, copper or tungsten, preferably, titanium, but not limited thereto. It is noted that the bottom electrode layer 251 disposed in the first opening 242 directly contacts the underlying storage node pad 211; the bottom electrode layer 251 disposed in the third opening 244 and the second opening 246 directly contacts the dielectric layer 230, and is located directly above the second contact 184 and the second bit line 164. As shown in fig. 7, after the bottom electrode layer 251 is formed, an etching process is performed through a mask layer (not shown), so as to completely remove the oxide layer (such as the first supporting layer 241 or the third supporting layer 245) in the supporting layer structure 240 and partially remove the nitride layer (such as the second supporting layer 243 or the fourth supporting layer 247) in the supporting layer structure 240.

Subsequently, as shown in fig. 8, a capacitor dielectric layer 253 and a top electrode layer 255 are sequentially formed on the bottom electrode layer 251, wherein a portion of the capacitor dielectric layer 253 and a portion of the top electrode layer 255 may further be filled between the remaining second supporting layer 243 and the fourth supporting layer 247, and between the remaining second supporting layer 243 and the dielectric layer 230. In one embodiment, the capacitor dielectric layer 253 comprises a high-k dielectric material selected from hafnium oxide (HfO)₂) Hafnium silicon oxide (HfSiO)₄) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO)₂) Titanium oxide (TiO)₂) And zirconia-alumina-zirconia (ZAZ), preferably including zirconia-alumina-zirconia; the top electrode layer 255 includes, for example, a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably, but not limited to, titanium.

Thus, the manufacturing process of the capacitor structure 250 is completed. The capacitor structure 250 includes a bottom electrode layer 251, a capacitor dielectric layer 253, and a top electrode layer 255 stacked in sequence to form a plurality of

capacitors

250a, 250b, 250c extending vertically. It should be noted that the capacitor structure 250 includes a plurality of first capacitors 250a and a plurality of third capacitors 250c, and the first capacitors 250a and the third capacitors 250c are alternately and separately disposed to respectively face the first contact 182 and the second contact 184. Each of the first capacitors 250a may be electrically connected to a transistor element (not shown) of the semiconductor memory device 300 through the storage node pad 211 and the storage node plug (i.e., the first contact 182), so that the first capacitor 250a may serve as a Storage Node (SN) of the semiconductor memory device 300, and the capacitor structure 250 and the transistor element may maintain a good contact relationship. On the other hand, the storage node pad 211 is not disposed under each third capacitor 250c, and cannot be electrically connected to the storage node plug (i.e., the contact 184) thereunder, and the bottom surface of the third capacitor 250c (i.e., the bottom surface of the bottom electrode layer 251 filling the second opening 246) only contacts the dielectric layer 230 to form an open circuit, which becomes a dummy storage node (dummy SN) to isolate the adjacent storage nodes, so as to maintain the overall device performance. Wherein the bottom surface of the third capacitor 250c is lower than the top surface of the dielectric layer 230, as shown in fig. 8.

It should be noted that the capacitor structure 250 further includes at least one second capacitor 250b, under which the storage node pad 211 is not disposed, and at least one second capacitor 250b is located outside all the first capacitors 250a and all the third capacitors 250c, corresponding to the second bit line 164 located in the peripheral region. In this way, the bottom surface of at least one second capacitor 250b (i.e., the bottom surface of the bottom electrode layer 251 filling the third opening 244) also directly contacts the dielectric layer 230 to form an open circuit, thereby serving as the dummy storage node to isolate the adjacent storage nodes. Although the cross-sectional view shown in fig. 8 only shows one second capacitor 250b located on the second bit line 164, it should be easily understood by those skilled in the art that a plurality of second capacitors 250b may be located on the second bit line 164 in cross-sectional views along other directions, such as a cross-sectional view along the extending direction of the second bit line 164, as shown in fig. 9. Thus, the semiconductor memory device 300 of the present embodiment can form a Dynamic Random Access Memory (DRAM) device, in which at least one transistor element and at least one first capacitor 250a form a minimum unit cell (memory cell) in a DRAM array to receive voltage information from the bit line 160 and the buried word line.

Thus, the semiconductor memory device 300 according to the first embodiment of the present invention is completed. According to the forming method of the present embodiment, the storage node pad 211 is formed by controlling the portion where the patterned mask 221 and the patterned mask 223 overlap with each other, so that the storage node pad 211 is only disposed above the first contact 182 and is not disposed above the second contact 184. Thus, after the capacitor structure 250 is formed, a first capacitor 250a serving as a storage node and a second capacitor 250b and/or a third capacitor 250c serving as a dummy storage node are formed, wherein the storage node (i.e., the first capacitor 250a) is electrically connected to a transistor element (not shown) of the semiconductor memory device 300 through a storage node pad 211 and the storage node plug (i.e., the first contact 182) disposed therebelow, and the dummy storage node (i.e., the second capacitor 250b and/or the third capacitor 250c) is not provided with the storage node pad 211 disposed therebelow and cannot be electrically connected to the storage node plug (i.e., the second contact 184) disposed therebelow. The dummy storage nodes are configured to stabilize and enhance the performance of the storage nodes, and to isolate adjacent storage nodes to maintain the overall device performance of the semiconductor memory device 300.

In addition, it should be readily apparent to those skilled in the art that other aspects of the present invention and methods of forming semiconductor memory devices and methods of forming the same are possible without limitation to the foregoing embodiments. For example, the dummy storage node may optionally have other configuration aspects. Further embodiments or variations of the method of the semiconductor memory device of the present invention are described below. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 10, a method for forming a semiconductor memory device 400 according to a second embodiment of the present invention is shown. The steps for forming the front end of the semiconductor memory device 400 in this embodiment are substantially the same as the steps for forming the front end of the semiconductor memory device 300 in the first embodiment, and are not described herein again. The main difference between the present embodiment and the first embodiment is that at least one second capacitor 450b penetrates through the dielectric layer 230 and can directly contact the cap layer 167 of the second bit line 164.

In detail, in the forming method of the present embodiment, when the opening is formed in the supporting layer structure 240, the etching process condition is further controlled, so that a second opening (not shown) corresponding to the second bit line 164 selectively penetrates through the dielectric layer 230 and stops on the top surface of the cap layer 167 of the second bit line 164, and thus the cap layer 167 of the second bit line 164 is exposed from the second opening. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253, and the top electrode layer 255 are sequentially formed, so that the capacitor structure 450 as shown in fig. 10 can be formed, wherein at least one second capacitor 450b extends into the dielectric layer 230 and directly contacts the top surface of the cap layer 167 of the second bit line 164 through the bottom electrode layer 251 with respect to the second bit line 164 located in the peripheral region, so that the at least one second capacitor 450b only contacts the dielectric layer 230 and the cap layer 167 to form an open circuit, thereby forming the virtual storage node. With this arrangement, the semiconductor memory device 400 of the present embodiment can also form a dynamic random access memory device, and the second capacitor 450b and the third capacitor 250c isolate the adjacent storage nodes to maintain the overall device performance.

Referring to fig. 11, a method for forming a semiconductor memory device 500 according to a third embodiment of the invention is shown. The steps for forming the front end of the semiconductor memory device 500 in this embodiment are substantially the same as the steps for forming the front end of the semiconductor memory device 300 in the first embodiment, and are not described herein again. The main difference between this embodiment and the first embodiment is that at least one second capacitor 550b penetrates through the dielectric layer 230 and further extends into a portion of the cap layer 167 of the second bit line 164.

In detail, in the forming method of the present embodiment, when the opening is formed in the supporting layer structure 240, the etching process condition is further controlled, and a second opening (not shown) located on the second bit line 164 is selectively made to penetrate through the dielectric layer 230 and a portion of the cap layer 167 of the second bit line 164, so that the second opening can extend into the portion of the cap layer 167. In other words, the bottom surface of the second opening may be lower than the top surface of the second bit line 164, and the portion of the cap layer 167 may be exposed from the second opening. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253, and the top electrode layer 255 are sequentially formed, so that the capacitor structure 550 shown in fig. 11 can be formed, wherein at least one second capacitor 550b is located on the second bit line 164 in the peripheral region, and extends into the portion of the cap layer 167 through the bottom electrode layer 251 thereof and directly contacts the portion of the cap layer 164, so that the bottom surface of at least one second capacitor 550b (i.e., the bottom surface of the bottom electrode layer 251 filling the second opening) can be lower than the top surface of the second bit line 164, and at least one second capacitor 550b only contacts the cap layer 167 to form an open circuit, thereby forming the dummy storage node. With this arrangement, the semiconductor memory device 500 of the present embodiment can also form a dynamic random access memory device, and the second capacitor 550b and the third capacitor 250c isolate the adjacent storage nodes to maintain the overall device performance.

Referring to fig. 12, a process of forming a semiconductor memory device 600 according to a fourth embodiment of the invention is shown. The steps for forming the front end of the semiconductor memory device 600 in this embodiment are substantially the same as the steps for forming the front end of the semiconductor memory device 300 in the first embodiment, and are not described herein again. The main difference between this embodiment and the first embodiment is that at least one second capacitor 650b is located above a portion of the second bit line 164 and a portion of the contact 180.

In detail, as shown in fig. 12, the forming method of the present embodiment is to overlap each of the storage node pads 211 with the underlying first contact 182 only partially when forming the storage node pads 211, so as to obtain a larger process space. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253, and the top electrode layer 255 are sequentially formed, so as to form the capacitor structure 650 as shown in fig. 12. Thus, each storage node pad 211 may be simultaneously located above a portion of the first contact 182, the spacer structure 170, and a portion of the first bit line 162, and the subsequently formed first capacitor 650a may be simultaneously located above a portion of the first contact 182, the spacer structure 170, and the first bit line 162, and the third capacitor 650c may be simultaneously located above a portion of the second contact 184, the spacer structure 170, and the first bit line 162. In addition, the second capacitor 650b located in the peripheral region may be simultaneously located above a portion of the second contact 184, the spacer structure 170 and the second bit line 164. It should be noted that, in the present embodiment, the etching process conditions may be further controlled to selectively enable the opening (not shown) located in the peripheral region to only penetrate through a portion of the dielectric layer 230, so that the bottom surface of the second capacitor 650b (i.e., the bottom surface of the bottom electrode layer 251 filling the opening) only contacts the dielectric layer 230, as shown in fig. 12, but not limited thereto. With this arrangement, the semiconductor memory device 600 of the present embodiment can also form a dynamic random access memory device, and the second capacitor 650b and the third capacitor 650c isolate the adjacent storage nodes to maintain the overall device performance.

In general, the present invention forms a storage node pad on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process, and forms the storage node pad only for a portion of a contact by controlling overlapping portions of patterned masks. Thus, after the capacitor structure is formed, a first capacitor which can be used as a storage node and a second capacitor which can be used as a virtual storage node can be respectively formed, wherein the storage node (i.e. the first capacitor) is electrically connected with a transistor component (not shown) of the semiconductor storage device through the storage node pad and the storage node plug (i.e. the contact) below, and the storage node pad is not arranged below the virtual storage node (i.e. the second capacitor) but directly contacts the cover layer of the virtual bit line, so that the storage node plug (i.e. the contact) cannot be electrically connected, and the adjacent storage node can be isolated, so that the overall element performance of the semiconductor storage device can be maintained.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic random access memory device, comprising:

a substrate;

a plurality of bit lines disposed on the substrate, the bit lines including a plurality of first bit lines and at least one second bit line, the at least one second bit line disposed outside all of the first bit lines;

a plurality of contacts disposed on the substrate and alternately and separately disposed from the bit lines;

a dielectric layer covering the contacts and the bit lines;

a plurality of storage node pads disposed within the dielectric layer and contacting the contacts, respectively; and

and the capacitor structure is arranged on the storage node bonding pad and comprises a plurality of first capacitors which are respectively positioned on the storage node bonding pad in a butt joint mode, and at least one second capacitor is positioned above the at least one second bit line.

2. The dynamic random access memory device of claim 1, wherein a bottom surface of the at least one second capacitor directly contacts the dielectric layer.

3. The dynamic random access memory device of claim 1, wherein the at least one second capacitor is located over both a portion of the contact and a portion of the second bit line.

4. The dynamic random access memory device of claim 1, wherein the bit lines respectively comprise a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence from bottom to top, and the at least one second capacitor directly contacts the cap layer of the at least one second bit line.

5. The dynamic random access memory device of claim 4, wherein the at least one second capacitor directly contacts the capping layer of the at least one second bit line.

6. The dynamic random access memory device of claim 1, wherein a bottom surface of the at least one second capacitor is lower than a top surface of the at least one second bit line.

7. The dynamic random access memory device of claim 1, wherein the at least one second bit line has a linewidth greater than the linewidth of the first bit line.

8. The dynamic random access memory device of claim 1, wherein the capacitor structure further comprises a plurality of third capacitors respectively aligned at the contacts, the third capacitors directly contacting the dielectric layer.

9. The dynamic random access memory device of claim 8, wherein the third capacitor and the first capacitor are alternately and separately disposed.

10. The dynamic random access memory device of claim 5, wherein the bottom surface of the third capacitor is lower than the top surface of the dielectric layer.

11. A method of forming a dynamic random access memory device, comprising:

providing a substrate;

forming a plurality of bit lines on the substrate, wherein the bit lines comprise a plurality of first bit lines and at least one second bit line, and the at least one second bit line is formed at the outer side of all the first bit lines;

forming a plurality of contacts on the substrate, wherein the bit lines and the contacts are alternately arranged;

forming a dielectric layer over the contacts and the bit lines, covering the contacts and the bit lines;

forming a plurality of storage node bonding pads in the dielectric layer, wherein the storage node bonding pads are respectively opposite to the contacts; and

and forming a capacitor structure on the storage node bonding pad, wherein the capacitor structure comprises a plurality of first capacitors which are respectively positioned on the storage node bonding pad in a pair mode, and at least one second capacitor is positioned above the at least one second bit line.

12. The method of claim 11, further comprising:

forming a support layer structure on the substrate, the support layer structure comprising at least one oxide layer and at least one nitride layer alternately stacked;

forming a plurality of openings in the supporting layer structure, wherein each opening penetrates through the supporting layer structure;

forming a bottom electrode layer in the opening; and

completely removing the oxide layer within the support layer structure.

13. The method of claim 9, further comprising sequentially forming a capacitor dielectric layer and a top electrode layer on the bottom electrode layer.

14. The method as claimed in claim 12, wherein the openings include a plurality of first openings and at least one second opening, the first openings respectively expose the storage node pads, and the at least one second opening exposes the at least one second bit line.

15. The method of claim 14, wherein a bottom surface of the at least one second opening is lower than a top surface of the at least one second bit line.

16. The method as claimed in claim 11, wherein the at least one second opening is formed outside all of the first openings.

17. The method of claim 11, wherein the openings further comprise a plurality of third openings, and the third openings respectively expose the dielectric layer.

18. The method as claimed in claim 17, wherein the third openings and the first openings are alternately disposed, and the at least one second opening is formed outside all of the first openings and all of the third openings.

19. The method of claim 17, wherein a bottom surface of the third opening is lower than a top surface of the dielectric layer.

20. The method as claimed in claim 14, wherein the bit lines respectively comprise a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence from bottom to top, and the bottom electrode layer formed in the at least one second opening directly contacts the cap layer of the at least one second bit line.