CN116209247B - Dynamic memory, manufacturing method thereof, reading method thereof and storage device - Google Patents

Dynamic memory, manufacturing method thereof, reading method thereof and storage device Download PDF

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Publication number
CN116209247B
CN116209247B CN202210945146.8A CN202210945146A CN116209247B CN 116209247 B CN116209247 B CN 116209247B CN 202210945146 A CN202210945146 A CN 202210945146A CN 116209247 B CN116209247 B CN 116209247B
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layer
electrode
substrate
drain
drain electrode
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CN116209247A (en
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朱正勇
康卜文
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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Priority to PCT/CN2023/098858 priority patent/WO2024032123A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application provides a dynamic memory, a manufacturing method, a reading method and a storage device thereof. The dynamic memory comprises a substrate, a plurality of word lines, a plurality of bit lines, a reference potential line and a plurality of memory cells which are arranged on the substrate, wherein a transistor is formed by a source electrode, a drain electrode, a semiconductor layer, a main grid electrode, a back grid electrode and the like in the memory cells, and a storage capacitor is formed by a capacitor electrode and the back grid electrode; in the memory cell, the back gate and the source electrode form an auxiliary capacitor, so that the capacitance of the memory cell is increased, and the refresh frequency of the dynamic memory is reduced; in the reading process of the dynamic memory, the data signals read by the bit lines in the two states of 1 or 0 have huge difference, so that the noise resistance of the dynamic memory is enhanced; because the signal can not be detected in the 0 state, the state judgment can be realized by utilizing the current detection or the voltage detection, thereby being convenient for designing the peripheral detection circuit according to specific requirements.

Description

Dynamic memory, manufacturing method thereof, reading method thereof and storage device
Technical Field
The present application relates to the field of memory technologies, and in particular, to a dynamic memory, a method for manufacturing the dynamic memory, a method for reading the dynamic memory, and a memory device.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and has the advantages of simpler structure, lower manufacturing cost and higher capacity density compared with the static memory.
DRAM memory typically includes a plurality of memory cells each including a transistor therein, which causes a gradual loss of charge stored in the memory cells due to leakage across the active layer, so that the stored data needs to be frequently refreshed to ensure the validity of the stored data.
In the current mainstream DRAM, in order to reduce the refresh rate, the conventional design is that the capacitor needs to be large enough, which makes the DRAM not compact in structure and low in integration level.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a dynamic memory, a manufacturing method, a reading method and a storage device thereof, which are used for solving the technical problem that the refresh frequency and the integration level of the DRAM memory are difficult to be compatible in the prior art.
In a first aspect, embodiments of the present application provide a dynamic memory, a substrate, a plurality of word lines, a plurality of bit lines, a reference potential line, and a plurality of memory cells on the substrate, the memory cells comprising:
The capacitor electrode is positioned on the substrate and is columnar, and the capacitor electrode is electrically connected with the reference potential line;
a back gate located between and surrounding the capacitive electrode and the substrate, the back gate being insulated from the capacitive electrode and constituting a storage capacitance with the capacitive electrode;
a drain electrode, a semiconductor layer and a source electrode which are positioned on one side of the substrate and are sequentially stacked in a direction away from the substrate, wherein the drain electrode, the semiconductor layer and the source electrode encircle the capacitor electrode and are positioned on one side of the back gate away from the capacitor electrode, the drain electrode, the semiconductor layer and the source electrode are annular in a section parallel to the substrate, the drain electrode is electrically connected with the back gate, and the back gate and the source electrode form an auxiliary capacitor;
a main gate surrounding an outer sidewall of the semiconductor layer, the main gate being electrically connected with the word line and insulated from the source and the drain.
Optionally, the memory cell further includes a connection portion, the connection portion is located between the substrate and the drain electrode and between the substrate and the back gate, the connection portion is directly in contact with the drain electrode and simultaneously in contact with the back gate, and a material of the connection portion is a conductive material; the area where orthographic projection of the connecting part on the substrate is located is a first area, the area surrounding the first area is a second area, and the thickness of the substrate located in the first area is larger than that of the substrate located in the second area.
Optionally, the storage unit further includes:
a first insulating layer located at one side of the source electrode away from the substrate;
the side wall is positioned at one side of the first insulating layer away from the substrate;
the side wall, the first insulating layer, the source electrode and the orthographic projection of the drain electrode on the substrate coincide, the orthographic projection of the semiconductor layer on the substrate is positioned in the orthographic projection of the drain electrode on the substrate, and the orthographic projection of the drain electrode on the substrate is positioned in the orthographic projection of the connecting part on the substrate.
Optionally, the side wall, the first insulating layer, the source electrode, the semiconductor layer and the drain electrode are all annular, the inner diameter of the semiconductor layer is larger than the inner diameter of the drain electrode, and the outer diameter of the semiconductor layer is smaller than the outer diameter of the drain electrode.
Optionally, the main gate is located in a region corresponding to the semiconductor layer between the source electrode and the drain electrode, the word line is made of the same material as the main gate and is in contact with the main gate, and the orthographic projection of the word line on the substrate is located in the second region; the potential reference line is positioned on one side of the capacitance electrode far away from the substrate and is in contact with the capacitance electrode; the bit line is located at one side of the potential reference line away from the substrate and is electrically connected with the source electrode through a via hole.
Optionally, the substrate is made of a P-type silicon material, the connecting portion is made of an N-type heavily doped silicon material, the drain is made of an N-type silicon material, the source is made of an N-type silicon material, and the semiconductor layer is made of a silicon germanium material.
In a second aspect, embodiments of the present application provide a storage device that includes the dynamic memory described above.
In a third aspect, an embodiment of the present application provides a method for manufacturing a dynamic memory, where the method includes:
providing a substrate, and forming a drain electrode layer, a semiconductor material layer and a source electrode layer which are sequentially stacked on one side of the substrate through a patterning process, wherein the drain electrode layer, the semiconductor material layer and the source electrode layer are cylindrical;
forming a main gate electrode surrounding the semiconductor layer, the main gate electrode being electrically connected to a word line and insulated from the source electrode and the drain electrode;
forming a containing hole penetrating through the drain electrode layer, the semiconductor material layer and the source electrode layer through a patterning process, wherein the drain electrode layer penetrated by the containing hole forms a drain electrode, the semiconductor material layer penetrated by the containing hole forms a semiconductor layer, and the drain electrode layer penetrated by the containing hole forms a drain electrode;
And a back grid electrode and a capacitor electrode are sequentially formed in the accommodating hole, and the capacitor electrode is electrically connected with a reference potential line and is insulated from the source electrode, the drain electrode, the main grid electrode and the back grid electrode, wherein the capacitor electrode and the back grid electrode form a storage capacitor, and the back grid electrode and the source electrode form an auxiliary capacitor.
Optionally, the memory cell further includes a connection portion between the substrate and the drain electrode and a first insulating layer located on a side of the source electrode layer away from the substrate, where the connection portion is directly in contact with the drain electrode and simultaneously in contact with the back gate electrode, and a material of the connection portion is a conductive material;
forming a drain layer, a semiconductor material layer and a source layer stacked in sequence on one side of the substrate through a patterning process, comprising:
sequentially growing a connecting layer, the drain electrode layer, a semiconductor material layer, a source electrode layer and a first insulating layer on one surface of the connecting layer, which is far away from the substrate, through an epitaxial growth method;
forming a plurality of side walls and sacrificial parts in the side walls on one side, far away from the substrate, of the first insulating layer through a patterning process, wherein the areas where the side walls and the sacrificial parts are located are first areas, and the area surrounding the first areas is a second area;
And etching the first insulating layer, the source electrode layer, the semiconductor material layer and the drain electrode layer according to the side wall to form a cylindrical first insulating layer, a cylindrical source electrode layer, a cylindrical semiconductor material layer and a cylindrical drain electrode layer, and etching a substrate positioned in a second area to enable the thickness of the substrate positioned in the first area to be larger than that of the substrate positioned in the second area.
Optionally, forming a main gate surrounding the semiconductor layer, the main gate being electrically connected to the word line and insulated from the source and the drain, comprising:
performing first partial etching on the semiconductor material layer to enable the outer diameter of the semiconductor material layer to be smaller than that of the drain electrode layer;
a first gate dielectric layer on the substrate in the second region, the first gate dielectric layer being located on the sidewalls of the connection layer, the drain layer, the semiconductor material layer, the source layer, and the first insulating layer after the first partial etch;
forming a main grid electrode on one side of the first grid electrode dielectric layer far away from the semiconductor material layer;
and forming a second insulating layer, a first conductive layer and a third insulating layer on the substrate of the second region in sequence.
Optionally, forming a receiving hole penetrating the drain layer, the semiconductor material layer, and the source layer through a patterning process includes:
etching the first insulating layer, the source electrode layer, the semiconductor material layer and the drain electrode layer according to the side wall to form a containing hole penetrating through the drain electrode layer, the semiconductor material layer and the source electrode layer;
and performing second partial etching on the semiconductor layer to enable the inner diameter of the semiconductor layer to be larger than that of the drain electrode.
Optionally, a back gate and a capacitor electrode are sequentially formed in the accommodating hole, the capacitor electrode is electrically connected with the reference potential line and insulated from the source electrode, the drain electrode, the main gate and the back gate, and includes:
forming a second gate dielectric layer in the accommodating hole, and etching the second gate dielectric layer at the bottom of the accommodating hole to expose the connecting part;
sequentially depositing a back grid electrode, a capacitance dielectric layer and a capacitance electrode in the accommodating hole, wherein the back grid electrode is contacted with the connecting part and the second grid dielectric layer;
removing part of the back gate positioned between the second gate dielectric layer and the capacitance dielectric layer to form an annular groove, and filling insulating materials in the annular groove to form a fourth insulating layer;
Etching the third insulating layer and the first conductive layer to remove the third insulating layer in an etching region, removing the first conductive layer in the etching region to form the word line, and depositing a fifth insulating layer in the etching region;
forming a reference potential line on the fifth insulating layer by patterning, and backing a sixth insulating layer on the reference potential line, the reference potential line being in contact with the capacitor electrode;
and forming a bit line on the sixth insulating layer through a patterning process, wherein the bit line is electrically connected with the source electrode through a via hole.
In a fourth aspect, an embodiment of the present application provides a method for reading and writing to and from the dynamic memory, where the method includes:
in a writing state, applying a first level to a main gate of a memory cell to be written through the word line to enable a transistor to be on, and transmitting a storage signal to a source of the memory cell to be written through a bit line to write the storage signal into the memory cell to be written as storage data;
in a read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
1) In the dynamic memory, the manufacturing method, the reading method and the memory device thereof provided by the embodiment, the source electrode, the drain electrode, the semiconductor layer, the main grid electrode, the back grid electrode and the like form a transistor, the capacitor electrode and the back grid electrode form a storage capacitor, namely each memory unit comprises a transistor and a storage capacitor, and in the memory unit, the back grid electrode and the source electrode form an auxiliary capacitor, so that the capacitance of the memory unit is increased, the storage node N1 can be maintained for a longer time, and the refresh frequency of the dynamic memory is reduced while the integration level of the dynamic memory is ensured without increasing a film layer.
2) In the dynamic memory, the manufacturing method, the reading method and the storage device thereof provided by the embodiment, in the reading process, when the storage unit is in the 1 state, the bit line can acquire the first node signal, and when the storage unit is in the 0 state, the bit line cannot acquire the first node signal, namely, the difference of data signals read by the bit line in the 1 state or the 0 state is huge, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the '1' or '0' state of the memory unit can be realized only by detecting the output current of the transistor, and the embodiment can utilize current detection and voltage signal detection as no signal is detected in the '0' state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the method has better adaptability.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic partial cross-sectional view of a dynamic memory according to an embodiment of the present application;
fig. 2 is a schematic circuit diagram of a memory cell in a dynamic memory according to an embodiment of the present application;
FIG. 3 is a graph of transfer characteristics of transistors in a dynamic memory when different data is written;
FIG. 4 is a schematic circuit diagram of a dynamic memory according to an embodiment of the present disclosure;
FIG. 5 is a schematic partial cross-sectional view of another embodiment of a dynamic memory;
fig. 6 is a schematic diagram of a frame structure of a storage device according to an embodiment of the present disclosure;
fig. 7 is a flow chart of a method for manufacturing a dynamic memory according to an embodiment of the present application;
fig. 8 is a schematic flow chart of step S1 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a side view process of step S101 in a method for fabricating a dynamic memory according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram illustrating a side view process of step S102 in the method for fabricating a dynamic memory according to the embodiment of the present application;
FIG. 11 is a schematic top view of step S102 in the method for fabricating a DRAM according to the embodiment of the present application;
fig. 12 is a schematic diagram of a side view process of step S103 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 13 is a schematic top view of step S104 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 14 is a schematic flow chart of step S2 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 15 is a schematic side view of the process of step S201 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 16 is a schematic diagram illustrating a side view process of steps S202 to S203 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 17 is a schematic top view of steps S202 to S203 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 18 is a schematic diagram illustrating a side view of step S204 in the method for fabricating a dynamic memory according to the embodiment of the present application;
fig. 19 is a schematic top view of step S204 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 20 is a schematic diagram illustrating a side view of step S3 in the method for fabricating a dynamic memory according to the embodiment of the present application;
fig. 21 is a schematic flow chart of step S4 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 22 is a schematic diagram illustrating a side view of step S401 in the method for fabricating a dynamic memory according to the embodiment of the present application;
FIG. 23 is a schematic diagram illustrating a side view of step S402 in the method for fabricating a dynamic memory according to the embodiment of the present application;
fig. 24 is a schematic top view of step S402 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 25 is a schematic side view of step S403 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 26 is a schematic top view of step S403 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 27 is a schematic diagram illustrating a side view of step S404 in the method for fabricating a dynamic memory according to the embodiment of the present application;
FIG. 28 is a schematic top view of step S404 in the method for fabricating a DRAM according to the embodiment of the present application;
fig. 29 is a schematic side view of the process of step S405 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
Fig. 30 is a schematic top view of step S405 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
FIG. 31 is a schematic diagram illustrating a side view of step S406 in the method for fabricating a dynamic memory according to the embodiment of the present application;
fig. 32 is a schematic top view of step S406 in the method for manufacturing a dynamic memory according to the embodiment of the present application;
fig. 33 is a flow chart of a method for reading and writing a dynamic memory according to an embodiment of the present application.
Reference numerals:
10-a memory cell; a T-transistor; c1-a storage capacitor; c2-auxiliary capacitance; BL-bit lines; WL-word line; vref—a reference potential line;
101-a substrate; 102-a connection; 103-drain electrode; 104-a semiconductor layer; 105-source; 106-a first insulating layer; 107-side walls; 108-a first gate dielectric layer; 109-main gate; 110-a second insulating layer; 111-a first conductive layer; 112-a third insulating layer; 113-a second gate dielectric layer; 114-back gate; 115-a capacitive dielectric layer; 116-capacitive electrodes; 117-a fourth insulating layer; 118-a fifth insulating layer; 119-a second conductive layer; 120-a sixth insulating layer; 121-a third conductive layer; 122-inter-group insulating layers;
100-a first region; 200-second region.
Detailed Description
Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, etc. that may be implemented as desired in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein refers to at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
DRAM memory typically includes a plurality of memory cells each including a transistor therein, which causes a gradual loss of charge stored in the memory cells due to leakage across the active layer, so that the stored data needs to be frequently refreshed to ensure the validity of the stored data. In the current mainstream DRAM, in order to reduce the refresh rate, the conventional design is that the capacitor needs to be large enough, which makes the DRAM not compact in structure and low in integration level.
The dynamic memory, the manufacturing method, the reading method and the storage device thereof aim to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. It should be noted that the following embodiments may be referred to, or combined with each other, and the description will not be repeated for the same terms, similar features, similar implementation steps, and the like in different embodiments.
The embodiment of the present application provides a dynamic memory, as shown in fig. 1 and 2, which includes a substrate 101, a plurality of word lines WL, a plurality of bit lines BL, a plurality of reference bit lines Vref, and a plurality of memory cells 10 on the substrate 101. In the present embodiment, the memory unit 10 includes:
a columnar capacitor electrode 116 located on the substrate 101, the capacitor electrode 116 being electrically connected to the reference potential line Vref;
a back gate 114 located between the capacitor electrode 116 and the substrate 101 and surrounding the capacitor electrode 116, the back gate 114 being insulated from the capacitor electrode 116 and forming a storage capacitor C1 with the capacitor electrode 116;
the drain 103, the semiconductor layer 104 and the source 105 are sequentially stacked on one side of the substrate 101 in a direction away from the substrate 101, the drain 103, the semiconductor layer 104 and the source 105 encircle the capacitor electrode 116 and are positioned on one side of the back gate 114 away from the capacitor electrode 116, the drain 103, the semiconductor layer 104 and the source 105 are annular in cross section parallel to the substrate 101, the drain 105 is electrically connected with the back gate 114, and the back gate 114 and the source 103 form an auxiliary capacitor C2;
a main gate 109 surrounding an outer sidewall of the semiconductor layer 104, the main gate 109 being electrically connected to the word line WL and insulated from the source 103 and the drain 105.
As shown in fig. 1 and 2, the source electrode 105, the drain electrode 103, the semiconductor layer 104, the main gate 109, the back gate 114, and the like constitute one transistor T, the capacitor electrode 116 and the back gate 114 constitute a storage capacitor C1, that is, each memory cell 10 includes one transistor T and one storage capacitor C1, and in this memory cell 10, the back gate 114 and the source electrode 105 constitute one auxiliary capacitor C2, thereby increasing the capacitance of the memory cell 10, enabling the storage node N1 to be maintained for a longer time, thereby reducing the refresh frequency of the dynamic memory without increasing a film layer to secure the integration level of the dynamic memory.
It should be noted that, since the back gate 114 has a back gate effect, that is, the potential of the back gate 114 affects the threshold voltage of the transistor T, the magnitude of the voltage for turning on the transistor T when the stored data is read is between the threshold voltage when the transistor T stores "1" and the threshold voltage when the transistor T stores "0".
Alternatively, as shown in fig. 1, the material of the substrate 101 is a P-type silicon material, the material of the connection portion 102 is an N-type heavily doped silicon material, the material of the drain 103 is an N-type silicon material, the material of the source 105 is an N-type silicon material, and the material of the semiconductor layer 104 is a silicon germanium material.
The connection part 102, the drain electrode 103 and the source electrode 105 are made of doped silicon materials, so that the dynamic memory can be manufactured by using an epitaxial growth method, and the production cost can be reduced.
As shown in fig. 2 and 3, at the time of data writing, when a first level is applied to the main gate 109 through the word line WL, the transistor T is turned on, and a data signal inputted through the bit line BL is written to the first node N1, and when data writing is completed, the transistor T is turned off by adjusting the potential applied to the main gate 109 through the word line WL, and after the transistor T is turned off, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can hold the potential of the first node N1 even though a leakage phenomenon is stored.
As shown in fig. 2 and 3, when the second level is applied to the main gate 109 during data reading, if the memory cell 10 is in the "1" state, the main gate 109 is turned on at the second level (for example, the main gate potential vg=0.3v, and the source potential vs=0 at this time), and the signal of the first node N1 can be obtained; if the memory cell 10 is in the "0" state, the transistor T is not turned on under the same gate and source 105 bias, and therefore the bit line BL does not acquire an electrical signal.
As can be seen from the above description, in the dynamic memory provided in this embodiment, during the reading process, the bit line BL can acquire the signal of the first node N1 when the memory cell 10 is in the "1" state, and the bit line BL cannot acquire the signal of the first node N1 when the memory cell 10 is in the "0" state, that is, the difference between the data signals read by the bit line BL in the "1" or "0" states is large, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the "1" or "0" state of the memory cell 10 can be realized only by detecting the magnitude of the output current of the transistor T, and in this embodiment, the signal can be detected by using the current signal or the voltage signal because the signal cannot be detected in the "0" state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the peripheral detection circuit has better adaptability.
Specifically, as shown in fig. 4, the dynamic memory includes 1 st to nth bit lines BL, 1 st to mth bit lines BL, and 1 st to mth reference bit lines Vref. By inputting the active level to the corresponding word line WL and bit line BL, writing and reading of data can be achieved.
As shown in fig. 5, in the dynamic memory provided in the present embodiment, a plurality of memory cells 10 are divided into a plurality of memory cell groups, and the plurality of memory cell groups are arranged in a direction perpendicular to a substrate 101; each memory cell group includes a plurality of memory cells 10 arranged in an array in a direction parallel to the substrate 101, wherein each memory cell 10 located in the same row is electrically connected to the same word line WL, and each memory cell 10 located in the same column is electrically connected to the same bit line BL. Specifically, the dynamic memory provided in this embodiment further includes an inter-group insulating layer 122, and the inter-group insulating layer 122 covers the bit lines WL in the memory cell group on the lower side.
Specifically, in the implementation process, different arrangement modes can be selected according to specific storage capacity requirements and limitation on the space of the memory, that is, by adjusting the number of the storage unit 10 groups and the number of the storage units 10 in each storage unit 10 group (including adjusting the number of the storage units 10 in each row and/or each column), the optimal design of the storage capacity and the storage space is realized.
Optionally, as shown in fig. 1, in the dynamic memory provided in this embodiment, the memory cell 10 further includes a connection portion 102, where the connection portion 102 is located between the substrate 101 and the drain electrode 103 and between the substrate 101 and the back gate 114, and the connection portion 102 is in direct contact with the drain electrode 103 and simultaneously in contact with the back gate 114, and the material of the connection portion 102 is a conductive material; the area where the orthographic projection of the connection portion 102 on the substrate 101 is located is a first area 100, the area surrounding the first area 100 is a second area 200, and the thickness of the substrate 101 located in the first area 100 is greater than the thickness of the substrate 101 located in the second area 200.
In this embodiment, the second region 200 of the substrate 101 is partially etched, so that the connection portion 102 on the substrate 101 can be sufficiently etched, so that the connection portion 102 in the adjacent memory cell 10 is prevented from being connected by mistake, and the risk of failure is reduced.
Optionally, as shown in fig. 1, in the dynamic memory provided in this embodiment, the memory cell 10 further includes a first insulating layer 106 located on a side of the source 105 away from the substrate 101 and a sidewall 107 located on a side of the first insulating layer 106 away from the substrate 101; the front projections of the side wall 107, the first insulating layer 106, the source electrode 105 and the drain electrode 103 on the substrate 101 are overlapped, the front projection of the semiconductor layer 104 on the substrate 101 is located in the front projection of the drain electrode 103 on the substrate 101, and the front projection of the drain electrode 103 on the substrate 101 is located in the front projection of the connecting portion 102 on the substrate 101.
Specifically, as shown in fig. 1, the sidewall 107, the first insulating layer 106, the source 105, the semiconductor layer 104 and the drain 103 are all ring-shaped, the inner diameter of the semiconductor layer 104 is larger than the inner diameter of the drain, and the outer diameter of the semiconductor layer 104 is smaller than the outer diameter of the drain 103.
Specifically, the sidewall 107 is annular, the inner diameter and the outer diameter of the source 105 and the drain 103 are determined by designing the inner diameter and the outer diameter of the sidewall 107, and the inner diameter and the outer diameter of the channel semiconductor layer 104 can be determined by combining the design of the sidewall 107 with the etching process of the channel semiconductor layer 104, so that the aspect ratio of the channel semiconductor layer 104 is determined, and the transistor T in the memory cell 10 has the required characteristics.
The sidewall 107 is provided in the dynamic memory provided in this embodiment, that is, the sidewall 107 is used as an etching mask for a plurality of film layers such as the source 105 and the drain 103 located below the sidewall 107, so that the manufacturing method is simpler, and the sidewall 107 technology is beneficial to improving the accuracy of the dynamic memory.
Optionally, as shown in fig. 1, in the dynamic memory provided in this embodiment, the main gate 109 is located between the source 105 and the drain 103, the word line WL is made of the same material as the main gate 109 and is in contact with the main gate 109, and the orthographic projection of the word line WL on the substrate 101 is located in the second region 200; the potential reference line Vref is positioned on one side of the capacitance electrode 116 away from the substrate 101 and is in contact with the capacitance electrode 116; the bit line WL is located on a side of the potential reference line Vref away from the substrate 101 and is electrically connected to the source 105 through a via.
Specifically, as shown in fig. 1, the dynamic memory provided in this embodiment further includes a first gate dielectric layer 108. The first gate dielectric layer 108 is located on the outer sidewalls of the connection 102, the drain 103, the semiconductor layer 104, the source 105 and the first insulating layer 106 and on the substrate 101 of the second region 200. The first gate dielectric layer 108 is used to insulate the main gate 109 from the source 105 and drain 103.
Specifically, as shown in fig. 1, the dynamic memory provided in this embodiment further includes a second insulating layer 110, where the second insulating layer 110 is located in the second area and is located on a side of the first gate dielectric layer 108 away from the substrate 101, and the second insulating layer 110 further improves the insulating performance between adjacent memory cells.
Specifically, as shown in fig. 1, the dynamic memory provided in this embodiment further includes a third insulating layer 112, where the third insulating layer 112 is located on a side of the word line WL away from the substrate 101, and the third insulating layer 112 serves to insulate the bit line BL and the potential reference line Vref from the word line 2. During manufacturing, the first metal layer 111 and the second insulating layer 112 are sequentially deposited on the second insulating layer 110, and then in subsequent processing, the second insulating layer 112 and the first metal layer 111 are subjected to patterning processing to form a patterned second insulating layer 112 and a plurality of word lines WL.
Specifically, as shown in fig. 1, the dynamic memory provided in this embodiment further includes a second gate dielectric layer 113 and a capacitance dielectric layer 115. The second gate dielectric layer 113 is located on the inner sidewalls of the connection portion 102, the drain electrode 103, the semiconductor layer 104, the source electrode 105 and the first insulating layer 106, the second gate dielectric layer 113 insulates the back gate 114 from the source electrode 105 and the drain electrode 103, and the second gate dielectric layer 113 serves as a dielectric layer between the source electrode 105 and the back gate 114 so that the source electrode 105 and the back gate 114 form an auxiliary capacitor C2. A capacitive dielectric layer 115 is located between the back gate 114 and the capacitive electrode 116, the capacitive dielectric layer 115 insulates the back gate 114 and the capacitive electrode 116, and the capacitive dielectric layer 115 acts as a dielectric between the back gate 114 and the capacitive electrode 116 such that the back gate 114 and the capacitive electrode 116 form a storage capacitor C1.
Specifically, as shown in fig. 1, the dynamic memory provided in this embodiment further includes a fourth insulating layer 117, a fifth insulating layer 118, and a sixth insulating layer 120. The fourth insulating layer 117 is located between the second gate dielectric layer 113 and the capacitor dielectric layer 115 and on a side of the back gate 114 away from the substrate 101, and serves to insulate the back gate 114 from the potential reference line Vref. The fifth insulating layer 118 fills the potential reference line Vref and the side of the third insulating layer 112, that is, the etched region after patterning the third insulating layer 112 and the first conductive layer 111. The sixth insulating layer 120 is located between the conductive layer (second conductive layer 119) where the potential reference line Vref is located and the conductive layer (third conductive layer 121) where the bit line BL is located.
In the present embodiment, the electrical connection between the word line WL and the main gate 109 is achieved by contacting the word line WL with the main gate 109, and the potential reference line Vref with the capacitor electrode 116, so that not only can the process be simplified, but also the integration level of the dynamic memory can be further improved.
Based on the same inventive concept, the embodiment of the present application provides a storage device, as shown in fig. 6, where the storage device includes the dynamic memory in the foregoing embodiment, and has the beneficial effects of the dynamic memory in the foregoing embodiment, which is not described herein again. Specifically, the storage device in the embodiment of the present application may be a main memory of a computer, and may be specifically determined according to an actual situation.
Based on the same inventive concept, the embodiment of the application provides a method for manufacturing a dynamic memory, as shown in fig. 1 and 7; the manufacturing method provided by the embodiment comprises the following steps:
s1: a substrate is provided, and a drain layer 103a, a semiconductor material layer 104a, and a source layer 105a are sequentially stacked on one side of the substrate by a patterning process, the drain layer 103a, the semiconductor material layer 104a, and the source layer 105a.
Specifically, as shown in fig. 8 to 13, when the memory cell 10 further includes the connection portion 102 and the first insulating layer 106, step S1 includes:
S101: a connection layer 102a, a drain layer 103a, a semiconductor material layer 104a, a source layer 105a, and a first insulating material layer 106a are sequentially grown on the substrate 101 by an epitaxial method.
Specifically, as shown in fig. 9, an N-type heavily doped silicon material is sequentially deposited as a connection layer, an N-type silicon material is deposited as a drain layer 103a, a silicon germanium material is deposited as a semiconductor material layer 104a, and an N-type silicon material is deposited as a source layer 105a on a P-type silicon substrate 101.
S102: a plurality of side walls 107 and sacrificial portions 300 located in the side walls 107 are formed on one side, away from the substrate 101, of the first insulating material layer 106a through a patterning process, wherein the area where the side walls 107 and the sacrificial portions 300 are located is a first area 100, and the area surrounding the first area 100 is a second area 200.
Specifically, as shown in fig. 10 and 11, the inner and outer diameters of the source and drain electrodes are determined by designing the inner and outer diameters of the sidewall 107, and the design of the sidewall 107 in combination with the etching process of the semiconductor layer can determine the inner and outer diameters of the semiconductor layer, thereby determining the aspect ratio of the semiconductor layer, and further enabling the transistor T in the memory cell 10 to have desired characteristics.
S103: the first insulating material layer 106a, the source layer 105a, the semiconductor material layer 104a, and the drain layer 103a are etched according to the sidewalls 107 to form a cylindrical first insulating material layer 106a, the source layer 105a, the semiconductor material layer 104a, and the drain layer 103a, and the substrate 101 in the second region 200 is etched such that the thickness of the substrate 101 in the first region 100 is greater than the thickness of the substrate 101 in the second region 200.
Specifically, as shown in fig. 12 and 13, the second region 200 of the substrate 101 is partially etched, so that the connection portion 102 on the substrate 101 can be sufficiently etched to prevent the connection portion 102 in the adjacent memory cell 10 from being connected by mistake, and the risk of failure can be reduced.
S2: a main gate electrode surrounding the semiconductor layer is formed, the main gate electrode being electrically connected to the word line and insulated from the source and drain layers.
Specifically, as shown in fig. 14 to 20, the memory cell 10 further includes the connection portion 102 and the first insulating layer 106 will be described as an example. At this time, step S2 includes:
s201: the semiconductor material layer 104a is subjected to a first partial etching so that the outer diameter of the semiconductor material layer 104a is smaller than the outer diameter of the drain layer 103 a.
Specifically, as shown in fig. 15, the first partial etching of the outer sidewall of the semiconductor material layer 104a not only can provide a space for the main gate 109 to enhance the integration level of the memory cell 10, but also can implement adjustment of parameters (e.g., aspect ratio) of the semiconductor material layer 104a of the transistor T.
S202: a first gate dielectric layer 108 is deposited on the sidewalls of the connection 102, the drain layer 103a, the semiconductor material layer 104a, the source layer 105a and the first insulating material layer 106a after the first partial etch and on the substrate 101 in the second region 200.
Specifically, as shown in fig. 16 and 17, the first gate dielectric layer 108 is used to insulate the main gate 109 from the source 105 and the drain 103.
S203: a main gate 109 is formed on a side of the first gate dielectric layer 108 away from the semiconductor material layer 104a, and a second insulating layer 110, a first conductive layer 111, and a third insulating layer 112 are sequentially formed on a side of the first gate dielectric layer 108 of the second region 200 away from the substrate 101, the first conductive layer 111 being in contact with the main gate 109.
Specifically, referring to fig. 16 and 17, the main gate 109 is located between the source layer 105a and the drain layer 103a and surrounds the semiconductor material layer 104a. As shown in fig. 18 and 19, the second insulating layer 110 can not only function to further enhance uniformity between adjacent memory cells; the first conductive layer 111 is used for manufacturing a word line WL, the word line is in direct contact with the main gate 111, which is beneficial to improving the integration level of the dynamic memory, and the third insulating layer 112 plays a role in insulating the subsequent conductive layer from the first conductive layer 112.
S3: and forming a containing hole penetrating through the drain electrode layer, the semiconductor material layer and the source electrode layer through a patterning process, wherein the drain electrode layer penetrated by the containing hole forms a drain electrode, the semiconductor material layer penetrated by the containing hole forms a semiconductor layer, and the drain electrode layer penetrated by the containing hole forms a drain electrode.
Specifically, as shown in fig. 20, the memory cell 10 further includes a connection portion 102 and a first insulating layer 106 is still described as an example. At this time, step S3 includes: the first insulating material layer 106a, the source electrode layer 105a, the semiconductor material layer 104a, and the drain electrode layer 103a are etched according to the sidewalls to form accommodating holes penetrating the first insulating material layer 106a, the source electrode layer 105a, the semiconductor material layer 104a, and the drain electrode layer 103a, the first insulating material layer 106a penetrated by the accommodating holes 400 is the first insulating layer 106, the source electrode layer 105a penetrated by the accommodating holes 400 is the source electrode 105, the semiconductor layer 104a penetrated by the accommodating holes 400 is the semiconductor layer 104, and the drain electrode layer 103a penetrated by the accommodating holes 400 is the drain electrode 103.
S4: a back gate 114 and a capacitor electrode 116 are sequentially formed in the accommodating hole 400, the capacitor electrode 116 is electrically connected to the reference potential line Vref and insulated from the source 105, the drain 103, the main gate 109 and the back gate 114, wherein the capacitor electrode 116 and the back gate 114 form a storage capacitor C1, and the back gate 114 and the source 105 form an auxiliary capacitor C2.
Specifically, as shown in fig. 21 to 32, the memory cell 10 further includes the connection portion 102 and the first insulating layer 106 will be described as an example. At this time, step S4 includes:
S401: the semiconductor layer 104 is subjected to a second partial etching so that the inner diameter of the semiconductor layer 104 is larger than the inner diameter of the drain electrode 103.
Specifically, as shown in fig. 21, the inner and outer diameters of the source electrode 105 and the drain electrode 103 are determined by designing the inner and outer diameters of the sidewall 107, and the design of the sidewall 107 in combination with the etching process of the semiconductor layer 104 can determine the inner and outer diameters of the semiconductor layer 104, thereby determining the aspect ratio of the semiconductor layer 104, and further enabling the transistor T in the memory cell 10 to have desired characteristics.
S402: the second gate dielectric layer 113 of the substrate 101 is disposed in the receiving hole 400, and the second gate dielectric layer 113 located at the bottom of the receiving hole 400 is etched to expose the connection portion 102.
Specifically, as shown in fig. 23 and 24, the second gate dielectric layer 113 insulates the back gate 114, which is fabricated later, from the source 105 and the drain 103, and the second gate dielectric layer 113 serves as a dielectric layer between the source 105 and the back gate 114 so that the source 105 and the back gate 114 form an auxiliary capacitor C2. The exposed connection 102 may be in direct contact with a subsequently fabricated back gate 114 to enable electrical connection of the back gate 114 and the drain 103.
S403: a back gate 114, a capacitive dielectric layer 115, and a capacitive electrode 116 are sequentially deposited in the receiving hole 400, the back gate 114 being in contact with the connection portion 102 and the second gate dielectric layer 113.
Specifically, as shown in fig. 25 and 26, the back gate 114 and the capacitor electrode 116 are insulated by the capacitor dielectric layer 115, and the capacitor dielectric layer 115 serves as a dielectric between the back gate 114 and the capacitor electrode 116 so that the back gate 114 and the capacitor electrode 116 constitute a storage capacitor C1.
S404: a portion of the back gate 114 between the second gate dielectric layer 113 and the capacitor dielectric layer 115 is removed to form a ring-shaped recess, and the ring-shaped recess is filled with an insulating material to form a fourth insulating layer 117.
Specifically, as shown in fig. 27 and 28, the fourth insulating layer 117 is used to insulate the reference potential line Vref, which is fabricated later, from the back gate 114.
S405: the third insulating layer 112 and the first conductive layer 111 are etched to remove the third insulating layer 112 of the etched region, and the first conductive layer 111 of the etched region is removed to form a word line WL, and a fifth insulating layer 118 is deposited in the etched region.
Specifically, as shown in fig. 29 and 30, in the manufacturing process, the patterned photoresist layer 500 is first manufactured, and then the patterned photoresist layer 500 is used as a mask for etching to remove the third insulating layer 112 of the etched region, and the first conductive layer 111 of the etched region is removed to form the word line WL.
S406: the reference potential line Vref is formed on the fourth insulating layer 117 by patterning, and the sixth insulating layer 120 of the substrate 101 is formed on the reference potential line Vref, and the reference potential line Vref is in contact with the capacitor electrode 116.
Specifically, as shown in fig. 31 and 32, the second conductive layer 119 is first formed on the fourth insulating layer 117 and etched to obtain the reference potential line Vref. The reference potential line Vref is used to provide a reference potential for the memory cell 10, and the reference potential line Vref is directly contacted with the capacitor electrode 116, which is also beneficial to reducing the film layer and reducing the production cost.
S407: a bit line BL is formed on the sixth insulating layer 120 through a patterning process, and the bit line BL is electrically connected to the source electrode 105 through a via hole.
Specifically, referring to fig. 1, in the specific fabrication, a third conductive layer 121 is formed on the sixth insulating layer 120 and etched to obtain a bit line BL. The source 105, the drain 103, the semiconductor layer 104, the main gate 109, the back gate 114, and the like in the memory cell 10 of the formed dynamic memory constitute one transistor T, the capacitor electrode 116 and the back gate 114 constitute a storage capacitor C1, that is, each memory cell 10 includes one transistor T and one storage capacitor C1, and in this memory cell 10, the back gate 114 and the source 105 constitute one auxiliary capacitor C2, thereby increasing the capacitance of the memory cell 10, enabling the storage node N1 to be maintained for a longer time, thereby reducing the refresh frequency of the dynamic memory while not increasing the film layer to ensure the integration level of the dynamic memory; the epitaxial growth and the side wall 107 technology are adopted for manufacturing, the manufacturing method is simple, and the side wall 107 technology is beneficial to improving the accuracy of the dynamic memory.
Based on the same inventive concept, the embodiments of the present application provide a read-write method for reading and writing the dynamic memory in the above embodiments, as shown in fig. 1 to 5 and 33, where the read-write method includes:
t1: in the writing state, a first level is applied to the main gate 109 of the memory cell 10 to be written through the word line WL to turn on the transistor T, and a storage signal is transmitted to the source 105 of the memory cell 10 to be written through the bit line BL to write the storage signal into the memory cell 10 to be written as storage data.
When the dynamic memory is in the writing operation mode, a first level (for example, 5V, a specific value may be adjusted according to the actual situation) is applied to the main gate 109 through the word line WL, so that the transistor T is in the on state, where the magnitude of the first level is related to factors such as the structure of the transistor T, the material of the active layer in the transistor T, and the like, and may be specifically adjusted according to the actual situation.
As shown in fig. 1 to 4, at the time of data writing, when a first level is applied to the main gate 109 through the word line WL, the transistor T is turned on, and a data signal inputted through the bit line BL is written to the first node N1, and when data writing is completed, the transistor T is turned off by adjusting the potential applied to the main gate 109 through the word line WL, and after the transistor T is turned off, the existence of the storage capacitor C1 and the auxiliary capacitor C2 can hold the potential of the first node N1 even though a leakage phenomenon is stored.
Since the back gate 114 and the source 105 constitute the auxiliary capacitance C2, even if the transistor T is turned to an off state after the data writing is completed, the electric charge stored in the auxiliary capacitance C2 can enable the electric potential of the first node N1 (i.e., the back gate 114, the drain 103, and the second electrode of the storage capacitance C1) to be maintained for a longer time, thereby reducing the refresh frequency.
T2: in the read state, a second level is applied to the main gate 109 of the memory cell 10 to be read through the word line WL so that the bit line BL senses the stored data of the memory cell 10 to be read.
As shown in fig. 1 to 3, when the second level is applied to the main gate 109 during data reading, if the memory cell 10 is in the "1" state, the main gate 109 is turned on at the second level (for example, the main gate potential vg=0.3v, and the source potential vs=0 at this time), and the signal of the first node can be obtained; if the memory cell 10 is in the "0" state, the transistor T is not turned on under the same gate and source bias, i.e., the signal of the first node cannot be detected.
During the read/write process of the dynamic memory, the reference potential is supplied to the reference potential line Vref. In one embodiment, the reference potential is a selected ground level.
The present embodiment provides a reading method, which can adopt either a current detection method or a voltage detection method. For example, when the memory cell 10 has previously stored data "1", the back gate 114 and the drain 103 have a higher potential, and the transistor T is turned on under the combined action of the second level, so that a more significant current can be measured through the bit line BL. When a more significant current is measured, the read data is judged to be "1". When the data "0" is stored in the memory cell 10 before, the transistor T is still in the off state after the second level is applied to the main gate 109, so that it can be considered that the bit line BL does not detect the current, and the read data is judged to be "0".
Note that, the magnitude of the threshold voltage of the transistor T is related to the magnitude of the electric potentials on the back gate 114 and the drain 103, and for an N-type field effect transistor (the carrier is an electron when the transistor is turned on), the higher the electric potentials of the back gate 114 and the drain 103, the smaller the threshold voltage, that is, the smaller the voltage difference between the main gate 109 and the source 105, the transistor T can be turned on; the lower the potential on the back gate 114 and the drain 103, the greater the threshold voltage.
As shown in fig. 3, the abscissa in fig. 3 is the voltage (i.e., the second level) applied to the main gate 109, and the ordinate is the output current of the transistor T. When the second level applied to the main gate 109 is a specific value (indicated by the dotted line in fig. 3), the voltage on the back gate 114 and the drain 103 (i.e., whether the data written by the transistor T is "1" or "0") will significantly differ in the magnitude of the output current of the transistor T (i.e., the current measured through the bit line BL). Reading data from the memory cell 10 can be achieved by detecting the current on the bit line BL, and when the transistor T writes data "1", the output current of the transistor T is larger, so the read data is also "1"; when the data written by the transistor T is "0", the output current of the transistor T is extremely weak, and thus the read data is also "0".
The value of the second level may be determined according to the parameters of the transistor T and the magnitude of the voltage applied to the back gate 114 and the drain 103 when performing a write operation. It should be noted that, the value of the second level needs to be appropriate (between the threshold voltage when the transistor T stores "1" and the threshold voltage when the transistor T stores "0"), otherwise there may be a risk that the transistor T is turned on or off by mistake, which affects the performance of the dynamic memory. Specifically, the most suitable value of the second level may be determined by an experimental or analog method to ensure that the transistor T is correctly turned on or off in different states, so as to improve the reading performance.
As can be seen from the above description, in the dynamic memory provided in this embodiment, during the reading process, the bit line BL can acquire the first node signal when the memory cell 10 is in the "1" state, and the bit line BL cannot acquire the first node signal when the memory cell 10 is in the "0" state, that is, the difference between the data signals read by the bit line BL in the "1" or "0" states is large, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the "1" or "0" state of the memory cell 10 can be realized only by detecting the magnitude of the output current of the transistor T, and in this embodiment, the signal can be detected by using the current signal or the voltage signal because the signal cannot be detected in the "0" state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the peripheral detection circuit has better adaptability.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
1) In the dynamic memory, the manufacturing method, the reading method and the memory device thereof provided by the embodiment, the source electrode, the drain electrode, the semiconductor layer, the main grid electrode, the back grid electrode and the like form a transistor, the capacitor electrode and the back grid electrode form a storage capacitor, namely each memory unit comprises a transistor and a storage capacitor, and in the memory unit, the back grid electrode and the source electrode form an auxiliary capacitor, so that the capacitance of the memory unit is increased, the memory node can be maintained for a longer time, and the refresh frequency of the dynamic memory is reduced while the integration level of the dynamic memory is ensured without increasing a film layer.
2) In the dynamic memory, the manufacturing method, the reading method and the storage device thereof provided by the embodiment, in the reading process, when the storage unit is in the 1 state, the bit line can acquire the first node signal, and when the storage unit is in the 0 state, the bit line cannot acquire the first node signal, namely, the difference of data signals read by the bit line in the 1 state or the 0 state is huge, so that the noise resistance of the dynamic memory is enhanced; compared with the prior art, the judgment of the '1' or '0' state of the memory unit can be realized only by detecting the output current of the transistor, and the embodiment can utilize current detection and voltage signal detection as no signal is detected in the '0' state, so that the peripheral detection circuit is conveniently designed according to specific requirements, and the method has better adaptability.
Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on the exemplary directions or positional relationships shown in the drawings, are for convenience of description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the apparatus or components referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the order in which the steps are performed is not limited to the order indicated by the arrows. In some implementations of embodiments of the present application, the steps in each flow may be performed in other orders as desired, unless explicitly stated herein. Moreover, some or all of the steps in the flowcharts may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of the sub-steps or stages may be executed at the same time, or may be executed at different times, where the execution sequence of the sub-steps or stages may be flexibly configured according to the requirements, which is not limited by the embodiment of the present application.
The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical ideas of the present application are adopted without departing from the technical ideas of the solutions of the present application, and also belong to the protection scope of the embodiments of the present application.

Claims (13)

1. A dynamic memory, comprising:
A substrate, a plurality of word lines, a plurality of bit lines, a reference potential line, and a plurality of memory cells on the substrate, wherein the memory cells comprise:
the capacitor electrode is positioned on the substrate and is columnar, and the capacitor electrode is electrically connected with the reference potential line;
a back gate located between and surrounding the capacitive electrode and the substrate, the back gate being insulated from the capacitive electrode and constituting a storage capacitance with the capacitive electrode;
a drain electrode, a semiconductor layer and a source electrode which are positioned on one side of the substrate and are sequentially stacked in a direction away from the substrate, wherein the drain electrode, the semiconductor layer and the source electrode encircle the capacitor electrode and are positioned on one side of the back gate away from the capacitor electrode, the drain electrode, the semiconductor layer and the source electrode are annular in a section parallel to the substrate, the drain electrode is electrically connected with the back gate, and the back gate and the source electrode form an auxiliary capacitor;
a main gate surrounding an outer sidewall of the semiconductor layer, the main gate being electrically connected with the word line and insulated from the source and the drain.
2. The dynamic memory of claim 1, wherein the memory cell further comprises a connection portion between the substrate and the drain electrode and between the substrate and the back gate electrode, the connection portion being in direct contact with the drain electrode while in contact with the back gate electrode, the connection portion being of a conductive material;
The area where orthographic projection of the connecting part on the substrate is located is a first area, the area surrounding the first area is a second area, and the thickness of the substrate located in the first area is larger than that of the substrate located in the second area.
3. The dynamic memory of claim 2, wherein the memory unit further comprises:
a first insulating layer located at one side of the source electrode away from the substrate;
the side wall is positioned at one side of the first insulating layer away from the substrate;
the side wall, the first insulating layer, the source electrode and the orthographic projection of the drain electrode on the substrate coincide, the orthographic projection of the semiconductor layer on the substrate is positioned in the orthographic projection of the drain electrode on the substrate, and the orthographic projection of the drain electrode on the substrate is positioned in the orthographic projection of the connecting part on the substrate.
4. The dynamic memory of claim 3, wherein the sidewall, the first insulating layer, the source electrode, the semiconductor layer, and the drain electrode are all ring-shaped, an inner diameter of the semiconductor layer is larger than an inner diameter of the drain electrode, and an outer diameter of the semiconductor layer is smaller than an outer diameter of the drain electrode.
5. The dynamic memory of claim 4, wherein,
the main grid electrode is positioned between the source electrode and the drain electrode, the word line is made of the same material as the main grid electrode and is in contact with the main grid electrode, and the orthographic projection of the word line on the substrate is positioned in the second area;
the potential reference line is positioned on one side of the capacitance electrode far away from the substrate and is in contact with the capacitance electrode;
the bit line is located at one side of the potential reference line away from the substrate and is electrically connected with the source electrode through a via hole.
6. The dynamic memory of any one of claims 2-5, wherein the substrate is P-type silicon material, the connection is N-type heavily doped silicon material, the drain is N-type silicon material, the source is N-type silicon material, and the semiconductor layer is silicon germanium material.
7. A memory device comprising the dynamic memory of any one of claims 1-6.
8. A method for manufacturing a dynamic memory, the method comprising:
providing a substrate, and forming a drain electrode layer, a semiconductor material layer and a source electrode layer which are sequentially stacked on one side of the substrate through a patterning process, wherein the drain electrode layer, the semiconductor material layer and the source electrode layer are cylindrical;
Forming a main gate surrounding the semiconductor material layer, the main gate being electrically connected to a word line and insulated from the source and drain layers;
forming a containing hole penetrating through the drain electrode layer, the semiconductor material layer and the source electrode layer through a patterning process, wherein the drain electrode layer penetrated by the containing hole forms a drain electrode, the semiconductor material layer penetrated by the containing hole forms a semiconductor layer, and the source electrode layer penetrated by the containing hole forms a source electrode;
and a back grid electrode and a capacitor electrode are sequentially formed in the accommodating hole, and the capacitor electrode is electrically connected with a reference potential line and is insulated from the source electrode, the drain electrode, the main grid electrode and the back grid electrode, wherein the capacitor electrode and the back grid electrode form a storage capacitor, and the back grid electrode and the source electrode form an auxiliary capacitor.
9. The method of claim 8, wherein the memory cell of the dynamic memory further comprises a connection portion between the substrate and the drain electrode and a first insulating layer on a side of the source electrode layer away from the substrate, the connection portion being in direct contact with the drain electrode and simultaneously in contact with the back gate electrode, the connection portion being made of a conductive material;
Forming a drain layer, a semiconductor material layer and a source layer stacked in sequence on one side of the substrate through a patterning process, comprising:
sequentially growing a connection layer, the drain electrode layer, a semiconductor material layer, a source electrode layer and a first insulating material layer on the substrate through an epitaxial growth method;
forming a plurality of side walls and sacrificial parts in the side walls on one side, far away from the substrate, of the first insulating material layer through a patterning process, wherein the areas where the side walls and the sacrificial parts are located are first areas, and the area surrounding the first areas is a second area;
and etching the first insulating material layer, the source electrode layer, the semiconductor material layer and the drain electrode layer according to the side walls to form a cylindrical first insulating layer, a cylindrical source electrode layer, a cylindrical semiconductor material layer and a cylindrical drain electrode layer, and etching a substrate positioned in a second area to enable the thickness of the substrate positioned in the first area to be larger than that of the substrate positioned in the second area.
10. The method of claim 9, wherein forming a main gate surrounding the semiconductor layer, the main gate electrically connected to the word line and insulated from the source and the drain, comprises:
Performing first partial etching on the semiconductor material layer to enable the outer diameter of the semiconductor material layer to be smaller than that of the drain electrode layer;
depositing a first gate dielectric layer on the connection portion, the drain layer, the semiconductor material layer, the source layer, and the outer sidewalls of the first insulating material layer and the substrate in the second region after the first partial etching;
forming a main grid electrode on one side of the first grid electrode dielectric layer far away from the semiconductor material layer;
and sequentially forming a second insulating layer, a first conductive layer and a third insulating layer on the substrate of the second region, wherein the first conductive layer is in contact with the main grid electrode.
11. The method of claim 10, wherein forming a receiving hole through the drain layer, the semiconductor material layer, and the source layer by a patterning process, comprises:
etching the first insulating layer, the source electrode layer, the semiconductor material layer and the drain electrode layer according to the side wall to form a containing hole penetrating through the drain electrode layer, the semiconductor material layer and the source electrode layer;
and performing second partial etching on the semiconductor layer to enable the inner diameter of the semiconductor layer to be larger than that of the drain electrode.
12. The method of claim 11, wherein forming a back gate and a capacitor electrode in the accommodating hole, the capacitor electrode being electrically connected to the reference potential line and insulated from the source electrode, the drain electrode, the main gate and the back gate, comprises:
forming a second gate dielectric layer in the accommodating hole, and etching the second gate dielectric layer at the bottom of the accommodating hole to expose the connecting part;
sequentially depositing a back grid electrode, a capacitance dielectric layer and a capacitance electrode in the accommodating hole, wherein the back grid electrode is contacted with the connecting part and the second grid dielectric layer;
removing part of the back gate positioned between the second gate dielectric layer and the capacitance dielectric layer to form an annular groove, and filling insulating materials in the annular groove to form a fourth insulating layer;
etching the third insulating layer and the first conductive layer to remove the third insulating layer in an etching region, removing the first conductive layer in the etching region to form the word line, and depositing a fifth insulating layer in the etching region;
forming a reference potential line on the fifth insulating layer by patterning, and backing a sixth insulating layer on the reference potential line, the reference potential line being in contact with the capacitor electrode;
And forming a bit line on the sixth insulating layer through a patterning process, wherein the bit line is electrically connected with the source electrode through a via hole.
13. A method for reading from and writing to the dynamic memory of any one of claims 1-6, the method comprising:
in a writing state, applying a first level to a main gate of a memory cell to be written through the word line to enable a transistor to be on, and transmitting a storage signal to a source of the memory cell to be written through a bit line to write the storage signal into the memory cell to be written as storage data;
in a read state, a second level is applied to the main gate of the memory cell to be read through the word line, so that the bit line senses the stored data of the memory cell to be read.
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