CN113224030B

CN113224030B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN113224030B
Application number: CN202010072770.2A
Authority: CN
Inventors: 金一球
Original assignee: Xia Tai Xin Semiconductor Qing Dao Ltd
Current assignee: Xia Tai Xin Semiconductor Qing Dao Ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2023-05-12
Anticipated expiration: 2040-01-21
Also published as: CN113224030A

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a first fin structure on the substrate and having a bar-shaped planar profile; and a first conductive line structure intersecting the middle region of the first fin structure at a level lower than a topmost surface of the first fin structure.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to providing a control line structure for semiconductor devices such as random access memory (DRAM).

Background

As Integrated Circuits (ICs) develop, the need for higher device densities and operating speeds is a forever pursuit by those skilled in the art. As feature density increases in IC devices, the critical dimensions that various device features are allowed to shrink dramatically. For this reason, advanced lithography techniques (e.g., multiple pattern lithography) or expensive manufacturing equipment (e.g., extreme Ultraviolet (EUV) lithography equipment) are often required, which increases manufacturing costs and process complexity. For example, multiple patterning techniques require multiple photomasks and multiple layers of etch masks to define high density features in a single device layer. However, each photomask incurs additional costs and additional reliability risks due to alignment/overlay challenges.

Disclosure of Invention

According to an embodiment, an aspect of the present disclosure provides a semiconductor device, including: a first fin structure on the substrate and having a bar-shaped planar profile; and a first conductive line structure intersecting the middle region of the first fin structure at a level lower than a topmost surface of the first fin structure.

According to an embodiment, an aspect of the present disclosure provides a semiconductor device, including: a first active region over the substrate; and a first bit line structure intersecting the first active region at a level lower than a topmost surface of the first active region, the first bit line structure including a barrier liner having a U-shaped profile in a width direction thereof and being in electrical contact with the first active region.

According to an embodiment, an aspect of the present disclosure provides a method of manufacturing a semiconductor device, including: forming a plurality of fin structures on a substrate, wherein each fin structure has a strip-shaped plane contour; disposing a dielectric material between and over the fin structures; patterning the dielectric material to form bit line trenches side-by-side with each other over the fin structures, wherein each of the bit line trenches obliquely intercepts a respective middle region of a row of the fin structures, the bit line trenches exposing the entire width of the middle region and edge portions (edge portions) of end regions (end regions) of the fin structures; recessing edge portions of the middle and end regions of the fin structure, thereby lowering a top surface of the middle region and creating a notch at the edge portions of the end regions; forming a spacer structure on a sidewall surface of the bit line trench, the spacer structure filling a gap at an edge portion of an end region; conformally forming a buffer liner on the exposed surfaces of the spacer structures and the intermediate regions of the fin structures; and disposing a metal material on the buffer liner layer and filling the bit line trench to form a bit line structure.

Drawings

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

Fig. 1 illustrates a region cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 2 illustrates an isometric view of an active area arrangement of a semiconductor device, according to some embodiments of the present disclosure.

Fig. 3 illustrates a schematic plan view of an active region arrangement of a semiconductor device according to some embodiments of the present disclosure.

Fig. 4 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

Fig. 5 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

Fig. 6 illustrates a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

Fig. 7 illustrates a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

Fig. 8 illustrates a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

Fig. 9 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Description of the main reference signs

Detailed Description

The invention will be further described in the following detailed description in conjunction with the above-described figures.

The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used herein, "comprises" and/or "comprising" or "includes" and/or "including" or "having" and/or "has", integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Furthermore, unless the context clearly defines otherwise, terms such as those defined in a general dictionary should be interpreted as having meanings consistent with their meanings in the relevant art and the present disclosure, and should not be interpreted as idealized or overly formal meanings.

An exemplary embodiment will be described below with reference to fig. 1 to 9. The detailed description will be described in detail with reference to the drawings, wherein the depicted elements are not necessarily shown to scale. The same or similar elements will be given the same or similar reference numerals or similar technical terms.

Fig. 1 illustrates a region cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. The exemplary device includes a substrate 100 on which is formed a plurality of layers of integrated circuit devices and features. For simplicity and clarity of illustration, some details/sub-components of the exemplary device are not explicitly labeled in the present figures.

The substrate 100 may include a crystalline silicon substrate (crystalline silicon substrate). According to design requirements, the substrateVarious doped regions (e.g., p-type substrate or n-type substrate) may be included. The doped region may be doped with a p-type dopant, such as boron or BF ₂ The method comprises the steps of carrying out a first treatment on the surface of the The dopant may be, for example, boron. n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. In some alternative embodiments, the substrate 100 may be made of other suitable elemental semiconductors, such as diamond or germanium; such as diamond or germanium. Suitable compound semiconductor materials, such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, siGeSn, gaAsP, alInAs, alGaAs, gaInAs, gaInP and GaInAsP. Other suitable materials; or a combination thereof. Further, although bulk substrates are utilized in the present illustrative example, in some embodiments, the substrates may include epitaxial layers (epi-layers) and/or may include semiconductor-on-insulator structures, such as silicon-on-insulator (silicon-insulator (SOI)), siGe-on-insulator (SiGeOI), ge-on-insulator (GeOI) structures, and the like.

The plurality of functional areas may be arranged laterally over the substrate (e.g., horizontally on the page as shown in fig. 1). For example, fig. 1 shows a substrate of an exemplary device that includes two co-planar arranged functional regions defined thereon, e.g., a cell region 110 and a peripheral region 120. In the example shown, the cell region 110 provides space to accommodate active circuit components (e.g., select transistors 130) and passive circuit components (e.g., storage components such as capacitors 116) of a dynamic random access memory (dynamic random access memory (DRAM)) device. Meanwhile, the peripheral region 120 accommodates circuit components for supporting various functions of the DRAM operation, such as a readout circuit, a decoder circuit, and an amplifier circuit. Based on different design rules, different functional areas may include circuit components of different critical dimensions (critical dimensions). Devices in different functional areas may be designed to operate under different operating requirements (e.g., different voltage ranges). Devices having different feature sizes may be arranged on the same plane of a substrate (e.g., a circuit chip) to achieve higher integration, thereby reducing signal paths and enhancing device performance.

The cell region may include an array of memory cells. Each memory cell typically includes a bit (bit) storage element (e.g., storage capacitor 116) and a select element (e.g., having transistor gate structure 130). The unit cells may employ a suitable cell architecture, such as a 1-T cell format (as shown in this example) or other types of cell arrangements (such as a 3T cell layout, not shown). The cell region 110 of the illustrated device has a gate structure 130 that spans (is buried) below the top surface of a plurality of active regions (e.g., fin structures 112) that are located between isolation features 111 (e.g., shallow trench isolation structures).

In some embodiments, the Active Area (AA) may be a raised (relative to the lower surface of the substrate) island structure that includes an elongated stripe-shaped top-down profile and is surrounded by isolation structures (e.g., STI 111). In some embodiments, the active region 112 may be disposed obliquely at an oblique angle with respect to the direction of travel of the word line (e.g., the direction of extension of the gate structure 130, which in the illustrated example is toward in/out of the page). For example, as shown in fig. 2, 3, the illustrated portion of the exemplary substrate 200 illustrates three raised fin-like features (e.g., raised portions 212 a) that extend away from one lower active surface 212b (e.g., the x-y plane) along a vertical direction (e.g., the z-axis). Depending on the dimensions of the critical dimensions, in some embodiments, the lower surface 200b of the substrate 200 may not be as flat as shown in the schematic diagram of the present figure. For example, in some embodiments where the active window distance is small, the lower surface of the substrate may have a parabolic profile.

Referring also to fig. 2, a plurality of active regions (e.g., 212 a) are surrounded by a dielectric material (e.g., STI 211). In some embodiments, each active region 212a has an elongated profile defining a long axis (e.g., A-A') and is disposed obliquely with respect to the x/y axis. The oblique arrangement of stacked/offset layout (folded/offset layout) between active regions may allow more unit cells to be packaged in the same area while maintaining a sufficient distance between them, thereby achieving higher device density while reducing inter-cell interference (e.g., cross-talk).

The gate structure 130 may be part of a memory cell selection device, such as a buried channel array transistor (buried channel array transistor, BCAT). In the illustrated example, the active region (defined between a pair of isolation features 111) includes a pair of gate structures 112 (corresponding to a pair of BCATs with respective source/drain (S/D) region connections to contact plugs, such as contact plugs/vias 114), with the pair of gate structures 130 buried under the active region (e.g., extending across the page).

The embedded gate structure 130 and the semiconductor region of the active region collectively define a pair of BCAT (their respective source/drain (S/D) regions connected to contact plugs, such as contact plug/via 114). The contact plug 114 enables electrical connection (e.g., via a disk not specifically labeled) between the select transistor (e.g., BCAT) and a lower electrode (e.g., 116L) of the storage capacitor 116.

The gate structure 130 of the exemplary buried device may include an embedded structure (in its cross-sectional profile) disposed/filled in the gate trench in the active region. In DRAM applications, gate structure 130 may be a laterally traveling linear structure (e.g., as shown in fig. 2 and 3) that intercepts multiple adjacent active regions (as shown in fig. 1) and serves as a Word Line (WL) for the memory device.

In the illustrated embodiment, several bit line (bit line) stacked features 140 are formed on the cell region 110 a. In practice, the bit line stack feature 140 may be a laterally extending linear structure (e.g., extending into/out of the page of FIG. 1) that projectively intercepts a plurality of word lines (e.g., word line 130). Each bit line stack feature 140 includes a bit line contact plug 141, a bit line conductor 142, and a bit line mask pattern 143. The bit line conductor 142 is a part of a memory cell selection device electrically connected to the active region 112a serving as a source of the selection device through the bit line contact plug 141. The bit line contact plug 141 may be part of a vertical interconnect and made of a conductive material such as metal or doped polysilicon. The bit line conductors 142 may be part of a lateral interconnect element and include a conductive material such as tungsten.

To ensure structural integrity and electrical isolation between adjacent components, bit line spacers 144 made of dielectric material are provided over the sidewalls of the bit line stack features 140. In some embodiments, the bit line spacers 144 comprise a composite structure composed of a plurality of sublayers. In some embodiments, portions of the bit line spacers 144 may extend down into the isolation structures (e.g., STI 111) and contact corner regions of the active area (e.g., AA 112). In some embodiments, the bit line spacers 144 may be made of a low-K material to mitigate parasitic capacitance. In some embodiments, an air gap/void may be incorporated between the bit line spacers to further reduce cross-talk effects.

The gate structure 130 includes a gate electrode embedded in a lower portion (e.g., partially filled) of the gate trench in the active region (a more complete buried gate structure is shown in fig. 5 (d)). The gate electrode may comprise one or more conductive materials, such as doped polysilicon, or metallic materials, such as tungsten, ruthenium, and cobalt. The gate structure 130 also includes a gate insulating liner lining the bottom of the trench and disposed between the gate electrode and the semiconductor material of the active region.

Buried transistors are suitable candidates as selection devices due to their extended channel length. The extended channel length is, for example, from one S/D region under the contact plug 114 longitudinally down to the bottom tip of the gate structure 130, then laterally across the tip of the buried gate electrode and back up to an opposite S/D region under the adjacent contact plug. Thereby achieving higher device density while mitigating the attendant short channel effects.

The gate insulating liner may be a conformally formed insulating layer covering the inner sidewalls of the gate trench. The gate insulating liner may be made of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or metal oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, or titanium oxide. The high-K dielectric material may be used to complement the metal-based gate electrode to enhance the performance of the field effect transistor. In some embodiments, the gate structure 130 may further include a barrier liner conformally disposed between the gate insulating liner and the gate electrode. The gate barrier liner may include a barrier metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN).

In the illustrated embodiment, a shared S/D region is defined between a pair of adjacent gate structures 130 in the active region (between STI structures 111) (e.g., may be better visualized by region "D" of fig. 2). In some embodiments, the bit lines 113 are arranged on shared S/D regions formed at the central region of the active region between the gate structures 130 (between the STI structures 111). The bit lines 140 are electrically connected to S/D regions of respective central regions of the plurality of active regions (e.g., respective S/D regions of the plurality of active regions arranged in a column; not shown in the current cross-sectional view of the region).

The contact plugs 114 may be formed on and through a dielectric layer (e.g., interlayer dielectric, interlayer dielectric, ILD) on the active area, thereby establishing a longitudinal conductive path from the surface of the substrate 100 to the upper layers of the device stack on the active area. In some embodiments, the contact plugs 114 may be used as storage node via plugs capable of making a longitudinal electrical connection with a lower electrode of a storage component (e.g., electrode 116L of the capacitor component 116). The interlayer dielectric layer may be made of a material such as an oxide or nitride of silicon. In some embodiments, the dielectric layer may comprise a low K material having a dielectric constant below, for example, 3.9. The contact plugs 114 may be made of one or more metallic or non-metallic conductive materials, such as polysilicon, tungsten, aluminum, and the like.

A storage element (e.g., storage capacitor 116) may be formed over storage node contact plug 114 in dielectric layer 117 (e.g., over a corresponding contact pad over the plug), the bottom end of the storage element being electrically connected to a portion of the active region. The storage capacitor 116 includes a lower electrode 116L, an upper electrode 116U, and a capacitor dielectric 116D disposed between the upper and lower electrodes.

An isolation layer (e.g., layer 115) may be disposed on the contact plug 114, through which a lower electrode (e.g., bottom electrode 116L) of the storage capacitor 116 passes to establish electrical connection with the contact plug 14. The isolation layer may comprise a nitride material (e.g., silicon nitride) and serve as an etch stop layer during the fabrication of the capacitor structure. Note that for ease of reference, the term "lower" electrode is relative to the surface of the substrate and should not be construed as unduly limiting the orientation of the device. The contact plugs 14 provide a longitudinal conduction path between the source/drain regions of the select devices (e.g., transistor 130) and the lower electrode (e.g., electrode 116L) of the memory component.

In some embodiments, the lower electrode 116L may be a cylindrical conductive structure having a high aspect ratio (i.e., a high depth to width ratio) that corresponds to a high upwardly open U-shaped cross-sectional profile (as shown in this example). In some embodiments, the lateral width of the conductive structure may be on the scale of tens of nanometers (nm), for example, having a critical dimension of about 40 nm. In some embodiments, the aspect ratio of the lower electrode 116L may be in the range of about 10 to 40. The lower electrode 116L may form a self-conformal conductive film that may be formed of one or more conductive materials such as BSRO ((Ba, sr) (RuO) ₃ )，CRO(CaRuO ₃ )，LSCo((La，Sr)CoO ₃ )，TiN，TiAlN，TaN，TaAlN，W，WN，Ru，RuO ₂ ，SrRuO ₃ ，Ir，IrO ₂ ，Pt，PtO，SRO(SrRuO ₃ ) Is prepared.

The capacitor dielectric 116D may be a conformally formed layer comprising nitride, oxide, metal oxide, or a combination thereof. For example, the capacitor dielectric 116D may include a material selected from the group consisting of silicon nitride, silicon oxide, metal oxide (e.g., hfO ₂ ,ZrO ₂ ,Al ₂ O ₃ ,La ₂ O ₃ ,Ta ₂ O ₃ And TiO ₂ ) Perovskite dielectric materials (e.g., STO (SrTiO ₃ ),BST((Ba,Sr)TiO ₃ ),BaTiO ₃ PZT, and PLZT or a combination thereof). In some embodiments, high-K dielectric materials may be used to enhance the performance of the capacitor, e.g., to enhance the capacitance of the capacitor at a given electrode surface area.

Upper electrode 116U may beTo be formed of one or more conductive materials such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof. For example, the upper electrode 116U may be made of a material including BSRO ((Ba, sr) RuO) ₃ ),CRO(CaRuO ₃ ),LSCo((La,Sr)CoO ₃ ),TiN,TiAlN,TaN,TaAlN,W,WN,Ru,RuO ₂ ,SrRuO ₃ ,Ir,IrO ₂ ,Pt,PtO,SRO(SrRuO ₃ ) Although a list of suitable materials is merely exemplary and not exhaustive.

Additional conductive features, such as interconnect features 118 and 119, may be formed on additional intermetal dielectric layers over upper electrode 116U to enable interconnection between circuit components.

As device integration increases, feature density increases. For example, in modern semiconductor devices, feature density between interconnect features (e.g., planar interconnect components such as features 118/119/129, or vertical interconnect components such as features 114/124/126/128) has increased substantially. Thus, not only does its feature size decrease, but the feature pitch/spacing also decreases.

The reduction of the pitch between the vertical interconnect components (e.g., contact plugs 141 or storage node contacts 114) typically requires advanced manufacturing techniques (e.g., multiple pattern lithography) or expensive manufacturing equipment (e.g., extreme Ultraviolet (EUV) lithography equipment), which can increase manufacturing costs and complexity. For example, various patterning techniques require the use of multiple photomasks (and multi-layer hard/soft masks) to define a large number of closely spaced contact features (e.g., longitudinal contact plugs 141/114). Each photomask incurs additional costs and additional reliability risks arising from alignment/overlay challenges. In addition, densely packed interconnect patterns in the inter-metal dielectric layer often lead to adverse cross-talk effects.

In some embodiments, voids (e.g., air gaps) may be incorporated between interconnect features to mitigate the adverse effects described above. Since air has a very low dielectric constant (about 1.00000), voids in the structure can provide equivalent dielectric constants as low as about 1.00059. Thus, the dielectric constant of the porous structure may be significantly lower than conventional intermetal dielectrics. In this embodiment, an air gap is created between adjacent conductive features to provide a reduced area dielectric constant. In general, the maximized air gap size and uniform air gap profile (e.g., the same gap width and height) may enhance the cross-talk reduction effect under allowable process conditions.

It is noted that the term "air gap" generally refers to the absence of material filling in a particular region (thereby forming a structure with voids), and does not necessarily imply a gaseous content therein. In some embodiments, the voids between the interconnect features may be substantially filled with one or more inert gases, such as gaseous argon or nitrogen. In some embodiments, the voids (air gaps) between the interconnect features may be substantially vacuum.

The peripheral region 110b may include various active device regions laterally separated by isolation features (e.g., STI 121). Active region 112b may include active circuit components (e.g., transistor gate structure 180) that constitute peripheral support circuitry, such as readout, decoder, or amplifier circuitry. The gate structure 180 may include a gate dielectric 181, a gate material 182 on the gate dielectric 181, and a gate capping material 183 on the gate material 182. The conductive material 182 may include tungsten.

On the active area there may be an upper inter-device layer, such as a dielectric layer 127, contact vias/plugs 124 may be provided through the dielectric layer 127 to enable longitudinal signal conduction from the surface of the substrate 100 to higher device layers. The contact plugs 124 may be connected to corresponding contact pads (not specifically labeled) thereabove in a similar manner as in the cell region 110 a.

Above the contact plug 124 of the presently illustrated embodiment is a dielectric layer 127, through which dielectric layer 127 one or more high aspect ratio interconnect features (e.g., contact vias 126) are formed. In some embodiments, the aspect ratio of the contact via 126 may have a range from about 10 to about 40. In some embodiments, the design rules of the devices in peripheral region 120 may assume a larger feature size than the devices in cell region 110 a. In some embodiments, the active circuit components in the peripheral region 110b are designed to operate at a higher operating voltage than the cell region 110 a.

The high aspect ratio features in both the cell region 110a and the peripheral region 110b are typically formed in a top-down fashion, such as etching. The etching of the high aspect ratio features is typically performed through one or more relatively thick device layers (e.g., 127). In some embodiments, special process arrangements and techniques may be utilized to produce high aspect ratio features having a lateral/sidewall profile that is substantially perpendicular relative to the major surface of the substrate.

Reference is made to fig. 2 and 3. Fig. 2 illustrates an isometric view of an active area arrangement of a semiconductor device, according to some embodiments of the present disclosure. Fig. 3 illustrates a plan view of an active region arrangement of a semiconductor device according to some embodiments of the present disclosure.

In the illustrated cross-sectional view, the illustrated portion of the substrate 200 defines a lower surface (e.g., 212 b) and columns (e.g., 3 columns in the illustrated example) of a plurality of fin-like features (e.g., 212 a) protruding from the lower substrate surface 212b generally along the z-axis direction. The fin feature 212a embedded in (and surrounded by) an insulating material (e.g., 211/311) may be made of a semiconductor material, for example, by a top-down method such as etching or a bottom-up method such as epitaxial formation (epitaxial formation).

In the illustrated embodiment, the circular planar outline (rounded planar contour) of the active regions (e.g., the area with the "S" tag) in the exposed x-y plane represents the end portion of one of the many active regions 212a arranged in a column. By way of example, the portion shown in fig. 2 includes three columns of active regions extending alongside one another. Moreover, each column includes two rows of active areas arranged in a laterally offset configuration. For example, as shown in fig. 2 and 3, the active region of each column of fin-like features has a stripe-shaped profile that spans a first end region (labeled "S"), a first control line intersection region (e.g., via control line 230), a middle region (labeled "D"), a second control line intersection region, and terminates at a second end region (labeled "S"). In addition, the lateral misalignment configuration may be observed by the arrangement of the first end region "S" of one active region aligned in the lateral direction (e.g., along the x-direction) with the intermediate region of an adjacent active region of an adjacent column.

Each control line structure 230 (shown extending along the x-axis direction in the present example) may intersect multiple rows of active regions and act as a shared gate line structure. For example, the control line structure 230 may be used as a word line of a memory device. As shown in fig. 2 and 3, each active region 212a is intersected by two control line structures 230. The two control lines 230 intersecting the active area intersection correspond to the gates of a pair of BCATs, with the area between the control lines 230 defining a shared drain area. The rounded ends of the active region define a plurality of source regions "S" of the transistor, respectively. In the example shown, each active region (e.g., 212 a) defines a longitudinal axis (e.g., a cross-section A1) that is disposed obliquely at an oblique angle (e.g., angle θ shown in fig. 3) with respect to the x-axis.

In the top layout view of fig. 3, a plurality of bit lines (e.g., 340-1,340-2, etc.) extending in the x-direction are disposed on active region 312a and projectively intersect a central region of active region 312a (e.g., the "D" region between a pair of intersecting control lines 330). In the current embodiment, a bit line contact (e.g., contact 340 represented by a dark shaded dot) is provided between the central region "D" of active region 312a and the corresponding bit line (e.g., 340-2) to establish an electrical connection therebetween. On the other hand, the slanted arrangement of the active region 312a allows the "S" regions at each end thereof to be projectively offset from the bit line coverage (i.e., the "S" regions of the active region 312a are at least partially exposed from the planar coverage portions of the intersecting bit lines), thereby allowing storage node contacts (e.g., contacts 314, represented by light-shaded dots) to be formed at planar locations between the grid-like patterns (i.e., defined by the projectively truncated plurality of control lines 330 and the plurality of bit lines 313) without shorting.

A storage component (e.g., storage capacitor 116 shown in fig. 1) may then be formed over storage node contact 314. In some embodiments employing a bit line width of about 20nm, the tilt angle θ may be set to about 65 to 75 degrees. In some embodiments, the tilt angle θ may be arranged at about 69 degrees (relative to the y-axis). Thus, a compact layout that enables higher feature densities can be achieved while maintaining sufficient device spacing to keep the interference problem within acceptable levels.

Fig. 4 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure. In one aspect, the cross-sectional views (a) - (e) of fig. 4 illustrate cross-sections taken at various stages of an exemplary active region formation process, the cross-sections (e.g., taken along cut line S1 shown in fig. 3) being substantially perpendicular to the long axis of the active region.

Referring to fig. 4 (a), a patterned mask layer 401 is provided over an active surface of a substrate 400. The etch mask 401 may include a multi-layered stacked structure including, for example, a disk (pad) oxide layer on an active area, a first hard mask layer including silicon nitride, and a second hard mask layer made of silicon, spin-on hard mask (SOH), amorphous carbon layer (Amorphous carbon layer, ACL), etc. In the illustrated embodiment, a stripe pattern (e.g., corresponding to the planar profile shown in fig. 3) is formed in the etch mask layer 401.

Referring to fig. 4 (b), an etching operation is performed through the patterned mask layer 401 to form a plurality of raised structures of semiconductor material (e.g., fins 412 a) over the active surface of the substrate 400.

Referring to fig. 4 (c), a dielectric material (e.g., oxide) is disposed on the active surface of the substrate 400 and fills the gaps between adjacent fin structures 412a to form isolation structures (e.g., STI 411). A planarization process (e.g., CMP) may then be performed on the dielectric material until the second hard mask layer is exposed (resulting in a reduced mask layer 401'). In some embodiments, the flowable dielectric material is applied by spin-coating techniques to ensure effective step coverage and to achieve proper gap filling between the protruding structures.

Referring to fig. 4 (d), a mask lift-off process is performed to remove at least a portion of the mask layer in preparation for junction engineering (junction engineering). The lift-off process may employ a suitable dry or wet etching technique to remove the mask pattern and expose one of the topmost surfaces U of the active regions 412 a. In some embodiments, a portion of the mask layer stack (e.g., the disk oxide layer) may remain over the fin structure (or in a different cut line, such as shown in the cross-section of fig. 5 (a)). A doping process, such as ion implantation, may then be performed to tailor the electrical properties of the active region for subsequent transistor formation.

Referring to fig. 4 (e), a post-strip fill process is performed in which a dielectric material 403 (e.g., oxide) is disposed on the active region 412a to fill the gaps previously occupied by the mask layer. A dry etch back or oxide CMP process may then be performed to planarize the STI structures and the top surface of the fill material 403.

Fig. 5 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure. In one aspect, the cross-sectional views (a) - (d) of fig. 5 show cross-sections taken at various stages of an exemplary buried gate line formation process, the cross-sections (e.g., taken along cut line A1 shown in fig. 3) being substantially perpendicular to the long axis of the active region 512 a.

Referring to fig. 5 (a), a parallel extending linear pattern 503' (e.g., substantially parallel lines 330-1 through 330-4 extending in the y-axis direction as shown in fig. 3) is formed in the hard mask layer 501 on the active surface of the substrate and in the disk dielectric layer 503 over a plurality of raised structures of semiconductor material (e.g., fins 512 a). From a planar (top view) perspective, the linear pattern 503' intercepts the fin structure obliquely at an oblique angle (e.g., angle θ as shown in fig. 3). In the illustrated cross-section, the mask layer (layers 501, 503) covers the top surface of fin structure 512a at the middle region M and ends E1, E2 of fin structure 512 a. Meanwhile, the pattern opening 530' exposes the top boundary U of the active region 512a at two positions between the mask patterns (e.g., corresponding to a pair of "G" regions as shown in fig. 3).

Referring to fig. 5 (b), an etching operation is performed through the mask pattern (layers 501, 503) to generate a trench pattern WL. The trench pattern WL may include a plurality of linear trench features extending side-by-side, as shown, which extend both in-page and out-of-page. The trench pattern WL may then be filled to form a parallel extending word line structure that extends through (and partially embeds) the array of active regions (e.g., fins 512 a).

Referring to fig. 5 (c), a dielectric layer 532 is provided to line the exposed bottom trench surface in the active region 512a, followed by a conductor deposition process to form a conductive feature 534, the conductive feature 534 being embedded at the bottom of the trench in the active region 512 a. The illustrated portions of dielectric layer 532 and conductive feature 534 may pertain to a gate line structure that extends laterally over the substrate (e.g., in the y-axis direction shown in fig. 3) and serves as a gate dielectric layer and a gate electrode.

In some embodiments, the dielectric layer 532 may be provided by techniques such as atomic layer deposition (atomic layer deposition, ALD). In some embodiments, the dielectric layer not only electrically isolates the conductive feature 534 from the semiconductor material of the active region 512a, but also extends vertically upward and to the upper surface (e.g., top boundary U) of the active region 512 a. In some embodiments, the buried gate conductor feature (e.g., feature 534) may be formed by a conductor deposition process that substantially fills the trench pattern WL with a conductive material, followed by an etch back process to recess the top boundary of the gate conductor to a height below the top boundary U of the active region 512 a. As shown in the current cross-section, portions of the trench pattern WL also traverse the isolation structures 511 and intercept other adjacent active areas that are not observable from the current view.

Referring to fig. 5 (d), a capping layer 536 is formed over the conductive member 534 and fills the trench pattern WL. The material of capping layer 536 may provide protection for the gate conductor (e.g., feature 534) in subsequent processes. In some embodiments, capping layer 536 comprises a nitride-containing material. The stack of layer 532, conductor 534, and capping layer 536 collectively form gate line structure 530.

The gate line structure 530 may be used as a word line for an array of buried transistors in a memory device. Buried transistors (e.g., BCAT) have become suitable candidates for high density switching devices due to their extended channel length (e.g., starting from the source region of E1, going vertically down to the bottom tip of the gate trench under conductive feature 534, then laterally crossing the tip of the buried gate electrode (e.g., feature 534), and returning to the drain region at M). Buried transistors (e.g., BCAT) achieve higher device density while mitigating the concomitant short channel effects.

Fig. 6 shows a schematic cross-sectional view of an intermediate structure from different cut lines at various stages of a fabrication process according to some embodiments of the present disclosure. In particular, fig. 6 shows different views taken from various cut lines during an exemplary bitline trench formation process. In one aspect, cross-sectional views (a 1) through (a 3) of fig. 1 show cross-sections substantially across three different locations (e.g., second end E2, middle portion M, and first end E1) of three adjacent active regions (e.g., fins 612-1, 612-2, and 612-3). As shown by cut line Y1 in fig. 3. On the other hand, the cross-sectional views (b 1) - (b 3) of fig. 3 show cross-sections taken substantially along the word line structure (e.g., gate line 330-3 as previously shown), as indicated by cut line Y2 in fig. 3. Meanwhile, the cross-sectional view (c 3) of fig. 6 shows a cross-section taken substantially along the conductive line structure (e.g., bit line 340-2 as previously shown), as shown by cut line X1 in fig. 3.

As shown in fig. 6 (a 1), a cross-section (with a slight tilt angle) of three active regions (e.g., fin structures 612-1, 612-2, and 612-3) can be seen from the current cross-sectional view. The active regions (612-1, 612-2, 612-3) are surrounded by dielectric material of an isolation structure (e.g., STI 611) whose top boundary is at a higher level than the top surface of the fin structure. A dielectric fill material 603 is disposed over the top surfaces of the fins (612-1, 612-2, 612-3) and defines a top boundary that is substantially coplanar with the top boundary of the STI 611.

An etch mask 607 is disposed over the dielectric material over the fin structures 612-1, 612-2, 612-3 and patterned to form a plurality of bit line openings 640' in preparation for a bit line trench etch process.

The bit line openings 640' may include a linear pattern of side-by-side extensions separated by regular planar intervals (e.g., by a pitch p). For example, the bit line openings (e.g., as shown by linear features 340-1 through 340-4 in FIG. 3) may be a series of parallel line patterns extending in the x-axis direction that are substantially perpendicular to the word line structures (e.g., linear features 330-1-330-4 as shown in FIG. 3). In addition, the bit line openings intercept a row of active regions (e.g., 312 a) at an acute angle. The bit line openings may projectively expose intermediate regions (e.g., 340) of multiple active regions in the same lateral row (row) (while the patterned etch mask 607 would cover a majority of each end of the active regions).

Please refer to fig. 6 (b 1) at the same time. Meanwhile, from the illustrated sectional view (e.g., the cutting line Y2 as illustrated in fig. 3), the stacked structure of the gate line 630 may be observed. For example, gate conductor feature 634 and gate capping feature 636 are shown traversing the root of fin structures 612-2, 612-3 (e.g., through the location of active region 612-2 between the middle region and the end regions). The thinner gate dielectric layer is omitted from this figure for clarity of illustration. From the current view, it can be seen that a patterned etch mask 607 and bit line openings 640' are provided on top of the gate cap features 636.

Referring to fig. 6 (a 2), a bit line trench formation process is performed in which an etching operation is performed through a bit line opening (e.g., defined in a patterned etch mask 607). As a result, dielectric material (e.g., oxide) over a particular portion of the active region is removed, and bit line trenches (e.g., trenches 640-1",640-2",640-3", each having a substantial depth" a ") are formed over the fin structures (e.g., 612-1, 612-2, 612-3). As previously described, each bit line trench 640' intercepts a row of fin structures (e.g., 612-2) obliquely at a middle region of the fin structures (as shown in FIG. 3). Further, due to the oblique intersection angle, the bit line trench 640' exposes the entire width of the middle region (e.g., width "w" in fig. 6 (a 2)) and edge portions of the end regions (e.g., outer edge e 1) of the fin structure, as indicated by the dashed circles in fig. 3 and 6 (a 2).

Referring also to fig. 6 (b 2), the bit line trenches (e.g., trenches 640-2", 640-3") extend further into cross section Y2 and intersect in plan with the upper portion (e.g., upper cap 636) of word line structure 630. Due to the differences in materials (e.g., nitride-based materials) and the concomitant etch selectivity, the bit line trench (e.g., 640-3 ") defines a shallower trench depth" b "at the section intersecting the word line (as compared to the trench depth" a "at the intersection with the active region).

Fig. 6 (c 3) shows a cross-sectional view along the bit line structure (e.g., cut line X1 along linear feature 340-2 shown in fig. 3). In the current cross-section, it can be observed that the bit line trenches (e.g., trench 640-2 ") traverse across multiple word line structures (e.g., 630-1 through 630-4). It can also be observed from the current cut line that the two word lines 630-2, 630-3 pass obliquely through the middle region M of the active region 612-2.

With further reference to fig. 6 (a 3), a trimming process of the active region is shown. During the active area trimming process, an etching operation is performed through the bit line trenches (e.g., trenches 640-1",640-2",640-3 ") to recess edge portions of the exposed middle and end regions of the fin structure. For example, the top surface of the middle region of fin 612-2 is recessed and lowered (e.g., to the lower dashed line, compared to the original height shown by the upper dashed line). Meanwhile, for adjacent fins 612-1 and 612-3, notches are created at the respective edge portions of the end regions of the active regions (e.g., a stepped notch profile as surrounded by the dashed circles of "e1" in fig. 6 (a 3) and 3).

Trimming in the middle region of the active region (e.g., fin 612-2) may ensure better electrical contact between the active region and a subsequently formed bit line conductor that would intercept directly to the upper region of the middle region of the active region. . On the other hand, trimming at the edge portions of the end regions of adjacent fins enables further insulation measures to be taken at these regions to ensure that shorting problems between subsequently formed bit lines (e.g., wires 740-1 and 740-3 as shown in fig. 7 (a 2)) and edges at the ends of adjacent fins (e.g., fins 612-1 and 612-3) are prevented.

Referring to fig. 6 (b 3), a cross-sectional view at cut line Y2 during active area trimming is shown. Fig. 6 (b 3) is substantially the same as that shown in fig. 6 (b 2) due to the carefully chosen etchant selectivity (mainly for the semiconductor material of the active region) and the protection from the overlying cap 636 during the trimming process.

Fig. 7 shows a schematic cross-sectional view of an intermediate structure from different cut lines at various stages of a fabrication process according to some embodiments of the present disclosure. In particular, fig. 7 shows different views taken from various cut lines during an exemplary bit line formation process. In one aspect, cross-sectional views (a 1) through (a 2) of fig. 7 show cross-sections substantially across three different locations (e.g., second end E2, middle portion M, and first end E1) of three adjacent active regions (e.g., fins 712-1, 712-2, and 712-3), as indicated by cut line Y1 in fig. 3. On the other hand, the cross-sectional views (b 1) - (b 2) of fig. 3 show cross-sections taken substantially along the word line structure (e.g., gate line 330-3 as previously shown), as indicated by cut line Y2 in fig. 3. Meanwhile, the cross-sectional view (c 2) of fig. 7 shows a cross-section taken substantially along the conductive line structure (e.g., bit line 340-2 as previously shown), as shown by cut line X1 in fig. 3.

Please refer to the drawings at the same time. Referring to fig. 7 (a 1) and 7 (b 1), wherein the insulation of the active region (e.g., the gap fill material 721, 723) and the bit line spacers (e.g., the bit line spacers 725) are formed through the bit line trench openings (e.g., openings 740-1",740-2",740-3 ").

In the illustrated embodiment, a thin dielectric liner (e.g., oxide liner 721) is formed at the notch (e.g., notch e1 as shown in fig. 6) at the end of the active region (e.g., fins 712-1, 712-3) to cover the exposed prior semiconductor surface of the upper edge portion of the fin structure. In some embodiments, atomic Layer Deposition (ALD) is employed in the liner to ensure continuous conformal coverage over the recessed notch surfaces.

Subsequently, a gap filler 723 is provided to fill the gap, thereby ensuring electrical isolation of the fin top region (e.g., at E1/E2) below the bit line. In some embodiments, the gap filler 723 may include a nitride-based material, such as silicon nitride. In some embodiments, the gap filler 723 may be provided by a technique having sufficient gap filling capability, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or spin-on process.

After filling the gaps, bit line spacers 725 may be formed over the sidewalls of bit line trenches 740-1",740-2",740-3 ". The spacers 725 may comprise a nitride-based material. In some embodiments, the spacer 725 may comprise a composite structure including more than one sub-layer. For example, in some embodiments, the spacers 725 may comprise a composite structure including an inner oxide layer and an outer nitride layer (not specifically shown).

In some embodiments, spacers 725 may be conformally disposed by a suitable thin-film deposition technique, such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), followed by an anisotropic etch to remove the bottom of the conformal liner overlying the trench bottom surfaces of the bit line trenches, thereby preserving the portions that substantially cover the side bit line trench walls. Further, in a middle region of the active region (e.g., region M of fin 712-2), a lower portion of the first insulating spacer structure (e.g., spacer 725) closer to the fin structure (e.g., fin 712-2) is not wider than an upper portion further from the fin structure. In some embodiments, the width profile of the spacers (e.g., spacers 725) remains substantially uniform from bottom to top.

Referring simultaneously to fig. 7 (a 2), 7 (b 2), and 7 (c 2), an exemplary bit line filling process is shown. After forming the bit line spacers (e.g., spacers 725), a buffer liner 742 is provided to provide a conformal coverage over the exposed trench surfaces (e.g., to cover the bit line trenches 740-1 "without filling the bit line trenches 740-1"). The buffer liner 742 may include one or more conductive materials that enhance adhesion between a dielectric material (e.g., spacer 725) and a subsequently disposed bit line conductor (e.g., conductor 744). The buffer liner 742 may also be made of a material that provides anti-diffusion properties (e.g., acts as a barrier when the bit line conductor 744 comprises an electrochemically active material such as Cu). In some embodiments, the buffer liner 742 may include one or more of tantalum (Ta), titanium (Ti), cobalt (Co), or nitrides thereof.

After forming the buffer liner (e.g., liner 742), a bit line conductor 744 is provided to fill the remainder of the bit line trench (e.g., 740-1", etc.). In some embodiments, the bit line conductors 744 may include one or more metallic materials, such as tungsten (W), ruthenium (Ru), cobalt (Co).

Thus, as shown in fig. 7 (a 2), at a middle region (e.g., region M) of an active region (e.g., fin 712-2), bit line structure 740-2 is formed to directly intercept the active region at a level below the topmost surface of the active region (e.g., as compared to the top boundary of adjacent fins 712-1/712-3). The bit line structure 740-2 includes a barrier liner 725 in electrical contact with the active region 712-2, the barrier liner 725 having a U-shaped profile in the width direction.

On the other hand, as shown in fig. 7 (c 2), along a cross-section along the length of the bit line conductor (e.g., bit line 740-2), the buffer liner 744 conformally lines an uneven topological profile (e.g., over multiple word line coverage, isolation, and active areas). Thus, from this perspective, the buffer liner 744 has a substantially square wave profile, with the lowermost portion of the buffer liner being in direct electrical contact with the middle region of the first fin structure 712-2.

As can be seen from the various views of fig. 7, the direct interception of the bit line structure (e.g., bit line 740-2) with the active region (e.g., the top of the middle portion M of fin 712-2) eliminates the need for additional longitudinal interconnect components (e.g., bit line contact 141 as shown in fig. 1). The elimination of the vertical bit line contact feature in turn avoids the need for a corresponding photomask and the attendant burden of complex multiple patterning processes.

Fig. 8 shows a schematic cross-sectional view of an intermediate structure from different cut lines at various stages of a fabrication process according to some embodiments of the present disclosure. In particular, FIG. 8 shows different views taken from various cut lines during an exemplary bit line overlay and storage node formation process. In one aspect, cross-sectional views (a 1) through (a 3) of fig. 8 illustrate three different locations (as indicated by cut line Y1 in fig. 3) substantially across three adjacent active regions (e.g., fins 812-1, 812-2, and 812-3). Meanwhile, the cross-sectional view (b 1) of fig. 8 shows a cross-section taken substantially along the word line structure (e.g., the gate line 330-3 as previously shown), as indicated by the cutting line Y2 in fig. 3.

Referring simultaneously to fig. 8 (a 1) and 8 (b 1), a bit line cap 846 is formed over the buffer liner 842 and bit line conductor 844. In some embodiments, the bit line overlay formation process includes recessing the buffer liner and bit line conductors (e.g., from the height shown in fig. 7 (a 2) that was previously filled) to a level below the top boundary of the surrounding dielectric material (e.g., the fill oxide 803 over the fin top and the STI811 around the fin structure). A dielectric deposition process is then performed to place a dielectric material (e.g., nitride) over the recessed bit line conductors, and then a polishing process (e.g., CMP) is performed to planarize the bit line cover 846, filling the oxide 803 and the top boundary STI811 of the oxide layer. In this way, a bit line structure (e.g., 840-2) may be formed that includes a buffer liner (e.g., liner 842), a bit line conductor (e.g., metal 844), and a bit line cap (e.g., cap feature 846).

Referring to fig. 8 (a 2), an etching process of the storage node contact is shown. In the illustrated embodiment, dielectric material between the bit line structures (e.g., fill oxide 803 and upper portions of STI 811) is removed (e.g., by oxide etching) to expose top corners of adjacent active regions (e.g., inner corners of fins 812-1/812-3, which are opposite insulating gap fill 823). In some embodiments, the exposed locations (i.e., between adjacent bit line structures) may correspond to locations where storage nodes contact (e.g., as shown by lighter shaded dots shown in fig. 3).

By using bit line structures (e.g., their sidewall spacers) as a self-aligned mask, subsequent storage node contacts (e.g., landing plugs 914 as shown in fig. 9 (a 1)) can be formed without the need for a dedicated photomask, further reducing manufacturing complexity and cost.

Referring to fig. 8 (a 3), an exemplary storage contact spacer formation process is shown. For example, in the illustrated embodiment, an inner spacer layer (e.g., oxide sublayer 835) and an outer spacer layer (e.g., nitride sublayer 837) are formed on opposite sidewalls between adjacent bit line structures (e.g., bit lines 840-1, 840-2). However, in some embodiments, the one or more spacer sublayers may be optional.

Fig. 9 shows a schematic cross-sectional view of a cut-from-cut line of an intermediate structure at various stages of a fabrication process according to some embodiments of the present disclosure. In particular, fig. 9 shows a view from the cut line during an exemplary storage landing plug and storage node landing and storage node formation process. In one aspect, cross-sectional views (a 1) through (a 2) of fig. 9 illustrate three different locations (as indicated by cut line Y1 in fig. 3) substantially across three adjacent active regions (e.g., fins 912-1, 912-2, and 912-3).

Referring to fig. 9 (a 1), a conductive material (e.g., feature 914) is disposed between the spacer structures of adjacent bit line structures to form a ground plug 914 extending vertically therebetween. The ground plug 914 may comprise a metallic or non-metallic conductive material such as doped polysilicon, aluminum, tungsten, ruthenium, and cobalt. After the conductor deposition process, a planarization process may be performed on the bit line cap 946 and the conductive feature 914. A separation layer 915 (e.g., made of a nitride-based material) may then be formed over the planarized surface to provide protection and serve as an etch stop layer for subsequent storage node formation processes.

In the illustrated cross-section, landing plugs 914 extend substantially longitudinally between the fin structures (e.g., between fins 912-1, 912-2) and electrically contact a side of an end region of the fin structures (e.g., fin 912-1) opposite the notch filler (feature 923). In some embodiments, contact plug 914 may also be observed to contact an outer spacer layer (e.g., nitride spacer 937) over notch filler 923.

Referring to fig. 9 (a 2), a storage node (e.g., capacitor structure 916) is formed over and in electrical contact with a storage node contact (e.g., landing plug 914).

Accordingly, an aspect of the present disclosure provides a semiconductor device, comprising: a first fin structure on the substrate and having a bar-shaped planar profile; and a first conductive line structure intersecting the middle region of the first fin structure at a level lower than a topmost surface of the first fin structure.

In some embodiments according to the present disclosure, the first wire structure intercepts the first fin structure at an oblique angle, the oblique angle being about 65 to 75 degrees, from a planar view.

In some embodiments according to the present disclosure, the first wire structure includes: a buffer liner layer having a substantially U-shaped profile in a cross section in a width direction of the first wire structure, the buffer liner layer being in electrical contact with the intermediate region of the first fin structure; a metal layer in the U-shaped profile of the buffer liner; and a capping layer over the metal layer.

In some embodiments according to the present disclosure, the first wire structure includes: a buffer liner having a generally square wave profile in cross-section along a length of the first wire structure, the buffer liner being in electrical contact with the intermediate region of the first fin structure; a metal layer over the buffer liner; and a capping layer over the metal layer.

In some embodiments according to the present disclosure, a first insulating spacer structure is further included extending from the first fin structure and covering sidewalls of the first wire structure, wherein a lower portion of the first insulating spacer structure proximate to the first fin structure is not wider than an upper portion of the first insulating spacer structure distal from the first fin structure.

In some embodiments according to the present disclosure, the first insulating spacer structure includes an outer nitride layer.

In some embodiments according to the present disclosure, further comprising a second fin structure having a striped planar profile on the substrate, an end region of the second fin structure overlapping in cross-section with a middle region of the first fin structure; a second wire structure extending side-by-side with the first wire structure, the second wire structure having a second insulating isolation structure extending from the second fin structure and covering sidewalls of the second wire structure; wherein the second insulating isolation structure comprises an outer nitride layer; and a connection plug extending vertically between and contacting the outer nitride layer of the first and second wire structures, wherein the vertical connection plug electrically contacts an inner edge of the second fin structure that is closer to the first fin structure.

In some embodiments according to the present disclosure, the second fin structure has a stair-step notch profile at an outer edge opposite the inner edge, wherein a nitride dielectric material fills the stair-step notch profile.

In some embodiments according to the present disclosure, a storage node is also included, which is arranged above the connection plug and is electrically connected with the end region of the second fin structure through the connection plug.

In some embodiments according to the present disclosure, a gate line structure is further included that is obliquely truncated to the first fin structure and extends below the first wire structure, the gate line structure being substantially perpendicular to the first wire structure in a planar view.

Accordingly, an aspect of the present disclosure provides a semiconductor device, comprising: a first active region over the substrate; and a first bit line structure intersecting the first active region at a level lower than a top-most surface (top-most surface) of the first active region, the first bit line structure including a barrier liner having a U-shaped profile in a width direction thereof, the barrier liner being in electrical contact with the first active region.

In some embodiments according to the present disclosure, further comprising a first bit line spacing structure extending vertically from the first active region and covering sidewalls of the first bit line structure, wherein a lower portion of the first bit line spacing structure proximate to the first active region is not wider than an upper portion of the first bit line spacing structure distal from the first active region; the first bit line spacing structure includes an outer nitride layer.

In some embodiments according to the present disclosure, a second active region on the substrate, the second active region overlapping in cross-section with a middle region of the first active region; a second bit line structure extending side by side with the first bit line structure, the second bit line structure having a second bit line isolation structure extending from the second active region and covering a sidewall of the second bit line structure; wherein the second bit line isolation structure comprises an outer nitride layer; and a connection plug extending vertically between and contacting the outer nitride layer of the first and second isolated bit line structures, wherein the connection plug electrically contacts an inner edge of the second active region that is closer to the first active region.

In some embodiments according to the present disclosure, the second active region has a notch in cross section at an outer edge opposite the inner edge, wherein a nitride dielectric material fills the notch.

In some embodiments according to the present disclosure, a capacitive structure is also included, which is disposed above the connection plug and electrically connected with the second active region through the connection plug.

In some embodiments according to the present disclosure, a word line structure is further included, buried in the first active region and under the first bit line structure.

Accordingly, an aspect of the present disclosure provides a method of manufacturing a semiconductor device, including: forming a plurality of fin structures on a substrate, wherein each fin structure has a strip-shaped plane contour; disposing a dielectric material between and over the fin structures; patterning the dielectric material to form bit line trenches side-by-side with each other over the fin structures, wherein each of the bit line trenches obliquely intercepts a respective middle region of a row of the fin structures, the bit line trenches exposing the entire width of the middle region and edge portions (edge portions) of end regions (end regions) of the fin structures; recessing edge portions of the middle and end regions of the fin structure, thereby lowering a top surface of the middle region and creating a notch at the edge portions of the end regions; forming a spacer structure on a sidewall surface of the bit line trench, the spacer structure filling a gap at an edge portion of an end region; conformally forming a buffer liner on the exposed surfaces of the spacer structures and the intermediate regions of the fin structures; and disposing a metal material on the buffer liner layer and filling the bit line trench to form a bit line structure.

In some embodiments according to the present disclosure, forming a word line structure obliquely intercepts the fin structure, the word line structure being lower and substantially perpendicular to the bit line structure, prior to patterning to form the bit line trench.

In some embodiments according to the present disclosure, further comprising disposing a conductive material between spacer structures of adjacent ones of the bit line structures to form vertically extending connection plugs between the spacer structures, the connection plugs being in electrical contact with a side of an end region of the fin structure opposite the notch.

In some embodiments according to the present disclosure, a capacitor structure is also included that is formed over the connection plug in electrical contact with the connection plug.

The embodiments shown and described above are examples only. Accordingly, many such details are not shown or described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of structure and function, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape and size. And in a manner that is within the scope of the principles, as well as in an arrangement of parts, up to and including the full scope, as determined by the broad general meaning of the terms used in the claims. It is therefore to be understood that within the scope of the appended claims, the above embodiments may be modified.

Claims

1. A semiconductor device, comprising:

a first fin structure on the substrate and having a bar-shaped planar profile;

a first conductive line structure intersecting the middle region of the first fin structure at a level lower than the topmost surface of the first fin structure; and

a second fin structure having a planar profile of a stripe shape on the substrate, an end region of the second fin structure overlapping in cross-section with a middle region of the first fin structure, the second fin structure having a notch profile at an outer edge, a nitride dielectric material filling the notch profile.

2. The device of claim 1, wherein the device comprises,

in a planar view, the first conductive line structure is truncated to the first fin structure at an oblique angle of 65 to 75 degrees.

3. The device of claim 1, wherein the device comprises,

the first wire structure includes:

a buffer liner layer having a substantially U-shaped profile in a cross section in a width direction of the first wire structure, the buffer liner layer being in electrical contact with the intermediate region of the first fin structure;

a metal layer in the U-shaped profile of the buffer liner; and

And a capping layer over the metal layer.

4. The device of claim 1, wherein the device comprises,

the first wire structure includes:

a buffer liner having a generally square wave profile in cross-section along a length of the first wire structure, the buffer liner being in electrical contact with the intermediate region of the first fin structure;

a metal layer over the buffer liner; and

and a capping layer over the metal layer.

5. The device of claim 4, further comprising

A first insulating spacer structure extending from the first fin structure and covering sidewalls of the first conductive line structure,

wherein a lower portion of the first insulating spacer structure proximate to the first fin structure is not wider than an upper portion of the first insulating spacer structure distal from the first fin structure.

6. The device of claim 5, wherein the device comprises,

the first insulating spacer structure includes an outer nitride layer.

7. The device of claim 6, further comprising

A second wire structure extending side-by-side with the first wire structure, the second wire structure having a second insulating isolation structure extending from the second fin structure and covering sidewalls of the second wire structure,

Wherein the second insulating isolation structure comprises an outer nitride layer; and

and a connection plug extending vertically between and contacting the outer nitride layers of the first and second conductive line structures, wherein the vertical connection plug electrically contacts an inner edge of the second fin structure that is closer to the first fin structure.

8. The device of claim 7, further comprising

A storage node arranged above the connection plug and electrically connected with the end region of the second fin structure through the connection plug.

9. The device of claim 1, further comprising

A gate line structure obliquely intercepting the first fin structure and extending below the first wire structure, the gate line structure being substantially perpendicular to the first wire structure in a planar view.