WO2024148672A1 - Semiconductor structure and manufacturing method therefor - Google Patents

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, wherein the substrate comprises semiconductor columns and first isolation columns, a plurality of semiconductor columns extend in a first direction and are arranged in an array in a second direction and a third direction, a plurality of first isolation columns extend in the third direction and are arranged in the second direction, each of the first isolation columns penetrates through a row of semiconductor columns arranged in the third direction, and the semiconductor columns encircle side faces of the first isolation columns; removing some of the first isolation columns to form first through holes, wherein the first through holes extend in the third direction, and the semiconductor columns are exposed out of two opposite sides of the first through holes; and forming a word line structure in the first through holes.

Description

Semiconductor structure and method for manufacturing the same

Related Application Citations

The present disclosure claims priority to Chinese Patent Application No. 202310070349.1, filed on January 13, 2023, entitled “Semiconductor Structure and Method for Making the Same,” the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in computer electronic devices. It is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

3D DRAM has attracted wide attention as the future DRAM architecture. However, for some 3D DRAM structures, it is difficult to control the word line structure morphology and cannot meet the demand.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can achieve good control over the outline of a word line structure.

An embodiment of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate, the substrate including a semiconductor column and a first isolation column, the semiconductor column extending along a first direction, and a plurality of the semiconductor columns are arranged in an array along a second direction and a third direction, the first isolation column extending along the third direction, and a plurality of the first isolation columns are arranged along the second direction, each of the first isolation columns penetrates a column of the semiconductor columns arranged along the third direction, and the semiconductor columns surround the side surfaces of the first isolation columns; removing a portion of the first isolation columns to form a first through hole, the first through hole extending along the third direction, and the two opposite side walls of the first through hole in the second direction expose the semiconductor column; and forming a word line structure in the first through hole.

In one embodiment, the method for forming the substrate includes: providing a stacked layer, the stacked layer including semiconductor layers and sacrificial layers stacked in sequence along a third direction; removing a portion of the stacked layer along the third direction to form a plurality of first primary semiconductor structures arranged along the second direction;

A second through hole is formed, wherein the second through hole extends along the third direction, and a plurality of the second through holes are arranged along the second direction, and each of the second through holes penetrates one of the first primary semiconductor structures; the first isolation column is formed in the second through hole; the sacrificial layer is removed, and the retained semiconductor layer serves as the semiconductor column.

In one embodiment, after the step of forming a plurality of first primary semiconductor structures arranged along the second direction, the step further includes: forming a first dielectric layer, wherein the first dielectric layer is filled between two adjacent first primary semiconductor structures; and before the step of removing the sacrificial layer, the step further includes removing the first dielectric layer.

In one embodiment, before the step of forming a plurality of first preliminary semiconductor structures arranged along the second direction, the method further includes: forming a covering A cap layer, wherein the cap layer covers the surface of the stacked layer; in the step of forming a plurality of first primary semiconductor structures arranged along the second direction, a portion of the cap layer is removed; in the step of forming a second through hole, the second through hole also penetrates the cap layer; in the step of removing the first dielectric layer, the remaining cap layer is removed.

In one embodiment, before the step of forming the first isolation column in the second through hole, the step further includes: ion doping the semiconductor layer exposed to the second through hole.

In one embodiment, the step of removing part of the stacked layer along the third direction to form a plurality of first primary semiconductor structures arranged along the second direction also includes: forming a second primary semiconductor structure extending along the second direction, the second primary semiconductor structure being connected to one end of the plurality of first primary semiconductor structures in the first direction; the step of removing the sacrificial layer also includes removing the sacrificial layer in the second primary semiconductor structure; after the step of forming the word line structure in the first through hole, the step also includes: removing the semiconductor layer in the second primary semiconductor structure to form a groove; forming a bit line structure in the groove, the bit line structure being connected to one end of the semiconductor column in the first direction.

In one embodiment, before the step of removing a portion of the first isolation pillars to form the first through-hole, the step further includes: forming a second dielectric layer, wherein the second dielectric layer fills the gaps between the semiconductor pillars and between the first isolation pillars.

In one embodiment, after the step of forming a word line structure in the first through hole, the step further includes: removing at least a portion of the first isolation column located at both ends of the second through hole in the first direction to expose the semiconductor column; performing metal silicide treatment on the exposed semiconductor column to form a first metal silicide layer and a second metal silicide layer.

In one embodiment, in the step of removing at least a portion of the first isolation column located at both ends of the second through hole in the first direction, only a portion of the first isolation column located at both ends of the second through hole in the first direction is removed, and the first isolation column covering the side wall of the word line structure is retained as an isolation side wall, and the area where the semiconductor column contacts the isolation side wall serves as a first source and drain region and a second source and drain region, the first source and drain region contacts the first metal silicide layer, and the second source and drain region contacts the second metal silicide layer.

In one embodiment, the step of removing at least a portion of the first isolation column located at both ends of the second through hole in the first direction includes forming a third through hole and a fourth through hole respectively; the step of performing metal silicide treatment on the exposed semiconductor column includes: filling metal material in the third through hole and the fourth through hole; performing metal silicide treatment to form the semiconductor column in contact with the metal material into the first metal silicide layer and the second metal silicide layer; and removing the metal material.

In one embodiment, after the step of performing metal silicide treatment on the exposed semiconductor pillar, the step further includes: filling a third dielectric layer in the third through hole and the fourth through hole.

In one embodiment, the substrate includes a transistor region and a capacitor region arranged along the first direction, the semiconductor column extends from the transistor region to the capacitor region, and the first isolation column passes through a row of the semiconductor columns arranged along the third direction in the transistor region; the substrate also includes a second isolation column, the second isolation column extends along the third direction, and a plurality of the second isolation columns are arranged along the second direction, in the capacitor region, each of the second isolation columns passes through a row of the semiconductor columns arranged along the third direction, and the The semiconductor column surrounds the side of the second isolation column; after the step of forming a word line structure in the first through hole, it also includes: exposing the semiconductor column in the capacitor area and removing the second isolation column to form a fifth through hole penetrating the semiconductor column on the semiconductor column; forming a lower electrode, the lower electrode covers the surface of the semiconductor column and covers the side wall of the fifth through hole; forming a dielectric layer on the lower electrode, and forming an upper electrode on the dielectric layer.

The disclosed embodiment also provides a semiconductor structure, comprising: a semiconductor pillar extending along a first direction, and a plurality of the semiconductor pillars are arranged in an array along a second direction and a third direction; a word line structure extending along the third direction, and a plurality of the word lines are arranged along the second direction, each of the word lines passes through a column of the semiconductor pillars arranged along the third direction, and the semiconductor pillars cover two opposite side surfaces of the word line structure in the second direction; and an isolation sidewall, the isolation sidewall covers the sidewall of the word line structure in the first direction, and the isolation sidewall passes through the semiconductor pillar.

In one embodiment, in the first direction, the isolation spacers are symmetrically arranged on two sides of the word line structure.

In one embodiment, the semiconductor column also includes a first metal silicide layer and a second metal silicide layer, and the area where the semiconductor column contacts the isolation side wall serves as a first source and drain region and a second source and drain region, the first source and drain region contacts the first metal silicide layer, and the second source and drain region contacts the second metal silicide layer.

In one embodiment, the semiconductor structure includes a transistor region and a capacitor region arranged along the first direction, the word line structure and the isolation sidewall are located in the transistor region; the semiconductor column extends from the transistor region to the capacitor region, and in the capacitor region, the semiconductor column has a through hole that penetrates the semiconductor column along a third direction, and the capacitor region includes: a lower electrode, covering the surface of the semiconductor column and the sidewall of the through hole; a dielectric layer, covering the lower electrode; and an upper electrode, covering the dielectric layer.

In one embodiment, the semiconductor structure further includes a bit line structure, the bit line structure extends along the second direction, and a plurality of the bit line structures are arranged along the third direction, and each of the bit line structures is connected to a row of the semiconductor pillars arranged along the second direction.

In one embodiment, in the first direction, the third dielectric layer is disposed on a side of the isolation spacer opposite to the word line structure and is in contact with the first metal silicide layer and the second metal silicide layer.

The semiconductor structure and preparation method thereof provided by the embodiments of the present disclosure utilize the first isolation column as a placeholder structure, and form a word line structure after removing the first isolation column, which can effectively control the contour shape of the word line structure and improve the reliability of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

2A to 2V are schematic diagrams of semiconductor structures formed by main steps of a preparation method provided in one embodiment of the present disclosure.

Detailed ways

The specific implementation of the semiconductor structure and the preparation method thereof provided by the present disclosure is described in detail below in conjunction with the accompanying drawings. The semiconductor structure in this specific implementation can be but is not limited to a DRAM.

FIG1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure. Referring to FIG1 , the method comprises: step S10, providing a substrate, the substrate comprising a semiconductor column and a first isolation column, the semiconductor column extending along a first direction, and a plurality of semiconductor The columns are arranged in an array along the second direction and the third direction, the first isolation columns extend along the third direction, and a plurality of first isolation columns are arranged along the second direction, each first isolation column penetrates a row of semiconductor columns arranged along the third direction, and the semiconductor columns surround the sides of the first isolation columns; step S11, removing part of the first isolation columns to form a first through hole, the first through hole extends along the third direction, and the two side walls of the first through hole opposite to each other in the second direction expose the semiconductor columns; step S12, forming a word line structure in the first through hole.

The method for preparing a semiconductor structure provided by the embodiment of the present disclosure utilizes a first isolation column as a placeholder structure and forms a word line structure after removing part of the first isolation column, which can effectively control the contour shape of the word line structure and improve the reliability of the semiconductor structure.

2A to 2V are schematic diagrams of semiconductor structures formed by main steps of a preparation method provided in one embodiment of the present disclosure.

Please refer to Figures 1, 2F and 2G, Figure 2G is a cross-sectional view along line A-A’ in Figure 2F, step S10, providing a substrate, the substrate including a semiconductor column 110 and a first isolation column 120, the semiconductor column 110 extends along the first direction D1, and a plurality of semiconductor columns 110 are arranged in an array along the second direction D2 and a third direction D3, the first isolation column 120 extends along the third direction D3, and a plurality of first isolation columns 120 are arranged along the second direction D2, each first isolation column 120 penetrates a column of semiconductor columns 110 arranged along the third direction D3, and the semiconductor column 110 surrounds the side of the first isolation column 120.

In some embodiments, the first direction D1 is the X direction in the Cartesian coordinate system, the second direction D2 is the Y direction in the Cartesian coordinate system, and the third direction D3 is the Z direction in the Cartesian coordinate system.

In some embodiments, the substrate includes a transistor region AA and a capacitor region CA, the transistor region AA and the capacitor region CA are arranged along a first direction D1, the semiconductor column 110 extends from the transistor region AA to the capacitor region CA, the first isolation column 120 is located in the transistor region AA, and the first isolation column 120 penetrates a row of semiconductor columns 110 arranged along a third direction D3 in the transistor region AA. The substrate further includes a second isolation column 130, the second isolation column 130 extends along the third direction D3, and a plurality of second isolation columns 130 are arranged along the second direction D2, in the capacitor region CA, each second isolation column 130 penetrates a row of semiconductor columns 110 arranged along the third direction D3, and the semiconductor column 110 surrounds the side of the second isolation column 130. In some embodiments, the first isolation column 120 and the second isolation column 130 are spaced apart by a set distance in the first direction D1.

As an example, an embodiment of the present disclosure further provides a method for forming a substrate. Specifically, the method includes:

Referring to FIG. 2A , a stacked layer 100 is provided, and the stacked layer 100 includes a semiconductor layer 101 and a sacrificial layer 102 stacked in sequence along a third direction D3. The material of the semiconductor layer 101 includes, but is not limited to, single crystal silicon, polycrystalline silicon, oxide semiconductor materials such as IGZO, and compound semiconductor materials such as InGaAs and GaN. The material of the sacrificial layer 102 includes, but is not limited to, silicon germanium, silicon nitride, etc. In this embodiment, the material of the semiconductor layer 101 is single crystal silicon, and the material of the sacrificial layer 102 is silicon germanium.

In some embodiments, a capping layer 103 is further formed on the top surface of the stacked layer 100. The capping layer 103 is used to protect the topmost semiconductor column 110 during the etching process. Due to the presence of the capping layer 103, in the subsequent process, the upper surface of the first isolation column 120 formed in the second through hole 420 (see FIG. 2D) can be higher than the topmost semiconductor column 110, so that the finally formed word line structure 140 (see FIG. 2L) is higher than the stacked semiconductor column 110, which facilitates the word line structure 140 to be connected through the lead without the need to form additional conductive connection columns aligned to form the word line structure. The capping layer 103 includes but is not limited to an oxide layer, such as a silicon oxide layer. Referring to FIG. 2B, a portion of the stacked layer 100 is removed along the third direction D3 to form a plurality of first primary semiconductor structures 300 arranged along the second direction D2. The first primary semiconductor structures 300 are arranged along the third direction D3. The first primary semiconductor structure 300 is formed by semiconductor pillars 110 and sacrificial layers 102 stacked along a third direction D3 and extending along the first direction D1.

In this embodiment, a second primary semiconductor structure 310 extending along the second direction D2 is also formed in this step. In some embodiments, a second primary semiconductor structure 310 is formed, and the second primary semiconductor structure 310 is disposed at one end of the first primary semiconductor structure 300 in the first direction D1, that is, the second primary semiconductor structure 310 is connected to one end of the plurality of first primary semiconductor structures 300 in the first direction D1. The second primary semiconductor structure 310 is composed of a semiconductor layer 101 and a sacrificial layer 102 stacked along a third direction D3 and extending along the second direction D2. In this embodiment, the capping layer 103 located on the surface of the first primary semiconductor structure 300 is also retained.

In some embodiments, referring to FIG. 2C , after forming the first primary semiconductor structure 300 and the second primary semiconductor structure 310, the following steps are further included: forming a first dielectric layer 330, the first dielectric layer 330 is filled between two adjacent first primary semiconductor structures 300, and covers the surfaces of the first primary semiconductor structure 300 and the second primary semiconductor structure 310. In this embodiment, the first dielectric layer 330 also covers the surface of the cover layer 103. The first dielectric layer 330 includes but is not limited to an oxide layer, such as a silicon oxide layer.

2D , a second through hole 420 is formed, the second through hole 420 extends along the third direction D3 , and a plurality of second through holes 420 are arranged along the second direction D2 , each second through hole 420 penetrates a first primary semiconductor structure 300 . In some embodiments, the second through hole 420 also penetrates the cover layer 103 .

In this step, a photolithography and etching process may be used to form the second through holes 420. In the present embodiment, each second through hole 420 penetrates the first dielectric layer 330, the capping layer 103, the semiconductor pillar 110 of the first primary semiconductor structure 300, and the sacrificial layer 102 along the third direction D3. In some embodiments, the length of the second through hole 420 along the first direction D1 is greater than the length of the subsequently formed word line structure along the first direction D1, so as to provide space for forming the isolation sidewall.

The second through hole 420 is formed in the transistor area AA. In some embodiments, in this step, a sixth through hole 460 is also formed in the capacitor area CA. The sixth through hole 460 extends along the third direction D3, and a plurality of sixth through holes 460 are arranged along the second direction D2. Each sixth through hole 460 penetrates a first primary semiconductor structure 300. In this step, the sixth through hole 460 can be formed at the same time as the second through hole 420 is formed. For example, the second through hole 420 and the sixth through hole 460 can be formed by photolithography and etching processes. In this embodiment, each sixth through hole 460 penetrates the first dielectric layer 330, the cover layer 103, and the semiconductor pillar 110 and the sacrificial layer 102 of the first primary semiconductor structure 300 along the third direction D3.

In some embodiments, after forming the second through hole 420, the semiconductor column 110 exposed to the second through hole 420 is ion doped, that is, the semiconductor column 110 of the first initial semiconductor structure is ion doped to serve as a channel region or a lightly doped drain region or a first source drain region and a second source drain region of a transistor formed subsequently. Ion doping includes but is not limited to N-type ion doping or P-type ion doping. In some embodiments, after forming the second through hole 420, the semiconductor column 110 exposed to the second through hole 420 is ion doped to form a lightly doped drain region to reduce leakage current.

2E , the first isolation column 120 is formed in the second through hole 420. In this embodiment, the sixth through hole 460 is formed. Second spacer 130. The material of the first spacer 120 and the second spacer 130 includes but is not limited to silicon nitride. In this step, the first spacer 120 and the second spacer 130 can be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition and other processes.

2F and 2G , the sacrificial layer 102 is removed, and the semiconductor layer 101 is retained as the semiconductor pillar 110. The sacrificial layer 102 in the first primary semiconductor structure 300 is removed, and a groove 500 is formed between two adjacent semiconductor pillars 110; in this step, the sacrificial layer 102 in the second primary semiconductor structure 310 is removed, and a groove 510 is formed between two adjacent semiconductor pillars 110. In this embodiment, before removing the sacrificial layer 102, the first dielectric layer 330 and the remaining capping layer 103 are also removed.

2H , a second dielectric layer 340 is formed to fill the gaps between the semiconductor pillars 110 and the first isolation pillars 120 to provide an isolation layer and a support layer for subsequent processes. The second dielectric layer 340 includes but is not limited to an oxide layer, such as a silicon oxide layer.

Please continue to refer to FIG. 1 , FIG. 2I and FIG. 2J , wherein FIG. 2J is a cross-sectional view along line A-A' in FIG. 2I , in step S11, a portion of the first isolation column 120 is removed to form a first through hole 410, the first through hole 410 extends along a third direction D3, and opposite side walls of the first through hole 410 expose the semiconductor column 110. In this step, a portion of the first isolation column 120 is removed along the third direction D3 by using a photolithography and etching process.

In some embodiments, in the semiconductor pillar 110 region, the first through hole 410 exposes the semiconductor pillar 110 along two opposite side walls in the second direction D2, and in the second dielectric layer 340 region, the first through hole 410 exposes the second dielectric layer 340 along two opposite side walls in the second direction D2.

In some embodiments, after removing part of the first isolation columns 120, the remaining first isolation columns 120 are arranged along the first direction D1, and are symmetrically arranged on both sides of the first through hole 410 with the axis of the first through hole 410 as the symmetry axis, and the remaining first isolation columns 120 on both sides of the first through hole 410 have the same area. In other embodiments, the remaining first isolation columns 120 may also be asymmetrically arranged on both sides of the first through hole 410, and the remaining first isolation columns 120 on both sides of the first through hole 410 have different areas.

In some embodiments, after forming the first through hole 410, the semiconductor column 110 exposed to the first through hole 410 is ion doped, that is, the semiconductor column 110 of a portion of the first initial semiconductor structure is ion doped to serve as the channel region of the transistor formed subsequently. Ion doping includes but is not limited to N-type ion doping or P-type ion doping. In some embodiments, the region of the semiconductor column 110 corresponding to the remaining first isolation column 120 serves as a lightly doped drain region or a first source drain region and a second source drain region, and the region of the semiconductor column 110 corresponding to the first through hole 410 serves as a channel region, and the doping type of the lightly doped drain region, the first source drain region, and the second source drain region is opposite to the doping type of the channel region.

Please continue to refer to FIG. 1 , FIG. 2K and FIG. 2L , wherein FIG. 2L is a cross-sectional view along line A-A' in FIG. 2K , step S12, forming a word line structure 140 in the first through hole 410. The region where the semiconductor pillar 110 contacts the word line structure 140 serves as a channel region CH.

The word line structure 140 includes a word line dielectric layer (not shown in the drawings) covering the semiconductor pillar 110 and a word line (not shown in the drawings) covering the word line dielectric layer. In this step, a word line dielectric layer may be formed in the first through hole 410 first, and then a word line may be formed, so that the word line fills the first through hole 410. In some embodiments, the word line dielectric layer only covers the surface of the semiconductor pillar 110 exposed to the first through hole 410. In other embodiments, the word line dielectric layer covers both the surface of the semiconductor pillar 110 exposed to the first through hole 410 and the sidewall of the second dielectric layer 340 exposed to the first through hole 410, and may also cover the remaining surface of the first isolation pillar 120 exposed to the first through hole 410.

The relationship between the word line structure 140 and the semiconductor column 110 is shown in FIG. 2M , which is a schematic diagram showing FIG. 2K without the second dielectric layer 340 . In the region where the semiconductor column 110 is located, the two outer surfaces of the word line structure 140 opposite to each other in the second direction D2 are in contact with the semiconductor column 110 , and the semiconductor column 110 in this region serves as a channel region CH.

The method for preparing the semiconductor structure provided by the embodiment of the present disclosure first forms a first isolation column 120, uses the first isolation column 120 as a placeholder structure, and then partially removes the first isolation column 120 to provide space for forming a word line structure 140, and then forms the word line structure 140, thereby effectively controlling the profile of the word line structure 140 and improving the performance of the semiconductor structure.

In some embodiments, after forming the word line structure 140, the preparation method further includes the following steps: please refer to Figures 2N and 2O, Figure 2N is a schematic diagram of hiding the second dielectric layer 340, and Figure 2O is a cross-sectional view along the A-A’ line in Figure 2N, removing at least a portion of the first isolation column 120 located at both ends of the second through hole 420 in the first direction D1 to expose the semiconductor column 110.

In some embodiments, in this step, only a portion of the first isolation column 120 located at both ends of the second through hole 420 in the first direction D1 is removed, and the first isolation column 120 covering the side wall of the word line structure 140 is retained as the isolation spacer 150, and the area where the semiconductor column 110 contacts the isolation spacer 150 is used as the first source and drain region and the second source and drain region. The isolation spacer 150 can isolate the word line structure 140 from the first source and drain region and the second source and drain region. Since the isolation spacer 150 is a part of the first isolation column 120, it can be self-aligned to form on both sides of the word line structure 140, so that it can have a larger process window and can improve the morphology uniformity of the semiconductor structure.

At least a portion of the first isolation column 120 located at both ends of the second through hole 420 in the first direction D1 is removed to form a third through hole 430 and a fourth through hole 440 . The third through hole 430 and the fourth through hole 440 penetrate the second dielectric layer 340 and the semiconductor column 110 .

Please refer to FIG. 2P and FIG. 2Q, wherein FIG. 2P is a schematic diagram in which the second dielectric layer 340 is hidden, and FIG. 2Q is a cross-sectional view along the line A-A' in FIG. 2P. The semiconductor pillar 110 exposed by the third through hole 430 and the fourth through hole 440 is subjected to metal silicide treatment to form the semiconductor pillar in contact with the metal material into a first metal silicide layer 160 and a second metal silicide layer 170. The first metal silicide layer 160 and the second metal silicide layer 170 are connected to the first source and drain region and the second source and drain region, respectively. Specifically, in the first direction D1, one end of the first metal silicide layer 160 is connected to the first source and drain region, and the other end is connected to the semiconductor pillar 110 of the second primary semiconductor structure 310, and one end of the second metal silicide layer 170 is connected to the second source and drain region, and the other end is connected to the region of the semiconductor pillar 110 located in the capacitor region CA.

As an example, some embodiments of the present disclosure further provide a method for forming a first metal silicide layer 160 and a second metal silicide layer 170, the method comprising: filling a metal material in the third through hole 430 and the fourth through hole 440; performing a metal silicide treatment, the semiconductor pillar 110 reacts with the metal material to form the first metal silicide layer 160 and the second metal silicide layer 170, and removing the metal material after forming the first metal silicide layer 160 and the second metal silicide layer 170. The method for performing the metal silicide treatment includes but is not limited to performing at least one annealing, and the metal material includes but is not limited to one of Ti, Co, Ni, and Ru.

In some embodiments, the semiconductor pillar 110 exposed by the third through hole 430 and the fourth through hole 440 is heavily doped, and the type of ion doping is opposite to the type of ion doping in the channel region of the transistor, so as to form the semiconductor pillar in contact with the metal material into a first source and drain region and a second source and drain region. The first source and drain region and the second source and drain region are respectively connected to the lightly doped drain region corresponding to the isolation sidewall 150, and the doping concentration of the lightly doped drain region is less than the doping concentration of the first source and drain region and the second source and drain region. Specifically, in the first direction D1, one end of the first source and drain region is One end of the second source/drain region is connected to the lightly doped drain region, and the other end is connected to the semiconductor column 110 of the second primary semiconductor structure 310 . One end of the second source/drain region is connected to the lightly doped drain region, and the other end is connected to the semiconductor column 110 located in the capacitor area CA.

2P and 2Q, after forming the first metal silicide layer 160 and the second metal silicide layer 170, the third dielectric layer 350 is filled in the third through hole 430 and the fourth through hole 440. The third dielectric layer 350 includes but is not limited to an oxide layer, such as a silicon oxide layer.

In some embodiments, after the step of forming the word line structure 140 in the first through hole 410, the step of forming a bit line is also included. Specifically, the step of forming the bit line includes:

Please refer to FIG. 2R and FIG. 2S, where FIG. 2R is a schematic diagram in which the second dielectric layer 340 is hidden, and FIG. 2S is a cross-sectional view along the line A-A' in FIG. 2R, wherein the semiconductor layer 101 in the second primary semiconductor structure 310 is removed to form a groove (not shown in the figure), and a bit line structure 180 is formed in the groove, and the bit line structure 180 is connected to one end of the semiconductor pillar 110 of the same layer in the first direction. The bit line structure 180 extends along the second direction D2, and a plurality of bit line structures 180 are arranged at intervals along the third direction D3, and a second dielectric layer 340 is disposed between adjacent bit line structures 180. In the present embodiment, the bit line structure 180 is connected to the first metal silicide layer 160 to reduce the contact resistance between the bit line structure 180 and the semiconductor pillar 110.

After forming the bit line structure 180, the preparation method further includes the step of forming a capacitor. Specifically, the step of forming a capacitor includes:

Please refer to FIG. 2T , the semiconductor column 110 of the capacitor region CA is exposed, and the second isolation column 130 is removed to form a fifth through hole 450 penetrating the semiconductor column 110 on the semiconductor column 110. In this step, in the capacitor region CA, the second dielectric layer 340 is removed by photolithography and etching processes to expose the semiconductor column 110; and the second isolation column 130 is removed. The fifth through hole 450 is formed in the area of the semiconductor column 110 filled with the second isolation column 130, and the semiconductor column 110 can be used as a support for the capacitor formed in the subsequent process. In some specific embodiments, when the second dielectric layer 340 is removed, the surface of the second metal silicide layer 170 is partially exposed to provide a conductive contact area for the lower electrode formed in the subsequent process.

Referring to FIG. 2U , a lower electrode 190 is formed, and the lower electrode 190 covers the surface of the semiconductor pillar 110 and the sidewall of the fifth through hole 450. In some embodiments, the lower electrode 190 is connected to the second metal silicide layer 170, that is, the lower electrode 190 is connected to the second source and drain region through the second metal silicide layer 170, which can reduce the contact resistance between the lower electrode 190 and the second source and drain region. The lower electrodes 190 on the surface of each semiconductor pillar 110 are isolated from each other by back etching or selective deposition.

In some embodiments, the lower electrode 190 may be formed by a deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition or plasma vapor deposition. The material of the lower electrode 190 includes but is not limited to metal materials such as titanium nitride, tantalum nitride, copper or tungsten.

Referring to FIG. 2V , a dielectric layer (not shown in the figure) is formed on the lower electrode 190, and an upper electrode 200 is formed on the dielectric layer. The material of the dielectric layer may be a high-K dielectric material to increase the capacitance of the capacitor per unit area, including one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx, or a stack of two or more of the above materials. The upper electrode 200 includes a metal nitride. and a compound formed by one or two of metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), or other conductive materials. In some embodiments, an upper electrode 200 covering the outer surface of the dielectric layer is formed by an atomic layer deposition process or a plasma vapor deposition process, a sputtering process, etc. In some embodiments, the upper electrode 200 not only covers the dielectric layer, but also fills the capacitor area CA. In other embodiments, the upper electrode 200 only covers the dielectric layer, and the preparation method further includes the step of forming a conductive filling layer, and the conductive filling layer is filled in the gap between the upper electrodes 200.

The lower electrode 190, the dielectric layer and the upper electrode 200 constitute a capacitor. In the preparation method provided in the embodiment of the present disclosure, the surface of the semiconductor column 110 and the side wall of the fifth through hole 450 are both used to deposit the lower electrode 190. This can increase the area of the lower electrode 190 while ensuring the supporting strength, thereby increasing the area of the formed capacitor and improving the capacity of the capacitor.

The present disclosure also provides a semiconductor structure formed by the above-mentioned preparation method. Referring to FIG. 2A to FIG. 2V , the semiconductor structure includes a semiconductor column 110, a word line structure 140 and an isolation spacer 150. The semiconductor column 110 extends along the first direction D1, and a plurality of semiconductor columns 110 are arranged in an array along the second direction D2 and the third direction D3. The word line structure 140 extends along the third direction D3, and a plurality of word lines are arranged along the second direction D2, each word line runs through a row of semiconductor columns 110 arranged along the third direction D3, and the semiconductor column 110 covers two opposite sides of the word line structure 140 in the second direction D2, and the area where the semiconductor column 110 contacts the word line structure 140 is used as a channel area. The isolation spacer 150 covers the sidewall of the word line structure 140 in the first direction D1, and the isolation spacer 150 runs through the semiconductor column 110, and the area where the semiconductor column 110 contacts the isolation spacer 150 is used as a first source and drain area and a second source and drain area.

The semiconductor structure provided by the embodiment of the present disclosure has a word line structure 140 with a controllable contour, which can greatly improve the reliability of the semiconductor structure. The sidewalls of the word line structure 140 are provided with isolation sidewalls 150, which can increase the supporting strength of the semiconductor structure. The isolation sidewalls 150 can also isolate the word line structure 140 from the first source and drain region and the second source and drain region, thereby reducing the leakage current between the word line structure 140 and the first source and drain region and the second source and drain region.

In some embodiments, the word line structure 140 includes a word line dielectric layer (not marked in the drawings) and a word line (not marked in the drawings), and the word line dielectric layer is disposed between the word line and the semiconductor pillar 110 to provide insulation isolation. The semiconductor pillars 110 located in the same column along the third direction D3 are penetrated by the same word line structure 140, that is, the semiconductor pillars 110 located in the same column along the third direction D3 share the same word line structure 140; the semiconductor pillars 110 located in the same row along the second direction D2 are penetrated by different word line structures 140, that is, the semiconductor pillars 110 located in the same row along the second direction D2 do not share the word line structure 140. In some embodiments, the two opposite side walls of the word line structure 140 along the second direction D2 are in contact with the semiconductor pillar 110, and the two opposite side walls of the word line structure 140 along the first direction D1 are in contact with the isolation spacer 150.

In some embodiments, in the first direction D1, the isolation spacers 150 are symmetrically disposed on both sides of the word line structure 140, that is, the isolation spacers 150 are symmetrically disposed on both sides of the word line structure 140 with the axis of the word line structure 140 as the symmetry axis. In other embodiments, in the first direction D1, the isolation spacers 150 may also be asymmetrically disposed on both sides of the word line structure 140.

In some embodiments, the semiconductor pillar 110 further includes a first metal silicide layer 160 and a second metal silicide layer 170. The first metal silicide layer 160 is in contact with the first source and drain regions, and the second metal silicide layer 170 is in contact with the second source and drain regions. The first metal silicide layer 160 and the second metal silicide layer 170 are both formed by metallizing the semiconductor pillar 110. The metal silicide layer 170 is located on the extension path of the semiconductor pillar 110 .

In some embodiments, the semiconductor structure further includes a capacitor region CA, the transistor region AA and the capacitor region CA are arranged along the first direction D1, the word line structure 140 and the isolation spacer 150 are located in the transistor region AA, the semiconductor column 110 extends from the transistor region AA to the capacitor region CA, and in the capacitor region CA, the semiconductor column 110 has a through hole (i.e., the fifth through hole 450 in FIG. 2T) that penetrates the semiconductor column 110 along the third direction D3. The capacitor region CA includes a lower electrode 190, a dielectric layer, and an upper electrode 200. The lower electrode 190 covers the surface of the semiconductor column 110 and the sidewall of the through hole; the dielectric layer covers the lower electrode 190; the upper electrode 200 covers the dielectric layer, the lower electrode 190, the dielectric layer, and the upper electrode 200 constitute a capacitor, and the semiconductor column 110 serves as a supporting structure of the capacitor. In some embodiments, one semiconductor column 110 corresponds to one capacitor, and each capacitor extends along the first direction D1, and multiple capacitors are arranged in an array along the second direction D2 and the third direction D3.

In some embodiments, the upper electrode 200 not only covers the dielectric layer but also fills the capacitor area CA. In other embodiments, the upper electrode 200 only covers the dielectric layer, and the semiconductor structure further includes a conductive filling layer, which fills the gaps between the upper electrodes 200 .

In some embodiments, the semiconductor structure further includes a bit line structure 180. In some embodiments, the bit line structure 180 is disposed on a side of the transistor region AA away from the capacitor region CA. The bit line structure 180 extends along the second direction D2, and a plurality of bit line structures 180 are arranged along the third direction D3. Each bit line structure 180 is connected to a row of semiconductor pillars 110 arranged along the second direction D2, and a column of semiconductor pillars 110 arranged along the third direction D3 is connected to different bit line structures 180.

In some embodiments, the bit line structure 180 is connected to the first metal silicide layer 160 , that is, the bit line structure 180 is connected to the first source and drain regions through the first metal silicide layer 160 , which greatly reduces the contact resistance between the bit line structure 180 and the first source and drain regions.

In the semiconductor structure provided in some embodiments of the present disclosure, due to the supporting effect of the isolation sidewall 150, the supporting strength of the semiconductor structure will not be reduced due to the existence of the through hole, and the surface of the semiconductor column 110 and the sidewall of the through hole are deposited with the lower electrode 190, which can increase the area of the lower electrode 190, thereby increasing the area of the formed capacitor and improving the capacity of the capacitor. That is, the semiconductor structure provided in some embodiments of the present disclosure can improve the capacity of the capacitor while ensuring the supporting strength.

The above are only preferred embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims (18)

1. A method for preparing a semiconductor structure, comprising:

   A substrate is provided, the substrate comprising a semiconductor column (110) and a first isolation column (120), the semiconductor column (110) extending along a first direction (D1), and a plurality of the semiconductor columns (110) being arranged in an array along a second direction (D2) and a third direction (D3), the first isolation column (120) extending along the third direction (D3), and a plurality of the first isolation columns (120) being arranged along the second direction (D2), each of the first isolation columns (120) penetrating a row of the semiconductor columns (110) arranged along the third direction (D3), and the semiconductor columns (110) surrounding the side surfaces of the first isolation columns (120);

   Removing a portion of the first isolation column (120) to form a first through hole (410), wherein the first through hole (410) extends along the third direction (D3), and opposite side walls of the first through hole (410) in the second direction (D2) expose the semiconductor column (110);

   A word line structure (140) is formed in the first through hole (410).
2. The method for preparing a semiconductor structure according to claim 1, wherein the method for forming the substrate comprises:

   Providing a stacked layer (100), the stacked layer (100) comprising a semiconductor layer (101) and a sacrificial layer (102) stacked in sequence along a third direction (D3);

   removing a portion of the stacked layer (100) along the third direction (D3) to form a plurality of first primary semiconductor structures (300) arranged along the second direction (D2);

   forming a second through hole (420), wherein the second through hole (420) extends along the third direction (D3), and a plurality of the second through holes (420) are arranged along the second direction (D2), and each of the second through holes (420) penetrates one of the first primary semiconductor structures (300);

   forming the first isolation column (120) in the second through hole (420);

   The sacrificial layer (102) is removed, and the remaining semiconductor layer (101) serves as the semiconductor column (110).
3. The method for preparing a semiconductor structure according to claim 2, wherein after the step of forming a plurality of first primary semiconductor structures (300) arranged along the second direction (D2), the method further comprises: forming a first dielectric layer (330), wherein the first dielectric layer (330) is filled between two adjacent first primary semiconductor structures (300); and before the step of removing the sacrificial layer (102), the method further comprises removing the first dielectric layer (330).
4. The method for preparing a semiconductor structure according to claim 3, wherein before the step of forming a plurality of first primary semiconductor structures (300) arranged along the second direction (D2), the method further comprises: forming a covering layer (103), wherein the covering layer (103) covers the surface of the stacked layer; in the step of forming a plurality of first primary semiconductor structures (300) arranged along the second direction (D2), the method further comprises removing a portion of the covering layer (103); in the step of forming a second through hole (420), the second through hole (420) also penetrates the covering layer (103); and in the step of removing the first dielectric layer (330), the method further comprises removing the remaining covering layer (103).
5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, wherein before the step of forming the first isolation column (120) in the second through hole (420), the method further comprises: Perform ion doping.
6. The method for preparing a semiconductor structure according to any one of claims 2 to 5, wherein the step of removing part of the stacked layer (100) along the third direction (D3) to form a plurality of first primary semiconductor structures (300) arranged along the second direction (D2) further comprises: forming a second primary semiconductor structure extending along the second direction (D2), the second primary semiconductor structure (310) being connected to one end of the plurality of first primary semiconductor structures (300) in the first direction (D1); and the step of removing the sacrificial layer (102) further comprises removing the sacrificial layer (102) in the second primary semiconductor structure (310);

   After the step of forming the word line structure (140) in the first through hole (410), the method further includes:

   removing the semiconductor layer (101) in the second primary semiconductor structure (310) to form a trench;

   A bit line structure (180) is formed in the trench, and the bit line structure (180) is connected to one end of the semiconductor column (110) in the first direction (D1).
7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, wherein before the step of removing part of the first isolation column (120) to form a first through hole (410), it also includes: forming a second dielectric layer (340), wherein the second dielectric layer (340) fills the gaps between the semiconductor columns (110) and between the first isolation columns (120).
8. The method for preparing a semiconductor structure according to any one of claims 2 to 6, wherein after the step of forming a word line structure (140) in the first through hole (410), the method further comprises:

   removing at least a portion of the first isolation column (120) located at both ends of the second through hole (420) in the first direction (D1) to expose the semiconductor column (110);

   The exposed semiconductor pillar (110) is subjected to metal silicide treatment to form a first metal silicide layer (160) and a second metal silicide layer (170).
9. The method for preparing a semiconductor structure according to claim 8, wherein, in the step of removing at least a portion of the first isolation column (120) located at both ends of the second through hole (420) in the first direction (D1), only a portion of the first isolation column (120) located at both ends of the second through hole (420) in the first direction (D1) is removed, and the first isolation column (120) covering the side wall of the word line structure (140) is retained as an isolation sidewall (150), and the area where the semiconductor column (110) contacts the isolation sidewall (150) serves as a first source and drain region and a second source and drain region, the first source and drain region contacts the first metal silicide layer (160), and the second source and drain region contacts the second metal silicide layer (170).
10. The method for preparing a semiconductor structure according to claim 8, wherein the step of removing at least a portion of the first isolation column (120) located at both ends of the second through hole (420) in the first direction (D1) comprises forming a third through hole (430) and a fourth through hole (440) respectively;

    The steps of performing metal silicide treatment on the exposed semiconductor column (110) include: filling metal material in the third through hole (430) and the fourth through hole (440); performing metal silicide treatment to form the semiconductor column (110) in contact with the metal material into the first metal silicide layer (160) and the second metal silicide layer (170); and removing the metal material.
11. The method for preparing a semiconductor structure according to claim 10, wherein after the step of performing metal silicide treatment on the exposed semiconductor pillar (110), the method further comprises: filling a third dielectric layer (350) in the third through hole (430) and the fourth through hole (440).
12. The method for preparing a semiconductor structure according to any one of claims 1 to 11, wherein the substrate comprises a transistor region (AA) and a capacitor region (CA) arranged along the first direction (D1), the semiconductor column (110) extends from the transistor region (AA) to the capacitor region (CA), and the first isolation column (120) penetrates a row of the semiconductor columns (110) arranged along the third direction (D3) in the transistor region (AA); the substrate further comprises a second isolation column (130), the second isolation column (130) extends along the third direction (D3), and a plurality of the second isolation columns (130) are arranged along the second direction (D2), in the capacitor region (CA), each of the second isolation columns (130) penetrates a row of the semiconductor columns (110) arranged along the third direction (D3), and the semiconductor column (110) surrounds the side surface of the second isolation column (130); after the step of forming a word line structure (140) in the first through hole (410), the method further comprises:

    Exposing the semiconductor column (110) of the capacitor region (CA), and removing the second isolation column (130) to form a fifth through hole (450) on the semiconductor column (110) that penetrates the semiconductor column (110);

    forming a lower electrode (190), wherein the lower electrode (190) covers the surface of the semiconductor column (110) and covers the side wall of the fifth through hole (450);

    A dielectric layer is formed on the lower electrode (190), and an upper electrode (200) is formed on the dielectric layer.
13. A semiconductor structure comprising:

    A semiconductor column (110) extending along a first direction (D1), and a plurality of the semiconductor columns (110) are arranged in an array along a second direction (D2) and a third direction (D3);

    A word line structure (140) extending along the third direction (D3), and a plurality of the word lines are arranged along the second direction (D2), each of the word lines passes through a row of the semiconductor pillars (110) arranged along the third direction (D3), and the semiconductor pillars (110) cover two opposite side surfaces of the word line structure (140) in the second direction (D2);

    An isolation sidewall (150), the isolation sidewall (150) covers the sidewall of the word line structure (140) in the first direction (D1), and the isolation sidewall (150) penetrates the semiconductor column (110).
14. The semiconductor structure according to claim 13, wherein in the first direction (D1), the isolation spacers (150) are symmetrically arranged on both sides of the word line structure (140).
15. The semiconductor structure according to claim 13 or 14, wherein the semiconductor column (110) further comprises a first metal silicide layer (160) and a second metal silicide layer (170), and the area where the semiconductor column (110) contacts the isolation sidewall (150) serves as a first source-drain region and a second source-drain region, the first source-drain region contacts the first metal silicide layer (160), and the second source-drain region contacts the second metal silicide layer (170).
16. The semiconductor structure according to any one of claims 13 to 15, wherein the semiconductor structure comprises a transistor region (AA) and a capacitor region (CA) arranged along the first direction (D1), the word line structure (140) and the isolation spacer (150) are located in the transistor region (AA) and the capacitor region (CA) are arranged along the first direction (D1), The semiconductor column (110) extends from the transistor region (AA) to the capacitor region (CA), and in the capacitor region (CA), the semiconductor column (110) has a through hole that penetrates the semiconductor column (110) along a third direction (D3), and the capacitor region (CA) comprises:

    A lower electrode (190) covering the surface of the semiconductor column (110) and the side wall of the through hole;

    A dielectric layer covering the lower electrode (190);

    An upper electrode (200) covers the dielectric layer.
17. The semiconductor structure according to any one of claims 13 to 16, wherein the semiconductor structure further comprises a bit line structure (180), the bit line structure (180) extends along the second direction (D2), and a plurality of the bit line structures (180) are arranged along the third direction (D3), and each of the bit line structures (180) is connected to a row of the semiconductor pillars (110) arranged along the second direction (D2).
18. The semiconductor structure according to claim 15, wherein, in the first direction (D1), the third dielectric layer (350) is disposed on a side of the isolation sidewall (150) opposite to the word line structure (140), and is in contact with the first metal silicide layer (160) and the second metal silicide layer (170).