WO2024099447A1

WO2024099447A1 - Semiconductor structure and preparation method therefor

Info

Publication number: WO2024099447A1
Application number: PCT/CN2023/131109
Authority: WO
Inventors: 邵光速
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-11
Filing date: 2023-11-10
Publication date: 2024-05-16
Also published as: CN118076092A

Abstract

A preparation method for a semiconductor structure. The preparation method comprises: providing a substrate, wherein the substrate comprises active columns arranged in an array and insulating layers arranged between the active columns; removing some of the active columns to form first via holes, which are defined by the insulating layers, in the tops of the active columns; forming a metal silicide in the first via holes; forming a dielectric layer provided with a second via hole, wherein the dielectric layer covers the insulating layers, and the second via hole exposes the metal silicide; etching the dielectric layer and the insulating layers from a bottom sidewall of the second via hole to form a groove, wherein the groove at least exposes some of the sidewalls of the metal silicide; and forming a conductive contact structure in the second via hole and the groove.

Description

Semiconductor structure and method for manufacturing the same

Related Application Citations

This application claims priority to Chinese Patent Application No. 202211415084.6 filed on November 11, 2022, entitled “Semiconductor Structure and Method for Making the Same,” the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same.

Background technique

With the development of dynamic random access memory (DRAM), in order to improve the storage capacity of memory, semiconductor devices are required to have higher integration density and smaller feature size. In order to improve the storage density, semiconductor devices have evolved from planar gates to all-around gates (Gate-All-Around, GAA for short). The all-around gate realizes the four-sided coverage of the channel by the gate, which improves the density of the memory. However, the preparation process of these memories is complex, and as the size of the memory is further reduced, the alignment between the transistor active pillar and the conductive contact structure is also challenging.

Summary of the invention

The technical problem to be solved by the present disclosure is to provide a semiconductor structure and a preparation method thereof, which has a simple preparation process and can achieve self-alignment of the active column and the conductive contact structure, reduce the contact resistance between the metal silicide and the conductive contact structure, and greatly improve the stability and reliability of the semiconductor structure.

In order to solve the above problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate comprising active pillars arranged in an array and an insulating layer arranged between the active pillars, the top surface of the active pillars being exposed to the surface of the substrate; removing part of the active pillars to form a first via hole defined by the insulating layer on the top of the active pillar; forming a metal silicide in the first via hole; forming a dielectric layer having a second via hole, the dielectric layer covering the insulating layer, the second via hole exposing the metal silicide; etching the dielectric layer and the insulating layer from the bottom side wall of the second via hole to form a groove, the groove at least exposing part of the side wall of the metal silicide; forming a conductive contact structure in the second via hole and the groove, the conductive contact structure being connected to the surface and at least part of the side surface of the metal silicide.

In one embodiment, in the step of providing the substrate, the top surface of the active pillar is lower than the surface of the insulating layer or flush with the surface of the insulating layer.

In one embodiment, the step of removing part of the active pillar includes: etching back the active pillar and retaining the insulating layer to form the first via hole.

In one embodiment, the step of forming metal silicide in the first via hole includes: forming polysilicon in the first via hole; and performing metallization treatment on the polysilicon to form the metal silicide.

In one embodiment, the step of forming the dielectric layer having the second via hole includes: forming a dielectric material layer, wherein the dielectric material layer covers the substrate and the metal silicide; and patterning the dielectric material layer to form the second via hole.

In one embodiment, before the step of etching the dielectric layer and the insulating layer from the bottom side wall of the second via hole, the step also includes: forming a side wall protection layer, the side wall protection layer covers the side wall of the second via hole, and has a notch at the bottom side wall of the second via hole, the notch exposes the bottom side wall of the second via hole; in the step of etching the dielectric layer and the insulating layer from the bottom side wall of the second via hole, the dielectric layer and the insulating layer are etched along the notch.

In one embodiment, the method for forming the sidewall protection layer includes: after the step of forming metal silicide in the first via hole, forming a dielectric material layer, the dielectric material layer covering the substrate and the metal silicide; forming an initial via hole in the dielectric material layer, the depth of the initial via hole being less than the depth of the second via hole; forming a protective material layer on the inner wall of the initial via hole; removing the protective material layer on the bottom wall of the initial via hole, and continuing to remove the dielectric material layer at the bottom of the initial via hole until the metal silicide is exposed to form the second via hole, and the protective material layer retained on the side wall of the initial via hole serves as the sidewall protection layer.

In one embodiment, in the step of etching the dielectric layer and the insulating layer from the sidewall of the bottom of the second via hole, the etching rate of the etching material on the dielectric layer and the insulating layer is greater than the etching rate on the sidewall protection layer.

In one embodiment, after the step of forming a conductive contact structure in the second via hole and the groove, the method further includes: forming a charge storage structure, wherein the charge storage structure is connected to the conductive contact structure.

An embodiment of the present disclosure also provides a semiconductor structure, which includes: a substrate, the substrate includes a vertical transistor array, the vertical transistor array includes active pillars arranged in an array, a bit line structure located at the bottom surface of the active pillars, and a word line structure arranged on the side of the active pillars; a metal silicide, which is arranged on the top surface of the active pillars; and a conductive contact structure, which is arranged on the metal silicide and connected to the surface and at least part of the side of the metal silicide.

In one embodiment, the substrate further includes an insulating layer, the insulating layer is disposed between the active pillars, and the top surface of the active pillars is lower than the top surface of the insulating layer, and the top surface of the metal silicide is flush with or lower than the top surface of the insulating layer.

In one embodiment, the semiconductor structure further includes a dielectric layer, the dielectric layer covers the insulating layer, and the conductive contact structure penetrates the dielectric layer and the insulating layer and is connected to the metal silicide.

In one embodiment, the conductive contact structure includes a first portion connected to the metal silicide and a second portion connected to the first portion, wherein a diameter of the first portion is greater than a diameter of the second portion.

In one embodiment, the diameter of the first portion is 1.2 to 1.5 times the diameter of the second portion.

In one embodiment, a portion of the side surfaces of the first portion of the conductive contact structure contacts the insulating layer, another portion of the side surfaces contacts the dielectric layer, and all of the side surfaces of the second portion of the conductive contact structure contacts the dielectric layer.

In one embodiment, the semiconductor structure further includes a sidewall protection layer, and the sidewall protection layer is disposed between the second portion of the conductive contact structure and the dielectric layer.

In one embodiment, a charge storage structure is further included, and the charge storage structure is disposed on the conductive contact structure and connected to the conductive contact structure.

The semiconductor structure and preparation method provided by the embodiment of the present disclosure use the insulating layer between the active pillars as a limiting structure to achieve self-alignment, and there is no need to set up an additional alignment structure to remove the top of the active pillar, which reduces the photomask, greatly reduces the process difficulty, simplifies the process, and saves costs. At the same time, the preparation method also uses the groove to increase the exposed surface area of the metal silicide, thereby increasing the contact area between the conductive contact structure and the metal silicide, reducing the contact resistance between the conductive contact structure and the metal silicide, and further improving the stability and reliability of the semiconductor structure. .

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by a first embodiment of the present disclosure;

2A to 2G are schematic diagrams of semiconductor structures formed by main process steps of the preparation method provided in the first embodiment of the present disclosure;

3A to 3F are schematic diagrams of semiconductor structures formed by main process steps of the preparation method provided in the second embodiment of the present disclosure.

Detailed ways

The specific implementation of the semiconductor structure and the preparation method thereof provided by the present disclosure is described in detail below in conjunction with the accompanying drawings. The semiconductor structure described in this specific implementation may be, but is not limited to, a DRAM.

FIG1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by a first embodiment of the present disclosure. Please refer to FIG1 , the method comprises: step S10, providing a substrate, the substrate comprising active pillars arranged in an array and an insulating layer disposed between the active pillars, the top surface of the active pillars being exposed to the surface of the substrate; step S11, removing a portion of the active pillars to form a first via hole defined by the insulating layer on the top of the active pillars; step S12, forming a metal silicide in the first via hole; step S13, forming a dielectric layer having a second via hole, the dielectric layer covering the insulating layer, the second via hole exposing the metal silicide; step S14, etching the dielectric layer and the second via hole from the bottom sidewall of the second via hole The insulating layer forms a groove, and the groove at least exposes a portion of the side wall of the metal silicide; step S15, forming a conductive contact structure in the second via hole and the groove, and the conductive contact structure is connected to the surface and at least a portion of the side of the metal silicide.

2A to 2G are schematic diagrams of a semiconductor structure formed by main process steps of the preparation method provided in the first embodiment of the present disclosure.

Please refer to Figures 1, 2A and 2B, wherein Figure 2A is a top view, and Figure 2B is a cross-sectional view along line A-A' in Figure 2A. In step S10, a substrate is provided, wherein the substrate includes active pillars 110 arranged in an array and an insulating layer 120 disposed between the active pillars 110, and the top surfaces of the active pillars 110 are exposed to the surface of the substrate.

In some embodiments, each of the active pillars 110 extends in a direction perpendicular to the top surface of the substrate (such as the Z direction in Figure 2B), and multiple active pillars 110 are arranged in an array in a direction parallel to the top surface of the substrate (such as the X direction and the Y direction in Figure 2A), and the insulating layer 120 is filled between adjacent active pillars 110 to support the active pillars 110.

In some embodiments, the base further includes a substrate 101, a plurality of bit line structures 130, and a plurality of word line structures 140. The bit line structures 130, the active pillars 110, and the word line structures 140 constitute a vertical transistor. The active pillars 110 arranged in an array, the bit line structures 130 located at the bottom of the active pillars 110, and the word line structures 140 disposed on the sides of the active pillars 110 constitute a vertical transistor array.

The substrate 101 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 101 may also be a stacked structure, such as a silicon/silicon germanium stack, etc.; in addition, the substrate 101 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 101, such as field effect transistors, capacitors, inductors and/or diodes, etc. In this embodiment, the substrate 101 is a silicon substrate, and other device structures may also be included therein, such as a transistor structure, a metal wiring structure, etc., but they are not shown because they are not related to the present application.

The bit line structure 130 is arranged on the surface of the substrate 101 and extends in a direction parallel to the top surface of the substrate (such as the Y direction in FIG. 2A ). A plurality of the bit line structures 130 are arranged at intervals in a direction parallel to the top surface of the substrate (such as the X direction in FIG. 2A ). The active pillar 110 is arranged on the bit line structure 130, that is, the bit line structure 130 is located on the bottom surface of the active pillar 110 and is connected to the active pillar 110. The bit line structure 130 is a conductive structure, including but not limited to a polysilicon layer, a metal tungsten layer, a titanium nitride layer and a combination thereof. An insulating isolation layer (not shown in the drawings) is filled between adjacent bit line structures 130, and the insulating isolation layer may be an oxide layer or a nitride layer. In FIG. 2A , the bit line structures 130 are electrically conductive. The wire structure 130 is blocked by the insulating layer 120 and is therefore illustrated with a dotted line.

The word line structure 140 is disposed on the side of the active pillar 110 and extends in a direction parallel to the top surface of the substrate (such as the X direction in FIG. 2A ). A plurality of the word line structures 140 are arranged at intervals in a direction parallel to the top surface of the substrate (such as the Y direction in FIG. 2A ). In some embodiments, the active pillar 110 is a rectangular pillar, and the word line structure 140 surrounds four sides of the active pillar 110. In other embodiments, the word line structure 140 surrounds part of the side of the active pillar 110, such as the opposite side of the active pillar 110, or three adjacent side surfaces. In this embodiment, the word line structure 140 surrounds four sides (i.e., all sides) of the active pillar 110 as an example for description.

The word line structure 140 includes a gate dielectric layer 141 and a conductive layer 142, wherein the gate dielectric layer 141 is disposed between the active pillar 110 and the conductive layer 142 to isolate the active pillar 110 from the conductive layer 142. The gate dielectric layer 141 includes but is not limited to a silicon dioxide layer or a high-K dielectric layer, and the conductive layer 142 includes but is not limited to a polysilicon layer, a metal tungsten layer, a titanium nitride layer, and a combination thereof. The insulating layer 120 covers the surface of the word line structure 140 and is used to isolate adjacent word line structures 140. The insulating layer 120 is also disposed between the bit line structure 130 and the word line structure 140 to prevent the bit line structure 130 from being conductive with the word line structure 140. In FIG. 2A , the word line structure 140 is blocked by the insulating layer 120 and is therefore depicted in dashed lines.

The insulating layer 120 includes but is not limited to a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer. In this embodiment, the insulating layer 120 is a silicon nitride layer as an example for description.

The top surface of the active pillar 110 is not covered by the insulating layer 120, but is exposed to the surface of the insulating layer 120. In some embodiments, the top surface of the active pillar 110 is lower than the surface of the insulating layer 120 or is flush with the surface of the insulating layer 120. For example, in this embodiment, the top surface of the active pillar 110 is flush with the surface of the insulating layer 120.

Please refer to Figures 1 and 2C, wherein Figure 2C is a cross-sectional view along the position indicated by the A-A’ line in Figure 2A. In step S11, a portion of the active pillar 110 is removed to form a first via 150 defined by the insulating layer 120 on the top of the active pillar 110.

In this step, the insulating layer 120 is used as a mask to etch back the active pillar 110, and the insulating layer 120 is retained to form the first via hole 150. The active pillar 110 may be etched back by a process such as dry etching. The depth of the first via hole 150 may be determined according to the thickness requirement of the metal silicide formed in the subsequent process.

When removing the active pillars 110 , the insulating layer 120 disposed between the active pillars 110 is used as a shield to achieve self-alignment without the need to additionally provide an alignment structure for removing the active pillars 110 , thereby greatly reducing the process difficulty and simplifying the process.

Please refer to FIG. 1 and FIG. 2D , wherein FIG. 2D is a cross-sectional view along the position indicated by the line AA′ in FIG. 2A , step S12, A metal silicide 160 is formed in the first via hole 150 , and the metal silicide 160 covers the top surface of the active pillar 110 to reduce the contact resistance between a conductive contact structure formed subsequently and the active pillar 110 .

In this embodiment, the top surface of the metal silicide 160 is flush with the top surface of the insulating layer 120 . In other embodiments, the top surface of the metal silicide 160 may also be lower than the top surface of the insulating layer 120 .

As an example, the embodiment of the present disclosure provides a method for forming the metal silicide 160, the method comprising: depositing polysilicon in the first via hole 150; performing metallization treatment on the polysilicon to form the metal silicide 160. The metallization treatment on the polysilicon comprises: depositing metal on the surface of the polysilicon; performing annealing treatment. The metal silicide 160 includes but is not limited to WSi ₂ , TiSi ₂ , CoSi ₂ and NiPtSi.

Please refer to Figures 1 and 2E, wherein Figure 2E is a cross-sectional view along the position indicated by the A-A’ line in Figure 2A. In step S13, a dielectric layer 170 having a second via hole 171 is formed. The dielectric layer 170 covers the insulating layer 120, and the second via hole 171 exposes the metal silicide 160.

In this embodiment, the second via 171 exposes the entire top surface of the metal silicide 160 , while in other embodiments, the second via 171 exposes a portion of the top surface of the metal silicide 160 , that is, a portion of the top surface of the metal silicide 160 is blocked by the dielectric layer 170 , and another portion of the top surface is exposed to the second via 171 .

As an example, an embodiment of the present disclosure provides a method for forming a dielectric layer 170 having a second via hole 171. The method includes:

A dielectric material layer is formed, and the dielectric material layer covers the substrate and the metal silicide 160. In this embodiment, the dielectric material layer covers the insulating layer 120 and the metal silicide 160. In this step, the dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition and other processes. The dielectric material layer includes but is not limited to oxide, nitride or oxynitride. In this embodiment, the dielectric material layer is a silicon nitride layer as an example for description.

The dielectric material layer is patterned to form the second via hole 171. In this step, a patterned photoresist layer may be formed on the surface of the dielectric material layer, and the dielectric material layer is etched using the photoresist layer as a mask to form a dielectric layer 170 having the second via hole 171. In this embodiment, after the second via hole 171 is formed, the photoresist layer is removed to expose the dielectric layer 170. In other embodiments, the photoresist layer may be retained, and the photoresist layer and the dielectric layer 170 serve as a mask layer together in subsequent processes.

Please refer to Figures 1 and 2F, wherein Figure 2F is a cross-sectional view along the position indicated by the A-A’ line in Figure 2A. In step S14, the dielectric layer 170 and the insulating layer 120 are etched from the bottom sidewall of the second via hole 171 to form a groove 172, and the groove 172 at least exposes a portion of the sidewall of the metal silicide 160.

The groove 172 extends toward the inside of the dielectric layer 170 and the insulating layer 120, thereby exposing the gold The groove 172 exposes at least a portion of the sidewall of the metal silicide 160 covered by the insulating layer 120. In this embodiment, the groove only exposes a portion of the sidewall of the metal silicide 160 covered by the insulating layer 120 to ensure that the groove 172 is not too deep to expose the active pillar 110. In other embodiments, the groove 172 exposes the entire sidewall of the metal silicide 160 covered by the insulating layer 120 to maximize the contact area between the subsequently formed conductive contact structure and the metal silicide 160.

As an example, in this embodiment, the Bosch etching process can be used to form the second via hole 171 and the groove 172. Specifically, in the step of forming the dielectric layer 170 having the second via hole 171, the dielectric material layer is first etched to form an initial via hole, and the etching depth of the initial via hole is less than the depth of the second via hole 171; the inner wall of the initial via hole is passivated to form a passivation layer; the passivation layer at the bottom of the initial via hole is removed by ion bombardment; the dielectric material layer at the bottom of the initial via hole is etched by an isotropic etching process to form the second via hole 171, and the dielectric material layer is continuously etched to expose the insulating layer 120; the insulating layer 120 is continuously etched to form the groove 172. It can be understood that in some embodiments, while etching the insulating layer 120, the dielectric material layer will continue to be etched to form the groove 172, so as to form a sufficiently large groove 172 to provide sufficient deposition space for the subsequent formation of a conductive contact structure, thereby avoiding the conductive contact structure being formed discontinuous due to insufficient deposition space in the groove 172.

In other embodiments, before forming the groove 172, the second via 171 only exposes a portion of the surface of the metal silicide 160, that is, a portion of the surface of the metal silicide 160 is covered by the dielectric layer 170. In the step of forming the groove, the dielectric layer 170 covering a portion of the surface of the metal silicide 160 is removed, and the entire top surface of the metal silicide 160 is exposed, and then the insulating layer 120 is removed to expose at least a portion of the side wall of the metal silicide 160.

Please refer to FIG. 1 and FIG. 2G, wherein FIG. 2G is a cross-sectional view along the position indicated by the line A-A' in FIG. 2A, step S15, forming a conductive contact structure 180 in the second via hole 171 and the groove 172, the conductive contact structure 180 being connected to the surface and at least a part of the side surface of the metal silicide 160. The conductive contact structure 180 fills the second via hole 171 and the groove 172, and covers the surface and side surface of the metal silicide 160 exposed in the second via hole 171 and the groove 172.

In this step, a conductive contact structure 180 may be formed in the second via hole 171 and the groove 172 by atomic layer deposition, vacuum evaporation, magnetron sputtering, chemical vapor deposition or physical vapor deposition. The material of the conductive contact structure 180 may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium TaTi, tungsten nitride (WN), copper (Cu) and aluminum (Al).

After the step of forming the conductive contact structure 180, the manufacturing method further includes: forming a charge storage structure (not shown in the drawings), the charge storage structure being connected to the conductive contact structure 180. The charge storage structure includes but is not limited to a capacitor, the lower electrode of the capacitor being electrically connected to the conductive contact structure 180.

The method for preparing the semiconductor structure provided by the embodiment of the present disclosure utilizes the insulating layer 120 between the active pillars 110 as a limiting structure to achieve self-alignment, and there is no need to set up an additional alignment structure in order to remove the top of the active pillar 110, thereby reducing the photomask, greatly reducing the process difficulty, simplifying the process, and saving costs. At the same time, the preparation method also utilizes the groove 172 to increase the exposed surface area of the metal silicide 160, thereby increasing the contact area between the conductive contact structure 180 and the metal silicide 160, reducing the contact resistance between the conductive contact structure 180 and the metal silicide 160, and further improving the stability and reliability of the semiconductor structure.

In some embodiments, such as the first embodiment, the second via hole 171 and the groove 172 are formed by a Bosch etching process. Another embodiment of the present disclosure further provides a method for forming the groove 172, specifically, forming a sidewall protection layer 190, the sidewall protection layer 190 covers the sidewall of the second via hole 171, and has a notch 191 at the bottom sidewall of the second via hole 171, the notch 191 exposes the bottom sidewall of the second via hole 171; and etching the dielectric layer 170 and the insulating layer 120 along the notch 191. The sidewall protection layer 190 is used to protect the sidewall of the second via hole 171 when etching the dielectric layer 170 and the insulating layer 120 to prevent it from being etched, thereby forming a conductive contact structure 180 that meets the design requirements in subsequent process steps.

As an example, the second embodiment of the present disclosure provides a method for forming the sidewall protection layer 190. The method includes:

Please refer to FIG3A, which is a cross-sectional view along the position indicated by the line A-A' in FIG2A. After the step of forming the metal silicide 160 in the first via hole 150 (please refer to FIG2D), a dielectric material layer 300 is formed, and the dielectric material layer 300 covers the substrate and the metal silicide 160. In this embodiment, the dielectric material layer 300 covers the insulating layer 120 and the metal silicide 160. In this step, the method and material for forming the dielectric material layer 300 are the same as those in the first embodiment, and will not be described in detail.

Please refer to FIG. 3B , which is a cross-sectional view along the position indicated by the line A-A’ in FIG. 2A , in which an initial via hole 301 is formed in the dielectric material layer 300, and the depth of the initial via hole 301 is less than the depth of the second via hole 171. The depth of the initial via hole 301 can be determined according to the height of the groove 172 formed subsequently, for example, the difference between the depth of the initial via hole 301 and the depth of the second via hole 171 is equal to half the height of the groove 172.

Please refer to FIG. 3C, which is a cross-sectional view along the position indicated by the line AA' in FIG. 2A, where a protective material layer 302 is formed on the inner wall of the initial via hole 301. The protective material layer 302 covers the sidewalls and bottom wall of the initial via hole 301. In an embodiment, the protective material layer 302 may be formed by chemical vapor deposition process and atomic layer deposition process.

Please refer to Figure 3D, which is a cross-sectional view along the position indicated by the A-A’ line in Figure 2A. The protective material layer 302 on the bottom wall of the initial via 301 is removed, and the dielectric material layer 300 at the bottom of the initial via 301 is further removed until the metal silicide 160 is exposed to form the second via 171. The protective material layer 302 retained on the side wall of the initial via 301 serves as the side wall protection layer 190.

Please refer to FIG. 3E , which is a cross-sectional view along the position indicated by the line A-A’ in FIG. 2A , with the sidewall protection layer 190 as a shield, the dielectric layer 170 is etched at the bottom sidewall position of the bottom of the second via 171 that is not covered by the sidewall protection layer 190 to expose the insulating layer 120; after exposing the insulating layer 120, the insulating layer 120 is further etched to form a groove 172, and the groove 172 at least exposes part of the sidewall of the metal silicide 160. It can be understood that in some embodiments, while etching the insulating layer 120, the dielectric layer 170 will also be further etched to form the groove 172, so as to form a sufficiently large groove 172 to provide sufficient deposition space for the subsequent formation of the conductive contact structure 180.

In some embodiments, the etching rate of the etching material on the dielectric layer 170 and the insulating layer 120 is greater than the etching rate on the sidewall protection layer 190, and the sidewall protection layer 190 is not etched or is only slightly etched when etching the dielectric layer 170 and the insulating layer 120, so as to provide good protection for the sidewall of the second via hole 171 covered by the sidewall protection layer 190. For example, in some embodiments, the material of the dielectric layer 170 and the insulating layer 120 is silicon nitride, and the material of the sidewall protection layer 190 is silicon dioxide, and an etching material with a low etching rate for silicon dioxide and a high etching rate for silicon nitride can be selected for etching.

Please refer to FIG. 3F , which is a cross-sectional view along the position indicated by the line A-A′ in FIG. 2A , a conductive contact structure 180 is formed in the second via hole 171 and the groove 172, and the conductive contact structure 180 is connected to the surface and at least part of the side surface of the metal silicide 160. The method for forming the conductive contact structure 180 is the same as the method for forming the conductive contact structure 180 of the first embodiment, and will not be described in detail.

In a second embodiment, the sidewall protection layer 190 is retained, the conductive contact structure 180 covers the sidewall protection layer 190 and fills the groove 172 and the second via 171. In other embodiments, before forming the conductive contact structure 180, the sidewall protection layer 190 is removed, and the conductive contact structure 180 fills the side walls of the second via 171 and the groove 172.

The third embodiment of the present disclosure further provides a semiconductor structure prepared by the above preparation method. Referring to FIG. 2A to FIG. 2G , in this embodiment, the semiconductor structure includes a substrate, a metal silicide 160 and a conductive contact structure 180 .

The substrate includes a vertical transistor array, the vertical transistor array includes active pillars 110 arranged in an array, The bit line structure 130 is disposed on the bottom surface of the active pillar 110 , and the word line structure 140 is disposed on the side surface of the active pillar 110 .

In this embodiment, the substrate further includes a substrate 101. The bit line structure 130 is disposed on the surface of the substrate 101 and extends in a direction parallel to the top surface of the substrate (such as the Y direction in FIG. 2A ), and a plurality of the bit line structures 130 are arranged at intervals in a direction parallel to the top surface of the substrate (such as the X direction in FIG. 2A ). The active pillar 110 is disposed on the bit line structure 130, and an insulating isolation layer (not shown in the drawings) is filled between adjacent bit line structures 130. The word line structure 140 is disposed on the side of the active pillar 110 and extends in a direction parallel to the top surface of the substrate (such as the X direction in FIG. 2A ), and a plurality of the word line structures 140 are arranged at intervals in a direction parallel to the top surface of the substrate (such as the Y direction in FIG. 2A ). The word line structure 140 includes a gate dielectric layer 170141 and a conductive layer 142, and the gate dielectric layer 170141 is disposed between the active pillar 110 and the conductive layer 142 to isolate the active pillar 110 from the conductive layer 142.

The substrate further includes an insulating layer 120, and the insulating layer 120 is disposed between the active pillars 110, and the top surface of the active pillars 110 is lower than the top surface of the insulating layer 120. The insulating layer 120 also covers the surface of the bit line structure 130 and the surface of the word line structure 140, and isolates the bit line structure 130 from the word line structure 140 and two adjacent word line structures 140, so as to prevent the bit line structure 130 from being conductive with the word line structure 140 and two adjacent word line structures 140 from being conductive.

The metal silicide 160 is disposed on the top surface of the active pillar 110. The top surface of the metal silicide 160 is flush with or lower than the top surface of the insulating layer 120. In this embodiment, the top surface of the metal silicide 160 is flush with the top surface of the insulating layer 120 as an example for description.

The conductive contact structure 180 is disposed on the metal silicide 160 and is connected to the surface and at least part of the side surfaces of the metal silicide 160. In this embodiment, the bottom surface of the conductive contact structure 180 is connected to the surface and part of the side surfaces of the metal silicide 160, while in other embodiments, the bottom surface of the conductive contact structure 180 is connected to the surface and all the side surfaces of the metal silicide 160, so as to further increase the contact area between the conductive contact structure 180 and the metal silicide 160, thereby further reducing the contact resistance between the conductive contact structure 180 and the metal silicide 160.

In some embodiments, the semiconductor structure further includes a dielectric layer 170 , the dielectric layer 170 covers the insulating layer 120 , the conductive contact structure 180 penetrates the dielectric layer 170 and the insulating layer 120 and is connected to the metal silicide 160 , and the dielectric layer 170 is used to support and protect the conductive contact structure 180 .

In this embodiment, the conductive contact structure 180 includes a first portion 181 connected to the metal silicide 160 and a second portion 182 connected to the first portion 181, wherein the diameter of the first portion 181 is greater than the diameter of the second portion 182. The conductive contact structure 180 is a structure with a bulged bottom to improve the conductive contact structure 180. The contact area between the bottom surface and the metal silicide 160 reduces the contact resistance between the conductive contact structure 180 and the metal silicide 160; and the top area of the conductive contact structure 180 is smaller than the bottom area, which can reduce the material usage of the conductive contact structure 180 while increasing the contact area, saving costs, and will not increase the top area of the conductive contact structure 180, which is conducive to optimizing the layout design.

In some embodiments, the diameter of the first portion 181 is 1.2 to 1.5 times the diameter of the second portion 182 , so as to increase the contact area between the conductive contact structure 180 and the metal silicide 160 while ensuring the reliability of electrical transmission of the conductive contact structure 180 .

In some embodiments, a portion of the side surface of the first portion 181 of the conductive contact structure 180 contacts the insulating layer 120, another portion of the side surface contacts the dielectric layer 170, and all of the side surfaces of the second portion 182 of the conductive contact structure 180 contacts the dielectric layer 170. For example, in the horizontal direction, the region of the conductive contact structure 180 corresponding to the side surface of the metal silicide 160 contacts the insulating layer 120, and the region not corresponding to the side surface of the metal silicide 160 contacts the dielectric layer 170.

In some embodiments, the semiconductor structure further includes a charge storage structure (not shown in the drawings), which is disposed on the conductive contact structure 180 and connected to the conductive contact structure 180. The charge storage structure includes but is not limited to a capacitor, and a lower electrode of the capacitor is electrically connected to the conductive contact structure 180.

The fourth embodiment of the present disclosure further provides a semiconductor structure, please refer to Figures 3A to 3F. In this embodiment, the semiconductor structure further includes a sidewall protection layer 190, and the sidewall protection layer 190 is disposed between the second portion 182 of the conductive contact structure 180 and the dielectric layer 170. The material of the sidewall protection layer 190 is different from that of the dielectric layer 170 and the insulating layer 120. In the etching process, the sidewall protection layer 190 is not etched or is only slightly etched, so as to provide good protection for the sidewalls of the second via holes 171 covered by the sidewall protection layer 190.

In the semiconductor structure provided by the embodiment of the present disclosure, the contact area between the conductive contact structure 180 and the metal silicide 160 is large, so that the contact resistance between the two is small, thereby improving the reliability and stability of the semiconductor structure.

The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

A method for preparing a semiconductor structure, comprising:

Providing a substrate, the substrate comprising active pillars (110) arranged in an array and an insulating layer (120) disposed between the active pillars (110), wherein the top surfaces of the active pillars (110) are exposed to the surface of the substrate;

Removing a portion of the active pillar (110) to form a first via hole (150) defined by the insulating layer (120) on the top of the active pillar (110);

forming a metal silicide (160) in the first via hole (150);

forming a dielectric layer (170) having a second via hole (171), wherein the dielectric layer (170) covers the insulating layer (120), and the second via hole (171) exposes the metal silicide (160);

The dielectric layer (170) and the insulating layer (120) are etched from the bottom sidewall of the second via hole (171) to form a groove (172), wherein the groove (172) at least exposes a portion of the sidewall of the metal silicide (160);

A conductive contact structure (180) is formed in the second via hole (171) and the groove (172), and the conductive contact structure (180) is connected to the surface and at least part of the side surface of the metal silicide (160).
The method for preparing a semiconductor structure according to claim 1, wherein, in the step of providing a substrate, a top surface of the active pillar (110) is lower than a surface of the insulating layer (120) or is flush with a surface of the insulating layer (120).
The method for preparing a semiconductor structure according to claim 1 or 2, wherein the step of removing part of the active pillar (110) comprises: etching back the active pillar (110), retaining the insulating layer (120), and forming the first via hole (150).
The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein the step of forming a metal silicide (160) in the first via hole (150) comprises:

forming polysilicon in the first via hole (150);

The polysilicon is subjected to a metallization process to form the metal silicide (160).
The method for preparing a semiconductor structure according to any one of claims 1 to 4, wherein the step of forming a dielectric layer (170) having a second via hole (171) comprises:

forming a dielectric material layer, wherein the dielectric material layer covers the substrate and the metal silicide (160);

The dielectric material layer is patterned to form the second via hole (171).
The method for preparing a semiconductor structure according to any one of claims 1 to 5, wherein before the step of etching the dielectric layer (170) and the insulating layer (120) from the bottom sidewall of the second via hole (171), the step further comprises:

A side wall protection layer (190) is formed, wherein the side wall protection layer (190) covers the side wall of the second via hole (171), and A notch (191) is provided at the bottom side wall of the second via hole (171), and the notch (191) exposes the bottom side wall of the second via hole (171);

In the step of etching the dielectric layer (170) and the insulating layer (120) from the bottom side wall of the second via hole (171), the dielectric layer (170) and the insulating layer (120) are etched along the notch (191).
The method for preparing a semiconductor structure according to claim 6, wherein the method for forming the sidewall protection layer (190) comprises:

After the step of forming a metal silicide (160) in the first via hole (150), forming a dielectric material layer (300), wherein the dielectric material layer (300) covers the substrate and the metal silicide (160);

forming an initial via hole (301) in the dielectric material layer (300), wherein the depth of the initial via hole (301) is less than the depth of the second via hole (171);

forming a protective material layer (302) on the inner wall of the initial via hole (301);

The protective material layer (302) on the bottom wall of the initial via hole (301) is removed, and the dielectric material layer (300) at the bottom of the initial via hole (301) is further removed until the metal silicide (160) is exposed to form the second via hole (171), and the protective material layer (302) retained on the side wall of the initial via hole (301) serves as the side wall protective layer (190).
The method for preparing a semiconductor structure according to claim 6 or 7, wherein, in the step of etching the dielectric layer (170) and the insulating layer (120) from the bottom side wall of the second via hole (171), the etching rate of the etching material on the dielectric layer (170) and the insulating layer (120) is greater than the etching rate on the side wall protection layer (190).
The method for preparing a semiconductor structure according to any one of claims 1 to 8, wherein after the step of forming a conductive contact structure (180) in the second via hole (171) and the groove (172), the method further includes: forming a charge storage structure, wherein the charge storage structure is connected to the conductive contact structure (180).
A semiconductor structure comprising:

A substrate, the substrate comprising a vertical transistor array, the vertical transistor array comprising active pillars (110) arranged in an array, a bit line structure (130) located at the bottom surface of the active pillars (110), and a word line structure (140) arranged on the side of the active pillars (110);

A metal silicide (160) is disposed on the top surface of the active pillar (110);

The conductive contact structure (180) is disposed on the metal silicide (160) and is connected to the surface and at least part of the side surface of the metal silicide (160).
The semiconductor structure according to claim 10, wherein the substrate further comprises an insulating layer (120), the insulating layer The layer (120) is arranged between the active pillars (110), and the top surface of the active pillars (110) is lower than the top surface of the insulating layer (120), and the top surface of the metal silicide (160) is flush with the top surface of the insulating layer (120) or lower than the top surface of the insulating layer (120).
The semiconductor structure according to claim 11, wherein the semiconductor structure further comprises a dielectric layer (170), the dielectric layer (170) covers the insulating layer (120), and the conductive contact structure (180) penetrates the dielectric layer (170) and the insulating layer (120) and is connected to the metal silicide (160).
The semiconductor structure according to claim 12, wherein the conductive contact structure (180) includes a first portion (181) connected to the metal silicide (160) and a second portion (182) connected to the first portion (181), wherein a diameter of the first portion (181) is greater than a diameter of the second portion (182).
The semiconductor structure according to claim 13, wherein the diameter of the first portion (181) is 1.2 to 1.5 times the diameter of the second portion (182).
A semiconductor structure according to claim 13 or 14, wherein a portion of the side surfaces of the first portion (181) of the conductive contact structure (180) contacts the insulating layer (120), another portion of the side surfaces contacts the dielectric layer (170), and all of the side surfaces of the second portion (182) of the conductive contact structure (180) contacts the dielectric layer (170).
The semiconductor structure according to any one of claims 13 to 15, wherein the semiconductor structure further comprises a sidewall protection layer (190), and the sidewall protection layer (190) is arranged between the second portion (182) of the conductive contact structure (180) and the dielectric layer (170).
The semiconductor structure according to any one of claims 10 to 16, further comprising a charge storage structure, wherein the charge storage structure is arranged on the conductive contact structure (180) and connected to the conductive contact structure (180).