WO2024093021A1

WO2024093021A1 - Semiconductor structure and preparation method therefor

Info

Publication number: WO2024093021A1
Application number: PCT/CN2023/070662
Authority: WO
Inventors: 宛伟
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-04
Filing date: 2023-01-05
Publication date: 2024-05-10
Also published as: CN118042823A

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate, which comprises an array area, a peripheral area, and a contact area located between the array area and the peripheral area; and a word line, which extends through the array area and the contact area to the peripheral area, and comprises a first part, a second part and a third part, wherein the first part is located in the array area, the second part is located in the contact area, the third part is located in the peripheral area, and the top surface of the second part is arranged staggered from the top surface of the first part and the top surface of the third part. During the preparation of the semiconductor structure, in the second part, a polycrystalline silicon layer on the surface of the word line can be removed before a via hole for accommodating a conductive contact structure is formed, or the polycrystalline silicon layer is not directly formed on the surface of the word line, such that residual polycrystalline silicon caused by insufficient removal of the polycrystalline silicon layer can be avoided, thereby avoiding an open circuit between the word line and the conductive contact structure, and thus improving the reliability of the semiconductor structure.

Description

Semiconductor structure and method for manufacturing the same

Related Application Citations

This application claims priority to Chinese Patent Application No. 202211376958.1, filed on November 4, 2022, and entitled “Semiconductor Structure and Method for Making the Same,” the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same.

Background technique

Semiconductor memory structures can be classified as volatile memory devices (in which the stored data disappears when the power supply is interrupted, such as static random access memory (SRAM) or dynamic random access memory (DRAM)), or non-volatile memory devices (in which the stored data is retained even when the power supply is interrupted, such as flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) or ferroelectric RAM (FRAM)).

DRAM includes memory cells, which are connected to word lines. In a read operation or a write operation of the DRAM, when a high voltage is applied to a selected word line, the selected word line is enabled, and the read and write operations on the memory cell are realized. However, in the contact area between the array area and the peripheral area of the DRAM, there may be a circuit break problem between the word line and the conductive contact structure, which may easily cause DRAM failure and reduce the reliability of the DRAM.

Summary of the invention

The technical problem to be solved by the present disclosure is to provide a semiconductor structure and a preparation method thereof, which can avoid the word line short circuit problem and improve the reliability of the semiconductor structure.

In order to solve the above problems, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, the substrate including an array area, a peripheral area and a contact area located between the array area and the peripheral area; a word line, the word line extends through the array area and the contact area to the peripheral area, the word line includes a first part, a second part and a third part, the first part is located in the array area, the second part is located in the contact area, the third part is located in the peripheral area, and the top surface of the second part is staggered with the top surface of the first part and the top surface of the third part.

In one embodiment, a top surface of the first portion is flush with a top surface of the third portion.

In one embodiment, the word line includes a metal conductive layer and a polysilicon layer, the polysilicon layer is located above the metal conductive layer, and the second portion of the word line does not include the polysilicon layer.

In one embodiment, the semiconductor structure further includes a conductive contact structure disposed in the contact region, the conductive contact structure being electrically connected to the second portion, and the orthographic projection of the conductive contact structure on the substrate surface being located inside the orthographic projection of the second portion on the substrate surface.

In one embodiment, it includes a plurality of word lines extending along a first direction, the plurality of word lines are arranged at intervals in a second direction, the first direction and the second direction intersect and are both parallel to the surface of the substrate; along the second direction, the top surface heights of the second portions of adjacent word lines are different.

In one embodiment, along the second direction, only the second portion of one of the two adjacent word lines includes the polysilicon layer.

In one embodiment, the semiconductor structure also includes a conductive contact structure arranged in the contact area, the conductive contact structure is electrically connected to the second part, the size of the conductive contact structure in the first direction is the same as the size of the second part, and the size of the conductive contact structure in the second direction is larger than the size of the second part.

In one embodiment, the first part and the third part both include a metal conductive layer and a polysilicon layer, and the second part includes a metal conductive layer; the top surface of the polysilicon layer of the first part and the top surface of the polysilicon layer of the third part are both lower than the top surface of the metal conductive layer of the second part.

In one embodiment, a top surface of the metal conductive layer in the second portion is lower than a surface of the substrate.

In one embodiment, a top surface of the metal conductive layer of the second portion is flush with a surface of the substrate.

An embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate comprising an array region, a peripheral region, and a contact region located between the array region and the peripheral region; forming a word line in the substrate, the word line extending through the array region and the contact region to the peripheral region, the word line comprising a first part, a second part, and a third part, the first part being located in the array region, the second part being located in the contact region, and the third part being located in the peripheral region, wherein a top surface of the second part is offset from a top surface of the first part and a top surface of the third part.

In one embodiment, the word line is formed in the substrate, including: forming a groove extending along a first direction in the substrate, forming a metal conductive layer and a polysilicon layer in the groove, wherein the polysilicon layer is located above the metal conductive layer; forming a first mask layer, wherein the first mask layer at least exposes a portion of the surface of the polysilicon layer located in the contact area, and etching away the exposed polysilicon layer.

In one embodiment, a groove extending along the first direction is formed in the substrate, including: forming a plurality of grooves arranged at intervals along the second direction in the substrate, the first direction and the second direction intersect and are both parallel to the surface of the substrate; forming the first mask layer, including: the first mask layer exposes the polysilicon layer corresponding to one of two adjacent grooves.

In one embodiment, the word line is formed in the substrate, including: forming a groove extending along a first direction in the substrate; forming a metal conductive layer, the metal conductive layer filling the groove and covering the surface of the substrate; forming a first dielectric layer above the metal conductive layer, forming a second mask layer above the first dielectric layer, the second mask layer exposing the first dielectric layer located in the array area and in the peripheral area, and etching to remove the exposed first dielectric layer.

In one embodiment, after etching away the exposed first dielectric layer, the second mask layer is removed to expose the metal conductive layer located in the array region, the metal conductive layer located in the peripheral region, and the first dielectric layer located in the contact region; the exposed metal conductive layer and the first dielectric layer are simultaneously etched, and the remaining metal conductive layer located in the array region serves as the first part of the word line, the remaining metal conductive layer located in the contact region serves as the second part of the word line, and the remaining metal conductive layer located in the peripheral region serves as the third part of the word line.

In one embodiment, the word line is formed in the substrate, including: forming a groove extending along a first direction in the substrate; forming a metal conductive layer, the metal conductive layer filling the groove and covering the surface of the substrate; forming a second dielectric layer above the metal conductive layer, forming a third mask layer above the second dielectric layer, the third mask layer exposing the second dielectric layer located in the contact area, and etching to remove the exposed second dielectric layer.

In one embodiment, after removing the exposed second dielectric layer, a portion of the metal conductive layer is etched so that a top surface of the metal conductive layer located in the contact area is flush with the surface of the substrate.

In one embodiment, the method further includes: forming a barrier layer on the top surface of the metal conductive layer located in the contact area, etching and removing the second dielectric layer and part of the metal conductive layer located in the array area and the peripheral area; the remaining metal conductive layer located in the array area serves as the first part of the word line, the remaining metal conductive layer located in the contact area serves as the second part of the word line, and the remaining metal conductive layer located in the peripheral area serves as the third part of the word line.

In one embodiment, a polysilicon layer is formed on the surfaces of the first portion and the third portion, and a height difference is formed between the first portion and the third portion and the second portion, and the height difference is greater than the thickness of the polysilicon layer.

In the semiconductor structure provided by the embodiment of the present disclosure, the top surface of the second part of the word line is staggered with the top surface of the first part and the top surface of the third part. When preparing the semiconductor structure, in the second part, the polysilicon layer on the surface of the word line can be removed before forming a via hole to accommodate the conductive contact structure, or the polysilicon layer is not directly formed on the surface of the word line, that is, in the contact area, the conductive contact structure is directly electrically connected to the metal conductive layer through the dielectric layer, and there is no polysilicon layer between the two, thereby avoiding polysilicon residue caused by poor removal of the polysilicon layer, thereby avoiding disconnection between the word line and the conductive contact structure, and improving the reliability of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1A is a top view of a semiconductor structure provided by a first embodiment of the present disclosure;

Fig. 1B is a cross-sectional view along line A-A' in Fig. 1A;

FIG2 is a top view of a semiconductor structure provided by a second embodiment of the present disclosure;

Fig. 3 is a cross-sectional view along line A-A' in Fig. 2;

Fig. 4 is a cross-sectional view along line B-B' in Fig. 2;

Fig. 5 is a cross-sectional view along line C-C' in Fig. 2;

FIG. 6 is a top view of a semiconductor structure provided by a third embodiment of the present disclosure.

Fig. 7 is a cross-sectional view along line B-B' in Fig. 6;

Fig. 8 is a cross-sectional view taken along the line A-A' in Fig. 2;

FIG9 is a cross-sectional view along the position indicated by the line B-B' in FIG2

Fig. 10 is a cross-sectional view taken along the line C-C' in Fig. 2;

FIG11 is a cross-sectional view of the semiconductor structure provided by the fifth embodiment of the present disclosure along the position indicated by the line B-B' in FIG2 ;

12 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided in a sixth embodiment of the present disclosure;

13A to 13G are schematic diagrams of semiconductor structures formed by main process steps of a preparation method provided in a sixth embodiment of the present disclosure;

14A to 14E are schematic diagrams of semiconductor structures formed by main process steps of a preparation method provided in a seventh embodiment of the present disclosure;

15A to 15G are schematic diagrams of a semiconductor structure formed by main process steps of a preparation method provided in the eighth embodiment of the present disclosure.

Detailed ways

The specific implementation of the semiconductor structure and the preparation method thereof provided by the present disclosure is described in detail below in conjunction with the accompanying drawings. The semiconductor structure described in this specific implementation may be, but is not limited to, a DRAM.

FIG1A is a top view of a semiconductor structure provided by the first embodiment of the present disclosure, and FIG1B is a cross-sectional view along the line A-A' in FIG1A. Please refer to FIG1A and FIG1B. The semiconductor structure includes an array area AA, a peripheral area PA, and a contact area CA located between the array area AA and the peripheral area PA. A word line 100 extends through the array area AA and the contact area CA to the peripheral area PA. A conductive contact structure 110 is provided in the contact area CA, and the conductive contact structure 110 extends from the top surface of the semiconductor structure to the inside of the semiconductor structure to the word line 100. In FIG1A, the word line 100 is blocked by the dielectric layer 120, and is therefore drawn with a dotted line.

The inventors found that in the contact area CA, there is a circuit break between the conductive contact structure 110 and the word line 100. After research, the inventors further found that in this embodiment, the word line 100 is a hybrid buried word line (HBW), which includes a metal conductive layer 101 and a polysilicon layer 102 located on the metal conductive layer 101. Before forming the conductive contact structure 110, the dielectric layer 120 and the polysilicon layer 102 covering the top surface of the word line 100 need to be removed in the contact area CA to form a via hole. The via hole extends from the top surface of the semiconductor structure to the metal conductive layer 101, and then the conductive contact structure 110 is formed in the via hole. The conductive contact structure 110 is connected to the metal conductive layer 101. Since the word line 100 is buried too deep in the substrate, the polysilicon layer 102 on the surface of the word line 100 cannot be completely removed when forming the via hole. As shown in the area circled by the ellipse E in FIG. 1B , there is residual polysilicon layer 102 between the conductive contact structure 110 and the metal conductive layer 101, and the polysilicon layer 102 can easily cause a short circuit between the conductive contact structure 110 and the word line 100.

In view of this, an embodiment of the present disclosure further provides a semiconductor structure, which can avoid a circuit break between the conductive contact structure 110 of the contact area CA and the word line 100, thereby improving the reliability of the semiconductor structure.

FIG. 2 is a top view of a semiconductor structure provided by a second embodiment of the present disclosure, FIG. 3 is a cross-sectional view along line A-A' in FIG. 2, FIG. 4 is a cross-sectional view along line B-B' in FIG. 2, and FIG. 5 is a cross-sectional view along line C-C' in FIG. 2. Please refer to FIG. 2, FIG. 3, FIG. 4 and FIG. 5. The semiconductor structure includes a substrate 200 and a word line 100. The substrate 200 includes an array area AA, a peripheral area PA and a contact area CA located between the array area AA and the peripheral area PA. The word line 100 extends through the array area AA and the contact area CA to the peripheral area PA. The word line 100 includes a first portion 100A, a second portion 100B and a third portion 100C. The first portion 100A is located in the array area AA, the second portion 100B is located in the contact area CA, and the third portion 100C is located in the peripheral area PA. The top surface of the second portion 100B is staggered with the top surface of the first portion 100A and the top surface of the third portion 100C.

The array area AA may form a plurality of repeated memory cells, and the memory cells include a memory transistor, a charge storage structure, and a landing pad therebetween, etc. The peripheral area PA may form a control circuit of the memory cell, such as a circuit for controlling data input/output, etc. The peripheral area PA is located at the periphery of the array area AA, and a contact area CA exists at the junction of the array area AA and at least a portion of the peripheral area PA. For example, in the present embodiment, the contact area CA exists at the junction of the array area AA and the peripheral area PA along the first direction D1, and in other embodiments, the contact area CA exists at the junction of the array area AA and the peripheral area PA along the second direction D2, or at the junction of the first direction D1 and the second direction D2.

The top surface of the second portion 100B is misaligned with the top surface of the first portion 100A and the top surface of the third portion 100C, which means that the top surface of the second portion 100B is not in the same plane as the top surface of the first portion 100A and the top surface of the third portion 100C in the direction perpendicular to the top surface of the semiconductor structure (such as the third direction D3 in FIG. 3 ). For example, in this embodiment, the top surface of the second portion 100B is lower than the top surface of the first portion 100A and the top surface of the third portion 100C in the direction perpendicular to the top surface of the semiconductor structure (such as the third direction D3 in FIG. 3 ); for another example, in another embodiment (please refer to FIG. 8 ), the top surface of the second portion 100B is higher than the top surface of the first portion 100A and the top surface of the third portion 100C in the direction perpendicular to the top surface of the semiconductor structure (such as the third direction D3 in FIG. 8 ).

The word line 100 includes a metal conductive layer 101 and a polysilicon layer 102, wherein the polysilicon layer 102 is located above the metal conductive layer 101, and the second part 100B of the word line 100 does not include the polysilicon layer 102, that is, the first part 100A and the third part 100C of the word line 100 both include the metal conductive layer 101 and the polysilicon layer 102 located on the metal conductive layer 101, and the second part 100B of the word line 100 only includes the metal conductive layer 101 but does not include the polysilicon layer 102, then the top surface of the polysilicon layer 102 serves as the top surface of the first part 100A and the third part 100C, and the top surface of the metal conductive layer 101 serves as the top surface of the second part 100B, so that the top surface of the second part 100B is lower than the top surface of the first part 100A and the third part 100C.

In some embodiments, the top surface of the first portion 100A is flush with the top surface of the third portion 100C, that is, in a direction perpendicular to the top surface of the semiconductor structure (such as the third direction D3 in FIG. 3 ), the top surface of the first portion 100A is on the same plane as the top surface of the third portion 100C. Specifically, in this embodiment, the top surface of the polysilicon layer 102 of the first portion 100A is flush with the top surface of the polysilicon layer 102 of the third portion 100C. In other embodiments, the top surface of the first portion 100A may be flush with the top surface of the third portion 100C or may not be flush, but both are higher or lower than the top surface of the second portion 100B.

In this embodiment, the semiconductor structure includes a plurality of word lines 100 extending along a first direction D1, and the plurality of word lines 100 are arranged at intervals in a second direction D2, and the first direction D1 and the second direction D2 intersect and are parallel to the surface of the substrate 200. In this embodiment, the first direction D1 intersects the second direction D2 perpendicularly, and in other embodiments, the first direction D1 may also intersect the second direction D2 at an acute angle.

In some embodiments, the semiconductor structure further includes a conductive contact structure 110 disposed in the contact area CA, and the conductive contact structure 110 is electrically connected to the second portion 100B of the word line 100, for example, the conductive contact structure 110 is electrically connected to the metal conductive layer 101 of the second portion 100B of the word line 100. The conductive contact structure 110 may be electrically connected to the second portion 100B of a portion of the word lines 100 arranged along the second direction D2, and may also be electrically connected to the second portion 100B of each word line 100.

In this embodiment, the conductive contact structure 110 is electrically connected to the second portion 100B of part of the word line 100. For example, the conductive contact structure 110 is electrically connected to the word lines 100 that are spaced apart. Specifically, please refer to Figure 2. The conductive contact structure 110 is electrically connected to one of the two word lines 100 adjacent to each other in the second direction D2. For another example, as shown in Figure 6, which is a top view of the semiconductor structure provided in the third embodiment of the present disclosure, in the third embodiment, the conductive contact structure 110 is connected to each of the word lines 100.

In the semiconductor structure provided by the embodiment of the present disclosure, in the contact area CA, the conductive contact structure 110 is directly electrically connected to the metal conductive layer 101 through the dielectric layer 120, and there is no polysilicon layer 102 therebetween, thereby avoiding a circuit break between the conductive contact structure 110 and the word line 100, thereby greatly improving the reliability of the semiconductor structure.

In some embodiments, since the conductive contact structure 110 is electrically connected to the second portion 100B of some of the word lines 100, the top surface height of the word line 100 electrically connected to the conductive contact structure 110 may be different from the top surface height of the word line 100 not electrically connected to the conductive contact structure 110. For example, in this embodiment, referring to FIG. 4 , the conductive contact structure 110 is electrically connected to one of the adjacent word lines 100, the second portion 100B of the word line 100 electrically connected to the conductive contact structure 110 only includes the metal conductive layer 101, and the second portion 100B of the word line 100 not electrically connected to the conductive contact structure 110 includes, in addition to the metal conductive layer 101, the polysilicon layer 102 located above the metal conductive layer 101, that is, the top surface of the word line 100 electrically connected to the conductive contact structure 110 is lower than the top surface of the word line 100 not electrically connected to the conductive contact structure 110.

In some embodiments, since the conductive contact structure 110 is electrically connected to the second portion 100B of each word line 100, the top surface heights of the second portions 100B of all word lines 100 are the same along the second direction D2. For example, please refer to FIGS. 6 and 7, wherein FIG. 6 is a top view of a semiconductor structure provided in the third embodiment of the present disclosure, and FIG. 7 is a cross-sectional view along the line B-B' in FIG. 6. In the third embodiment, along the second direction D2, the second portions 100B of all word lines 100 only include the metal conductive layer 101 but not the polysilicon layer 102, and the top surface heights of the metal conductive layer 101 are the same, that is, in the contact area CA, along the second direction D2, the top surface heights of the second portions 100B of all word lines 100 are the same.

In some other embodiments, the conductive contact structure 110 is electrically connected to the second portions 100B of some of the word lines 100 , and the top surfaces of the second portions 100B of all the word lines 100 may be arranged to have the same height in the contact area CA.

In some embodiments, the orthographic projection of the conductive contact structure 110 on the surface of the substrate 200 is located inside the orthographic projection of the second portion 100B on the surface of the substrate 200, that is, the orthographic projection of the second portion 100B on the surface of the substrate 200 covers the orthographic projection of the conductive contact structure 110 on the surface of the substrate 200. For example, as shown in FIG. 2 and FIG. 3 , in this embodiment, there is a distance between the edge of the conductive contact structure 110 and the edge of the second portion 100B, then the orthographic projection of the conductive contact structure 110 on the surface of the substrate 200 is located inside the orthographic projection of the second portion 100B on the surface of the substrate 200. In some embodiments, the second portion 100B refers to the region between the polysilicon layer 102 of the first portion 100A and the polysilicon layer 102 of the third portion 100C, then the edge of the second portion 100B refers to the edge of the polysilicon layer 102 of the first portion 100A close to the contact area CA and the edge of the polysilicon layer 102 of the third portion 100C close to the contact area CA.

In some embodiments, the size of the conductive contact structure 110 in the first direction D1 is the same as the size of the second part 100B, and the size of the conductive contact structure 110 in the second direction D2 is larger than the size of the second part 100B, so as to ensure the process window, facilitate the electrical connection between the conductive contact structure 110 and the second part 100B, and prevent the conductive contact structure 110 and the second part 100B from being relatively offset due to etching deviation in the process, thereby causing the conductive contact structure 110 and the word line 100 to be disconnected.

In a second embodiment, the top surface of the polysilicon layer 102 of the first part 100A and the top surface of the polysilicon layer 102 of the third part 100C are both higher than the top surface of the metal conductive layer 101 of the second part 100B, while in other embodiments, the top surface of the polysilicon layer 102 of the first part 100A and the top surface of the polysilicon layer 102 of the third part 100C are both lower than the top surface of the metal conductive layer 101 of the second part 100B.

For example, Figure 8 is a cross-sectional view along the position indicated by the A-A’ line in Figure 2, Figure 9 is a cross-sectional view along the position indicated by the B-B’ line in Figure 2, and Figure 10 is a cross-sectional view along the position indicated by the C-C’ line in Figure 2. Please refer to Figures 8 to 10. In the fourth embodiment, the first part 100A and the third part 100C of the word line 100 both include a metal conductive layer 101 and a polysilicon layer 102, and the second part 100B of the word line 100 only includes the metal conductive layer 101, and the top surface of the metal conductive layer 101 of the second part 100B is higher than the top surface of the polysilicon layer 102 of the first part 100A and the third part 100C.

In some semiconductor structures, for example, in the semiconductor structure provided in the first embodiment, due to the limitation of the semiconductor process, the metal conductive layer 101 of the second part 100B is flush with the top surface of the metal conductive layer 101 of the first part 100A and the third part 100C, which makes the metal conductive layer 101 of the second part 100B buried too deep in the substrate 200, and the conductive contact structure 110 connected to the metal conductive layer 101 is too high, and a structure with the same width at the top and bottom cannot be formed. The conductive contact structure 110 is shaped like a "V" with a smaller bottom size. The contact area between the bottom of the conductive contact structure 110 and the metal conductive layer 101 of the second part 100B is small, and the contact resistance value is large, which affects the electrical performance of the semiconductor structure. In the fourth embodiment of the present disclosure, since the top surface of the metal conductive layer 101 of the second part 100B is higher than the top surfaces of the polysilicon layer 102 of the first part 100A and the third part 100C, that is, the distance from the top surface of the second part 100B to the top surface of the dielectric layer 120 is smaller, the depth of the conductive contact structure 110 extending into the semiconductor structure is shallower, the width of the top and bottom of the conductive contact structure 110 is not much different, the contact area between the bottom of the conductive contact structure 110 and the metal conductive layer 101 of the second part 100B is large, and the contact resistance is small, so that the semiconductor structure has excellent electrical properties.

In the fourth embodiment, the top surface of the metal conductive layer 101 of the second part 100B is lower than the surface of the substrate 200, the surface of the substrate 200 is also covered with a dielectric layer 120, and the conductive contact structure 110 passes through the dielectric layer 120 and the substrate 200 to be electrically connected to the metal conductive layer 101. In other embodiments of the present disclosure, for example, please refer to FIG. 11, which is a cross-sectional view of the semiconductor structure provided in the fifth embodiment of the present disclosure along the position shown by the B-B' line in FIG. 2. In the fifth embodiment of the present disclosure, the top surface of the metal conductive layer 101 of the second part 100B is flush with the surface of the substrate 200, the surface of the substrate 200 is covered with a dielectric layer 120, and the conductive contact structure 110 passes through the dielectric layer 120 to be electrically connected to the metal conductive layer 101. In this embodiment, the height of the top surface of the metal conductive layer 101 of the second part 100B is further increased, so that the contact area between the metal conductive layer 101 and the conductive contact structure 110 can be further increased, the contact resistance can be reduced, and the electrical performance of the semiconductor structure can be improved.

The present disclosure also provides a method for preparing the semiconductor structure. FIG12 is a schematic diagram of the steps of the method for preparing the semiconductor structure provided by the sixth embodiment of the present disclosure. Please refer to FIG12. The method comprises: step S10, providing a substrate 200, wherein the substrate 200 comprises an array area AA, a peripheral area PA, and a contact area CA located between the array area AA and the peripheral area PA; step S11, forming a word line 100 in the substrate 200, wherein the word line 100 extends through the array area AA and the contact area CA to the peripheral area PA, wherein the word line 100 comprises a first portion 100A, a second portion 100B, and a third portion 100C, wherein the first portion 100A is located in the array area AA, the second portion 100B is located in the contact area CA, and the third portion 100C is located in the peripheral area PA, wherein the top surface of the second portion 100B is offset from the top surface of the first portion 100A and the top surface of the third portion 100C.

13A to 13G are schematic diagrams of a semiconductor structure formed by main process steps of a preparation method provided in a sixth embodiment of the present disclosure.

Please refer to FIG. 12 and FIG. 13A , in step S10 , a substrate 200 is provided, wherein the substrate 200 includes an array area AA, a peripheral area PA, and a contact area CA located between the array area AA and the peripheral area PA.

The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate or an SOI substrate, etc.; the substrate 200 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 200 may also be a stacked structure, such as a silicon/silicon germanium stack, etc.; in addition, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 200, such as field effect transistors, capacitors, inductors and/or diodes, etc. In this embodiment, the substrate 200 is described as a silicon substrate as an example.

In this embodiment, a shallow trench 300 isolation structure 201 and an active area 202 defined by the shallow trench 300 isolation structure 201 are further provided in the substrate 200 , and the surface of the substrate 200 is further covered with an insulating protection layer 203 .

Please refer to Figure 12 and Figures 13D to 13G, wherein Figure 13D is a top view, Figure 13E is a cross-sectional view along line A-A’ in Figure 13D, Figure 13F is a cross-sectional view along line B-B’ in Figure 13D, and Figure 13G is a cross-sectional view along line C-C’ in Figure 13D. In step S11, a word line 100 is formed in the substrate 200, and the word line 100 extends through the array area AA and the contact area CA to the peripheral area PA. The word line 100 includes a first portion 100A, a second portion 100B and a third portion 100C, wherein the first portion 100A is located in the array area AA, the second portion 100B is located in the contact area CA, and the third portion 100C is located in the peripheral area PA, wherein a top surface of the second portion 100B is offset from a top surface of the first portion 100A and a top surface of the third portion 100C.

In some embodiments, the word line 100 extends along the first direction D1 and penetrates the shallow trench isolation structure and the active area.

As an example, the embodiment of the present disclosure further provides a method for forming a word line 100 in the substrate 200. The method comprises the following steps:

Please refer to Figures 13B and 13C, wherein Figure 13B is a top view, and Figure 13C is a cross-sectional view along line A-A’ in Figure 13B. A groove 300 extending along a first direction D1 is formed in the substrate 200, and a metal conductive layer 101 and a polysilicon layer 102 are formed in the groove 300, and the polysilicon layer 102 is located above the metal conductive layer 101.

The groove 300 is recessed toward the inside of the substrate 200, and passes through the array area AA and the contact area CA to the peripheral area PA along the first direction D1. The recessed depth of the groove 300 can be determined according to the depth requirement of the word line 100 structure formed in the subsequent step. In this embodiment, a plurality of grooves 300 arranged at intervals along the second direction D2 are formed in the substrate 200. The first direction D1 and the second direction D2 intersect and are parallel to the surface of the substrate 200. The metal conductive layer 101 and the polysilicon layer 102 are formed in each of the grooves 300. The metal conductive layer 101 includes but is not limited to a metal tungsten conductive layer. In this step, the metal conductive layer 101 and the polysilicon layer 102 can be formed by chemical vapor deposition, atomic layer deposition and other processes.

13D to 13G, a first mask layer 301 is formed, wherein the first mask layer 301 at least exposes a portion of the surface of the polysilicon layer 102 located in the contact area CA, and the exposed polysilicon layer 102 is etched away. In this step, an etching gas may be used to etch the polysilicon layer 102, and the etching gas includes but is not limited to CF4, HBr, and O2.

In this embodiment, the first mask layer 301 exposes a portion of the surface of the polysilicon layer 102 located in the contact area CA, that is, the grooves 300 arranged at intervals along the second direction D2 are partially exposed to the opening 301A of the first mask layer 301 in the polysilicon layer 102 corresponding to the contact area CA. Specifically, the first mask layer 301 exposes the polysilicon layer 102 corresponding to one of the two adjacent grooves 300, and the polysilicon layer 102 corresponding to the other groove 300 is not exposed. In the step of removing the polysilicon layer 102, only the exposed polysilicon layer 102 is removed.

In some embodiments, the manufacturing method further includes the step of forming a conductive contact structure 110. Referring to Figures 2 to 5, a conductive contact structure 110 is formed in the contact area CA, and the conductive contact structure 110 is electrically connected to the second portion 100B of the word line 100.

As an example, this embodiment provides a method for forming the conductive contact structure 110, the method comprising: removing the first mask layer 301 and forming a dielectric layer 120, the dielectric layer 120 covering the surface of the substrate 200, and in the contact area CA, the dielectric layer 120 fills the original position of the polysilicon layer 102 and covers the metal conductive layer 101; forming a via (not shown in the drawings) in the contact area CA, the via penetrates the dielectric layer 120 to the surface of the metal conductive layer 101; filling the via with a conductive material, the conductive material contacts the metal conductive layer 101, and the conductive material serves as the conductive contact structure 110.

In some other embodiments, the first mask layer 301 exposes the entire surface of the polysilicon layer 102 located in the contact area CA, that is, the grooves 300 arranged at intervals along the second direction D2 in the polysilicon layer 102 corresponding to the contact area CA are all exposed to the first mask layer 301; in the step of etching and removing the polysilicon layer 102, the grooves 300 arranged at intervals along the second direction D2 in the polysilicon layer 102 corresponding to the contact area CA are all removed; in the step of forming the conductive contact structure 110, the dielectric layer 120 is filled in the original position of the polysilicon layer 102, and the via hole is formed only at the position where the conductive contact structure 110 needs to be formed, and then the conductive material is filled in the via hole to form the conductive contact structure 110, please refer to Figures 6 and 7.

In the preparation method provided in the embodiment of the present disclosure, the polysilicon layer 102 is removed before the dielectric layer 120 is formed. This can avoid polysilicon residue caused by poor removal of the polysilicon layer 102 in the step of forming the via, thereby avoiding disconnection between the word line 100 and the conductive contact structure 110, thereby improving the reliability of the semiconductor structure.

As an example, the seventh embodiment of the present disclosure also provides another method for forming a word line 100 in the substrate 200. The method comprises the following steps:

Please refer to FIG. 14A and FIG. 14B, where FIG. 14A is a top view and FIG. 14B is a cross-sectional view along the line A-A' in FIG. 14A, a groove 300 extending along the first direction D1 is formed in the substrate 200; a metal conductive layer 101 is formed, the metal conductive layer 101 fills the groove 300 and covers the surface of the substrate 200; a first dielectric layer 130 is formed above the metal conductive layer 101; a second mask layer 302 is formed above the first dielectric layer 130, the second mask layer 302 exposes the first dielectric layer 130 located in the array area AA and the peripheral area PA. The structure of the groove 300 is the same as that of the groove 300 of the sixth embodiment, and will not be described in detail. In FIG. 14A, the position of the groove 300 is indicated by a dotted line.

Please refer to FIG. 14C, which is a cross-sectional view along the position indicated by the line A-A' in FIG. 14A. The second mask layer 302 is used as a shield to remove the exposed first dielectric layer 130 by etching. In the array area AA and the peripheral area PA, the metal conductive layer 101 is exposed, and the first dielectric layer 130 in the contact area CA is retained. The first dielectric layer 130 is etched with the metal conductive layer 101 as an etching stop layer, and the etching method includes but is not limited to wet etching.

In this embodiment, after etching away the exposed first dielectric layer 130, the following step is also included: removing the second mask layer 302 to expose the metal conductive layer 101 located in the array area AA, the metal conductive layer 101 located in the peripheral area PA, and the first dielectric layer 130 located in the contact area CA.

Please refer to FIG. 14D, which is a cross-sectional view along the position indicated by the line A-A' in FIG. 14A, wherein the exposed metal conductive layer 101 and the first dielectric layer 130 are etched simultaneously, and the remaining metal conductive layer 101 located in the array area AA is used as the first part 100A of the word line 100, the remaining metal conductive layer 101 located in the contact area CA is used as the second part 100B of the word line 100, and the remaining metal conductive layer 101 located in the peripheral area PA is used as the third part 100C of the word line 100. In this step, in the contact area CA, the first dielectric layer 130 is etched away before etching the corresponding metal conductive layer 101, so that the top surface of the second part 100B (i.e., the surface of the metal conductive layer 101) is higher than the top surface of the first part 100A and the top surface of the third part 100C (i.e., the surface of the metal conductive layer 101), and a height difference is formed between the first part 100A and the third part 100C and the second part 100B.

Please refer to FIG. 14E, which is a cross-sectional view along the position indicated by the line A-A' in FIG. 14A. A polysilicon layer 102 is formed on the surface of the first portion 100A and the third portion 100C of the word line 100, and the height difference between the first portion 100A and the third portion 100C and the second portion 100B is greater than the thickness of the polysilicon layer 102. That is, in the semiconductor structure formed in this step, in the direction perpendicular to the top surface of the semiconductor structure, the top surface of the first portion 100A and the third portion 100C is lower than the top surface of the second portion 100B. The method for forming the polysilicon layer 102 may be to form a polysilicon material layer on the surface of the substrate 200; and to etch back the polysilicon material layer to a set depth, and only retain the polysilicon material layer located in the first portion 100A and the third portion 100C as the polysilicon layer 102.

Referring to FIGS. 8 to 10 , a conductive contact structure 110 is formed in the contact area CA. The conductive contact structure 110 is electrically connected to the second portion 100B of the word line 100 .

As an example, this embodiment provides a method for forming the conductive contact structure 110, the method comprising: forming a dielectric layer 120, the dielectric layer 120 covering the surface of the substrate 200, the surface of the polysilicon layer 102 of the first part 100A and the third part 100C, and the surface of the metal conductive layer 101 of the second part 100B; forming a via (not shown in the drawings) in the contact area CA, the via penetrating the dielectric layer 120 to the surface of the metal conductive layer 101; filling the via with a conductive material, the conductive material being in contact with the metal conductive layer 101, and the conductive material serving as the conductive contact structure 110.

As an example, the eighth embodiment of the present disclosure also provides another method for forming a word line 100 in the substrate 200. The method comprises the following steps:

Please refer to FIG. 15A and FIG. 15B, where FIG. 15A is a top view and FIG. 15B is a cross-sectional view along line A-A' in FIG. 15A, a groove 300 extending along a first direction D1 is formed in the substrate 200; a metal conductive layer 101 is formed, the metal conductive layer 101 fills the groove 300 and covers the surface of the substrate 200; a second dielectric layer 140 is formed above the metal conductive layer 101, and a third mask layer 303 is formed above the second dielectric layer 140, the third mask layer 303 exposes the second dielectric layer 140 located in the contact area CA. In this embodiment, the opening 303A of the third mask layer 303 exposes the second dielectric layer 140. The structure of the groove 300 is the same as that of the groove 300 in the sixth embodiment, and will not be repeated.

Please refer to FIG. 15C , which is a cross-sectional view along the position indicated by the line A-A’ in FIG. 15A , where the exposed second dielectric layer 140 is removed by etching.

Please refer to FIG. 15D , which is a cross-sectional view along the position indicated by the line A-A′ in FIG. 15A , in which a portion of the metal conductive layer 101 is etched so that the top surface of the metal conductive layer 101 located in the contact area CA is flush with the surface of the substrate 200. In this step, the third mask layer 303 and the second dielectric layer 140 are used as shields to etch a portion of the metal conductive layer 101 in the contact area CA.

In this embodiment, the preparation method further includes: referring to FIG. 15E, which is a cross-sectional view along the position indicated by the line A-A' in FIG. 15A, a barrier layer 150 is formed on the top surface of the metal conductive layer 101 located in the contact area CA. The barrier layer 150 is only formed in the contact area CA, and is not formed in the array area AA and the peripheral area PA.

Please refer to FIG. 15F, which is a cross-sectional view along the position indicated by the line A-A' in FIG. 15A, wherein the second dielectric layer 140 and part of the metal conductive layer 101 located in the array area AA and the peripheral area PA are removed by etching; the remaining metal conductive layer 101 located in the array area AA is used as the first part 100A of the word line 100, the remaining metal conductive layer 101 located in the contact area CA is used as the second part 100B of the word line 100, and the remaining metal conductive layer 101 located in the peripheral area PA is used as the third part 100C of the word line 100. In this step, the second dielectric layer 140 and the metal conductive layer 101 are etched with the barrier layer 150 as a shield. The barrier layer 150 includes but is not limited to a silicon nitride layer.

In this step, after forming the metal conductive layer 101 flush with the substrate 200 in the contact area CA, the metal conductive layer 101 in the array area AA and the peripheral area PA is removed, so that the top surface of the metal conductive layer 101 located in the array area AA and the peripheral area PA is lower than the top surface of the metal conductive layer 101 located in the contact area CA, that is, the first part 100A and the third part 100C of the word line 100 have a height difference with the second part 100B of the word line 100.

Please refer to Figure 15G, which is a cross-sectional view along the position indicated by the A-A’ line in Figure 15A. A polysilicon layer 102 is formed on the surfaces of the first part 100A and the third part 100C, and the height difference between the first part 100A and the third part 100C and the second part 100B is greater than the thickness of the polysilicon layer 102. That is, in the semiconductor structure formed in this step, in the direction perpendicular to the top surface of the semiconductor structure (such as the third direction D3 in the figure), the top surfaces of the first part 100A and the third part 100C are lower than the top surface of the second part 100B.

8 to 10 , a conductive contact structure 110 is formed in the contact area CA, and the conductive contact structure 110 is electrically connected to the second portion 100B of the word line 100. The method of forming the conductive contact structure 110 is the same as that of the seventh embodiment, and will not be described again.

In the preparation method provided by the embodiment of the present disclosure, in the contact area CA, before the conductive contact structure 110 is formed, there is no polysilicon layer 102 on the surface of the metal conductive layer 101 connected to the conductive contact structure 110, so that the polysilicon residue caused by the poor removal of the polysilicon layer 102 in the step of forming the via hole can be avoided, thereby avoiding the word line 100 and the conductive contact structure 110 from being disconnected, thereby improving the reliability of the semiconductor structure; and the top surface of the second part 100B of the word line 100 is higher than the top surfaces of the first part 100A and the third part 100C of the word line 100, so the depth of the conductive contact structure 110 extending into the semiconductor structure is shallow, the width of the top and bottom of the conductive contact structure 110 is not much different, the contact area between the bottom of the conductive contact structure 110 and the metal conductive layer 101 of the second part 100B is large, and the contact resistance is small, so that the semiconductor structure has excellent electrical properties.

The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

A semiconductor structure comprising:

A substrate, the substrate comprising an array region, a peripheral region, and a contact region between the array region and the peripheral region;

A word line extends through the array region and the contact region to the peripheral region, the word line comprises a first portion, a second portion and a third portion, the first portion is located in the array region, the second portion is located in the contact region, the third portion is located in the peripheral region, and a top surface of the second portion is offset from a top surface of the first portion and a top surface of the third portion.
The semiconductor structure of claim 1, wherein a top surface of the first portion is flush with a top surface of the third portion.
The semiconductor structure according to claim 1, wherein the word line comprises a metal conductive layer and a polysilicon layer, the polysilicon layer is located above the metal conductive layer, and the second portion of the word line does not include the polysilicon layer.
The semiconductor structure as described in claim 3, wherein the semiconductor structure further includes a conductive contact structure arranged in the contact area, the conductive contact structure is electrically connected to the second part, and the orthographic projection of the conductive contact structure on the surface of the substrate is located inside the orthographic projection of the second part on the surface of the substrate.
The semiconductor structure as described in claim 1, wherein it includes a plurality of word lines extending along a first direction, the plurality of word lines are arranged at intervals in a second direction, the first direction and the second direction intersect and are both parallel to the surface of the substrate; along the second direction, the top surface heights of the second portions of adjacent word lines are different.
The semiconductor structure according to claim 5, wherein along the second direction, only the second portion of one of the two adjacent word lines comprises the polysilicon layer.
The semiconductor structure as described in claim 5 or 6, wherein the semiconductor structure also includes a conductive contact structure arranged in the contact area, the conductive contact structure is electrically connected to the second part, the size of the conductive contact structure in the first direction is the same as the size of the second part, and the size of the conductive contact structure in the second direction is larger than the size of the second part.
The semiconductor structure as described in claim 1, wherein the first part and the third part both include a metal conductive layer and a polysilicon layer, and the second part includes a metal conductive layer; the top surface of the polysilicon layer of the first part and the top surface of the polysilicon layer of the third part are both lower than the top surface of the metal conductive layer of the second part.
The semiconductor structure according to claim 8, wherein a top surface of the metal conductive layer in the second portion is lower than a surface of the substrate.
The semiconductor structure according to claim 8, wherein a top surface of the metal conductive layer of the second portion is flush with a surface of the substrate.
A method for preparing a semiconductor structure, comprising:

Providing a substrate, the substrate comprising an array region, a peripheral region, and a contact region between the array region and the peripheral region;

A word line is formed in the substrate, the word line extends through the array region and the contact region to the peripheral region, the word line includes a first portion, a second portion and a third portion, the first portion is located in the array region, the second portion is located in the contact region, and the third portion is located in the peripheral region, wherein a top surface of the second portion is offset from a top surface of the first portion and a top surface of the third portion.
The method for preparing a semiconductor structure according to claim 11, wherein forming the word line in the substrate comprises: forming a trench extending along a first direction in the substrate, forming a metal conductive layer and a polysilicon layer in the trench, wherein the polysilicon layer is located above the metal conductive layer;

A first mask layer is formed, wherein the first mask layer at least exposes a portion of the surface of the polysilicon layer located in the contact area, and the exposed polysilicon layer is removed by etching.
The method for preparing a semiconductor structure as described in claim 12, wherein forming a groove extending along the first direction in the substrate comprises: forming a plurality of grooves arranged at intervals along the second direction in the substrate, the first direction and the second direction intersecting and both parallel to the surface of the substrate; forming the first mask layer comprises: the first mask layer exposing the polysilicon layer corresponding to one of two adjacent grooves.
The method for preparing a semiconductor structure as described in claim 11, wherein forming the word line in the substrate comprises: forming a groove extending along a first direction in the substrate; forming a metal conductive layer, the metal conductive layer filling the groove and covering the surface of the substrate; forming a first dielectric layer above the metal conductive layer, forming a second mask layer above the first dielectric layer, the second mask layer exposing the first dielectric layer located in the array area and in the peripheral area, and etching to remove the exposed first dielectric layer.
The method for preparing a semiconductor structure as claimed in claim 14, wherein, after etching away the exposed first dielectric layer, the second mask layer is removed to expose the metal conductive layer located in the array region, the metal conductive layer located in the peripheral region, and the first dielectric layer located in the contact region; the exposed metal conductive layer and the first dielectric layer are etched simultaneously, and the remaining metal conductive layer located in the array region serves as the first part of the word line, the remaining metal conductive layer located in the contact region serves as the second part of the word line, and the remaining metal conductive layer located in the peripheral region serves as the third part of the word line.
The method for preparing a semiconductor structure as described in claim 11, wherein forming the word line in the substrate comprises: forming a groove extending along a first direction in the substrate; forming a metal conductive layer, the metal conductive layer filling the groove and covering the surface of the substrate; forming a second dielectric layer above the metal conductive layer, forming a third mask layer above the second dielectric layer, the third mask layer exposing the second dielectric layer located in the contact area, and etching to remove the exposed second dielectric layer.
The method for preparing a semiconductor structure as claimed in claim 16, wherein, after removing the exposed second dielectric layer, a portion of the metal conductive layer is etched so that the top surface of the metal conductive layer located in the contact area is flush with the surface of the substrate.
The method for preparing a semiconductor structure according to claim 17, further comprising: forming a barrier layer on the top surface of the metal conductive layer located in the contact area, etching and removing the second dielectric layer and part of the metal conductive layer located in the array area and the peripheral area; the remaining metal conductive layer located in the array area serves as the first part of the word line, the remaining metal conductive layer located in the contact area serves as the second part of the word line, and the remaining metal conductive layer located in the peripheral area serves as the third part of the word line.
The method for preparing a semiconductor structure as described in claim 15, wherein a polysilicon layer is formed on the surfaces of the first part and the third part, and a height difference is formed between the first part and the third part and the second part, and the height difference is greater than the thickness of the polysilicon layer.
The method for preparing a semiconductor structure as described in claim 18, wherein a polysilicon layer is formed on the surfaces of the first part and the third part, and a height difference is formed between the first part and the third part and the second part, and the height difference is greater than the thickness of the polysilicon layer.