CN112951825A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN112951825A CN112951825A CN201911257093.5A CN201911257093A CN112951825A CN 112951825 A CN112951825 A CN 112951825A CN 201911257093 A CN201911257093 A CN 201911257093A CN 112951825 A CN112951825 A CN 112951825A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
The invention relates to a semiconductor device and a manufacturing method thereof. The method comprises the following steps: obtaining a substrate comprising a memory cell array region; forming a word line trench; forming a word line conductive film in the word line groove; forming photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line part and exposes the word line conductive film outside the word line contact part; the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure which is not covered by the photoresist. By forming the photoresist on the surface of the substrate, the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure which is not covered by the photoresist, so that the windowing position depth of a word line contact hole in the word line contact structure is reduced, the process time in the process of forming the contact hole is reduced, the excessive erosion of the side wall of the contact hole with shallow windowing depth in the process of forming the contact hole is reduced, and the short circuit abnormality of a device caused by the abnormal contact hole is avoided.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
When the dynamic random access memory is used for manufacturing a contact window structure, because the depths of contact holes corresponding to different contact window structures are different, the problem of insufficient process windowing depth can occur when the contact holes of different contact window structures are manufactured by using the same process, for example, when the contact hole of an active area stops on the surface of the active area, a word line contact hole with a deeper position stops above a word line conductive structure and does not complete windowing, the active area contact hole is etched into the active area when the word line contact hole is continuously etched, and simultaneously, the side wall of the contact hole can also have the problem of hole expansion, so that the characteristic dimension of a device is increased or the device short circuit caused by side wall etching is abnormal easily caused.
Disclosure of Invention
In view of the above, it is necessary to provide a new method for manufacturing a semiconductor device and a new semiconductor device.
A method for manufacturing a semiconductor device includes:
obtaining a substrate, wherein the substrate comprises a storage unit array area;
forming word line grooves arranged at intervals in the memory cell array area;
filling word line conductive materials in the word line grooves to form word line conductive films;
forming photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact part and exposes the word line conductive film outside the word line contact part;
etching the word line conductive film uncovered by the photoresist to a target height by using the photoresist as a barrier layer to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact part is greater than that of the word line conductive structure uncovered by the photoresist;
and removing the photoresist.
In one embodiment, the word line contact is located at an end of the word line conductive structure.
In one embodiment, a ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0.
In one embodiment, after the removing the photoresist, the method further includes:
forming a first insulating medium layer on the surface of the substrate;
and patterning the first insulating medium layer to form word line contact holes on the word line contact parts.
In one embodiment, the substrate further includes a peripheral circuit region, the peripheral circuit region includes a transistor active region, a second insulating medium layer is formed on the surface of the active region, the second insulating medium layer is patterned, and an active region contact hole is formed in a source region/drain region of the active region.
In one embodiment, the height difference between the active area contact holes and the word line contact holes is greater than or equal to 0 and less than twenty percent of the height of the active area contact holes.
In one embodiment, the word line contact hole and the active region contact hole are formed through the same process.
In one embodiment, the first insulating dielectric layer and the second insulating dielectric layer are formed by the same process.
In one embodiment, the semiconductor device is a dynamic random access memory.
The manufacturing method comprises the following steps: obtaining a substrate, wherein the substrate comprises a storage unit array area; forming word line grooves arranged at intervals in the memory cell array area; filling word line conductive materials in the word line grooves to form word line conductive films; forming photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact part and exposes the word line conductive film outside the word line contact part; and etching the word line conductive film uncovered by the photoresist to a target depth by using the photoresist as a barrier layer to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact part is greater than that of the word line conductive structure uncovered by the photoresist. The method comprises the steps of forming photoresist on the surface of a substrate, etching the word line conductive film uncovered by the photoresist to a target height by using the photoresist as a barrier layer, so that the thickness of the word line conductive structure of the word line contact part in the formed word line conductive structure is larger than that of the word line conductive structure uncovered by the photoresist, and compared with the thickness of the word line conductive structure of the word line contact part in the word line conductive structure which is equal to that of the word line conductive structure uncovered by the photoresist, the window opening position depth of the word line contact hole in the word line contact part is reduced, the process time in the contact hole forming process is reduced, and excessive erosion to the side wall of the contact hole with shallow window opening depth in the contact hole process is reduced, the device short circuit abnormity caused by the abnormity of the contact hole is avoided.
A semiconductor device, comprising:
the memory device comprises a substrate, a first substrate and a second substrate, wherein a memory cell array area is formed on the substrate, and word line grooves are formed in the memory cell array area at intervals;
word line conductive structures including word line conductive structures of the word line contact portions and word line conductive structures outside the word line contact portions;
the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure outside the word line contact part.
In one embodiment, the word line contact is located at an end of the word line conductive structure.
In one embodiment, the ratio of the thickness of the word line conductive structure of the word line contact part to the thickness of the word line conductive structure outside the word line contact part is greater than or equal to 1.5 and less than or equal to 4.0.
In one embodiment, the device further comprises:
a peripheral circuit region including a transistor active region having source/drain regions;
the insulating medium layer is positioned on the surfaces of the word line conductive structure and the active region;
a word line contact structure on and in contact with the word line contact;
an active region contact structure on and in contact with source/drain regions of the transistor active region.
In one embodiment, the height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than twenty percent of the height of the active area contact structure.
In one embodiment, the active region contact structure and the word line contact structure are formed simultaneously.
In one embodiment, the semiconductor device is a dynamic random access memory.
The semiconductor device comprises a substrate, wherein a memory cell array area is formed on the substrate, and word line grooves are formed in the memory cell array area at intervals; the word line conductive structure comprises a word line conductive structure of a word line contact part and a word line conductive structure outside the word line contact part; the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure outside the word line contact part. The device substrate surface of the application is formed with the word line conducting structure of word line contact portion's thickness is greater than the word line conducting structure of the thickness of the word line conducting structure outside the word line contact portion, compare with the device of the word line conducting structure of word line contact portion's thickness equals the word line conducting structure's outside the word line contact portion in the word line conducting structure, the windowing position degree of depth of word line contact hole has been reduced, the process time in the contact hole forming process is reduced, the excessive erosion to the contact hole that the depth of windowing is shallower in the contact hole process has been reduced, the device short circuit that contact hole anomaly arouses is avoided unusual.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor device in one embodiment;
FIG. 2a is a flow chart of forming word line contact holes in one embodiment;
FIG. 2b is a flow chart of forming active area contact holes in one embodiment;
FIG. 3a is a cross-sectional view of a semiconductor device in one embodiment;
FIG. 3b is a cross-sectional view of the semiconductor device after forming a word line conductive film in one embodiment;
FIG. 3c is a cross-sectional view of a semiconductor device after forming an insulating dielectric layer in one embodiment;
FIG. 4a is a cross-sectional view of a word line contact in a direction perpendicular to the word line conductive film after forming the word line conductive film in one embodiment;
FIG. 4b is a corresponding cross-sectional view of FIG. 4a after formation of a photoresist in one embodiment;
FIG. 4c is a corresponding cross-sectional view of FIG. 4b after forming a layer of insulating dielectric in one embodiment;
FIG. 5a is a cross-sectional view of the area outside the word line contact portion after forming the word line conductive film in the vertical direction of the word line conductive film in one embodiment;
FIG. 5b is a corresponding cross-sectional view of FIG. 5a after formation of a word line conductive structure in one embodiment;
FIG. 5c is a cross-sectional view corresponding to FIG. 5b after forming a dielectric layer in one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
When a typical dynamic random access memory is used for manufacturing Contact window structures of a plurality of structures, namely a source region/drain region and a transistor gate region, which are connected with a Word line, a bit line, a transistor Active region, because Contact holes corresponding to different Contact window structures need to be windowed to different target depths, when the Contact holes are prepared by using the same process, one Contact hole reaches the corresponding target depth, and other Contact holes do not complete windowing, the Contact holes continue windowing at the moment, the side walls of the Contact holes are continuously reamed while the depth of the Contact holes is increased, so that the characteristic size of a device is increased or a side-etched device is short-circuited abnormally, for example, the Contact holes (AA Contact) of the transistor Active region are stopped on the surface of the Active region, and the Word lines (Word line Contact, WL Contact) of the deeper Contact holes are stopped above the Word line conductive structure and do not complete windowing, when the etching is continued, the contact hole of the active region of the transistor is etched into the active region, and a spike effect (spiking) is generated.
As shown in fig. 1, fig. 3a, fig. 3b, fig. 3c, fig. 4a to 4c, and fig. 5a to 5c, in one embodiment, there is provided a method for manufacturing a semiconductor device, including:
s102, a substrate is obtained.
The substrate 102 includes a memory cell array region, which may be at least one of silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (SSiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI).
And S104, forming a word line groove.
In one embodiment, the word line trench is formed by dry etching. In another embodiment, the word line trench is formed by wet etching.
In one embodiment, the word line trench is formed by two process processes.
And S106, forming a word line conductive film.
The word line trench 104 is filled with a word line conductive material to form a word line conductive film 108. In one embodiment, forming the word line conductive film 108 further includes forming an insulating layer 110 on an inner wall of the word line trench 104, and the insulating layer 110 may be a silicon dioxide film layer.
In one embodiment, before filling the word line trench 104 with the word line conductive material, a first metal layer is formed on the inner wall of the word line trench, for example, the first metal layer may be a titanium/titanium nitride metal layer that functions as a blocking layer.
In one embodiment, the word line conductive material is formed by a plasma chemical vapor deposition process. In one embodiment, the word line conductive material is formed by a physical vapor deposition process. In one embodiment, the word line conductive material is a metal conductive material, such as a metal tungsten material, a composite material of metal tungsten, a metal aluminum material, or the like.
In one embodiment, after removing excess word line conductive material from the substrate surface, a word line conductive film 108 is formed in the word line trench 104.
In one embodiment, the excess word line conductive material on the surface of the substrate is removed by chemical mechanical polishing. In another embodiment, the excess word line conductive material on the surface of the substrate is removed by etching, such as wet etching, dry etching, etc.
And S108, forming photoresist.
A photoresist 112 is formed on the surface of the substrate 102, that is, a photoresist with a photoresist pattern is formed on the surface of the substrate, the photoresist 112 covers the word line trench 115 of the word line contact portion 114, that is, the word line conductive film of the word line contact portion, and exposes the word line trench 116 outside the word line contact portion 114, that is, the word line conductive film outside the word line contact portion.
Specifically, a photoresist is coated on the surface of the substrate, and then the photoresist is exposed and developed to expose the word line conductive film (i.e., the array region of the device is developed) outside the word line contact portion, and the unexposed photoresist covers the word line conductive film at the word line contact portion, thereby playing a role in protecting the word line conductive film at the word line contact portion.
And S110, forming a word line conductive structure.
The word line conductive film uncovered by the photoresist is etched to a target height by using the photoresist 112 as a blocking layer to obtain a word line conductive structure 117, that is, the word line conductive film 108 is thinned by using the photoresist 112 as a blocking layer to obtain the word line conductive structure 117, so that the thickness of the word line conductive structure of the word line contact portion 114 is greater than that of the word line conductive structure uncovered by the photoresist 112. The word line conductive film which is not covered by the photoresist is etched to a target height, namely the word line conductive film which is not covered by the photoresist is etched until the residual word line conductive film is lower than the surface of the substrate by less than 5 nanometers, so long as the residual word line conductive film can achieve the purpose of avoiding short circuit of structures such as word lines, bit lines and other contact windows.
And S112, removing the photoresist.
And removing the photoresist on the surface of the substrate.
In one embodiment, the word line conductive structure 117 is located on the shallow trench isolation oxide layer 121.
In one embodiment, the word line contact 114 is located at an end of the word line conductive structure 117.
In one embodiment, a ratio of a thickness of the word line conductive structure of the word line contact portion to a thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0. In an actual process, values of ratios of thicknesses of the word line conductive structures of the word line contact portions to thicknesses of the word line conductive structures not covered by the photoresist, such as 1.7, 1.9, 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, and the like, are set as required.
As shown in fig. 2a, in an embodiment, step S112 is followed by:
and S202, forming a first insulating medium layer.
And forming a first insulating medium layer on the surface of the word line conductive structure 117.
In one embodiment, after removing the photoresist on the word line conductive structure, a first insulating dielectric layer film is formed on the substrate surface, for example, the first insulating dielectric layer film may be formed on the substrate surface by physical vapor deposition or chemical vapor deposition; and then removing the redundant first insulating medium layer film on the surface of the substrate in an etching or chemical mechanical grinding mode to form a first insulating medium layer.
In one embodiment, the first insulating dielectric layer is a silicon oxide insulating layer.
And S204, forming a word line contact hole.
As shown in fig. 3a, the first insulating dielectric layer is patterned to form word line contact holes 119 on the word line contacts 114.
As shown in fig. 2b, in an embodiment, the substrate further includes a peripheral circuit region, the peripheral circuit region includes a transistor active region, and the method for manufacturing a semiconductor device further includes:
and S201, forming a second insulating medium layer.
And forming a second insulating medium layer on the surface of the transistor active region.
In one embodiment, the second insulating dielectric layer and the first insulating dielectric layer are formed by the same process.
And S203, forming an active region contact hole.
The second insulating dielectric layer is patterned to form active region contact holes 120 on the source/drain regions 106 of the active region.
In one embodiment, the height difference between active area contact hole 120 and word line contact hole 119 is greater than or equal to 0 and less than twenty percent of the height of the active area contact hole, and the height difference between the active area contact hole and word line contact hole 119 may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, etc. of the height of the active area contact hole in the actual process.
In one embodiment, the word line contact hole 119 and the active region contact hole 120 are formed through the same process.
In one embodiment, the semiconductor device is a dynamic random access memory.
The manufacturing method comprises the following steps: obtaining a substrate, wherein the substrate comprises a storage unit array area; forming word line grooves arranged at intervals in the memory cell array area; filling word line conductive materials in the word line grooves to form word line conductive films; forming photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact part and exposes the word line conductive film outside the word line contact part; and etching the word line conductive film uncovered by the photoresist to a target depth by using the photoresist as a barrier layer to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact part is greater than that of the word line conductive structure uncovered by the photoresist. The method comprises the steps of forming photoresist on the surface of a substrate, etching the word line conductive film uncovered by the photoresist to a target height by using the photoresist as a barrier layer, so that the thickness of the word line conductive structure of the word line contact part in the formed word line conductive structure is larger than that of the word line conductive structure uncovered by the photoresist, and compared with the thickness of the word line conductive structure of the word line contact part in the word line conductive structure which is equal to that of the word line conductive structure uncovered by the photoresist, the window opening position depth of the word line contact hole in the word line contact part is reduced, the process time in the contact hole forming process is reduced, and excessive erosion to the side wall of the contact hole with shallow window opening depth in the contact hole process is reduced, the device short circuit abnormity caused by the abnormity of the contact hole is avoided.
As shown in fig. 3a, 3b, 3c, in an embodiment, there is provided a semiconductor device including:
the memory device includes a substrate 102, and a memory cell array region formed on the substrate 102, the memory cell array region being formed with word line trenches 104 arranged at intervals. The memory cell array region is formed with a plurality of mutually independent word line grooves, the word line grooves extend along a first direction and are arranged at intervals along a second direction, and the first direction and the second direction are intersected. The substrate may be at least one of silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-germanium-on-insulator (SSiGeOI), silicon-on-germanium-on-insulator (siggeoi), and germanium-on-insulator (GeOI).
A word line conductive structure 117, the word line conductive structure 117 including a word line conductive structure of the word line contact 114 and a word line conductive structure outside the word line contact 114.
In one embodiment, the word line contact 114 is located at an end of the word line conductive structure 117.
In one embodiment, the word line conductive structure 117 is a metal conductive structure, such as a metal tungsten conductive structure, a composite conductive structure of metal tungsten, a metal aluminum conductive structure, and the like.
The thickness of the word line conductive structure of the word line contact portion 114 is greater than the thickness of the word line conductive structure outside the word line contact portion 114.
In one embodiment, the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.0. In the actual semiconductor device design process, the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is set according to the requirement, such as 1.7, 1.9, 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, etc.
In one embodiment, the device further comprises:
word line contact hole 119, word line contact hole 119 is formed on word line contact portion 114 and the bottom of word line contact hole 119 contacts the upper surface of word line contact portion 114.
Active region contact holes 120, the active region contact holes 120 being formed on the active regions of the transistors and the bottoms of the active region contact holes 120 being in contact with the upper surfaces of the source/drain regions 106 of the active regions of the transistors.
In one embodiment, the device further comprises:
a peripheral circuit region including a transistor active region having source/drain regions 106;
and the insulating medium layer 118 is positioned on the surfaces of the word line conductive structure and the active region, and the insulating medium layer 118 is positioned on the surfaces of the word line conductive structure and the active region.
In one embodiment, the insulating dielectric layer 118 includes a first insulating dielectric layer on the surface of the word line conductive structure 117 and a second insulating dielectric layer on the surface of the transistor active region.
A word line contact structure on the word line contact 114 and in contact with the word line contact 114.
The word line contact structure is located in a word line contact hole 119 formed on the word line contact portion 114, and the word line contact structure is a conductive structure for leading out the word line conductive structure 117.
In one embodiment, the word line contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a composite conductive structure of metal tungsten, a metal aluminum conductive structure, and the like.
An active region contact structure located over and in contact with the source/drain regions 106 of the transistor active region.
The active region contact structure is located in the active region contact hole 120 formed on the source/drain region 106, and the active region contact structure is a conductive structure for leading out the source/drain region 106 of the transistor.
In one embodiment, the active region contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a composite conductive structure of metal tungsten, a metal aluminum conductive structure, or the like.
In one embodiment, a height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than twenty percent of a height of the active area contact structure, and in an actual semiconductor device, the height difference between the active area contact structure and the word line contact structure may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, and the like of the height of the active area contact structure.
In one embodiment, the height difference between active area contact holes 120 and word line contact holes 119 is greater than or equal to 0 and less than twenty percent of the active area contact hole height, and in an actual semiconductor device, the height difference between active area contact holes and word line contact holes 119 may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, etc. of the active area contact hole height.
In one embodiment, the device further includes a first metal layer located in the word line trench, an upper surface of the first metal layer being in contact with a lower surface of the word line conductive structure, for example, the first metal layer may be a titanium/titanium nitride metal layer for adhesion and barrier.
In one embodiment, the semiconductor device is a dynamic random access memory.
The semiconductor device comprises a substrate, wherein a memory cell array area is formed on the substrate, and word line grooves are formed in the memory cell array area at intervals; the word line conductive structure comprises a word line conductive structure of a word line contact part and a word line conductive structure outside the word line contact part; the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure outside the word line contact part. The device substrate surface of the application is formed with the word line conducting structure of word line contact portion's thickness is greater than the word line conducting structure of the thickness of the word line conducting structure outside the word line contact portion, compare with the device of the word line conducting structure of word line contact portion's thickness equals the word line conducting structure's outside the word line contact portion in the word line conducting structure, the windowing position degree of depth of word line contact hole has been reduced, the process time in the contact hole forming process is reduced, the excessive erosion to the contact hole that the depth of windowing is shallower in the contact hole process has been reduced, the device short circuit that contact hole anomaly arouses is avoided unusual.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device includes:
obtaining a substrate, wherein the substrate comprises a storage unit array area;
forming word line grooves arranged at intervals in the memory cell array area;
filling word line conductive materials in the word line grooves to form word line conductive films;
forming photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact part and exposes the word line conductive film outside the word line contact part;
etching the word line conductive film uncovered by the photoresist to a target height by using the photoresist as a barrier layer to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact part is greater than that of the word line conductive structure uncovered by the photoresist;
and removing the photoresist.
2. The method of claim 1, wherein the wordline contact is located at an end of the wordline conductive structure.
3. The method of claim 1, wherein after removing the photoresist, further comprising:
forming a first insulating medium layer on the surface of the substrate;
and patterning the first insulating medium layer to form word line contact holes on the word line contact parts.
4. The method of claim 3, wherein the substrate further comprises a peripheral circuit region comprising a transistor active region, the method further comprising:
forming a second insulating medium layer on the surface of the active region;
and patterning the second insulating medium layer, and forming an active region contact hole on the source/drain region of the active region.
5. The method of claim 4, wherein the word line contact hole and the active region contact hole are formed by a same process.
6. The method of claim 4, wherein the first insulating dielectric layer and the second insulating dielectric layer are formed by a same process.
7. A semiconductor device, comprising:
the memory device comprises a substrate, a first substrate and a second substrate, wherein a memory cell array area is formed on the substrate, and word line grooves are formed in the memory cell array area at intervals;
word line conductive structures including word line conductive structures of the word line contact portions and word line conductive structures outside the word line contact portions;
the thickness of the word line conductive structure of the word line contact part is larger than that of the word line conductive structure outside the word line contact part.
8. The device of claim 7, wherein the word line contact is located at an end of the word line conductive structure.
9. The device of claim 7, wherein a ratio of a thickness of the word line conductive structure of the word line contact to a thickness of the word line conductive structure outside the word line contact is greater than or equal to 1.5 and less than or equal to 4.0.
10. The device of claim 7, further comprising:
a peripheral circuit region including a transistor active region having source/drain regions;
the insulating medium layer is positioned on the surfaces of the word line conductive structure and the active region;
a word line contact structure formed on and in contact with the word line contact;
an active region contact structure formed on the transistor active region and in contact with source/drain regions of the transistor active region.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911257093.5A CN112951825A (en) | 2019-12-10 | 2019-12-10 | Semiconductor device and manufacturing method thereof |
| US17/420,125 US20220157830A1 (en) | 2019-12-10 | 2020-11-17 | A Semiconductor Device and A Manufacturing Method |
| PCT/CN2020/129374 WO2021115042A1 (en) | 2019-12-10 | 2020-11-17 | Semiconductor device and manufacturing method therefor |
| EP20898273.6A EP3971975A4 (en) | 2019-12-10 | 2020-11-17 | Semiconductor device and manufacturing method therefor |
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| CN201911257093.5A CN112951825A (en) | 2019-12-10 | 2019-12-10 | Semiconductor device and manufacturing method thereof |
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| CN112951825A true CN112951825A (en) | 2021-06-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
| WO2024093021A1 (en) * | 2022-11-04 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
| WO2024093021A1 (en) * | 2022-11-04 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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