CN111508966B

CN111508966B - Three-dimensional memory and preparation method thereof

Info

Publication number: CN111508966B
Application number: CN202010349737.XA
Authority: CN
Inventors: 肖莉红
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-04-28
Filing date: 2020-04-28
Publication date: 2021-04-20
Anticipated expiration: 2040-04-28
Also published as: CN111508966A; CN113314543A; CN113314543B

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a laminated structure formed on the surface of a substrate; etching the laminated structure to form a channel hole penetrating through the laminated structure; and sequentially forming a blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole, wherein the tunneling layer is abutted against the blocking layer at the top and the bottom of the channel hole so that the charge trapping layer is surrounded by the tunneling layer and the blocking layer. The technical scheme of the application solves the problems that in a channel plug with transverse extension in the prior art, charges are easy to diffuse out of a charge trapping layer, so that the risk of charge accumulation at the channel plug is greatly increased, and the reliability of a three-dimensional memory is influenced.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof.

Background

In a three dimensional memory, the channel plug at the End of the NAND string is connected to a BEOL (Back End of line) line, such as a bit line, through a conductive contact via V0. At present, a memory layer is formed on an inner wall of a channel hole, the memory layer is an Oxide-Nitride-Oxide (ONO) structure composed of a tunneling layer, a charge trapping layer and a blocking layer, a channel layer is formed on a surface of the memory layer, a channel Oxide is filled to cover the channel layer and fill the channel hole, a portion of the channel Oxide is removed to form an opening, and finally, a polysilicon is filled in the opening to form a channel plug connected with the channel layer.

Since the channel plug has a conductive property that is conductively connected to conductive contact hole V0, such that conductive contact hole V0 can be disposed only at a range of lateral dimensions of the channel plug, it is important to increase the wiring range of conductive contact hole V0, i.e., the lateral dimension of the channel plug.

At present, in a channel plug with a laterally expanded size, charges are easy to diffuse out of a charge trapping layer, so that the risk of charge accumulation at the channel plug is greatly increased, and the reliability of the three-dimensional memory is affected.

Disclosure of Invention

In view of this, the present application provides a three-dimensional memory and a method for manufacturing the same, so as to solve the problem that in the prior art, in a laterally extended channel plug, charges are easily diffused from a charge trapping layer, so that the risk of charge accumulation at the channel plug is greatly increased, and the reliability of the three-dimensional memory is affected.

In a first aspect, the present application provides a method for manufacturing a three-dimensional memory, including:

providing a semiconductor structure, wherein the semiconductor structure comprises a laminated structure formed on the surface of a substrate;

etching the laminated structure to form a channel hole penetrating through the laminated structure; and the number of the first and second groups,

and sequentially forming a blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole, wherein the parts of the tunneling layer at the top and the bottom of the channel hole are abutted against the blocking layer so that the charge trapping layer is surrounded by the tunneling layer and the blocking layer.

In one possible embodiment, the sequentially forming a blocking layer, a charge trapping layer and a tunneling layer on the sidewall of the channel hole includes:

forming an epitaxial layer at the bottom of the channel hole;

forming a blocking layer, a charge capturing layer and a first tunneling layer on the side wall of the channel hole and the surface of the epitaxial layer in sequence;

sequentially etching the first tunneling layer, the charge trapping layer and the blocking layer at the bottom of the channel hole to expose the epitaxial layer;

etching the charge trapping layer to enable a groove to be formed between the part of the charge trapping layer, which is positioned at the top of the channel hole and at the bottom of the channel hole, and the adjacent first tunneling layer and the adjacent blocking layer; and the number of the first and second groups,

and forming a second tunneling layer on the exposed surface of the tunneling layer and the exposed surface of the epitaxial layer, so that the second tunneling layer fills the groove and is connected with the first tunneling layer to form the tunneling layer.

In one possible embodiment, after forming a second tunneling layer on the exposed surface of the tunneling layer and the exposed surface of the epitaxial layer, so that the second tunneling layer fills the groove and is connected with the first tunneling layer to form a tunneling layer, the method includes:

and forming a channel layer which covers the tunneling layer and is abutted to the epitaxial layer.

In one possible embodiment, the forming a channel layer overlying the tunneling layer and abutting the epitaxial layer includes:

forming a first channel layer on the surface of the tunneling layer;

sequentially etching the first channel layer and the tunneling layer at the bottom of the channel hole to expose the epitaxial layer; and the number of the first and second groups,

and forming the second channel layer on the exposed surface of the epitaxial layer so that the second channel layer is connected with the first channel layer to form a channel layer which covers the tunneling layer and is abutted to the epitaxial layer.

In one possible embodiment, a top layer of the stacked structure is a hard mask layer, and after the forming of the channel layer covering the tunneling layer and abutting against the epitaxial layer, the method includes:

and filling a channel oxide in the channel hole, wherein the channel oxide covers the channel layer.

In one possible embodiment, after the filling of the trench oxide in the trench hole and the trench oxide covering the channel layer, the method includes:

and carrying out planarization treatment on the blocking layer, the tunneling layer, the channel layer and the channel oxide by taking the hard mask layer as a stop layer to form a channel structure positioned in the channel hole.

In one possible embodiment, after the planarization process is performed on the blocking layer, the tunneling layer, the channel layer, and the channel oxide by using the hard mask layer as a stop layer to form a channel structure located in the channel hole, the method includes:

and removing the part of the channel structure positioned on the hard mask layer and at least part of the second-level layer positioned on the laminated structure so as to enable the top surface of the channel structure to be lower than that of the second-level layer.

In one possible embodiment, after removing the portion of the channel structure located on the hard mask layer and at least the portion located on the second top layer of the stacked structure to make the top surface of the channel structure lower than the top surface of the second top layer, the method includes:

and forming a channel plug connected with the channel layer, wherein the channel plug covers the hard mask layer and the channel structure.

In one possible embodiment, after the forming of the channel plug connected to the channel layer, the method includes:

and carrying out planarization treatment on the hard mask layer and the channel plug by taking the secondary top layer as a stop layer.

and performing first planarization treatment on the channel plug by taking the hard mask layer as a stop layer.

In one possible embodiment, after the first planarization treatment is performed on the channel plug by using the hard mask layer as a stop layer, the method includes:

removing the hard mask layer;

and performing second planarization treatment on the channel plug by taking the secondary top layer as a stop layer.

and carrying out planarization treatment on the hard mask layer, the blocking layer, the tunneling layer, the channel layer and the channel oxide by taking the second-to-top layer of the laminated structure as a stop layer to form a channel structure in the channel hole.

In one possible embodiment, after the step of planarizing the hard mask layer, the blocking layer, the tunneling layer, the channel layer, and the channel oxide by using the second-to-top layer of the stacked structure as a stop layer to form a channel structure located in the channel hole, the method includes:

sequentially forming an anti-reflection layer and a positive photoresist layer on the secondary top layer and the top surface of the channel structure;

and etching the positive photoresist layer and the anti-reflection layer in sequence to expose the channel structure.

In one possible embodiment, after the sequentially etching the positive photoresist layer and the anti-reflection layer to expose the trench structure, the method includes:

and removing the positive photoresist layer and at least part of the channel structure positioned on the anti-reflection layer and the secondary top layer so that the top surface of the channel structure is lower than that of the secondary top layer.

In one possible embodiment, after the removing the positive photoresist layer and the portion of the channel structure located on the anti-reflection layer and the at least portion located on the secondary top layer to make the top surface of the channel structure lower than the top surface of the secondary top layer, the method includes:

forming a channel plug connected to the channel layer, wherein the channel plug covers the second-level layer and the channel structure.

and carrying out planarization treatment on the anti-reflection layer and the channel plug by taking the secondary top layer as a stop layer.

and carrying out planarization treatment on the channel plug by taking the anti-reflection layer as a stop layer.

In one possible embodiment, after the planarization treatment is performed on the channel plug by using the anti-reflection layer as a stop layer, the method includes:

removing the anti-reflection layer to expose the secondary top layer;

buffer forming an insulating layer, wherein the insulating layer covers the secondary top layer and the channel structure;

and carrying out buffer planarization treatment on the insulating layer.

In a second aspect, the present application provides a three-dimensional memory comprising:

a semiconductor structure comprising a stacked structure formed on a surface of a substrate;

a channel hole formed in the laminated structure, the channel hole penetrating through the laminated structure;

an epitaxial layer formed at the bottom of the channel hole;

the tunnel layer is located at the top and the bottom of the channel hole and is abutted to the blocking layer so that the charge capturing layer is surrounded by the tunnel layer and the blocking layer, and the blocking layer and the tunnel layer are abutted to the epitaxial layer.

In a possible embodiment, the method further comprises:

and the channel layer is formed on the surface of the tunneling layer and is abutted against the epitaxial layer.

In a possible embodiment, the method further comprises:

and the channel oxide is filled in the channel hole and covers the channel layer.

In one possible embodiment, the blocking layer, the charge trapping layer, the tunneling layer, the channel layer, and the channel oxide form a channel structure, and a top surface of the channel structure and a sidewall of the channel hole jointly form a wall of the accommodating groove through an etching process.

In a possible embodiment, the method further comprises:

and the channel plug is formed in the accommodating groove and is connected with the channel layer.

The utility model provides a technical scheme forms the barrier layer, charge trapping layer and tunnel layer through the lateral wall at the trench hole in proper order to make the tunnel layer be located the top of trench hole and the part of bottom directly be connected with the barrier layer, thereby make the charge trapping layer as the intermediate level surround by barrier layer and tunnel layer completely, even make even if form channel layer and channel plug in follow-up technology, charge trapping layer is because of being blocked layer and tunnel layer encapsulation, also can not be in top position department and channel plug lug connection, and in bottom position department and channel layer lug connection. The charge can be kept in the charge trapping layer for storage operation, and can not be diffused out and accumulated in the position of the channel plug in a large amount, so that the threshold voltage deviation can be prevented, especially the threshold voltage deviation of the top selection gate and the bottom selection gate which can be formed subsequently can be prevented, the high stability can be ensured after repeated erasing, reading and programming operations, and the device performance of the three-dimensional memory can be further improved.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a three-dimensional memory according to the prior art;

FIG. 2 is a schematic diagram of another prior art three-dimensional memory structure;

fig. 3 is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a semiconductor structure of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a trench hole of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart illustrating a method for manufacturing a memory layer of a three-dimensional memory according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a memory layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of an epitaxial layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a blocking layer, a charge trapping layer and a first tunneling layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a blocking layer, a charge trapping layer and a first tunneling layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a blocking layer, a charge trapping layer and a first tunneling layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 12 is a schematic flowchart of another method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

fig. 13 is a schematic flowchart of another method for manufacturing a channel layer of a three-dimensional memory according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a channel layer of another three-dimensional memory according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a first channel layer of another three-dimensional memory according to an embodiment of the present application;

fig. 16 is a schematic diagram illustrating a state of a first channel layer of another three-dimensional memory according to an embodiment of the present disclosure;

FIG. 17 is a schematic diagram of another three-dimensional memory tunnel oxide structure according to an embodiment of the present application;

FIG. 18 is a state diagram of another three-dimensional memory according to an embodiment of the present disclosure;

FIG. 19 is a schematic structural diagram of a channel structure of another three-dimensional memory according to an embodiment of the present application;

FIG. 20 is a schematic diagram of another state of a channel structure of another three-dimensional memory according to an embodiment of the present application;

fig. 21 is a schematic view illustrating a state of a channel plug of another three-dimensional memory according to an embodiment of the present disclosure;

FIG. 22 is a schematic structural diagram of another three-dimensional memory according to an embodiment of the present application;

FIG. 23 is a diagram illustrating a state of another three-dimensional memory according to an embodiment of the present application;

FIG. 24 is a diagram illustrating another state of another three-dimensional memory according to an embodiment of the present application;

FIG. 25 is a schematic diagram of another state of a channel structure of another three-dimensional memory according to an embodiment of the present application;

FIG. 26 is a schematic view of an anti-reflective layer and a positive photoresist layer of another three-dimensional memory according to an embodiment of the present application;

FIG. 27 is a schematic diagram illustrating a state of an anti-reflective layer and a positive photoresist layer of another three-dimensional memory according to an embodiment of the present application;

FIG. 28 is a schematic diagram illustrating another structure of a channel structure of a three-dimensional memory according to an embodiment of the present application;

FIG. 29 is a schematic diagram illustrating another state of a channel structure of another three-dimensional memory according to an embodiment of the present application;

FIG. 30 is a schematic view of another state of a channel plug of another three-dimensional memory according to an embodiment of the present application;

FIG. 31 is a diagram illustrating another state of another three-dimensional memory according to an embodiment of the present application;

FIG. 32 is a schematic diagram of another state of a three-dimensional memory according to an embodiment of the present application;

fig. 33 is a schematic structural diagram of another three-dimensional memory according to an embodiment of the present application.

Detailed Description

Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it is to be understood that the invention may be practiced otherwise than as specifically described and that the invention is therefore not limited to the following embodiments.

In a three dimensional memory, the channel plug at the End of the NAND string is connected to a BEOL (Back End of line) line, such as a bit line, through a conductive contact via V0. At present, a memory layer is formed on an inner wall of a Channel Hole (CH), the memory layer is an Oxide-Nitride-Oxide (ONO) structure formed by a tunneling layer, a charge trapping layer and a blocking layer, a Channel layer is formed on a surface of the memory layer, a Channel Oxide is filled to cover the Channel layer and fill the Channel hole, a portion of the Channel Oxide is removed to form an opening, and finally, a polysilicon is filled in the opening to form a Channel plug connected to the Channel layer.

Since the channel plug has a conductive property, it can be conductively connected to conductive contact hole V0, so that conductive contact hole V0 can be disposed only in the lateral dimension range of the channel plug, that is, only in the lateral range indicated by the dotted line in fig. 1, resulting in limitation of the wiring position and the wiring margin thereof. Therefore, it is important to increase the wiring range of the conductive contact hole V0, i.e., the lateral size of the channel plug.

As shown in fig. 2, in the channel plug with the laterally expanded dimension, the charge trapping layer is easily connected to the channel plug at the Top position thereof, i.e., the position of the Top Select Gate (TSG) in the stacked structure, and is directly connected to the channel layer at the Bottom position thereof, i.e., the position of the Bottom Select Gate (BSG) in the stacked structure, because the channel plug and the channel layer both have conductivity, the channel layer is connected to the channel plug, thereby causing charges to diffuse out of the charge trapping layer and to be greatly accumulated at the channel plug, thereby causing a Threshold voltage (Vt) shift, affecting the reliability of the three-dimensional memory, especially after repeated reading, programming and erasing, the large charges accumulated at the channel plug cause a further shift of the Threshold voltages of the Top select gate and the Bottom select gate, further resulting in device performance degradation of the three-dimensional memory.

In view of the above, the present application provides a method for manufacturing a three-dimensional memory 100, and fig. 3 is a flowchart illustrating the method for manufacturing the three-dimensional memory 100 according to an embodiment of the present application. As shown in fig. 3, the method for manufacturing the three-dimensional memory 100 at least includes steps S100, S200, and S300, which are described in detail as follows:

s100: a semiconductor structure is provided, wherein the semiconductor structure comprises a stacked structure formed on a surface of a substrate.

S200: the stack is etched to form a trench hole through the stack.

S300: and sequentially forming a blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole, wherein the parts of the tunneling layer at the top and the bottom of the channel hole are abutted against the blocking layer so that the charge trapping layer is surrounded by the tunneling layer and the blocking layer.

Each step will be further described below.

The above step S100 will be described with reference to fig. 4, wherein fig. 4 is a schematic structural diagram of the semiconductor structure 10 of the three-dimensional memory 100 according to an embodiment of the present disclosure.

S100: a semiconductor structure 10 is provided, wherein the semiconductor structure 10 includes a stacked structure 12 formed on a surface of a substrate 11.

First, a substrate 11 is provided.

In the embodiment of the present application, the substrate 11 is a semiconductor substrate. For example, the substrate 11 may be a single crystal Silicon (Si) substrate, a single crystal Germanium (Ge) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like. The substrate 11 may also be a P-doped substrate or an N-doped substrate. The substrate 11 may be made of any suitable material according to practical requirements, and the present application is not limited to this material. Of course, in other embodiments, the material of the substrate 11 may also be a semiconductor or a compound including other elements. For example, the substrate 11 may be a gallium arsenide (GaAs) substrate, an Indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. Further, the substrate 11 may include a high voltage P-type well region (HVPW).

Next, a stacked structure 12 is formed on the surface of the substrate 11.

The laminated structure 12 includes dielectric layers 13 and sacrificial layers 14 that are successively and alternately laminated in a direction perpendicular to the substrate 11, and the laminated structure 12 having a multilayer structure is formed by the successive and alternate lamination of the dielectric layers 13 and the sacrificial layers 14. Specifically, the material of the dielectric layer 13 may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide. The material of the sacrificial layer 14 may be silicon nitride. In the embodiments of the present application, the material of the dielectric layer 13 is silicon oxide, and the material of the sacrificial layer 14 is silicon nitride.

And since the dielectric layer 13 and the sacrificial layer 14 have different etching selectivity, the sacrificial layer 14 as the gate sacrificial layer 14 will be removed in a subsequent process, and the space of the sacrificial layer 14 will be filled with a highly conductive material to form a gate layer. Specifically, the highly conductive material may be metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof. Of course, in other embodiments, the sacrificial layer 14 may also be a gate layer.

In an embodiment of the present application, the stacked structure 12 may further include a hard mask layer 15, where the hard mask layer 15 is a top layer of the stacked structure 12 shown in fig. 2, and can protect the dielectric layer 13 and the sacrificial layer 14 from being damaged when the stacked structure 12 is subsequently etched. For example, the hard mask layer 15 may be silicon nitride. Note that the hard mask layer 15 is removed in a subsequent process.

Further, in the stacked-layer structure 12, the sacrificial layer 14 includes a first sacrificial layer 141, a second sacrificial layer 142, and a third sacrificial layer 143. The first sacrificial layer 141 is a layer structure in which the sacrificial layers 14 are alternately stacked with the dielectric layers 13 and are replaced with gate layers in a subsequent process. The second sacrificial layer 142 is a layer structure closest to the substrate 11 in the sacrificial layer 14, and is replaced with a bottom select gate BSG in a subsequent process. The third sacrificial layer 143 is a layer of the sacrificial layer 14 closest to the hard mask layer 15, and is replaced with a top select gate TSG in a subsequent process.

The above step S100 will be described with reference to fig. 5, where fig. 5 is a schematic structural diagram of a trench hole 20 of a three-dimensional memory 100 according to an embodiment of the present disclosure.

S200: the stack 12 is etched to form a trench hole 20 through the stack 12.

It is understood that the trench hole 20 may be etched using a dry etching or wet etching process. The substrate 11 may be exposed when the channel hole 20 is etched to be formed, and after this etching step, the upper surface of the substrate 11 may be etched by a small amount. In addition, the portion of the substrate 11 exposed by the channel hole 20 may be a region where HVPW ions are implanted, and since P-type ions are implanted, the carrier density of the substrate 11 can be effectively increased.

The above step S300 will be described below with reference to fig. 6 and fig. 7, where fig. 6 is a schematic flow chart of a method for manufacturing the memory layer 30 of the three-dimensional memory 100 according to an embodiment of the present application, and fig. 7 is a schematic structural diagram of the memory layer 30 of the three-dimensional memory 100 according to an embodiment of the present application.

S300: a blocking layer 31, a charge trapping layer 32 and a tunneling layer 33 are sequentially formed on the sidewall of the channel hole 20, wherein portions of the tunneling layer 33 at the top and bottom of the channel hole 20 abut against the blocking layer 31 so that the charge trapping layer 32 is surrounded by the tunneling layer 33 and the blocking layer 31.

It is understood that the blocking layer 31, the charge trapping layer 32 and the tunneling layer 33 form the memory layer 30, and the memory layer 30 accordingly forms the ONO stack 12, since the blocking layer 31 may be Oxide such as silicon Oxide, the charge trapping layer 32 may be Nitride such as silicon Nitride, silicon oxynitride, a single layer or a multi-layer composite film thereof, and the tunneling layer 33 may be Oxide such as silicon Oxide, silicon oxynitride, a single layer or a multi-layer composite film thereof. The blocking layer 31 is formed between the sidewall of the trench hole 20 and the charge trapping layer 32, and can block the outflow of charges (electrons or holes). The charge trapping layer 32 is formed between the blocking layer 31 and the tunneling layer 33, so that charges from a subsequently formed channel layer can tunnel to the charge trapping layer 32 through the tunneling layer 33 to store the charges for a storage operation. The storage or removal of charge in the charge trapping layer 32 can affect the switching state and/or conductance of the channel structure within the channel hole 20. A tunneling layer 33 is formed over the charge-trapping layer 32 and is capable of tunneling charges from the channel layer.

As shown in fig. 6, the method for preparing the memory layer 30 may at least include steps S310, S320, S330, S340, and S350, which are described in detail as follows:

s310: an epitaxial layer is formed at the bottom of the channel hole.

S320: and sequentially forming a blocking layer, a charge trapping layer and a first tunneling layer on the side wall of the channel hole and the surface of the epitaxial layer.

S330: and sequentially etching the first tunneling layer, the charge trapping layer and the blocking layer at the bottom of the channel hole to expose the epitaxial layer.

S340: and etching the charge trapping layer so that the charge trapping layer is positioned at the top of the channel hole and a groove is formed between the part of the charge trapping layer positioned at the bottom of the channel hole and the adjacent first tunneling layer and the adjacent blocking layer.

S350: and forming a second tunneling layer on the surface of the exposed blocking layer and the surface of the exposed epitaxial layer so that the second tunneling layer fills the groove and is connected with the first tunneling layer to form the tunneling layer.

Each step will be further described below.

The above step S310 will be described with reference to fig. 8, where fig. 8 is a schematic structural diagram of an epitaxial layer of the three-dimensional memory 100 according to an embodiment of the present disclosure.

S310: an epitaxial layer 34 is formed at the bottom of the channel hole 20.

Specifically, the epitaxial layer 34 may be a silicon layer formed on the HVPW region of the substrate 11 by Selective Epitaxial Growth (SEG), which is located at the bottom of the channel hole 20 and covers the substrate 11, and the bottom select gate adjacent to the epitaxial layer 34 can constitute the bottom select transistor of the three-dimensional memory 100 when the subsequent sacrificial layer 14 is removed to form a gate layer. Wherein epitaxial layer 34 may serve as a channel for the bottom select transistor.

The above step S320 will be described with reference to fig. 9, wherein fig. 9 is a schematic structural diagram of the blocking layer 31, the charge trapping layer 32 and the first tunneling layer 331 of the three-dimensional memory 100 according to an embodiment of the present disclosure.

S320: a blocking layer 31, a charge trapping layer 32, and a first tunneling layer 331 are sequentially formed on the sidewall of the trench hole 20 and the surface of the epitaxial layer 34.

Since the epitaxial layer 34 is formed at the bottom of the channel hole 20 in the previous step, both the sidewall of the channel hole 20 and the surface of the epitaxial layer 34 are exposed at this time. Thereby, the blocking layer 31, the charge trapping layer 32, and the first tunneling layer 331 are sequentially formed on the sidewall of the channel hole 20 and the surface of the epitaxial layer 34. The blocking layer 31, the charge trapping layer 32 and the first tunneling layer 331 are stacked and formed of an ONO structure.

In addition, in this step, the blocking layer 31, the charge trapping layer 32 and the first tunneling layer 331 not only cover the sidewalls of the channel hole 20 and the surface of the epitaxial layer 34, but also cover the hard mask layer 15 (top layer) of the stacked-layer structure 12.

The above step S330 will be described with reference to fig. 10, wherein fig. 10 is another structural diagram of the blocking layer 31, the charge trapping layer 32 and the first tunneling layer 331 of the three-dimensional memory 100 according to an embodiment of the disclosure.

S330: the first tunneling layer 331, the charge trapping layer 32, and the blocking layer 31 at the bottom of the channel hole 20 are sequentially etched to expose the epitaxial layer 34.

Since the blocking layer 31, the charge trapping layer 32 and the first tunneling layer 331 are sequentially formed on the surface of the epitaxial layer 34, when the bottom layer structure needs to be opened to expose the epitaxial layer 34, the first tunneling layer 331, the charge trapping layer 32 and the blocking layer 31 need to be sequentially etched to form an opening for exposing the epitaxial layer 34, thereby facilitating the subsequent processes. In one possible embodiment, the etching process is a punch etch.

Note that in this etching step, the first tunneling layer 331 on top of the hard mask layer 15 is also etched a small amount.

The above step S330 will be described with reference to fig. 11, where fig. 11 is a schematic structural diagram of a blocking layer 31, a charge trapping layer 32 and a first tunneling layer 331 of a three-dimensional memory 100 according to an embodiment of the present disclosure.

S340: the charge trapping layer 32 is etched such that the portion of the charge trapping layer 32 at the top of the channel hole 20 and at the bottom of the channel hole 20 forms a recess 40 with the adjacent first tunneling layer 331 and blocking layer 31.

Since the material of the charge trapping layer 32 can be a single layer of silicon nitride, silicon oxynitride, or a multi-layer composite film thereof, the material of the blocking layer 31 and the first tunneling layer 331 may be a single layer or a multi-layer composite film of silicon oxide, silicon oxynitride, etc., in addition, because the charge trapping layer 32 and the first tunneling layer 331 contain different nitrogen concentrations or different nitrogen-oxygen concentration ratios, and the wet etching speeds of different nitrogen concentrations or different nitrogen-oxygen concentration ratios are different, thereby enabling selective etching of the charge trapping layer 32, and therefore, etching is performed using a process of high etching selectivity caused by different N/O concentration ratios, so that the charge trapping layer 32 is etched, while the blocking layer 31 and the first tunneling layer 331 are left, so that the portion of the charge trapping layer 32 on top of the channel hole 20 forms a recess 40 with the adjacent first tunneling layer 331 and blocking layer 31, and the portion of the charge trapping layer 32 at the bottom of the channel hole 20 and the adjacent first tunneling layer 331 and blocking layer 31 also form a recess 40.

It is understood that the first tunneling layer 331, the charge trapping layer 32, and the blocking layer 31 at the bottom of the channel hole 20 are removed in the foregoing step, so that the charge trapping layer 32 at the opposite sides of the bottom of the channel hole 20 are exposed. Therefore, when etching is performed by using a process with high etching selectivity caused by different N/O concentration ratios, not only a portion of the charge trapping layer 32 located at the top of the channel hole 20 is etched away, but also a portion of the charge trapping layer 32 located at the bottom of the channel hole 20 is etched away, and in addition, the etching precision of the charge trapping layer 32 can be controlled by controlling the time, so as to achieve a predetermined etching effect. In the embodiment of the present application, the predetermined etching effect is to etch the portions of the charge trapping layer 32 located at the top of the channel hole 20 and located at the bottom of the channel hole 20. Specifically, etching the portion of the charge trapping layer 32 on top of the channel hole 20 refers to etching a portion of the charge trapping layer 32 near the third sacrificial layer 143 (a top select gate TSG is formed in a subsequent process). And etching the portion of the charge trapping layer 32 at the bottom of the channel hole 20 refers to etching a portion of the charge trapping layer 32 near the second sacrificial layer 142 (a bottom select gate BSG is formed in a subsequent process).

In addition, in this etching step. The portion of the charge trapping layer 32 above the hard mask layer 15 is also etched.

The above step S350 will be described with reference to fig. 7, wherein fig. 7 is a schematic structural diagram of the memory layer 30 of the three-dimensional memory 100 according to an embodiment of the present disclosure.

S350: a second tunneling layer 332 is formed on the exposed surface of the blocking layer 31 and the exposed surface of the epitaxial layer 34, such that the second tunneling layer 332 fills the recess 40 and connects with the first tunneling layer 331 to form a tunneling layer 33.

It is understood that in the tunneling layer 33 of fig. 7, the dashed box is divided into the first tunneling layer 331 and the dashed box is divided into the second tunneling layer 332.

Since the filling-material-free groove 40 is formed by etching the charge trapping layer 32 in the foregoing steps, the structural stability of the three-dimensional memory 100 is easily affected, and in the process of etching the charge trapping layer 32, the first tunneling layer 331 may also be removed by a small amount, so that the first tunneling layer 331 is too thin, and the overall reliability of the memory layer 30 is affected. Therefore, the recess 40 formed in the previous step needs to be filled, and at the same time, the reliability of the memory layer 30 as a whole needs to be ensured.

Thus, in this step, the second tunneling layer 332 is formed, so that the second tunneling layer 332 fills the groove 40 and is connected to the first tunneling layer 331 to form the tunneling layer 33. It is understood that the tunneling layer 33 is formed by the first tunneling layer 331 and the second tunneling layer 332 together, as compared with the direct formation of the first tunneling layer 331, so that the thickness thereof can be ensured, thereby improving the reliability of the whole memory layer 30. The tunneling layer 33 abuts against the blocking layer 31, so that the charge trapping layer 32 is completely surrounded by the tunneling layer 33 and the blocking layer 31, that is, the charge trapping layer 32 is equivalently sealed by the blocking layer 31 and the tunneling layer 33, so that even if the channel layer 35 and the channel plug are formed in a subsequent process, the charge trapping layer 32 is completely surrounded by the tunneling layer 33 and the blocking layer 31, and thus the charge trapping layer is not directly connected with the channel layer 35 at the position of the second sacrificial layer 142, and is not directly connected with the channel plug at the position of the third sacrificial layer 143.

In other words, by sequentially forming the blocking layer 31, the charge trapping layer 32, and the tunneling layer 33 on the sidewall of the channel hole 20 and directly connecting the portions of the tunneling layer 33 at the top and the bottom of the channel hole 20 with the blocking layer 31, the charge trapping layer 32 as an intermediate layer is completely surrounded by the blocking layer 31 and the tunneling layer 33, so that even if the channel layer 35 and the channel plug are formed in the subsequent process, the charge trapping layer 32 is not directly connected with the channel plug at the top position and is not directly connected with the channel layer 35 at the bottom position because it is encapsulated by the blocking layer 31 and the tunneling layer 33. The charges can be retained in the charge trapping layer 32 for storage operation, and will not diffuse out and accumulate in the channel plug position in a large amount, which is beneficial to preventing the threshold voltage shift, especially the threshold voltage shift of the top select gate and the bottom select gate which will be formed subsequently, and ensuring stronger stability after repeated erasing, reading and programming operations, thereby further improving the device performance of the three-dimensional memory 100.

Referring to fig. 12, fig. 12 is a schematic flow chart illustrating a method for manufacturing another three-dimensional memory 100 according to an embodiment of the present disclosure. As shown in fig. 12, the method for manufacturing the three-dimensional memory 100 may further include at least step S400 in addition to steps S100 to S300, which is described in detail as follows:

s400: and forming a channel layer which covers the tunneling layer and is abutted to the epitaxial layer.

It should be noted that, in this embodiment, only step S400 is used as a detailed description, and the repeated contents of steps S100 to S300 are not repeated. Step S400 is actually performed after step S350. That is, after the second tunneling layer 332 is formed on the surface of the exposed tunneling layer 33 and the surface of the exposed epitaxial layer 34, so that the second tunneling layer 332 fills the recess 40 and is connected to the first tunneling layer 331 to form the tunneling layer 33, the channel layer 35 is formed to cover the tunneling layer 33 and abut against the epitaxial layer 34.

It is understood that the channel layer 35 in this step is the channel layer 35 described above, and the channel layer 35 can provide a channel for movement of carriers for the three-dimensional memory 100. By forming the channel layer 35 in contact with the epitaxial layer 34 on the surface of the tunneling layer 33, the channel layer 35 and the epitaxial layer 34 can be electrically connected. In an embodiment of the present application, the material of the channel layer 35 may be polysilicon.

The above step S400 will be described below with reference to fig. 13 and fig. 14, where fig. 13 is a schematic flow chart of a method for manufacturing the channel layer 35 of another three-dimensional memory 100 provided in the embodiment of the present application, and fig. 14 is a schematic structural view of the channel layer 35 of another three-dimensional memory 100 provided in the embodiment of the present application.

As shown in fig. 13, the method of manufacturing the channel layer 35 may include at least steps S410, S420, and S430, which are described in detail as follows:

s410: and forming a first channel layer on the surface of the tunneling layer.

S420: and sequentially etching the first channel layer and the tunneling layer at the bottom of the channel hole to expose the epitaxial layer.

S430: and forming a second channel layer on the surface of the exposed epitaxial layer so that the second channel layer is connected with the first channel layer to form a channel layer which covers the tunneling layer and is abutted to the epitaxial layer.

Each step will be further described below.

The above step S410 will be described below with reference to fig. 15, where fig. 15 is a schematic structural diagram of the first channel layer 351 of another three-dimensional memory 100 provided in this embodiment of the present application.

S410: the first channel layer 351 is formed on the surface of the tunneling layer 33.

It is understood that the first channel layer 351 is a layer structure covering the surface of the tunneling layer 33, and the material thereof may be polysilicon. Specifically, the first channel layer 351 covers not only the tunneling layer 33 located in the channel hole 20, but also the tunneling layer 33 located above the hard mask layer 15, so as to ensure that the tunneling layer 33 can be covered in an omnidirectional manner, and further ensure that the charges inside the tunneling layer 33 can be tunneled.

The above step S430 is described below with reference to fig. 16, where fig. 16 is a schematic diagram of a state of the first channel layer 351 of another three-dimensional memory 100 according to an embodiment of the present application.

S420: the first channel layer 351 and the tunneling layer 33 at the bottom of the channel hole 20 are sequentially etched to expose the epitaxial layer 34.

Since the tunneling layer 33 and the first channel layer 351 are sequentially formed on the surface of the epitaxial layer 34. In other words, there is still a tunneling layer 33 between the first channel layer 351 and the epitaxial layer 34, so that direct conduction between the first channel layer 351 and the epitaxial layer 34 cannot be achieved. Therefore, the tunneling layer 33 at the bottom of the channel hole 20 needs to be etched away. Thus, the subsequent processes are facilitated by sequentially etching the first channel layer 351 and the tunneling layer 33 to expose the epitaxial layer 34. In one possible embodiment, the etching process is a punch etch.

Further, in this step, after the epitaxial layer 34 is exposed, the trench hole 20 may be cleaned, so that by-products generated by etching may be cleaned and removed, thereby ensuring the yield of the three-dimensional memory 100.

The above step S430 is described below with reference to fig. 14, where fig. 14 is a schematic structural diagram of the channel layer 35 of another three-dimensional memory 100 provided in the embodiment of the present application.

S430: a second channel layer 352 is formed on the exposed surface of the epitaxial layer 34, and a channel layer 35 that covers the tunneling layer 33 and is in contact with the epitaxial layer 34 is formed by connecting the second channel layer 352 to the first channel layer 351.

It is understood that in the channel layer 35 of fig. 14, the dotted line includes an upper portion as the first tunneling layer 331 and a lower portion as the second tunneling layer 332.

Since the first channel layer 351 located at the bottom of the channel hole 20 is etched away in the foregoing steps, the first channel layer 351 and the epitaxial layer 34 are still in an unconnected state. As a result, the second channel layer 352 is formed on the exposed surface of the epitaxial layer 34, the second channel layer 352 is formed at the position of the tunneling layer 33 etched away in the above step, and the channel layer 35 that covers the tunneling layer 33 and is in contact with the epitaxial layer 34 is formed by connecting the second channel layer 352 to the first channel layer 351, whereby the channel layer 35 and the epitaxial layer 34 can be electrically connected.

Referring to fig. 17, fig. 17 is a schematic structural diagram of a tunnel oxide 36 of another three-dimensional memory 100 according to an embodiment of the present disclosure.

As shown in fig. 17, after forming the channel layer 35 that covers the tunneling layer 33 and abuts the epitaxial layer 34, the channel hole 20 is filled with a tunnel oxide 36, and the tunnel oxide 36 covers the channel layer 35.

It is understood that after the blocking layer 31, the charge trapping layer 32, the tunneling layer 33 and the channel layer 35 are sequentially formed on the sidewall of the channel hole 20, there is still a gap in the channel hole 20, and in order to support the channel hole 20 and improve the reliability of the three-dimensional memory 100, the channel oxide 36 is filled in the channel hole 20 to cover the channel layer 35, so that the channel hole 20 is filled with the blocking layer 31, the charge trapping layer 32, the tunneling layer 33, the channel layer 35 and the channel oxide 36. In one possible embodiment, the material of the tunnel oxide 36 may be silicon oxide.

Referring to fig. 18, fig. 18 is a diagram illustrating a state of a channel structure 37 of another three-dimensional memory 100 according to an embodiment of the present disclosure.

As shown in fig. 18, in the first embodiment of this embodiment, after the tunnel oxide 36 is filled in the channel hole 20 and the tunnel oxide 36 covers the channel layer 35, the barrier layer 31, the tunneling layer 33, the channel layer 35, and the channel oxide 36 are planarized using the hard mask layer 15 as a stop layer, thereby forming a channel structure 37 located in the channel hole 20.

Due to the multi-layer structure of the blocking layer 31, the tunneling layer 33, the channel layer 35 and the tunnel oxide 36 covering the trench 20 and the hard mask layer 15 in the foregoing steps, the multi-layer structure makes it difficult for the three-dimensional memory 100 to have a flat surface, and thus the yield of the three-dimensional memory 100 is easily affected. Therefore, it needs to be planarized so that the three-dimensional memory 100 has a flat surface.

It is understood that the planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method to perform the planarization process according to the actual situation, and the application is not limited thereto. The hard mask layer 15 is used as a stop layer to perform the planarization process, which means that the planarization process stops on the upper surface of the hard mask layer 15, that is, the structures above the hard mask layer 15 and the channel hole 20 are removed, so that the surface of the hard mask layer 15 and the channel hole 20 filled with the channel structure 37 can be exposed. And the channel structure 37 may be a structure collectively formed by the blocking layer 31, the charge trapping layer 32, the tunneling layer 33, the channel layer 35, and the channel oxide 36 and located within the channel hole 20. Accordingly, the channel structure 37 can fill the channel hole 20 to support the channel hole 20, thereby ensuring the stability of the three-dimensional memory 100.

Referring to fig. 19 and 20 together, fig. 19 is a schematic structural diagram of a channel structure 37 of another three-dimensional memory 100 according to an embodiment of the present application, and fig. 20 is a schematic state diagram of the channel structure 37 of the another three-dimensional memory 100 according to the embodiment of the present application.

Specifically, after the barrier layer 31, the tunneling layer 33, the channel layer 35 and the channel oxide 36 are planarized using the hard mask layer 15 as a stop layer to form the channel structure 37 in the channel hole 20, a portion of the channel structure 37 located in the hard mask layer 15 and at least a portion of the channel structure 37 located in the second-most layer of the stacked-layer structure 12 are removed, so that the top surface of the channel structure 37 is lower than the top surface of the second-most layer.

It is to be appreciated that after forming the channel structure 37 filling the channel hole 20, removing the portion of the channel structure 37 located on the hard mask layer 15 and at least the portion located on the second-level layer can provide for forming the channel plug 38 in a subsequent process. In one possible embodiment, as shown in fig. 19, all portions of the channel structure 37 are uniformly etched below the top surface of the second-level layer, and the top surface of the channel structure 37 is a plane or a cambered surface. In another possible embodiment, as shown in fig. 20, only the structure of the channel layer 35 in the channel structure 37 is not etched, in other words, only the blocking layer 31, the tunneling layer 33 and the channel oxide 36 formed of the silicon oxide material may be etched in this step, while the channel layer 35 formed of the polysilicon material remains.

It should be noted that, no matter how much the channel structure 37 is removed in this step, it is always necessary to ensure that the charge trapping layer 32 is completely surrounded by the tunneling layer 33 and the blocking layer 31, so as to ensure that the charges in the charge trapping layer 32 can be retained in the charge trapping layer 32 without being diffused out, which results in the reliability of the three-dimensional memory 100 being reduced.

Referring to fig. 21, fig. 21 is a schematic diagram illustrating a state of a channel plug 38 of another three-dimensional memory 100 according to an embodiment of the present disclosure.

As shown in fig. 21, after removing a portion of the channel structure 37 located on the hard mask layer 15 and at least a portion located on the next-to-top layer of the stacked-layer structure 12 such that the top surface of the channel structure 37 is lower than the top surface of the next-to-top layer, a channel plug 38 connected to the channel layer 35 is formed, wherein the channel plug 38 covers the hard mask layer 15 and the channel structure 37.

It is understood that, since the portion of the trench structure 37 in the trench hole 20 is removed in the previous step, in this step, when forming the trench plug 38, the trench plug 38 fills the trench hole 20 that is left blank in the previous step due to the removal of the portion of the trench structure 37 and covers the hard mask layer 15. In one possible embodiment, the material of the channel plug 38 may be polysilicon, and the channel plug 38 and the channel layer 35 are not only physically connected but also electrically connected.

In addition, the outer wall of the trench plug 38 abuts against the side wall of the trench hole 20, so that the lateral dimension of the trench plug 38 is further enlarged, which is beneficial to widening the wiring range of the conductive contact hole V0 when the conductive contact hole V0 is formed subsequently. Meanwhile, since the charge trapping layer 32 formed in the foregoing step can be completely surrounded by the blocking layer 31 and the tunneling layer 33, the charge trapping layer 32 is not electrically connected to the channel plug 38, and the risk of charge leakage in the charge trapping layer 32 is greatly reduced.

In a possible implementation manner, please refer to fig. 22, and fig. 22 is a schematic structural diagram of another three-dimensional memory 100 according to an embodiment of the present disclosure.

As shown in fig. 22, after forming the channel plug 38 connected to the channel layer 35, the hard mask layer 15 and the channel plug 38 are planarized with the sub-top layer as a stop layer.

It is understood that the planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method to perform the planarization process according to the actual situation, and the application is not limited thereto. The second-level layer is a dielectric layer 13 located below the hard mask layer 15 in the stacked structure 12, and the planarization process performed on the second-level layer with the second-level layer as a stop layer means that the planarization process stops on the upper surface of the second-level layer, that is, the hard mask layer 15 and a portion of the channel plug 38 located above the second-level layer are removed, so that the surface of the second-level layer and the surface of the channel plug 38 can be exposed, and the three-dimensional memory 100 has a flat surface.

In another possible implementation manner, please refer to fig. 22, 23 and 24 together, in which fig. 22 is a schematic structural diagram of another three-dimensional memory 100 provided in the embodiment of the present application, fig. 23 is a schematic state diagram of another three-dimensional memory 100 provided in the embodiment of the present application, and fig. 24 is a schematic state diagram of another three-dimensional memory 100 provided in the embodiment of the present application.

As shown in fig. 23, unlike the foregoing embodiment, after the channel plug 38 connected to the channel layer 35 is formed, the channel plug 38 is subjected to the first planarization process using the hard mask layer 15 as a stopper.

It is understood that the first planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method for performing the planarization process according to practical situations, and the application is not limited thereto. The hard mask layer 15 is used as a stop layer to planarize the hard mask layer 15, which means that the planarization stops on the upper surface of the hard mask layer 15, that is, a portion of the trench plug 38 above the hard mask layer 15 is removed, so that the surface of the hard mask layer 15 and the surface of the trench plug 38 can be exposed, and the three-dimensional memory 100 has a planar surface.

Next, as shown in fig. 24, in order to remove the film layer provided as the protective stacked structure 12 for the subsequent process of the three-dimensional memory 100, the hard mask layer 15 is removed.

Then, as shown in fig. 22, a second planarization process is performed on the channel plug 38 with the second-to-top layer as a stop layer, so that the three-dimensional memory 100 has a flat surface. It is understood that the second planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method for performing the planarization process according to practical situations, and the application is not limited thereto.

Referring to fig. 25, fig. 25 is a schematic view illustrating another state of a channel structure 37 of another three-dimensional memory 100 according to an embodiment of the present disclosure.

As shown in fig. 25, in the second embodiment of the present embodiment, different from the first embodiment, after the trench hole 20 is filled with the tunnel oxide 36 and the tunnel oxide 36 covers the channel layer 35, the barrier layer 31, the tunneling layer 33, the channel layer 35, and the tunnel oxide 36 are planarized using the second-to-top layer of the stacked-layer structure 12 as a stop layer, thereby forming a channel structure 37 located in the trench hole 20.

It is understood that the planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method to perform the planarization process according to the actual situation, and the application is not limited thereto. The second-to-top layer is a dielectric layer 13 located below the hard mask layer 15 in the stacked structure 12, and the planarization process performed on the second-to-top layer with the second-to-top layer as a stop layer means that the planarization process stops on the upper surface of the second-to-top layer, that is, the structures above the second-to-top layer, such as the hard mask layer 15, etc., are removed, so that the surface of the second-to-top layer and the channel hole 20 filled with the channel structure 37 can be exposed. And the channel structure 37 may be a structure collectively formed by the blocking layer 31, the charge trapping layer 32, the tunneling layer 33, the channel layer 35, and the channel oxide 36 and located within the channel hole 20. Accordingly, the channel structure 37 can fill the channel hole 20 to support the channel hole 20, thereby ensuring the stability of the three-dimensional memory 100.

Referring to fig. 26 and 27 together, fig. 26 is a schematic diagram of an anti-reflection layer 41 and a positive photoresist layer 42 of another three-dimensional memory 100 provided in the present embodiment, and fig. 27 is a schematic diagram of a state of the anti-reflection layer 41 and the positive photoresist layer 42 of another three-dimensional memory 100 provided in the present embodiment.

As shown in fig. 26, after the hard mask layer 15, the barrier layer 31, the tunneling layer 33, the channel layer 35 and the tunnel oxide 36 are planarized with the second-highest layer of the stacked-layer structure 12 as a stop layer to form the channel structure 37 in the channel hole 20, the anti-reflection layer 41 and the positive photoresist layer 42 are sequentially formed on the second-highest layer and the top surface of the channel structure 37; and, as shown in fig. 27, the positive photoresist layer 42 and the anti-reflection layer 41 are sequentially etched to expose the channel structure 37.

It is understood that the anti-reflection layer 41 can prevent the reflection of plasma during sputtering, the positive photoresist layer 42 has a property of being removed after exposure, and the positive photoresist layer 42 and the anti-reflection layer 41 can be exposed and etched using a mask used when forming the channel hole 20, so that the anti-reflection layer 41 and the positive photoresist layer 42 above the channel hole 20 are removed to expose the channel structure 37 in the channel hole 20.

In other embodiments, the positive photoresist layer may not be disposed, but a negative photoresist layer may be disposed, and then the negative photoresist layer corresponding to the channel structure is removed by using a mask and light irradiation, and the anti-reflection layer corresponding to the channel structure is etched to expose the channel structure.

Referring to fig. 28 and 29 together, fig. 28 is another schematic structural diagram of a channel structure 37 of another three-dimensional memory 100 according to an embodiment of the present disclosure, and fig. 29 is another schematic state diagram of the channel structure 37 of the another three-dimensional memory 100 according to the embodiment of the present disclosure.

Specifically, after the positive photoresist layer 42 and the anti-reflection layer 41 are sequentially etched to expose the channel structure 37, a portion of the positive photoresist layer 42 and the channel structure 37 located on the anti-reflection layer 41 and at least a portion located on the sub-top layer are removed so that the top surface of the channel structure 37 is lower than the top surface of the sub-top layer.

It is understood that, after the channel structure 37 filling the channel hole 20 is formed, the positive photoresist layer 42 and at least a portion of the channel structure 37 located at the anti-reflection layer 41 and at the sub-top layer are removed, so that preparation can be made for forming the channel plug 38 in a subsequent process. In one possible embodiment, as shown in fig. 28, all portions of the channel structure 37 are uniformly etched below the top surface of the second-level layer, and the top surface of the channel structure 37 is a plane or a cambered surface. In another possible embodiment, as shown in fig. 29, only the structure of the channel layer 35 in the channel structure 37 is not etched, in other words, only the blocking layer 31, the tunneling layer 33 and the channel oxide 36 formed of silicon oxide material may be etched in this step, while the channel layer 35 formed of polysilicon material remains.

Referring to fig. 30, fig. 30 is a schematic view illustrating another state of a channel plug 38 of another three-dimensional memory 100 according to an embodiment of the present disclosure.

It is to be understood that the channel plug 38 connected to the channel layer 35 is formed after removing the positive photoresist layer 42 and at least a portion of the channel structure 37 located on the anti-reflection layer 41 and on the sub-top layer such that the top surface of the channel structure 37 is lower than the top surface of the sub-top layer, wherein the channel plug 38 covers the sub-top layer and the channel structure 37.

Since the trench structure 37 in the trench hole 20 is partially removed in the above step, in this step, when forming the trench plug 38, the trench plug 38 fills the trench hole 20 that is left blank in the above step because the trench structure 37 is partially removed and covers the hard mask layer 15. In one possible embodiment, the material of the channel plug 38 may be polysilicon, and the channel plug 38 and the channel layer 35 are not only physically connected but also electrically connected.

As shown in fig. 22, the sub-top layer refers to a dielectric layer 13 located below the hard mask layer 15 in the stacked-layer structure 12, and after forming the channel plug 38 connected to the channel layer 35, the anti-reflection layer 41 and the channel plug 38 are planarized using the sub-top layer as a stopper.

It is understood that the planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method to perform the planarization process according to the actual situation, and the application is not limited thereto. The planarization process performed by using the second-highest layer as a stop layer means that the planarization process stops on the upper surface of the second-highest layer, that is, the hard mask layer 15 and the portion of the channel plug 38 located above the second-highest layer are removed, so that the surface of the second-highest layer and the surface of the channel plug 38 can be exposed, and the three-dimensional memory 100 has a flat surface.

In another possible implementation manner, please refer to fig. 31, 32 and 33 together, in which fig. 31 is a schematic diagram of another state of the three-dimensional memory 100 according to the embodiment of the present application, fig. 32 is a schematic diagram of another state of the three-dimensional memory 100 according to the embodiment of the present application, and fig. 33 is a schematic diagram of a structure of the three-dimensional memory 100 according to the embodiment of the present application.

As shown in fig. 31, unlike the foregoing embodiment, after the channel plug 38 connected to the channel layer 35 is formed, the channel plug 38 is subjected to planarization processing with the antireflective layer 41 as a stopper layer.

It is understood that the planarization process may be a Chemical Mechanical Polishing (CMP) process or a recess etching process, and those skilled in the art can select an appropriate method to perform the planarization process according to the actual situation, and the application is not limited thereto. The anti-reflection layer 41 is used as a stop layer to planarize the anti-reflection layer 41 means that the planarization process stops on the upper surface of the anti-reflection layer 41, that is, a portion of the trench plug 38 above the anti-reflection layer 41 is removed, so that the surface of the anti-reflection layer 41 and the surface of the trench plug 38 can be exposed, and the three-dimensional memory 100 has a flat surface.

Next, as shown in fig. 32, after the channel plug 38 is subjected to the planarization process with the anti-reflection layer 41 as a stopper, the anti-reflection layer 41 is removed to expose the sub-top layer. It is to be understood that the sub-top layer refers to the dielectric layer 13 of the layer of the stacked-layer structure 12 that is located below the hard mask layer 15.

An insulating layer is then buffer formed, covering the sub-top layer and the channel structure 37. It is understood that the buffer formation of the insulating layer means that a slight deposition of silicon oxide is performed at the position of the anti-reflection layer 41 removed in the previous step to ensure that the secondary layer can cover away the position of the original anti-reflection layer 41.

Finally, as shown in fig. 33, the insulating layer 16 is subjected to a buffer CMP (buffer CMP) process so that the top surface of the second-highest layer is coplanar with the top surface of the channel plug 38, thereby providing the three-dimensional memory 100 with a flat top surface.

The three-dimensional memory 100 provided by the present application is also provided, and it can be understood that the three-dimensional memory 100 provided by the present application can be prepared by the foregoing preparation method of the three-dimensional memory 100, and the detailed structure and the features thereof have been described in the foregoing, and most of the contents are not repeated.

Referring to fig. 4 and fig. 22 together, fig. 4 is a schematic structural diagram of a semiconductor structure 10 of a three-dimensional memory 100 according to an embodiment of the present disclosure, and fig. 22 is a schematic structural diagram of another three-dimensional memory 100 according to an embodiment of the present disclosure.

The three-dimensional memory 100 provided by the present application includes a semiconductor structure 10, the semiconductor structure 10 including a stacked structure 12 formed on a surface of a substrate 11; a channel hole 20 formed in the stacked structure 12, the channel hole 20 penetrating the stacked structure 12; an epitaxial layer 34 formed at the bottom of the channel hole 20; and a blocking layer 31, a charge trapping layer 32 and a tunneling layer 33 sequentially formed on the sidewall of the channel hole 20, wherein the portions of the tunneling layer 33 at the top and the bottom of the channel hole 20 abut against the blocking layer 31 so that the charge trapping layer 32 is surrounded by the tunneling layer 33 and the blocking layer 31, and the blocking layer 31 and the tunneling layer 33 abut against the epitaxial layer 34.

In one possible embodiment, the three-dimensional memory 100 further includes a channel layer 35 formed on the surface of the tunneling layer 33, and the channel layer 35 abuts against the epitaxial layer 34.

In one possible embodiment, the three-dimensional memory 100 further includes a channel oxide 36 filled in the channel hole 20, and the channel oxide 36 covers the channel layer 35.

In one possible embodiment, the blocking layer 31, the charge trapping layer 32, the tunneling layer 33, the channel layer 35 and the tunnel oxide 36 form a channel structure 37, and the top surface of the channel structure 37 and the sidewall of the channel hole 20 jointly form the wall of the accommodating groove 50 through an etching process

In one possible embodiment, the three-dimensional memory 100 further includes a channel plug 38 formed in the receiving groove 50, and the channel plug 38 is connected to the channel layer 35.

The foregoing is illustrative of the present invention and it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and are intended to be within the scope of the invention.

Claims

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

2. The method of claim 1, wherein sequentially forming a blocking layer, a charge trapping layer, and a tunneling layer on sidewalls of the channel hole comprises:

forming an epitaxial layer at the bottom of the channel hole;

3. The method of claim 2, wherein after the forming a second tunneling layer on the exposed surface of the tunneling layer and the exposed surface of the epitaxial layer such that the second tunneling layer fills the recess and is connected to the first tunneling layer to form a tunneling layer, the method comprises:

4. The method of claim 3, wherein the forming a channel layer overlying the tunneling layer and abutting the epitaxial layer comprises:

forming a first channel layer on the surface of the tunneling layer;

and forming a second channel layer on the exposed surface of the epitaxial layer so that the second channel layer is connected with the first channel layer to form a channel layer which covers the tunneling layer and is abutted to the epitaxial layer.

5. The method of claim 3, wherein a top layer of the stacked structure is a hard mask layer, and after the forming a channel layer overlying the tunneling layer and abutting the epitaxial layer, the method comprises:

6. The method of claim 5, wherein after the filling of a channel oxide within the channel hole and the channel oxide covering the channel layer, the method comprises:

7. The method of claim 6, wherein after the planarizing the blocking layer, the tunneling layer, the channel layer, and the channel oxide with the hard mask layer as a stop layer to form a channel structure within the channel hole, the method comprises:

8. The method of claim 7, wherein after removing the portion of the channel structure located on the hard mask layer and at least the portion located on the second level layer of the stacked structure such that the top surface of the channel structure is lower than the top surface of the second level layer, the method comprises:

9. The method of claim 8, wherein after the forming a channel plug connected to the channel layer, the method comprises:

10. The method of claim 8, wherein after the forming a channel plug connected to the channel layer, the method comprises:

11. The method of claim 10, wherein after the first planarization process for the channel plug with the hard mask layer as a stop layer, the method comprises:

removing the hard mask layer; and the number of the first and second groups,

12. The method of claim 5, wherein after the filling of a channel oxide within the channel hole and the channel oxide covering the channel layer, the method comprises:

13. The method of claim 12, wherein after the planarizing the hardmask layer, the blocking layer, the tunneling layer, the channel layer, and the channel oxide with the second-to-top layer of the stack structure as a stop layer to form a channel structure within the channel hole, the method comprises:

sequentially forming an anti-reflection layer and a positive photoresist layer on the secondary top layer and the top surface of the channel structure; and the number of the first and second groups,

14. The method of claim 13, wherein after the sequentially etching the positive photoresist layer and the anti-reflective layer to expose the channel structure, the method comprises:

15. The method of claim 14, wherein after said removing the positive photoresist layer and the portion of the trench structure located in the anti-reflective layer and at least the portion located in the secondary top layer such that the top surface of the trench structure is lower than the top surface of the secondary top layer, the method comprises:

16. The method of claim 15, wherein after the forming a channel plug connected to the channel layer, the method comprises:

17. The method of claim 16, wherein after the forming a channel plug connected to the channel layer, the method comprises:

18. The method of claim 17, wherein after the planarizing the channel plug with the anti-reflection layer as a stop layer, the method comprises:

removing the anti-reflection layer to expose the secondary top layer;

buffer forming an insulating layer, wherein the insulating layer covers the secondary top layer and the channel structure; and the number of the first and second groups,

and carrying out buffer planarization treatment on the insulating layer.

19. A three-dimensional memory, comprising:

an epitaxial layer formed at the bottom of the channel hole; and the number of the first and second groups,

20. The three-dimensional memory according to claim 19, further comprising:

21. The three-dimensional memory according to claim 20, further comprising:

22. The three-dimensional memory according to claim 21, wherein the blocking layer, the charge trapping layer, the tunneling layer, the channel layer, and the channel oxide form a channel structure, and a top surface of the channel structure and a sidewall of the channel hole jointly form a wall of the receiving recess by an etching process.

23. The three-dimensional memory according to claim 22, further comprising: