CN113178454B - 3D NAND memory and manufacturing method thereof - Google Patents
3D NAND memory and manufacturing method thereof Download PDFInfo
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- CN113178454B CN113178454B CN202110383312.5A CN202110383312A CN113178454B CN 113178454 B CN113178454 B CN 113178454B CN 202110383312 A CN202110383312 A CN 202110383312A CN 113178454 B CN113178454 B CN 113178454B
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides a 3D NAND memory and a manufacturing method thereof, wherein a stacked structure comprising a bottom sacrificial layer and a sacrificial layer and an insulating layer which are alternately stacked and formed above the bottom sacrificial layer is formed on a substrate, the bottom sacrificial layer is replaced by a source electrode layer, the source electrode layer is subjected to oxidation treatment, a first isolation layer is formed on the surface of the source electrode layer, and the function of back selection gate oxide is realized. The method is beneficial to controlling the thickness of the first isolation layer and improving the uniformity of the first isolation layer, thereby being beneficial to the uniform inversion of the source electrode layer and ensuring the channel of electrons in the read-write operation of the memory. The problem of thickness and uniformity of the source electrode layer caused by the problem of thickness of the back selective gate oxide layer is solved, and the continuity of the P-type well and the supply of holes in the erasing process can be realized. The source electrode layer is formed in the channel structure in the stacking direction, so that the contact area of the source electrode layer and the channel layer is increased, and the electric connection between the source electrode layer and the channel layer is enhanced.
Description
The application is a divisional application of patent application number 202010369421.7 of applicant 'Changjiang memory technology Limited liability company' filed on 30 th of application day 2020, 04 month, and the invention name is '3D NAND memory and manufacturing method thereof'.
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a 3D NAND memory and a method of fabricating the same.
Background
With the continued shrinking of feature sizes of devices in integrated circuits, 3D memory technologies that stack multiple planes of memory cells to achieve greater memory capacity and lower cost per bit are becoming increasingly favored. 3D memory is a technology for stacking data units, and stacking of more than 32 layers, even 72 layers, 96 layers, 128 layers or more data units is currently achievable. As the number of stacked layers increases, the extraction of memory structures through the stacked structure presents an increasing challenge.
Conventional methods of achieving channel structure communication with the substrate often suffer from defects in epitaxial structure uniformity and continuity, or from the difficult control of the thickness of the back-side select gate oxide. The problem of increased difficulty in etching the stacked structure is also faced in the multilayer channel hole process.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a 3D NAND memory and a method of manufacturing the same, in which a bottom sacrificial layer in a stacked structure includes a first sacrificial material layer and a second sacrificial material layer, over which sacrificial layers and insulating layers are alternately formed. And replacing the first sacrificial material layer and the second sacrificial material layer with source electrode layers, oxidizing the source electrode layers, and forming a first isolation layer on the surfaces of the source electrode layers. The method can realize the continuity of the P-type trap and the replenishment of holes in the erasing process; the method is beneficial to improving the uniformity of the back selection gate oxide layer, the uniform inversion of the back selection gate and the increase of the electric connection between the source electrode layer and the channel layer.
To achieve the above and other related objects, the present invention provides a 3D NAND memory manufacturing method, comprising the steps of:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a bottom sacrificial layer, and sacrificial layers and insulating layers which are alternately stacked;
forming a channel structure penetrating through the stacked structure;
forming a gate line slit penetrating the stacked structure and exposing the bottom sacrificial layer;
forming a source electrode layer by replacing the bottom sacrificial layer;
forming a first isolation layer on the surface of the source electrode layer;
a gate is formed between the insulating layers of the stacked structure.
Optionally, a substrate is provided, and a stacked structure is formed on the substrate, and the method further includes the following steps:
forming a barrier layer on the substrate;
forming a first sacrificial material layer and a second sacrificial material layer over the barrier layer;
the sacrificial layers and insulating layers are alternately formed over the second sacrificial material layer.
Optionally, before forming the source layer in place of the bottom sacrificial layer, the method further includes the steps of:
forming a grid line interlayer on the side wall and the bottom of the grid line gap;
and removing the interlayer between the grid lines at the bottoms of the grid line gaps until the bottom sacrificial layer is exposed.
Optionally, forming a source layer in place of the bottom sacrificial layer, further includes the steps of:
removing the first sacrificial material layer to expose the blocking layer, the second sacrificial material layer and the charge blocking layer of the channel structure;
removing the blocking layer and the exposed charge blocking layer on the substrate to expose the charge trapping layer of the channel structure;
removing the second sacrificial material layer, and exposing the charge trapping layer and the tunneling layer covered by the charge trapping layer to expose the channel layer of the channel structure to form a trench;
and filling conductive materials in the grooves to form source electrode layers.
Optionally, filling the trench with a conductive material to form a source layer includes: and filling P-type polycrystalline silicon in the groove.
Optionally, removing the second sacrificial material layer, and exposing the charge-trapping layer and the tunneling layer covered by the charge-trapping layer, to expose the channel layer of the channel structure, to form a trench, further comprising the steps of:
removing the second sacrificial material layer to form a first part of the groove;
the charge trapping layer and the tunneling layer covered by the charge trapping layer are removed, a second portion of the trench is formed, and a width of the second portion is greater than a width of the first portion in a stacking direction of the stacked structure.
Optionally, forming a first isolation layer on the surface of the source electrode layer, and further comprising the following steps:
forming an opening in the source layer through the gate line slit, the opening exposing the substrate;
removing the sacrificial layer of the stacked structure through the gate line gap to form a gate groove;
and oxidizing the source electrode layer, and forming a first isolation layer on the surface of the source electrode layer and the side wall and the bottom of the opening.
Optionally, forming a first isolation layer on the surface of the source electrode layer, and further comprising the following steps:
forming an opening in the source layer through the gate line slit, the opening exposing the substrate;
removing the sacrificial layer of the stacked structure through the gate line gap to form a gate groove;
and depositing an oxide layer on the surface of the source electrode layer exposed by the gate trench to form the first isolation layer.
Optionally, forming a gate between the insulating layers of the stacked structure further includes the steps of:
forming a dielectric layer on the side wall of the gate trench;
and filling a gate conductive material in the gate trench.
Optionally the 3D NAND memory manufacturing method further comprises the steps of:
forming a second isolation layer on the side wall of the grid line gap;
and forming a common source electrode communicated with the substrate in the gate line gap.
Optionally, the 3D NAND memory manufacturing method further includes:
etching back the grid conductive material;
etching the dielectric layer at the bottom of the opening and the first isolation layer to expose the substrate.
Optionally, forming a channel structure penetrating the stacked structure further includes the steps of:
forming a channel hole penetrating through the stacked structure;
sequentially forming a charge blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole;
forming a channel layer in the channel hole;
and forming a dielectric layer in the middle of the channel hole.
The present invention also provides a 3D NAND memory, the 3D NAND memory comprising:
a substrate;
a stacked structure formed over the substrate, the stacked structure including a source layer formed over the substrate, a first isolation layer formed over the source layer, and alternately stacked gate layers and insulating layers formed over the first isolation layer;
a channel structure extending through the stacked structure;
a common source extending through the stacked structure and in communication with the substrate;
wherein the source layer includes a first portion located under the stack structure and a second portion formed in the channel structure to communicate with the channel structure, and a width of the second portion is larger than a width of the first portion in a stacking direction of the stack structure.
Optionally, the channel structure includes:
channel holes arranged through the array of the stacked structure;
a charge blocking layer, a charge trapping layer and a tunneling layer sequentially formed on the sidewall of the channel hole;
a channel layer formed within the channel hole; and
and a dielectric layer formed in the middle of the channel hole.
Optionally, the common source includes:
a gate line slit penetrating the stacked structure;
a second isolation layer formed on the sidewall of the gate line slit;
the common source electrode material layer is formed on the surface of the second isolation layer and at the bottom of the grid line gap and communicated with the substrate; and
and a common source contact material layer formed in the gate line slit.
Optionally, the first isolation layer, the dielectric layer and the second isolation layer are further formed between the common source and the source layer.
Optionally, a dielectric layer is further included between the gate layer and the insulating layer and the second isolation layer.
Optionally, the source electrode layer is a P-type polysilicon layer.
As described above, the 3D NAND memory and the method for manufacturing the same provided by the invention have at least the following beneficial technical effects:
the 3D NAND memory manufacturing method forms a stacked structure on a substrate, wherein a bottom sacrificial layer in the stacked structure comprises a first sacrificial material layer and a second sacrificial material layer, the bottom sacrificial layer is replaced by a source electrode layer, a first isolation layer is formed on the surface of the source electrode layer, for example, the source electrode layer is subjected to oxidation treatment to form an oxide layer on the surface of the source electrode layer, or an oxide layer is deposited on the surface of the source electrode layer, and the oxide layer forms the first isolation layer to realize the function of back selection gate oxide. In addition, the method is beneficial to improving the uniformity of the first isolation layer, so that the uniform inversion of the source electrode layer is facilitated, and the channel of electrons is ensured in the read-write operation of the memory. According to the method, the first isolation layer is formed on the surface by processing the source electrode layer, so that the problems of thickness and uniformity of the source electrode layer caused by the thickness problem of the back selection gate oxide layer are solved, the continuity of the P-type well and the supply of holes in the erasing process can be realized, and the service life of the device is prolonged.
In the method of the invention, when the second sacrificial material layer and the blocking layer between the bottom sacrificial layer and the substrate are removed, the charge blocking layer, the charge capturing layer and the tunneling layer of the channel structure are removed at the same time, and the charge capturing layer and the tunneling layer are further removed in the stacking direction, so that the contact area between the subsequently formed source electrode layer and the channel structure is increased, and the electrical connection between the source electrode layer and the channel layer is enhanced.
The 3D NAND memory of the present invention is prepared by the above method, and thus also has the above advantageous effects.
Drawings
Fig. 1a and 1b are schematic views of a prior art structure for forming a channel structure and a source layer.
Fig. 2 shows a flow chart of a method for manufacturing a 3D NAND memory according to the present invention.
Fig. 3 is a schematic structural view of a substrate and a stacked structure formed on the substrate according to the present embodiment.
Fig. 4 is a schematic view showing a structure of forming a channel structure in the stacked structure shown in fig. 3.
Fig. 5 is a schematic view showing a structure of forming a gate line slit in the structure shown in fig. 4.
Fig. 6 is a schematic view showing formation of a gate line spacer on sidewalls of the gate line slit shown in fig. 5.
Fig. 7 is a schematic view showing a structure of removing the interlayer between the gate lines at the bottom of the gate line slit shown in fig. 6.
Fig. 8 is a schematic diagram showing a structure of removing the first sacrificial material layer in the bottom sacrificial layer through the gate line slit shown in fig. 7.
Fig. 9 is a schematic view showing a structure of removing a barrier layer on a substrate through a gate line slit shown in fig. 8.
Fig. 10 is a schematic diagram showing a structure of removing the second sacrificial material layer in the bottom sacrificial layer through the gate line slit shown in fig. 9 to form a trench.
Fig. 11 is a schematic view showing a structure of filling a conductive material in the trench shown in fig. 10 to form a source layer.
Fig. 12 is a schematic view showing a structure of forming an opening in a source layer through a gate line slit shown in fig. 11.
Fig. 13 is a schematic diagram of a structure for forming a gate trench by removing the remaining sacrificial layer in the stacked structure.
Fig. 14 is a schematic view showing a structure in which an oxide layer is formed on the surface of a source layer.
Fig. 15 is a schematic diagram showing a structure of forming a dielectric layer on a sidewall of a gate trench.
Fig. 16 is a schematic view showing a structure of forming a word line layer in the gate trench shown in fig. 15.
Fig. 17 is a schematic view showing a structure of forming a common source in the gate line slit shown in fig. 16.
Description of element reference numerals
010. Substrate 1031 charge blocking layer
011. Source layer 1032 charge trapping layer
012. Back select gate oxide 1033 tunneling layer
013. Selective epitaxial structure 1034 channel layer
014. Channel layer 1035 dielectric layer
020. Substrate 104 gate line slit
021. Source layer 1041 gate line spacer
022. Back select gate oxide 105 trench
023. First portion of channel layer 1051 trench
100. Second portion of substrate 1052 trench
101. Bottom sacrificial layer 106 source layer
1011. Barrier layer 107 opening
1012. First sacrificial material layer 108 gate trench
1013. Second sacrificial material layer 109 oxide layer
102. Stacked structure 110 dielectric layer
1021. Sacrificial layer 111 grid electrode
1022. Insulating layer 112 second isolation layer
103. Channel structure 113 source material layer
114. Source electrode contact layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment only illustrate the basic concept of the present invention by way of illustration, but only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number, positional relationship and proportion of each component in actual implementation may be changed at will on the premise of implementing the present technical solution, and the layout of the components may be more complex.
As the number of 3D NAND memory layers increases, the extraction process challenges for channel structures become greater. In the prior art, the channel structure is typically formed by two methods as shown in fig. 1a and 1 b.
As shown in fig. 1a, a selective epitaxial structure 013 is typically formed at the bottom of the channel hole after the channel hole is formed, then a memory layer and a channel layer are formed in the channel hole, the channel layer 014 being in communication with the selective epitaxial structure 013; and forming a grid electrode layer to realize the communication between the source electrode layer and the selective epitaxial structure. Such an approach is detrimental to the uniformity of the selective epitaxial structure against an increase in the number of layers, and typically suffers from poor contact between the selective epitaxial structure and the substrate and source layers. With the increase of the layer number, the difficulty of etching the stacked structure is also generally faced, and particularly for the case of a multi-layer channel hole, the difficulty of etching is particularly remarkable.
As shown in fig. 1b, in another method, a memory layer and a channel layer 023 are first sequentially formed in a channel hole, and then the memory layer is removed through a gate line slit and a source layer 021 is formed by filling, for example, polysilicon or epitaxial silicon, and the channel layer 023 is communicated with a substrate 020. This approach also suffers from polysilicon or epitaxial silicon uniformity issues; in addition, if the source electrode layer 021 is made of P-type polysilicon, the combination with the substrate is poor, and the P-type polysilicon generally has thickness and uniformity problems due to the existence of the original back selection gate oxide layer 022 and the thickness thereof; if the source electrode layer 021 adopts N-type polysilicon, it is necessary to erase data by using a GIDL (Gate-Induced Drain Leakage, gate induced drain leakage current) data erase mode, and the GIDL data erase mode requires a higher voltage to be applied to the drain electrode layer, so that the device is easily damaged, thereby reducing the service life of the memory.
In view of the above-mentioned drawbacks of the prior art, the present invention provides a 3D NAND memory and a method for manufacturing the same, which solve the above-mentioned drawbacks. The invention will now be described in detail by the following specific examples in connection with the accompanying drawings.
Example 1
The present embodiment provides a method for manufacturing a 3D NAND memory, as shown in fig. 2, including the steps of:
step S101: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises sacrificial layers and insulating layers which are alternately stacked;
referring to fig. 3, a substrate 100 is first provided, and a stacked structure 102 is formed on the substrate 100. The substrate 100 in this embodiment may be a substrate of silicon, single crystal silicon on insulator, or other suitable material. And a P-type well on top of the substrate 100 and an N-type well (not shown in detail herein) under the P-type well may also be formed in the substrate 100. The stack 102 may be 64 layers, 96 layers, 128 layers, or even more.
Still referring to fig. 3, in forming the above-described stacked structure 102, first, a bottom sacrificial layer 101 is formed over a substrate 100, and then sacrificial layers 1021 and insulating layers 1022 are alternately formed over the bottom sacrificial layer. The sacrificial layer 1021 may be silicon oxide and the insulating layer 1022 may be silicon nitride, i.e., a stacked structure forms an ONO stacked structure in which silicon oxide and silicon nitride are alternately arranged. Forming the bottom sacrificial layer 101 specifically includes: a barrier layer 1011 is first formed on the surface of the substrate 100, a first sacrificial material layer 1012 is formed over the barrier layer, and then a second sacrificial material layer 1013 is formed over the first sacrificial material layer 1012. Preferably, the first sacrificial material layer 1012 and the second sacrificial material layer 1013 are different material layers. For example, the first sacrificial material layer is a polysilicon layer, and the second sacrificial material layer 1013 is a silicon nitride layer. The silicon nitride layer of the second sacrificial material layer 1013 may be the same as or a different silicon nitride layer than the silicon nitride layer of the sacrificial layer 1021. For example, in the present embodiment, the second sacrificial material layer 1013 is a doped silicon nitride layer having a higher etching selectivity than that of the silicon nitride layer of the sacrificial layer 1021.
Step S102: forming a channel structure penetrating through the stacked structure;
referring to fig. 4, after the stack structure 102 is formed, a channel structure 103 penetrating the stack structure 102 is formed. The channel structure may be formed using techniques commonly used in the art. For example, the stack 102 on the substrate 100 is first etched to form a channel hole through the stack 102, and in a preferred embodiment, portions of the substrate 100 are etched at the same time so that the channel hole extends into the substrate. Then, a charge blocking layer 1031, a charge trapping layer 1032, and a tunneling layer 1033 are sequentially formed on the sidewalls of the channel hole, and then a channel layer 1034 is formed in the channel hole, and a dielectric layer 1035 may be filled in the center of the channel hole.
In a preferred embodiment, the material of the charge blocking layer may be a high-k dielectric. The high-k dielectric material has a thinner equivalent oxide thickness (EOT, equivalence Oxide Thickness) which effectively reduces gate leakage while maintaining transistor performance. The high-k dielectric may be, for example, aluminum oxide, hafnium oxide, zirconium oxide, or the like. The charge blocking layer may be a single layer of dielectric oxide or a multi-layer model such as high-k oxide and silicon oxide. The charge trapping layer 1032 may be made of SiN. In another embodiment, the charge trapping layer 1032 may be a multi-layer structure, such as a SiN/SiON/SiN multi-layer structure. In some embodiments, tunneling layer 1033 may likewise be a multi-layer structure, such as a SiO/SiON/SiO multi-layer structure. The channel layer 1034 may be made of polysilicon via a furnace low pressure Chemical Vapor Deposition (CVD) process.
Step S203: forming a gate line slit penetrating the stacked structure and exposing the bottom sacrificial layer;
as shown in fig. 5, a gate line slit 104 is formed in the stacked structure 102. As shown in fig. 5, the stacked structure 102 is etched until the bottom sacrificial layer 101 is exposed, forming a gate line slit 104. In a preferred embodiment, the stack 102 is etched to a portion of the first sacrificial material layer 1012 of the bottom sacrificial layer 101, exposing the first sacrificial material layer 1012.
Step S204: forming a source electrode layer by replacing the bottom sacrificial layer;
as shown in fig. 11, after the gate line slit 104 is formed, the bottom sacrificial layer 101 is removed through the gate line slit 104 and replaced with the source layer 106. In a preferred embodiment, the source layer 106 is a polysilicon layer. The source layer is formed over the substrate in communication with the substrate and the channel layer 1034 of the channel structure.
As shown in fig. 6, in a preferred embodiment, before removing the bottom sacrificial layer 101, a gate line spacer 1041 is further formed on the sidewall and bottom of the gate line slit 104 to protect the sacrificial layer and the insulating layer in the stacked structure from damage when the bottom sacrificial layer is replaced later. The gate line spacer 1041 may be a multilayer structure, for example, a multilayer structure formed of SiO/SiON/SiO. After the formation of the above-mentioned inter-gate spacer 1041, as shown in fig. 7, the inter-gate spacer 1041 at the bottom of the gate line slit (i.e., formed on the first sacrificial material layer of the bottom sacrificial layer) is removed, and the gate line slit is opened again, exposing the first sacrificial material layer 1012 of the bottom sacrificial layer 101.
As shown in fig. 8 to 10, in another preferred embodiment, the bottom sacrificial layer 101 is removed specifically by:
as shown in fig. 8, first, the first sacrificial material layer 1012 in the bottom sacrificial layer 101 is removed through the gate line slit 104, and after the first sacrificial material layer 1012 is removed, the charge blocking layer 1031 of the channel structure is exposed. Then, as shown in fig. 9, the blocking layer 1011 is removed above the substrate, and in a preferred embodiment, the blocking layer 1011 and the charge blocking layer 1031 are both oxide layers, for example, silicon oxide layers, so that the exposed charge blocking layer 1031 is removed simultaneously with the removal of the blocking layer 1011, and at this time, the charge trapping layer 1032 of the channel structure 103 is exposed. Then, as shown in fig. 10, the second sacrificial material layer 1013 in the bottom sacrificial layer 101 is removed, at this time, the first portion 1051 of the trench 105 is formed, and since the second sacrificial material layer is a SiN layer, which is the same or similar to the charge trapping layer and the tunneling layer, the exposed charge trapping layer 1032 and the tunneling layer covered by the portion of the charge trapping layer are removed simultaneously with the removal of the second sacrificial material layer 1013, and in a preferred embodiment, the charge trapping layer and the tunneling layer are continuously etched in the stacking direction, exposing the channel layer 1034 of the channel structure, thereby forming a second portion 1052 of the trench 105, and the first portion 1051 and the second portion 1052 form the through trench 105. As can be seen from fig. 10, the width of the above-mentioned second portion 1052 of the trench 105 is larger than the width of the first portion 1051 in the stacking direction of the stacked structure.
After forming the trench 105, polysilicon, which in a more preferred embodiment is P-doped polysilicon, is deposited in the trench 105 to form the source layer 106. Because the sacrificial layer in the stacked structure is formed above the bottom sacrificial layer 101, there is no back select gate oxide layer, and there is no influence on the deposited polysilicon due to the thickness of the back select gate protection layer, so the method of this embodiment can ensure uniformity of the deposited source layer. Meanwhile, the continuity of the P-type well and the replenishment of holes in the erasing process are realized. In addition, since the width of the second portion 1052 of the trench is larger than the width of the first portion 1051, the width of the second portion 1062 of the source layer 106 formed in the second portion 1052 and the first portion 1051 of the trench is larger than the width of the first portion 1061, whereby the contact area of the source layer and the channel layer can be increased, and the electrical connectivity of the two can be enhanced.
Step S205: forming a first isolation layer on the surface of the source electrode layer;
as shown in fig. 14, the source layer 106 is subjected to an oxidation treatment, and a first isolation layer 109 is formed on the source layer surface. After depositing the source layer 106 as shown in fig. 11, the source layer 106 is etched back through the gate line slit 104, and an opening 107 is formed in the source layer 106, which exposes the substrate 100 as shown in fig. 12. At the same time, polysilicon deposited on the sidewalls of the gate line slits is removed.
Then, as shown in fig. 13, the sacrificial layer 1021 in the stacked structure is removed to form a gate trench 108, and the gate trench 108 over the source layer 106 exposes the surface of the source layer 106. For example, an acid etching method commonly used in the art may be adopted, the acid enters the stacked structure through the gate line slit 104, etches the sacrificial layer and finally removes the sacrificial layer, a gate trench 108 is formed at a position of the sacrificial layer, and after the gate trench is formed, the surface of the source layer is exposed by the lowermost gate trench. It can be appreciated that before removing the sacrificial layer 1021, the inter-gate spacer 1041 remaining on the sidewalls of the gate line slit 104 is removed first, exposing the sacrificial layer and the insulating layer of the stacked structure.
In an alternative embodiment, the source layer 106 is subjected to an oxidation treatment, and a silicon oxide layer, i.e., a first isolation layer, is formed on the surface of the source layer. For example, the polysilicon source layer 106 may be oxidized using a high temperature furnace oxidation process (high temperature oxidation). The reaction time is controlled to be between 30 seconds and 60 minutes at the reaction temperature of 650-1100 ℃, and the reaction gas can be oxygen (O) 2 ) Or other oxidizing gases, e.g. ozone (O) 3 ) And the like, and the flow rate of the reaction gas is controlled to be 50 sccm-10 s1m, and the reaction pressure is controlled to be 50mtorr-1000torr. The above parameters are selected and controlled, and the upper surface of the source layer 106 is oxidized to form the first isolation layer 109 having excellent thickness uniformity, i.e., the upper surface of the polysilicon layer is oxidized to form the polysilicon oxide layer having excellent thickness uniformity. In a preferred embodiment of the present invention, taking a source layer formed of P-type doped polysilicon as an example, the reaction temperature is controlled to be 900 ℃ and the reaction time is controlled to be 60 seconds, the flow rate of the oxygen gas of the reaction gas is selected to be 10s1m, and the reaction is reversedThe pressure should be selected to be 1000torr. The structure shown in fig. 13 is placed in a furnace tube, the temperature of the furnace tube is first raised to a set temperature of 900 ℃, then, the reaction gas oxygen is introduced into the furnace tube, the reaction time is kept for 60 seconds at the reaction temperature, and a silicon oxide layer with the thickness of about 10nm to 50nm is formed on the surface of the polysilicon, and the silicon oxide layer is used as the first isolation layer 109. By controlling the amount of the oxidizing gas introduced, the oxidation temperature, the oxidation time and other parameters, the thickness and uniformity of the formed first isolation layer can be precisely controlled. Thereby forming a first isolation layer of desired thickness and uniformity.
In another alternative embodiment, after forming the gate trench 108 and exposing the surface of the source layer 106, a first isolation layer 109 is formed on the surface of the source layer 106 by a deposition process. A silicon oxide layer having a degree of deposition of about 10nm to 50nm is deposited on the surface of the source layer 106, for example, by a plasma chemical vapor deposition process or an atomic layer deposition process. In the deposition process, the thickness and uniformity of the formed first isolation layer can be precisely controlled by controlling parameters such as deposition temperature, deposition time and the like. Thereby forming a first isolation layer of desired thickness and uniformity.
Step S206: forming a gate electrode between the insulating layers of the stacked structure;
after the gate trench 108 is formed, as shown in fig. 16, the trench 108 is filled with a conductive material, for example, a metal material, to form a gate 111. In a preferred embodiment, as shown in fig. 15, a dielectric layer 110 is first formed on the sidewalls of the gate trench, i.e., a dielectric layer 110 surrounding the insulating layer forming the gate trench 108 is formed on the surface of the insulating layer. The dielectric layer is preferably a high-k dielectric layer such as alumina, zirconia, or the like. Further reducing gate leakage while maintaining good device performance.
In a preferred embodiment of the present embodiment, the 3D NAND memory manufacturing method further includes a step of forming a common source. As shown in fig. 17, after forming the gate 111, the gate 111 is etched back through the gate line slit, and the dielectric layer 110 and the first isolation layer 109 at the bottom of the opening 107 are etched at the same time until the substrate 110 is exposed, or a portion of the substrate 100 is etched to expose the substrate 100. A second isolation layer 112 is then formed on the sidewalls of the gate line slit, the second isolation layer 112 being simultaneously formed in the cavity formed by etching back the gate 111 to enhance isolation from the gate 111. The second isolation layer may also be a layer of high-k dielectric material. A common source material layer 113 is then filled in the gate line slits, the common source material layer being in communication with the substrate 100. The common source material layer may also be a polysilicon layer, for example. A common source contact material layer 114, which may be a metal material such as tungsten or the like, is then filled in the gate line slits.
Example two
The present embodiment provides a 3D NAND memory, referring also to fig. 3 to 17, including:
a substrate; a stacked structure formed over the substrate, the stacked structure including a source layer formed over the substrate, a first isolation layer formed over the source layer, and alternately stacked gate layers and insulating layers formed over the first isolation layer;
a channel structure extending through the stacked structure;
a common source extending through the stacked structure and in communication with the substrate;
wherein the source layer includes a first portion located under the stack structure and a second portion formed in the channel structure to communicate with the channel structure, and a width of the second portion is larger than a width of the first portion in a stacking direction of the stack structure.
Referring to fig. 3-17, the substrate 100 in this embodiment may be a substrate of silicon, single crystal silicon on insulator, or other suitable material. And a P-type well on top of the substrate 100 and an N-type well (not shown in detail herein) under the P-type well may also be formed in the substrate 100. The stack 102 may be 64 layers, 96 layers, 128 layers, or even more. A stacked structure 102 is formed over the substrate 100. The stacked structure 102 includes a source layer 106 formed on the substrate 100, a first isolation layer 109 formed over the source layer 106, and alternately stacked gate layers 111 and insulating layers 1022 formed over the first isolation layer 109. In a preferred embodiment, the source layer 106 is a polysilicon layer, and an oxide layer, i.e., the first isolation layer 109, is formed on the surface of the source layer 106 by oxidizing the polysilicon layer. After the grid electrode is formed subsequently, the first isolation layer plays a role of a back selection grid oxide layer, and the first isolation layer has good uniformity, so that the uniform inversion of the back selection grid is facilitated, and an electron channel is ensured during read-write operation.
As described in the first embodiment above, the polysilicon source layer 106 is oxidized using a high temperature furnace oxidation process (high temperature oxidation). Specifically, a high temperature furnace tube oxidation method is adopted and oxygen (O) is introduced 2 ) Or other oxidizing gases, e.g. ozone (O) 3 ) To oxidize the upper surface of the source layer 106 and form a silicon oxide layer, i.e., the first isolation layer 109, having a thickness of about 10nm to 50 nm. By controlling the amount of the oxidizing gas introduced, the oxidation temperature, the oxidation time and other parameters, the thickness and uniformity of the formed first isolation layer can be precisely controlled. Thereby forming a first isolation layer of desired thickness and uniformity.
The first isolation layer 109 may also be formed on the surface of the source layer 106 by the deposition process described in the above embodiments. A silicon oxide layer having a degree of deposition of about 10nm to 50nm is deposited on the surface of the source layer 106, for example, by a plasma chemical vapor deposition process or an atomic layer deposition process. In the deposition process, the thickness and uniformity of the formed first isolation layer can be precisely controlled by controlling parameters such as deposition temperature, deposition time and the like. Thereby forming a first isolation layer of desired thickness and uniformity.
In addition, as shown in fig. 17, the width of the second portion 1062 of the source layer 106 is greater than the width of the first portion 1061, thereby increasing the contact area with the channel layer 1034 and enhancing the electrical connectivity of the two.
Referring also to fig. 4, the channel structure 103 of the memory includes channel holes arranged through the array of the stacked structure, a charge blocking layer 1031, a charge trapping layer 1032, and a tunneling layer 1033 sequentially formed on sidewalls of the channel holes; a channel layer 1034 formed within the channel hole; and a dielectric layer 1035 formed in the middle of the channel hole. In a preferred embodiment, the material of the charge blocking layer may be a high-k dielectric. The high-k dielectric material has a thinner equivalent oxide thickness (EOT, equivalence Oxide Thickness) which effectively reduces gate leakage while maintaining transistor performance. The high-k dielectric may be, for example, alumina, zirconia, or the like. The charge blocking layer may be a single layer of dielectric oxide or a multi-layer model such as high-k oxide and silicon oxide. The charge trapping layer 1032 may be made of SiN. In another embodiment, the charge trapping layer 1032 may be a multi-layer structure, such as a SiN/SiON/SiN multi-layer structure. In some embodiments, tunneling layer 1033 may likewise be a multi-layer structure, such as a SiO/SiON/SiO multi-layer structure. The channel layer 1034 may be made of polysilicon via a furnace low pressure Chemical Vapor Deposition (CVD) process.
Referring to fig. 16 and 17, the common source includes: a gate line slit 104 penetrating the stacked structure; a second isolation layer 112 formed on sidewalls of the gate line slits; a common source material layer 113 formed on the surface of the second isolation layer and at the bottom of the gate line gap and communicated with the substrate; and a common source contact material layer 114 formed in the gate line slit. Referring also to fig. 17, the first isolation layer 109, the dielectric layer 110, and the second isolation layer 112 are further formed between the common source material layer 113 and the source layer 106. As also shown in fig. 17, a dielectric layer 110 is further included between the gate layer 111 and the insulating layer 1022 and the second isolation layer 112.
The source electrode layer of the 3D NAND memory has good uniformity, and can realize the continuity of a P-type well and the replenishment of holes in the erasing process. An oxide layer, i.e., a first isolation layer 109, is formed on the surface of the source layer 106 by oxidizing the polysilicon layer. After the grid electrode is formed subsequently, the first isolation layer plays a role of a back selection grid oxide layer, and the first isolation layer has good uniformity, so that the uniform inversion of the back selection grid is facilitated, and an electron channel is ensured during read-write operation.
As described above, the 3D NAND memory and the method for manufacturing the same provided by the present invention have at least the following beneficial technical effects:
the 3D NAND memory manufacturing method forms a stacked structure on a substrate, wherein a bottom sacrificial layer in the stacked structure comprises a first sacrificial material layer and a second sacrificial material layer, the bottom sacrificial layer is replaced by a source electrode layer, the source electrode layer is processed, for example, oxidation treatment is carried out, a first isolation layer is formed on the surface of the source electrode layer, and the function of back selection gate oxide is achieved. In addition, the method is beneficial to improving the uniformity of the first isolation layer, so that the uniform inversion of the source electrode layer is facilitated, and the channel of electrons is ensured in the read-write operation of the memory. According to the method, the first isolation layer is formed on the surface by processing the source electrode layer, so that the problems of thickness and uniformity of the source electrode layer caused by the thickness problem of the back selection gate oxide layer are solved, the continuity of the P-type well and the supply of holes in the erasing process can be realized, and the service life of the device is prolonged.
In the method of the invention, when the second sacrificial material layer and the blocking layer between the bottom sacrificial layer and the substrate are removed, the charge blocking layer, the charge capturing layer and the tunneling layer of the channel structure are removed at the same time, and the charge capturing layer and the tunneling layer are further removed in the stacking direction, so that the contact area between the subsequently formed source electrode layer and the channel structure is increased, and the electrical connection between the source electrode layer and the channel layer is enhanced.
The 3D NAND memory of the present invention is prepared by the above method, and thus also has the above advantageous effects.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (18)
1. A method of manufacturing a 3D NAND memory, comprising the steps of:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a bottom sacrificial layer, and sacrificial layers and insulating layers which are alternately stacked;
forming a channel structure penetrating through the stacked structure;
forming a gate line slit penetrating the stacked structure and exposing the bottom sacrificial layer;
forming a source electrode layer by replacing the bottom sacrificial layer;
forming an opening in the source layer through the gate line slit, the opening exposing the substrate;
removing the sacrificial layer of the stacked structure through the gate line gap to form a gate trench, wherein the gate trench of the lowest layer exposes the surface of the source electrode layer;
forming a first isolation layer on the surface of the source electrode layer;
etching back the first isolation layer at the bottom of the gate line gap to expose the substrate;
forming a second isolation layer on the side wall of the grid line gap;
forming a common source electrode material layer communicated with the substrate on the surface of the second isolation layer and at the bottom of the gate line gap; and
and forming a common source contact material layer in the gate line gap.
2. The 3D NAND memory manufacturing method of claim 1 further comprising the steps of:
oxidizing the source electrode layer, and forming a first isolation layer on the surface of the source electrode layer and the side wall and the bottom of the opening;
a gate is formed in the gate trench.
3. The 3D NAND memory manufacturing method of claim 1 further comprising the steps of:
depositing an oxide layer on the surface of the source electrode layer exposed by the gate trench to form a first isolation layer;
a gate is formed in the gate trench.
4. The method of manufacturing a 3D NAND memory of claim 1 wherein providing a substrate, forming a stacked structure on the substrate, further comprises the steps of:
forming a barrier layer on the substrate;
forming a first sacrificial material layer and a second sacrificial material layer over the barrier layer;
the sacrificial layers and insulating layers are alternately formed over the second sacrificial material layer.
5. The 3D NAND memory manufacturing method of claim 1 further comprising the steps of, prior to forming a source layer in place of the bottom sacrificial layer:
forming a grid line interlayer on the side wall and the bottom of the grid line gap;
and removing the interlayer between the grid lines at the bottoms of the grid line gaps until the bottom sacrificial layer is exposed.
6. The method of manufacturing a 3D NAND memory of claim 4 wherein forming a source layer in place of the bottom sacrificial layer further comprises the steps of:
removing the first sacrificial material layer to expose the blocking layer, the second sacrificial material layer and the charge blocking layer of the channel structure;
removing the blocking layer and the exposed charge blocking layer on the substrate to expose the charge trapping layer of the channel structure;
removing the second sacrificial material layer, and exposing the charge trapping layer and the tunneling layer covered by the charge trapping layer to expose the channel layer of the channel structure to form a trench;
and filling conductive materials in the grooves to form source electrode layers.
7. The method of manufacturing a 3D NAND memory of claim 6 wherein filling conductive material in the trench to form a source layer comprises: and filling P-type polycrystalline silicon in the groove.
8. The method of manufacturing a 3D NAND memory of claim 6 wherein removing the second sacrificial material layer and exposing the charge-trapping layer and the tunneling layer covered by the charge-trapping layer exposes the channel layer of the channel structure to form a trench, further comprising the steps of:
removing the second sacrificial material layer to form a first part of the groove;
the charge trapping layer and the tunneling layer covered by the charge trapping layer are removed, a second portion of the trench is formed, and a width of the second portion is greater than a width of the first portion in a stacking direction of the stacked structure.
9. The 3D NAND memory manufacturing method of claim 2 or 3 wherein forming a gate in the gate trench further comprises the steps of:
forming a dielectric layer on the side wall of the gate trench;
and filling a gate conductive material in the gate trench.
10. The 3D NAND memory manufacturing method of claim 9 further comprising:
etching back the grid conductive material;
etching the dielectric layer at the bottom of the opening and the first isolation layer to expose the substrate.
11. The 3D NAND memory manufacturing method of claim 1 wherein forming a channel structure through the stacked structure further comprises the steps of:
forming a channel hole penetrating through the stacked structure;
sequentially forming a charge blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole;
forming a channel layer in the channel hole;
and forming a dielectric layer in the middle of the channel hole.
12. A 3D NAND memory, comprising:
a substrate;
a stacked structure formed over the substrate, the stacked structure including a source layer formed over the substrate, a first isolation layer formed over the source layer, and alternately stacked gate layers and insulating layers formed over the first isolation layer;
a channel structure extending through the stacked structure;
a gate line slit penetrating the stacked structure;
a second isolation layer formed on the sidewall of the gate line slit;
the common source electrode material layer is formed on the surface of the second isolation layer and at the bottom of the gate line gap and communicated with the substrate, and a first isolation layer and a dielectric layer are formed between the common source electrode material layer and the source electrode layer; and
and a common source contact material layer formed in the gate line slit.
13. The 3D NAND memory of claim 12 wherein the channel structure comprises:
channel holes arranged through the array of the stacked structure;
a charge blocking layer, a charge trapping layer and a tunneling layer sequentially formed on the sidewall of the channel hole;
a channel layer formed within the channel hole; and
and a dielectric layer formed in the middle of the channel hole.
14. The 3D NAND memory of claim 12 further comprising a dielectric layer between the gate layer and the insulating layer and the second isolation layer.
15. The 3D NAND memory of claim 12 wherein the source layer comprises a first portion located under the stacked structure and a second portion formed in the channel structure in communication with the channel structure, and wherein a width of the second portion is greater than a width of the first portion in a stacking direction of the stacked structure.
16. The 3D NAND memory of claim 12 wherein the source layer is a P-type polysilicon layer.
17. The 3D NAND memory of claim 12 wherein the common source material layer is a polysilicon layer and the common source contact material layer is a metal material layer.
18. The 3D NAND memory of claim 17 wherein the common source contact material layer is a metal tungsten layer.
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