CN113013172B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN113013172B CN113013172B CN202110243935.2A CN202110243935A CN113013172B CN 113013172 B CN113013172 B CN 113013172B CN 202110243935 A CN202110243935 A CN 202110243935A CN 113013172 B CN113013172 B CN 113013172B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention relates to a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises the following steps: forming a first stacked structure on a substrate, the first stacked structure including a plurality of gate sacrificial layers and insulating layers alternately stacked in a direction perpendicular to the substrate; forming an isolation layer on the first stacked structure; forming a first channel hole through the isolation layer and the first stacked structure; and forming an epitaxial layer at the bottom of the first channel hole through selective epitaxial growth, wherein the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is greater than the selective epitaxial growth selection ratio of the substrate relative to the outermost layer of the first laminated structure deviating from the substrate, so that in the epitaxial growth process, the formation of epitaxial aggregation blocks on the laminated structure can be reduced, and the yield and the reliability of the three-dimensional memory are further improved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of memories, in particular to a three-dimensional memory and a manufacturing method thereof.
[ background of the invention ]
As technology evolves, the semiconductor industry is continually looking for new ways of production so that each memory die in a memory device has a greater number of memory cells. Among them, the 3D NAND (three-dimensional NAND) memory has become a leading-edge three-dimensional memory technology with great development potential due to its advantages of high storage density and low cost.
The existing 3D NAND memory comprises a substrate, a laminated structure arranged on the substrate, a channel hole penetrating through the laminated structure from top to bottom to the substrate, and an epitaxial layer arranged at the bottom of the channel hole. However, in the manufacturing process of the 3D NAND memory, when the epitaxial layer is formed at the bottom of the channel hole by selective epitaxial growth, the selective epitaxial growth is not sufficient, so that aggregation nucleation is likely to occur on the stacked structure during the epitaxial growth process to form an epitaxial aggregation block, and the epitaxial aggregation block is likely to block the channel hole, which is not beneficial to improving the yield and reliability of the 3D NAND memory.
[ summary of the invention ]
The invention aims to provide a three-dimensional memory and a manufacturing method thereof, which are used for reducing the formation of epitaxial aggregation blocks on a laminated structure in the epitaxial growth process so as to improve the yield and the reliability of the three-dimensional memory.
In order to solve the above problems, the present invention provides a method for manufacturing a three-dimensional memory, the method comprising:
forming a first stacked structure on a substrate, the first stacked structure including a plurality of gate sacrificial layers and insulating layers alternately stacked in a direction perpendicular to the substrate;
forming an isolation layer on the first stacked structure;
forming a first channel hole through the isolation layer and the first stacked structure;
and forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth, wherein the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is larger than that of the outermost layer of the substrate relative to the first laminated structure, which is far away from the substrate.
The first laminated structure is in contact with the isolation layer through the grid sacrificial layer.
The gate sacrificial layer is made of silicon nitride, and the isolation layer is made of silicon oxide or an insulating material containing no silicon element.
Wherein the first stacked structure is in contact with the isolation layer through the insulating layer.
The insulating layer is made of silicon oxide, and the isolating layer is made of an insulating material without silicon element.
Wherein, form the first channel hole that passes isolation layer and first laminated structure, specifically include:
etching the isolation layer to the surface of the first laminated structure to pattern the isolation layer;
and etching the first laminated structure to the substrate by using the patterned isolation layer as a hard mask so as to form a first channel hole.
Before etching the isolation layer to the surface of the first laminated structure, the method further comprises the following steps:
sequentially forming a bottom anti-reflection layer and a photoresist layer on the isolation layer;
carrying out exposure and development to pattern the photoresist layer;
etching the bottom anti-reflection layer according to the patterned photoresist layer;
etching the isolation layer to the surface of the first laminated structure, specifically comprising:
and etching the isolation layer to the surface of the first laminated structure according to the patterned photoresist layer.
Wherein, before the epitaxial layer is formed at the bottom of the first channel hole by selective epitaxial growth, the method further comprises the following steps:
and cleaning the inner wall of the first channel hole and the upper surface of the substrate positioned below the first channel hole by using a preset cleaning solution.
Wherein, after the epitaxial layer is formed at the bottom of the first channel hole by selective epitaxial growth, the method further comprises the following steps:
forming a protective layer covering the epitaxial layer in the first channel hole;
forming a sacrificial material layer covering the protective layer in the first channel hole;
forming a second stacked structure on the first stacked structure and the sacrificial material layer;
forming a second channel hole penetrating through the second lamination structure, the second channel hole being communicated with the first channel hole;
the sacrificial material layer and the protective layer are removed through the second trench hole.
Wherein, after the epitaxial layer is formed at the bottom of the first channel hole by selective epitaxial growth, the method further comprises the following steps:
a first oxide layer, a nitride layer and a second oxide layer as a memory function layer, and a semiconductor layer as a channel are sequentially deposited on sidewalls of the first channel hole.
Wherein, still include:
forming a gate line slit penetrating the first stacked structure in a direction perpendicular to the substrate;
and replacing the grid sacrificial layer in the first laminated structure into a grid layer through the grid line gap.
In order to solve the above problems, the present invention also provides a three-dimensional memory, including:
a substrate;
a first stacked layer structure on the substrate, the first stacked layer structure including a plurality of gate layers and insulating layers alternately stacked in a direction perpendicular to the substrate;
an isolation layer on the first stacked structure;
a first channel hole passing through the isolation layer and the first stacked structure;
and the epitaxial layer is positioned at the bottom of the first channel hole and is obtained through selective epitaxial growth, and the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is greater than that of the substrate relative to the outermost layer of the first laminated structure deviating from the substrate.
Wherein the first stacked structure is in contact with the isolation layer through the gate layer.
The isolation layer is made of silicon oxide or an insulating material without silicon element.
Wherein the first stacked structure is in contact with the isolation layer through the insulating layer.
The insulating layer is made of silicon oxide, and the isolating layer is made of an insulating material without silicon element.
Wherein, still include:
a first oxide layer, a nitride layer and a second oxide layer as a memory function layer, and a semiconductor layer as a channel are sequentially provided on a sidewall of the first channel hole.
Wherein, still include:
a second stacked structure on the first stacked structure;
a second channel hole penetrating the second laminated structure, the first channel hole communicating with the second channel hole;
and the channel structures are positioned in the first channel hole and the second channel hole and positioned on the epitaxial layer.
The invention has the beneficial effects that: different from the prior art, the method for manufacturing the three-dimensional memory provided by the invention comprises the steps of forming a first laminated structure on a substrate, wherein the first laminated structure comprises a plurality of gate sacrificial layers and insulating layers which are alternately laminated in a direction vertical to the substrate, forming an isolation layer on the first laminated structure, forming a first channel hole penetrating through the isolation layer and the first laminated structure, and forming an epitaxial layer at the bottom of the first channel hole through selective epitaxial growth, wherein the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is larger than that of the substrate relative to the outermost layer of the first laminated structure, which is far away from the substrate, so that the occurrence of aggregation nucleation of epitaxial materials on the laminated structure can be reduced in the epitaxial growth process, the formation of epitaxial aggregation blocks on the laminated structure is further reduced, and the occurrence of channel hole blockage by the epitaxial aggregation blocks is reduced, the yield and the reliability of the three-dimensional memory are improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention;
FIGS. 2a to 2m are schematic cross-sectional views of a process flow for fabricating a three-dimensional memory according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of epitaxial material nucleation on a stacked structure during the fabrication of a three-dimensional memory provided by the prior art;
fig. 4 is another flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the various figures, elements of similar structure are identified by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, some well-known elements may not be shown in the figures.
The present invention may be embodied in various forms, some examples of which are described below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention, where a specific flow of the method for manufacturing the three-dimensional memory may be as follows:
step S11: a first stacked structure including a plurality of gate sacrificial layers and insulating layers alternately stacked in a direction perpendicular to a substrate is formed on the substrate.
Fig. 2a shows a schematic cross-sectional structure of the completed step S11.
The substrate 11 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). The first stacked structure 12 may include a plurality of gate sacrificial layers 121 and insulating layers 122 alternately stacked in a direction perpendicular to the substrate 11. The outermost layer of the first stacked structure 12 facing away from the substrate 11 may be a gate sacrificial layer 121 (as shown in fig. 2 a) or an insulating layer 122.
Specifically, in the first stacked structure 12, the insulating layer 122 may be formed between adjacent gate sacrificial layers 121, the gate sacrificial layer 121 may be, but is not limited to, silicon nitride, the insulating layer 122 may be, but is not limited to, silicon oxide, so as to form a silicon nitride layer/silicon oxide layer stacked structure, and in the subsequent steps, the gate sacrificial layer 121 is replaced by a replacement process and a conductive material (e.g., tungsten) is filled at the same position to form a gate layer.
In the three-dimensional memory, the number of layers of the first stacked structure 12 determines the number of memory cells included in the vertical direction (the direction perpendicular to the substrate 21), for example, the number of layers of the first stacked structure 12 may be 32, 64, 96, 128, or the like, and the greater the number of layers of the first stacked structure 12, the higher the integration level of the three-dimensional memory.
Step S12: an isolation layer is formed on the first stacked structure.
Fig. 2b shows a schematic cross-sectional structure of the completed step S12.
In this embodiment, in the subsequent step of forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth, the selective epitaxial growth selectivity of the substrate 11 with respect to the isolation layer 13 is greater than the selective epitaxial growth selectivity of the substrate 11 with respect to the outermost layer of the first stacked structure 12 facing away from the substrate 11.
It will be appreciated that the above selective epitaxial growth selection is used to characterize the rate of epitaxial growth on one material over another material under the same epitaxial growth conditions, somewhat faster. Epitaxial growth to form an epitaxial layer on only a selected layer structure can be achieved by increasing the selective epitaxial growth selectivity ratio. Wherein, the selective epitaxial growth selection ratio of the substrate 11 relative to the isolation layer 13 is greater than the selective epitaxial growth selection ratio of the substrate 11 relative to the outermost layer of the first stacked structure 12 away from the substrate 11, which may refer to: in the epitaxial growth process, the ratio of the rate of epitaxial growth on the substrate 11 to the rate of epitaxial growth on the isolation layer 13 is greater than the ratio of the rate of epitaxial growth on the substrate 11 to the rate of epitaxial growth on the outermost layer of the first stacked structure 12 away from the substrate 12, that is, the rate of epitaxial growth on the isolation layer 13 is less than the rate of epitaxial growth on the outermost layer of the first stacked structure 12 away from the substrate 11, so that, compared with the scheme of epitaxial growth formation on the outermost layer of the substrate and the outermost layer of the stacked structure away from the substrate in the prior art, the scheme of epitaxial growth formation on the epitaxial layers on the substrate and the isolation layer in the embodiment can improve the selectivity of epitaxial growth, reduce the growth of epitaxial materials on regions other than the substrate, and further reduce epitaxial aggregation blocks formed by aggregation nucleation of the epitaxial materials on the outermost layer of the first stacked structure away from the substrate in the epitaxial growth process, the method reduces the occurrence of the condition that the epitaxial aggregation block blocks the channel hole, and can greatly improve the yield and the reliability of the three-dimensional memory.
Specifically, the material of the isolation layer 13 may be an insulating material, for example, but not limited to, silicon oxide, silicon sulfide, or an insulating material containing no silicon element, wherein the insulating material containing no silicon element may include an inorganic insulating material containing no silicon element (for example, any one of an oxide, a nitride, a sulfide, or a mixture of at least two of an oxide, a nitride, and a sulfide), or may be an organic insulating material containing no silicon element (for example, at least one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and a polyether sulfone substrate). In a specific embodiment, the spacer layer 13 may be formed on the first stacked structure 12 by a sputtering method, an evaporation method, a plasma-assisted deposition method, a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, a metallorganic thermal decomposition method, a laser-assisted deposition method, a thermal oxidation method, or the like. The spacer layer 13 may be deposited on the first stacked structure 12 by, for example, a chemical vapor deposition method.
Step S13: a first channel hole is formed through the isolation layer and the first stacked structure.
Fig. 2c shows a schematic cross-sectional structure after step S13 is completed.
Specifically, the first channel hole 14 may be formed through the isolation layer 13 and the first stacked structure 12 up to the substrate 11 by sequentially etching the isolation layer 13 and the first stacked structure 12 from top to bottom to expose a portion of the substrate 11. In an embodiment, as shown in fig. 2c, the first channel hole 14 may further penetrate through the isolation layer 13 and the first stacked structure 12 and extend into the substrate 11 to form a groove 11B on the substrate 11, so as to achieve sufficient etching to ensure that the substrate 11 can be exposed through the first channel hole 14, and further to increase a supporting effect of a channel structure formed in the first channel hole 14 in a subsequent process on the first stacked structure 12.
In a specific embodiment, the step S13 may specifically include:
step S131: and etching the isolation layer to the surface of the first laminated structure to pattern the isolation layer.
The patterned isolation layer 13 may include an opening pattern, and the shape of the opening pattern may correspond to the first channel hole 14. For example, the first channel hole 14 may have a circular shape, and the opening pattern of the patterned isolation layer 13 may have a corresponding circular shape. Specifically, an anisotropic etching process, for example, a dry etching process (e.g., a plasma etching process, a reactive ion etching process, etc.), may be used to etch and remove the predetermined region of the isolation layer 13, so as to obtain the patterned isolation layer 13.
Step S132: and etching the first laminated structure to the substrate by using the patterned isolation layer as a hard mask so as to form a first channel hole.
The patterned isolation layer 13 may be a hard mask layer. In practice, the first stacked structure 12 exposed through the opening pattern of the patterned isolation layer 13 may be etched and removed by an anisotropic etching process (e.g., a plasma etching process) to reach the substrate 11, so as to obtain the first channel hole 14. It is understood that, during the process of forming the first channel hole 14 by using the anisotropic etching process, the patterned isolation layer 13 can better function as an etching barrier and is not etched to be thinned, or only a local area near the first channel hole 14 is etched to be thinned.
In other embodiments, the first stacked structure 12 exposed through the opening pattern of the patterned isolation layer 13 may be etched and removed to the substrate 11 by an isotropic etching process, for example, a wet etching process, so as to obtain the first channel hole 14. It is understood that, during the etching process of forming the first channel hole 14 by using the isotropic etching process, the patterned isolation layer 13 has a certain etching selectivity with respect to the first stacked structure 12, the patterned isolation layer 13 and the first stacked structure 12 can be consumed by reacting with the etchant at the same time, and the thickness of the patterned isolation layer 13 should be large enough to ensure that it still has a certain thickness when the etching process is completed.
In some specific embodiments, before the step S131, the method may further include:
step A: and sequentially forming a bottom anti-reflection layer and a photoresist layer on the isolation layer.
For example, a bottom anti-reflective layer and a photoresist layer may be sequentially coated on the above-described isolation layer. The bottom anti-reflection layer may be made of, but not limited to, silicon oxynitride.
And B: and carrying out exposure and development to pattern the photoresist layer.
In the exposure and development process, the bottom anti-reflection layer can effectively eliminate the phenomena of light reflection cut-in and standing wave. The opening pattern of the patterned photoresist layer may correspond to the first channel hole 14, for example, when the first channel hole 14 has a circular shape, the opening pattern of the patterned photoresist layer also has a circular shape.
And C: the bottom antireflective layer is etched according to the patterned photoresist layer.
Accordingly, the step S131 may specifically include: and etching the isolation layer to the surface of the first laminated structure according to the patterned photoresist layer. Also, the bottom anti-reflection layer may be etched based on the same process as the isolation layer 13, that is, the step C and the step S131 may be performed simultaneously. In addition, after the etching of the isolation layer 13, that is, after the step S131, the method may further include: the remaining bottom anti-reflection layer on the isolation layer 13 and the patterned photoresist layer are removed. It is understood that the above method for forming the first channel hole 14 may be formed by directly using a photoresist layer as a pattern mask and simultaneously etching the isolation layer 13 and the first stacked structure 12 in a modified embodiment.
Step S14: an epitaxial layer is formed by selective epitaxial growth at the bottom of the first channel hole.
Fig. 2d shows a schematic cross-sectional structure after step S14 is completed.
The epitaxial layer 13 and the substrate 11 may be made of the same material, and for example, if the substrate 11 is made of monocrystalline silicon, the epitaxial layer 13 may be made of monocrystalline silicon. In other embodiments, the materials of the epitaxial layer 13 and the substrate 11 may also be different, and this is not particularly limited in this embodiment of the present invention. In specific implementation, a single crystal silicon epitaxial layer may be grown on the surface of the substrate 11 by chemical reaction using a gaseous compound of silicon. In addition, when the epitaxial layer 13 is formed, the gate sacrificial layer 121 located at the bottom of the first stacked structure 12 may be used as a bottom select gate sacrificial layer, and the epitaxial layer 13 formed at the bottom of the first channel hole 12A is controlled to extend from the substrate 11 to a corresponding position of the insulating layer 122 on the upper surface of the bottom select gate sacrificial layer, so as to ensure the yield and stability of the subsequently formed bottom select transistor.
The inventor has found that, according to the method for manufacturing a three-dimensional memory in the prior art, as shown in fig. 3, when the epitaxial layer 25 is formed at the bottom of the channel hole 24 by selective epitaxial growth, since the outermost layer of the stacked structure 22 facing away from the substrate 21 is generally a sacrificial material layer 221 (e.g., a silicon nitride layer) or an insulating layer 222 (e.g., a silicon oxide layer), and the selective epitaxial growth selectivity ratio of the outermost layer relative to the substrate 21 is not large, atoms in the epitaxial material tend to gather and nucleate on the outermost layer of the stacked structure 22 facing away from the substrate 21 during the epitaxial growth process, and form an epitaxial gather 25A on the outermost layer of the stacked structure 22 facing away from the substrate 21, and when the epitaxial gather 25A is formed above or around the channel hole 24, the channel hole 24 is prone to be blocked by the epitaxial gather 25A, and the subsequent process for forming other film layer structures in the channel hole 24 cannot be performed normally, the abnormity is easy to occur, and the yield of the finally obtained product is greatly reduced.
In order to avoid the above problem, in this embodiment, when the first stacked structure 12 is in contact with the isolation layer 13 through the gate sacrificial layer 121, that is, when the outermost layer of the first stacked structure 12 facing away from the substrate 11 is the gate sacrificial layer 121, when the manufacturing materials of the gate sacrificial layer 121 and the isolation layer 13 are selected, the selective epitaxial growth selectivity of the substrate 11 relative to the isolation layer 13 may be controlled to be greater than the selective epitaxial growth selectivity of the substrate 11 relative to the gate sacrificial layer 121, so as to realize that the selective epitaxial growth selectivity of the isolation layer 13 is less than the selective epitaxial growth selectivity of the outermost layer of the first stacked structure 12 facing away from the substrate 11. For example, the gate sacrificial layer 121 may be made of silicon nitride, and the isolation layer 13 may be made of silicon oxide or an insulating material containing no silicon element because the selective epitaxial growth selectivity of the substrate 11 with respect to silicon oxide is greater than the selective epitaxial growth selectivity of the substrate 11 with respect to silicon nitride, and the selective epitaxial growth selectivity of the substrate 1 with respect to an insulating material containing no silicon element is greater than the selective epitaxial growth selectivity of the substrate 11 with respect to silicon oxide.
In other embodiments, when the first stacked structure 12 is in contact with the isolation layer 13 through the insulating layer 122, that is, the outermost layer of the first stacked structure 12 facing away from the substrate 11 is the insulating layer 122, when the materials for manufacturing the insulating layer 122 and the isolation layer 13 are selected, the selective epitaxial growth selectivity of the substrate 11 relative to the isolation layer 13 may be controlled to be greater than the selective epitaxial growth selectivity of the substrate 11 relative to the insulating layer 122, so as to achieve that the selective epitaxial growth selectivity of the isolation layer 13 is less than the selective epitaxial growth selectivity of the outermost layer of the first stacked structure 12 facing away from the substrate 11. For example, the insulating layer 122 may be made of silicon oxide, and the isolation layer 13 may be made of silicon oxide or an insulating material containing no silicon element because the selective epitaxial growth selectivity of the substrate 11 with respect to the insulating material containing no silicon element is greater than the selective epitaxial growth selectivity of the substrate 11 with respect to silicon oxide.
In one embodiment, in order to ensure the growth quality of the epitaxial layer at the bottom of the first channel hole 14 and reduce epitaxial defects, the impurity element-contaminated film layer formed in the previous step and located in the first channel hole 14 may be removed before the epitaxial layer 15 is formed, that is, before the step S14, so as to provide a clean and pollution-free epitaxial growth environment. For example, before the step S14, the method may include: and cleaning the inner wall of the first channel hole and the upper surface of the substrate positioned below the first channel hole by using a preset cleaning solution. The preset cleaning liquid can be one of a phosphoric acid solution, a glacial acetic acid solution, a dilute hydrofluoric acid solution and a dilute nitric acid solution, or a mixed liquid obtained by mixing a plurality of solutions according to a certain proportion.
It is understood that, before the epitaxial layer 15 is formed, when the inner wall of the first channel hole 14 and the upper surface of the substrate 11 under the first channel hole 14 are cleaned by the predetermined cleaning solution, the film structure (e.g., the residual bottom anti-reflection layer and the photoresist layer) on the isolation layer 13 may also be simultaneously removed by the predetermined cleaning solution, so as to expose the upper surface of the isolation layer 13.
In a specific embodiment, after the step S14, the method further includes:
step S15: a first oxide layer, a nitride layer and a second oxide layer as a memory function layer, and a semiconductor layer as a channel are sequentially deposited on sidewalls of the first channel hole.
Fig. 2e shows a schematic cross-sectional structure diagram after step S15 is completed.
Specifically, a first oxide layer, a nitride layer, and a second oxide layer may be sequentially deposited on the sidewall of the first channel hole 14 and the surface of the epitaxial layer 15 as the storage function layer 161, then a portion of the storage function layer 161 on the surface of the epitaxial layer 15 is removed to expose the epitaxial layer 15, a semiconductor layer (e.g., a polysilicon layer) as the channel 162 is formed from the surface of the storage function layer 161 to the bottom of the first channel hole 15, and then a layer of oxide layer 163 is deposited inside the channel 162 to fill the remaining space in the first channel hole 15, thereby obtaining the channel structure 16. It is understood that the memory function layer 161 illustrated herein is an ONO structure composed of a first oxide layer, a nitride layer, and a second oxide layer, but may have other possible structures, such as NONO, SONO, and the like.
In some embodiments, after the epitaxial layer 15 is formed and before the trench structure 16 is formed, the isolation layer 13 remaining on the first stacked structure 12 may be removed by wet etching or chemical mechanical polishing, so as to facilitate stability of a film structure formed on the first stacked structure 12. Accordingly, the cross-sectional structure of the step S15 may be as shown in fig. 2 f.
In another embodiment, in order to increase the storage density of the memory, one or more other stacked structures may be further stacked on the first stacked structure 12 after the epitaxial layer 15 is formed. Specifically, as shown in fig. 4, after the step S14, the method may further include:
step S16: a protective layer is formed in the first channel hole to cover the epitaxial layer.
Fig. 2g shows a schematic cross-sectional structure diagram after step S16 is completed.
Specifically, after the epitaxial layer 15 is formed, a protective layer 17 covering the epitaxial layer 15 may be formed next to protect the epitaxial layer from being damaged in the subsequent step of removing the sacrificial material layer through the second channel hole. The material of the protection layer 17 may be, but is not limited to, silicon oxide or metal silicide.
Step S17: a sacrificial material layer is formed in the first channel hole to cover the protective layer.
Fig. 2h shows a schematic cross-sectional structure of the completed step S17.
Specifically, a chemical vapor deposition process may be used to deposit a filling sacrificial material in the first channel hole 14, and chemical mechanical planarization is used to remove the sacrificial material outside the first channel hole 14 to obtain the sacrificial material layer 18. Wherein the sacrificial material may be any one of polysilicon, carbon and tungsten. Defects such as voids may exist within the sacrificial material layer 18, however, after the sacrificial material fills the first channel hole 14, the first stacked structure 12 may still obtain a complete structure surface for subsequent formation of a second stacked structure.
Step S18: a second stacked structure is formed on the first stacked structure and the sacrificial material layer.
Fig. 2i shows a schematic cross-sectional structure after step S18 is completed.
The second stacked structure 19 includes gate sacrificial layers 191 and insulating layers 192 alternately stacked in a plurality of layers in a direction perpendicular to the substrate 11. The method for forming the second stacked structure 19 is the same as the method for forming the first stacked structure 12, and therefore, the description thereof is omitted.
In some embodiments, before forming the second stacked structure 19, the isolation layer 13 remaining on the first stacked structure 12 may be removed by wet etching or chemical mechanical polishing, so as to facilitate stability of a film structure (e.g., the second stacked structure 19) subsequently formed on the first stacked structure 12. Accordingly, the schematic cross-sectional structure after the step S18 is completed can also be shown in fig. 2 j.
Step S19: a second channel hole is formed through the second laminate structure, the second channel hole communicating with the first channel hole.
Fig. 2k shows a schematic cross-sectional structure after step S19 is completed.
Specifically, the second channel hole 19A may be formed through the second stacked structure 19 up to the surface of the isolation layer 13 (or the first stacked structure 12) by etching the above-described second stacked structure 19 from top to bottom, and the bottom of the second channel hole 19A exposes the top surface of the sacrificial material layer 14 in the first channel hole 14.
Step S20: the sacrificial material layer and the protective layer are removed through the second trench hole.
Fig. 2l shows a schematic cross-sectional structure after step S20 is completed.
Specifically, the sacrificial material layer 18 may be removed via the second channel hole 19A, and a selective etchant may be employed to remove the sacrificial material layer 18 and the protective layer 17 selectively with respect to the first and second stacked structures 12 and 19.
Accordingly, the step S15 may specifically include: a channel structure is formed in the first channel hole and the second channel hole. The schematic cross-sectional structure corresponding to the completed step S15 can be shown in fig. 2 m. Specifically, a first oxide layer, a nitride layer, and a second oxide layer may be sequentially deposited on the sidewalls of the first and second channel holes 14 and 19A and the surface of the epitaxial layer 15 as the storage function layer 161, then a portion of the storage function layer 161 on the surface of the epitaxial layer 15 is removed to expose the epitaxial layer 15, and a semiconductor layer (e.g., a polysilicon layer) as the channel 162 is formed from the surface of the storage function layer 161 to the bottom of the first channel hole 15, and then a layer of oxide layer 163 is deposited inside the channel 162 to fill the remaining space in the first and second channel holes 15 and 19A, thereby obtaining the channel structure 16.
In some embodiments, the method for manufacturing the three-dimensional memory may further include:
step S21: a gate line slit penetrating the first stacked structure in a direction perpendicular to the substrate is formed.
For example, the first stacked structure 12 may be etched from top to bottom to form a gate line slit (not shown in the drawings because it is not a feature of the present invention) penetrating through the first stacked structure 12. When the isolation layer 13 and the second stacked structure 19 are present on the first stacked structure 12, the gate line slit also penetrates through the isolation layer 13 and the second stacked structure 19.
Step S22: and replacing the grid sacrificial layer of the first laminated structure into a grid layer through the grid line gap.
For example, the gate sacrificial layer 121 of the first stacked structure 12 may be replaced by a replacement process, and a conductive material (e.g., tungsten) may be filled at the same position to form a gate layer of the first stacked structure 12. Moreover, when the second stacked structure 19 is present on the first stacked structure 12, the gate sacrificial layer 191 of the second stacked structure 19 may be replaced by a replacement process, and a conductive material (e.g., tungsten) may be filled at the same position to form a gate layer of the second stacked structure 19.
In some embodiments, after S22, the replaced gate electrode layer may be further etched through the gate line gap to form a gap between the gate electrode layer and the gate line gap, and in a subsequent process, when the gate line gap is filled with a semiconductor material and/or a metal material, the gap between the gate electrode layer and the gate line gap may also be filled with an insulating layer and the semiconductor material and/or the metal material.
Further, after the step S22, the method may further include:
step S23: and filling a semiconductor material and/or a metal material in the gate line gap.
For example, the gate line gap may be filled with a spacer layer (e.g., an oxide layer) as a dielectric layer and a conductive material (e.g., titanium or titanium nitride, polysilicon and/or tungsten) as a common source to obtain a common source structure.
In the above embodiments, although the three-dimensional memory with a two-layer stack structure is taken as an example for description, the manufacturing method of the three-dimensional memory provided in the embodiments of the present invention is not limited to be applied to the three-dimensional memory with a two-layer stack structure, and can also be applied to the three-dimensional memory with a three-layer or more stack structure. In some embodiments, the method for manufacturing a three-dimensional memory provided by the embodiments of the present invention may also be applied to a three-dimensional memory with a single-layer stack structure. It is understood that, when the three-dimensional memory is formed by using the method for fabricating the three-dimensional memory provided by the embodiment of the invention, by providing an isolation layer in advance on the outermost layer of the first layer stack facing away from the substrate before the epitaxial layer is formed, and the rate of epitaxial growth on the isolation layer is made to be less than the rate of epitaxial growth on the outermost layer of the first stacked structure away from the substrate by selecting the manufacturing materials of the outermost layer of the first stacked structure and the isolation layer, thereby improving the selectivity of epitaxial growth, reducing the growth of epitaxial materials on regions except the substrate, so as to reduce epitaxial aggregation blocks formed by the epitaxial materials due to aggregation nucleation on the outermost layer of the first laminated structure away from the substrate in the epitaxial growth process, the method reduces the occurrence of the condition that the epitaxial aggregation block blocks the channel hole, and can greatly improve the yield and the reliability of the three-dimensional memory.
Different from the prior art, the method for manufacturing a three-dimensional memory provided in this embodiment includes forming a first stacked structure on a substrate, where the first stacked structure includes a gate sacrificial layer and an insulating layer that are alternately stacked in a direction perpendicular to the substrate, forming an isolation layer on the first stacked structure, forming a first channel hole that penetrates the isolation layer and the first stacked structure, and forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth, where a selective epitaxial growth selection ratio of the substrate with respect to the isolation layer is greater than a selective epitaxial growth selection ratio of the substrate with respect to an outermost layer of the first stacked structure that is away from the substrate, so that during the epitaxial growth process, occurrence of epitaxial material aggregation nucleation on the stacked structure can be reduced, formation of epitaxial aggregation blocks on the stacked structure can be reduced, and occurrence of channel hole blockage by the epitaxial aggregation blocks can be reduced, the yield and the reliability of the three-dimensional memory are improved.
The three-dimensional memory fabricated according to the above method embodiment of the present invention is shown in fig. 2e, and includes a substrate 11, a first stacked structure 12 on the substrate 11, an isolation layer 13 on the first stacked structure 12, a first channel hole passing through the isolation layer 13 and the first stacked structure 13, and an epitaxial layer 15 at the bottom of the first channel hole, wherein the first stacked structure 12 may include a plurality of gate layers 121 and insulating layers 122 alternately stacked in a direction perpendicular to the substrate 11. In the present embodiment, the epitaxial layer 15 is obtained by selective epitaxial growth, and a selective epitaxial growth selection ratio of the substrate 11 with respect to the isolation layer 13 is greater than a selective epitaxial growth selection ratio of the substrate 11 with respect to an outermost layer of the first stacked structure 12 away from the substrate 11.
Specifically, the material of the isolation layer 13 may be an insulating material, for example, but not limited to, silicon oxide, silicon sulfide, or an insulating material containing no silicon element, wherein the insulating material containing no silicon element may include an inorganic insulating material containing no silicon element (for example, any one of an oxide, a nitride, a sulfide, or a mixture of at least two of an oxide, a nitride, and a sulfide), or may be an organic insulating material containing no silicon element (for example, at least one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and a polyether sulfone substrate).
In one embodiment, as shown in fig. 2e, the first stacked structure 12 may be in contact with the isolation layer 13 through the gate layer 121. Correspondingly, the material of the isolation layer 13 may be silicon oxide or an insulating material containing no silicon element.
In another embodiment, the first stacked structure 12 may also be in contact with the isolation layer 13 through the insulating layer 122. Correspondingly, the insulating layer 122 may be silicon oxide, and the isolation layer 13 may be an insulating material containing no silicon element.
In a specific embodiment, as shown in fig. 2e, the three-dimensional memory may further include a channel structure 16 located in the first channel hole 14, and the channel structure 16 may include a first oxide layer, a nitride layer, and a second oxide layer as the memory function layer 161, and a semiconductor layer as the channel 162. The storage function layer 161 is located on the sidewall of the first channel hole 14, and the channel 162 is located on the surface of the storage function layer 161 and extends to the bottom of the first channel hole 14. The first oxide layer and the second oxide layer may be made of silicon oxide, the nitride layer may be made of silicon nitride, and the semiconductor layer may be made of polysilicon. Further, the trench structure 16 may further include an oxide layer 163 located inside the trench 162, and the oxide layer 163 may be used to fill the remaining space in the first trench hole 14.
In another embodiment, in order to increase the storage density of the memory, as shown in fig. 2m, the three-dimensional memory may further include a second stacked structure 19 on the first stacked structure 12 and a second channel hole penetrating through the second stacked structure 19, wherein the first channel hole is communicated with the second channel hole, and the channel structure 16 is located in the first channel hole and the second channel hole and covers the epitaxial layer 15.
Different from the prior art, the three-dimensional memory provided by the embodiment has the advantages that the isolation layer is arranged on the outermost layer of the first laminated structure deviating from the substrate, and the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is larger than the selective epitaxial growth selection ratio of the substrate relative to the outermost layer of the first laminated structure deviating from the substrate, so that in the epitaxial growth process, the occurrence of aggregation nucleation of epitaxial materials on the laminated structure can be reduced, the formation of epitaxial aggregation blocks on the laminated structure is further reduced, the occurrence of channel hole blockage of the epitaxial aggregation blocks is reduced, and the yield and the reliability of the three-dimensional memory are improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
forming a first laminated structure on a substrate, wherein the first laminated structure comprises a plurality of gate sacrificial layers and insulating layers which are alternately laminated in a direction vertical to the substrate;
forming an isolation layer on the first stacked structure;
forming a first channel hole through the isolation layer and the first stacked structure;
and forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth, wherein the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is larger than that of the outermost layer of the substrate relative to the first laminated structure, which is far away from the substrate.
2. The method of claim 1, wherein the first stacked structure is in contact with the isolation layer through the gate sacrificial layer.
3. The method of claim 2, wherein the gate sacrificial layer is made of silicon nitride, and the isolation layer is made of silicon oxide or an insulating material without silicon element.
4. The method of claim 1, wherein the first stacked structure is in contact with the isolation layer through the insulating layer.
5. The method according to claim 4, wherein the insulating layer is made of silicon oxide, and the isolation layer is made of an insulating material containing no silicon element.
6. The method according to claim 1, wherein the forming a first channel hole through the isolation layer and the first stacked structure comprises:
etching the isolation layer to the surface of the first laminated structure to pattern the isolation layer;
and etching the first laminated structure to the substrate by taking the patterned isolation layer as a hard mask so as to form a first channel hole.
7. The method of manufacturing according to claim 1, further comprising, after forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth:
forming a protective layer covering the epitaxial layer in the first channel hole;
forming a sacrificial material layer covering the protective layer in the first channel hole;
forming a second stacked structure on the first stacked structure and the sacrificial material layer;
forming a second channel hole penetrating the second laminate structure, the second channel hole communicating with the first channel hole;
removing the sacrificial material layer and the protective layer through the second trench hole.
8. The method of manufacturing according to claim 1, further comprising, after forming an epitaxial layer at the bottom of the first channel hole by selective epitaxial growth:
and sequentially depositing a first oxide layer, a nitride layer and a second oxide layer as a memory function layer and a semiconductor layer as a channel on the side wall of the first channel hole.
9. The method of manufacturing according to claim 1, further comprising:
forming a gate line slit penetrating the first stacked structure in a direction perpendicular to the substrate;
and replacing the grid sacrificial layer in the first laminated structure into a grid layer through the grid line gap.
10. A three-dimensional memory, comprising:
a substrate;
a first stacked-layer structure on the substrate, the first stacked-layer structure including gate layers and insulating layers alternately stacked in a plurality of layers in a direction perpendicular to the substrate;
an isolation layer on the first stacked structure;
a first channel hole passing through the isolation layer and the first stacked structure;
the epitaxial layer is located at the bottom of the first channel hole and is obtained through selective epitaxial growth, and the selective epitaxial growth selection ratio of the substrate relative to the isolation layer is larger than that of the substrate relative to the outermost layer of the first laminated structure deviating from the substrate.
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