CN111540749B - Three-dimensional memory and forming method thereof - Google Patents
Three-dimensional memory and forming method thereof Download PDFInfo
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- CN111540749B CN111540749B CN202010325957.9A CN202010325957A CN111540749B CN 111540749 B CN111540749 B CN 111540749B CN 202010325957 A CN202010325957 A CN 202010325957A CN 111540749 B CN111540749 B CN 111540749B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof. The method for forming the three-dimensional memory comprises the following steps: providing a substrate, wherein the substrate comprises a stacking area and a peripheral area positioned outside the stacking area; forming a first trench in the substrate, the first trench being located at least in the peripheral region; forming a filling layer in the first groove; forming a sacrificial layer and a stacking layer positioned on the surface of the sacrificial layer on the surface of the substrate in the stacking region, wherein the stacking layer is internally provided with a channel hole, a charge storage layer filled in the inner wall of the channel hole and a channel layer covered on the surface of the charge storage layer; forming a second trench through the stacked layers in a direction perpendicular to the substrate, the second trench extending into the fill layer. The invention avoids the substrate damage caused by the over-fast etching rate of the peripheral area and improves the electrical property of the three-dimensional memory.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to pursue lower production costs of unit memory cells, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force.
The 3D NAND memory is based on the small volume and the large capacity, the design concept of the three-dimensional mode layer-by-layer stacking height integration of the storage units is adopted, the memory with high unit area storage density and high-efficiency storage unit performance is produced, and the mainstream process of the design and production of the emerging memory is formed.
For a 3D NAND memory with 128 or more stacked layers, the SWS (Side Wall SEG) structure is a preferred structure because the SWS structure can avoid the challenge of etching the channel function layer due to the increase of the number of layers in the 3D NAND. However, in the current formation process of the SWS structure, damage is often caused to the substrate in the peripheral area of the 3D NAND memory, thereby seriously affecting the electrical performance of the 3D NAND memory.
Therefore, how to avoid damage to the substrate in the SWS structure forming process, so as to improve the electrical performance of the 3D NAND memory, is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a three-dimensional memory and a forming method thereof, which are used for solving the problem that a substrate is easy to damage in the process of forming an SWS in the prior art so as to improve the electrical property of a 3D NAND memory.
In order to solve the above problems, the present invention provides a method for forming a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a stacking area and a peripheral area positioned outside the stacking area;
forming a first trench in the substrate, the first trench being located at least in the peripheral region;
forming a filling layer in the first groove;
forming a sacrificial layer and a stacking layer positioned on the surface of the sacrificial layer on the surface of the substrate in the stacking region, wherein the stacking layer is internally provided with a channel hole, a charge storage layer filled in the inner wall of the channel hole and a channel layer covered on the surface of the charge storage layer;
forming a second trench through the stacked layers in a direction perpendicular to the substrate, the second trench extending into the fill layer.
Optionally, the specific step of forming the first trench in the substrate includes:
and etching the substrate to form the first groove extending from the peripheral region to the stacking region.
Optionally, the specific step of forming the filling layer in the first trench includes:
and depositing an insulating material in the first groove to form the filling layer.
Optionally, after the filling layer is formed, the method further includes the following steps:
planarizing the fill layer such that a top surface of the fill layer is flush with a top surface of the substrate.
Optionally, the specific steps of forming a sacrificial layer on the substrate surface of the stacking region and forming a stacking layer on the surface of the sacrificial layer include:
forming the sacrificial layer on the substrate surface of the stacking area;
and forming a stacking layer on the surface of the sacrificial layer, wherein the stacking layer comprises a core region and a step region positioned outside the core region, and the first groove extends to the inside of the substrate corresponding to the step region.
Optionally, the second trench is a gate line isolation trench.
Optionally, the stacked layer has a channel hole, a charge storage layer filled in an inner wall of the channel hole, and a channel layer covering a surface of the charge storage layer; after forming a second trench penetrating the stacked layers in a direction perpendicular to the substrate, the method further includes the steps of:
removing the sacrificial layer and a portion of the charge storage layer along the second trench, exposing the channel layer;
and forming an epitaxial layer at least covering the side surface of the channel layer.
Optionally, the stacked layer includes interlayer insulating layers and dummy gate layers alternately stacked in a direction perpendicular to the substrate; after an epitaxial layer at least covering the side surface of the channel layer is formed, the method further comprises the following steps:
removing the dummy gate layer along the second trench to form a gap region between two adjacent interlayer insulating layers;
and filling a conductive material in the gap area to form a gate layer.
Optionally, after the gate layer is formed, the method further includes the following steps:
forming a spacer layer covering the side wall of the second groove;
removing the filling layer and part of the substrate at the bottom of the second trench;
and filling a conductive material in the second groove to form an array common source which is in contact with the substrate.
In order to solve the above problem, the present invention also provides a three-dimensional memory, including:
a substrate including a stack region and a peripheral region located outside the stack region, the substrate surface of the stack region having a stack structure;
a first trench located at least in the substrate in the peripheral region;
the filling layer is filled in the first groove;
a second trench penetrating the stacked structure in a direction perpendicular to the substrate and extending into the fill layer;
and the spacing layer covers the surface of the side wall of the second groove.
Optionally, the second trench is a gate line isolation trench; the three-dimensional memory further includes:
and the array common source is filled in the second groove and penetrates through the filling layer.
Optionally, the method further includes:
and the spacing layer covers the surface of the side wall of the second groove.
Optionally, a top surface of the filling layer is flush with a top surface of the substrate.
Optionally, the first trench extends from the peripheral region to the stacking region.
Optionally, the stacked structure includes a core region and a step region located outside the core region, and the first trench extends to an inside of the substrate corresponding to the step region.
Optionally, the method further includes:
a channel hole penetrating the stacked structure in a direction perpendicular to the substrate and extending to an inside of the substrate;
the charge storage layer covers the inner wall surface of the channel hole;
the channel layer is filled in the channel hole and covers the surface of the charge storage layer, and the side wall of the charge storage layer is provided with a notch exposing the channel layer;
and the epitaxial layer is filled in the gap and covers the surface of the substrate.
According to the three-dimensional memory and the forming method thereof, before the stacked layer is etched, the first groove is formed at least in the substrate of the peripheral area, and the filling layer is formed in the first groove, so that in the subsequent process of etching the stacked layer, substrate damage caused by the fact that the etching rate of the peripheral area is too high is avoided, the integrity of the substrate structure is ensured, the conductive structure in the substrate is prevented from being damaged, and the electrical property of the three-dimensional memory is improved. In addition, the three-dimensional memory and the forming method thereof provided by the invention have the advantages that the process is simple, the process is easy to control, and the yield of the three-dimensional memory is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the present invention;
FIGS. 2A-2J are schematic cross-sectional views illustrating the main processes of forming a three-dimensional memory according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a three-dimensional memory and a method for forming the same according to the present invention with reference to the accompanying drawings.
By adopting the SWS structure, the etching challenge of a charge storage layer of a three-dimensional memory such as a 3D NAND memory caused by the increase of the number of stacked layers can be avoided. The substrate surface is generally provided with a stacking area and a peripheral area positioned outside the stacking area, the stacking area is provided with stacking layers, and a step area and the peripheral area of each stacking layer are covered with dielectric layers so as to realize the planarization of the step area and the peripheral area. In forming the SWS, it is often necessary to form trenches through the stack by etching. However, during the etching process, the etching rate of the dielectric layer in the peripheral region outside the stacked layer is faster than that of the stacked layer, so that the etching of the peripheral region may extend into the substrate while the trench penetrating through the stacked layer is formed in the stacked region, thereby causing damage to the substrate. However, the substrate in the peripheral region has various conductive structures, and damage to the substrate may damage the conductive structures in the substrate, which may seriously even cause the P-well in the substrate to be blocked, thereby affecting the electrical erasing performance of the P-well in the three-dimensional memory.
In order to avoid damage to the substrate in the peripheral region during the process of etching the stack layer, thereby improving the electrical performance of the three-dimensional memory, the present embodiment provides a three-dimensional memory and a forming method thereof, fig. 1 is a flow chart of a forming method of the three-dimensional memory in the embodiment of the present invention, and fig. 2A to 2I are schematic cross-sectional views of main processes of the three-dimensional memory in the forming process in the embodiment of the present invention. The three-dimensional memory described in this detailed description may be, but is not limited to, a 3D NAND memory. As shown in fig. 1 and fig. 2A to fig. 2J, the method for forming a three-dimensional memory according to the present embodiment includes the following steps:
step S11, providing a substrate 20, where the substrate 20 includes a stacking region and a peripheral region PA located outside the stacking region.
Step S12 is to form a first trench 31 in the substrate 20, where the first trench 31 is at least located in the peripheral area PA, see fig. 2I.
Optionally, the specific step of forming the first trench 31 in the substrate 20 includes:
the substrate 20 is etched to form the first trench 31 extending from the peripheral area PA to the stack area.
In particular, the material of the substrate 20 may be, but is not limited to, silicon, the substrate 20 being used to support device structures thereon. In the present embodiment, before forming other device structures on the surface of the substrate 20, a wet etching process, a dry etching process, or a plasma etching process is first used to etch from the surface of the substrate 20 (i.e., the top surface of the substrate 20) to the inside of the substrate 20, so as to form the first trench 31. The depth of the first trench 31 may be set by a person skilled in the art according to actual needs, for example, the depth of a second trench to be formed subsequently, the kind of etchant used in the process of etching the stack region subsequently, and the like, which is not limited in this embodiment. In the process of forming the first trench 31, the first trench may be directly etched by using an alignment Mask (Zero Mask) according to a position of a second trench to be formed subsequently, without an additional alignment structure.
Step S13, a filling layer 21 is formed in the first trench 31, as shown in fig. 2A, fig. 2A is a schematic cross-sectional view along a-a' direction in fig. 2I, that is, fig. 2A is a schematic cross-sectional view of the peripheral area PA.
Optionally, the specific step of forming the filling layer 21 in the first trench 31 includes:
an insulating material is deposited in the first trench 31 to form the filling layer 21.
Optionally, after forming the filling layer 21, the method further includes the following steps:
the filling layer 21 is planarized so that the top surface of the filling layer 21 is flush with the top surface of the substrate 20.
Specifically, after the first trench 31 is formed, an insulating material may be deposited in the first trench 31 by using a chemical vapor deposition process, a physical vapor deposition process, or a plasma deposition process, so as to form the filling layer 21 filling the first trench 31. In order not to affect the subsequent device structure formation process on the surface of the substrate 20, after the filling layer 21 is deposited, a chemical mechanical polishing process may be further used to planarize the filling layer 21 so that the top surface of the filling layer 21 is flush with the top surface of the substrate 20. The material of the filling layer 21 may be, but is not limited to, one or a combination of two or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and an oxynitride material (e.g., silicon oxynitride).
Step S14, forming a sacrificial layer 26 and a stacked layer 24 on the surface of the sacrificial layer 26 on the surface of the substrate 20 in the stacked region, where the stacked layer 24 has a channel hole, a charge storage layer filled in the inner wall of the channel hole, and a channel layer covering the surface of the charge storage layer, as shown in fig. 2D, and fig. 2D is a schematic cross-sectional view of the core region CA in fig. 2I.
Optionally, the specific steps of forming the sacrificial layer 26 on the surface of the substrate 20 in the stacking region and forming the stacking layer on the surface of the sacrificial layer 26 include:
forming the sacrificial layer 26 on the surface of the substrate 20 in the stacking region;
forming a stack layer 24 on the surface of the sacrificial layer 26, where the stack layer 24 includes a core area CA and a step area SS located outside the core area CA, and the first trench 31 extends into the substrate 20 corresponding to the step area SS.
Specifically, after the filling layer 21 is formed, a sacrificial layer 26 and a stack layer 24 on a surface of the sacrificial layer 26 are formed prior to the stack region on the surface of the substrate 20, and the stack layer 24 includes interlayer insulating layers 241 and dummy gate layers 242 alternately stacked in a direction perpendicular to the substrate 20. The material of the interlayer insulating layer 241 may be, but is not limited to, an oxide material (e.g., silicon oxide), and the material of the dummy gate layer 242 may be, but is not limited to, an oxynitride material (e.g., silicon oxynitride). The stack layer 24 includes a core area CA and a step area SS located outside the core area CA. After the step area SS is formed, a dielectric material is deposited on the step area SS and the peripheral area PA, a dielectric layer 22 covering the step area SS and the peripheral area PA is formed, and the dielectric layer 22 is subjected to planarization processing, so that the formed structure is as shown in fig. 2B, where fig. 2B is a schematic cross-sectional view in the direction of a-a' in fig. 2I.
Then, the stacked layer 24, the sacrificial layer 26 and a portion of the substrate 20 in the core area CA are etched to form a channel hole that penetrates through the stacked layer 24 and the sacrificial layer 26 in a direction perpendicular to the substrate 20 and extends to the inside of the substrate 20. Meanwhile, a dummy channel hole may be formed in the step region SS. The charge storage layer includes a blocking layer 251 covering an inner wall of the channel hole, a charge trapping layer 252 covering a surface of the blocking layer 251, and a tunneling layer 253 covering a surface of the charge trapping layer 252, and the channel layer 254 covers a surface of the tunneling layer 253. The material of the blocking layer 251 may be silicon oxide and/or silicon oxynitride, the material of the charge trapping layer 252 may be a single-layer or multi-layer material of silicon nitride and/or silicon oxynitride, the material of the tunneling layer 253 may be silicon oxide and/or silicon oxynitride, and the material of the channel layer 254 may be an intrinsic polysilicon material. The charge storage layer and the channel layer 254 together constitute a storage function layer. In addition, an insulating layer (e.g., a silicon oxide material) may be further covered on the surface of the channel layer, and the insulating layer and the memory function layer together form an OPONO structure. An Air Gap (Air Gap) may also be formed in the insulating layer.
As shown in fig. 2I, the first trench 31 may extend from the inside of the substrate 20 in the peripheral area PA to the inside of the substrate 20 corresponding to the step area SS of the stacked layer 24, and may even extend from the inside of the substrate 20 corresponding to the step area SS to the inside of the substrate 20 corresponding to the core area CA, so as to further avoid damage to the substrate 20 corresponding to the step area SS during etching the stacked layer. The length of the first trench 31 may be selected by a person skilled in the art according to actual needs, and in this embodiment, in order to further avoid the substrate 20 corresponding to the step region SS from being damaged, the first trench 31 extends from the inside of the substrate 20 in the peripheral region PA to the inside of the substrate 20 corresponding to the step region SS.
Step S15, forming a second trench 23 penetrating through the stacked layer 24 in a direction perpendicular to the substrate 20, wherein the second trench 23 extends into the filling layer 21, as shown in fig. 2C and 2D, and fig. 2C is a schematic cross-sectional view along a-a' direction in fig. 2I.
Optionally, the second trench 23 is a gate line isolation trench. In other embodiments, the second trench 23 may have other structures penetrating through the stacked layer 24.
The depth of the first trench 31 is such that the second trench 23 is formed without penetrating the filling layer 21, and the width of the first trench 31 is larger than the second trench 23. Taking the second trench 23 as a gate line spacer as an example, the stacked layer 24 of the core region CA, the stacked layer 24 and the dielectric layer 22 of the step region SS, and the dielectric layer 22 of the peripheral region PA may be etched synchronously by wet etching process to form the second trench 23 penetrating through the stacked layer 24 in a direction perpendicular to the substrate 20. Since the etching rate of the dielectric layer 22 is greater than that of the stack layer 24, in the process of etching the peripheral area PA, the second trench 23 extends to the inside of the substrate 20 of the peripheral area PA, but since the first trench 31 and the filling layer 21 filled in the first trench 31 are formed in advance in the inside of the substrate 20, the substrate 20 can be effectively prevented from being damaged, and the conductive structure in the substrate 20 is protected.
Optionally, the stacked layer 24 has a channel hole therein, a charge storage layer filled in an inner wall of the channel hole, and a channel layer 254 covering a surface of the charge storage layer; after forming the second trench 23 penetrating the stacked layer 24 in a direction perpendicular to the substrate 20, the method further includes the steps of:
removing the sacrificial layer 26 and a portion of the charge storage layer along the second trench 23, exposing the channel layer 254;
an epitaxial layer 27 is formed to cover at least the side of the channel layer 254, as shown in fig. 2E, and fig. 2E is a schematic cross-sectional view of the core region CA in fig. 2I.
Alternatively, the stacked layer 24 includes interlayer insulating layers 241 and dummy gate layers 242 alternately stacked in a direction perpendicular to the substrate 20; after forming the epitaxial layer 27 covering at least the side of the channel layer 254, the method further includes the steps of:
removing the dummy gate layer 242 along the second trench 23 to form a void region 243 between two adjacent inter-layer insulating layers 241, as shown in fig. 2F, where fig. 2F is a schematic cross-sectional view of the core region CA in fig. 2I;
conductive material is filled in the void area 243 to form a gate layer.
Specifically, after the second trench 23 penetrating the stack layer 24 is formed and the sacrificial layer 26 is exposed, the sacrificial layer 26 and a portion of the charge storage layer are removed along the second trench 23 by using a wet etching process, and the channel layer 254 and the surface of the substrate 20 of the core region CA are exposed. Then, silicon or the like is grown on the sidewall of the channel hole and the surface of the substrate 20, and the epitaxial layer 27 in contact with the channel layer 254 and the substrate 20 is formed. Then, a wet etching process is used to remove the dummy gate layer 242 in the stack layer 24 along the second trench 23, forming a void area 243 between two adjacent layers of the interlayer insulating layer 241, and filling a conductive material such as tungsten in the void area 243 to form the gate layer.
Optionally, after the gate layer is formed, the method further includes the following steps:
forming a spacer layer 28 covering the sidewalls of the second trench 23;
removing the filling layer 21 and part of the substrate 20 at the bottom of the second trench 23;
a conductive material is filled in the second trench 23 to form an array common source 30 in contact with the substrate 20, as shown in fig. 2H, where fig. 2H is a schematic cross-sectional view along a-a' direction in fig. 2I.
Specifically, after the gate layer is formed, an insulating material is deposited on the inner wall surface of the second trench 23, and a spacer layer 28 covering the surface of the remaining filling layer 21 is formed, as shown in fig. 2G, where fig. 2G is a schematic cross-sectional view along a-a' direction in fig. 2I. And then, removing the spacer layer 28 at the bottom of the second trench 23 and the residual filling layer 21 and part of the substrate 20 at the bottom of the first trench 31 by using an etching process. Then, an adhesion layer 29 is formed on the surface of the spacer layer 28, the exposed surface of the filling layer 21 and the exposed surface of the substrate 20 along the second trench 31. Then, a material such as polysilicon is filled in the second trench 23 to form an array common source 30 in contact with the substrate 20. Specifically, the array common source 30 is electrically connected to a source region inside the substrate (not shown). Wherein the material of the spacer layer 28 may be, but is not limited to, an oxide material (e.g., silicon oxide); the material of the adhesion layer 29 may be, but is not limited to, titanium nitride.
In the process of forming the array common source 30, the filling layer 21 and a portion of the substrate 20 at the bottom of the second trench 31 are removed, so that the finally formed adhesion layer 29 and the array common source 30 extend out of the first trench 31 in the Z-axis direction, as shown in fig. 2H. One skilled in the art may also remove, according to actual needs, only the filling layer 21 at the bottom of the second trench 31 to expose the surface of the substrate 20, so that the finally formed adhesion layer 29 and the array common source 30 do not extend out of the first trench 31, that is, the bottom surface of the filling layer 21 remaining after the formation of the array common source 30 is flush with the bottom surface of the adhesion layer 29, as shown in fig. 2J.
Moreover, the present embodiment further provides a three-dimensional memory. The three-dimensional memory provided by the present embodiment can be formed by the method shown in fig. 1 and fig. 2A to 2I. Referring to fig. 1, 2A to 2I, the three-dimensional memory provided by the present embodiment includes:
a substrate 20, the substrate 20 including a stacking region and a peripheral region PA located outside the stacking region, the substrate 20 surface of the stacking region having a stacking structure;
a first trench 30 located at least in the substrate 20 of the peripheral area PA;
a filling layer 21 filled in the first trench 30;
and a second trench 23 penetrating the stacked structure in a direction perpendicular to the substrate 20 and extending to the filling layer 21.
Optionally, the second trench 23 is a gate line isolation trench; the three-dimensional memory further includes:
and the array common source 30 is filled in the second trench 23 and penetrates through the filling layer 21.
Optionally, the three-dimensional memory further includes:
and a spacer layer 28 covering the sidewall surface of the second trench 23.
Optionally, the top surface of the filling layer 21 is flush with the top surface of the substrate 20.
Optionally, the first trench 30 extends from the peripheral area PA to the stack area.
Optionally, the stacked structure includes a core region CA and a step region SS located outside the core region CA, and the first trench 30 extends into the substrate 20 corresponding to the step region SS.
Optionally, the three-dimensional memory further includes:
a channel hole penetrating the stacked structure in a direction perpendicular to the substrate 20 and extending to the inside of the substrate 20;
the charge storage layer covers the inner wall surface of the channel hole;
the channel layer 254 is filled in the channel hole and covers the surface of the charge storage layer, and the side wall of the charge storage layer is provided with a gap exposing the channel layer 254;
and the epitaxial layer 27 is filled in the gap and covers the surface of the substrate 20.
In the three-dimensional memory and the forming method thereof provided by the present embodiment, before etching the stack layer, the first trench is formed at least in the substrate in the peripheral region, and the filling layer is formed in the first trench, so that in the subsequent process of etching the stack layer, substrate damage caused by an excessively fast etching rate of the peripheral region is avoided, the integrity of the substrate structure is ensured, the conductive structure in the substrate is prevented from being damaged, and thus, the electrical performance of the three-dimensional memory is improved. In addition, the three-dimensional memory and the forming method thereof provided by the invention have the advantages that the process is simple, the process is easy to control, and the yield of the three-dimensional memory is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (14)
1. A method for forming a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a stacking area and a peripheral area positioned outside the stacking area;
etching the substrate to form a first trench extending from the peripheral region to the stack region;
forming a filling layer in the first groove;
forming a sacrificial layer and a stacking layer positioned on the surface of the sacrificial layer on the surface of the substrate in the stacking area;
forming a second trench through the stacked layers in a direction perpendicular to the substrate, the second trench extending into the fill layer.
2. The method of claim 1, wherein the step of forming a filling layer in the first trench comprises:
and depositing an insulating material in the first groove to form the filling layer.
3. The method of claim 1, further comprising the following steps after forming the filling layer:
planarizing the fill layer such that a top surface of the fill layer is flush with a top surface of the substrate.
4. The method as claimed in claim 1, wherein the step of forming a sacrificial layer on the surface of the substrate in the stacking region and a stacking layer on the surface of the sacrificial layer comprises:
forming the sacrificial layer on the substrate surface of the stacking area;
and forming a stacking layer on the surface of the sacrificial layer, wherein the stacking layer comprises a core region and a step region positioned outside the core region, and the first groove extends to the inside of the substrate corresponding to the step region.
5. The method of claim 1, wherein the second trench is a gate line spacer.
6. The method as claimed in claim 5, wherein the stacked layer has a channel hole, a charge storage layer filled in an inner wall of the channel hole, and a channel layer covering a surface of the charge storage layer; after forming a second trench penetrating the stacked layers in a direction perpendicular to the substrate, the method further includes the steps of:
removing the sacrificial layer and a portion of the charge storage layer along the second trench, exposing the channel layer;
and forming an epitaxial layer at least covering the side surface of the channel layer.
7. The method according to claim 6, wherein the stacked layers include interlayer insulating layers and dummy gate layers alternately stacked in a direction perpendicular to the substrate; after an epitaxial layer at least covering the side surface of the channel layer is formed, the method further comprises the following steps:
removing the dummy gate layer along the second trench to form a gap region between two adjacent interlayer insulating layers;
and filling a conductive material in the gap area to form a gate layer.
8. The method of claim 7, further comprising the following steps after the gate layer is formed:
forming a spacer layer covering the side wall of the second groove;
removing the filling layer and part of the substrate at the bottom of the second trench;
and filling a conductive material in the second groove to form an array common source which is in contact with the substrate.
9. A three-dimensional memory, comprising:
a substrate including a stack region and a peripheral region located outside the stack region, the substrate surface of the stack region having a stack structure;
a first trench extending from the peripheral region to the stack region;
the filling layer is filled in the first groove;
a second trench penetrating the stacked structure in a direction perpendicular to the substrate and extending into the fill layer;
and the spacing layer covers the surface of the side wall of the second groove.
10. The three-dimensional memory according to claim 9, wherein the second trench is a gate line spacer; the three-dimensional memory further includes:
and the array common source is filled in the second groove and penetrates through the filling layer.
11. The three-dimensional memory according to claim 10, further comprising:
and the spacing layer covers the surface of the side wall of the second groove.
12. The three-dimensional memory according to claim 11, wherein a top surface of the fill layer is flush with a top surface of the substrate.
13. The three-dimensional memory according to claim 12, wherein the stacked structure includes a core region and a step region outside the core region, and the first trench extends to an inside of the substrate corresponding to the step region.
14. The three-dimensional memory according to claim 9, further comprising:
a channel hole penetrating the stacked structure in a direction perpendicular to the substrate and extending to an inside of the substrate;
the charge storage layer covers the inner wall surface of the channel hole;
the channel layer is filled in the channel hole and covers the surface of the charge storage layer, and the side wall of the charge storage layer is provided with a notch exposing the channel layer;
and the epitaxial layer is filled in the gap and covers the surface of the substrate.
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| CN108447865A (en) * | 2018-04-19 | 2018-08-24 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN109244075A (en) * | 2018-09-04 | 2019-01-18 | 长江存储科技有限责任公司 | The manufacturing method of 3D memory device |
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| CN110676258A (en) * | 2019-01-08 | 2020-01-10 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN110770913A (en) * | 2017-07-25 | 2020-02-07 | 闪迪技术有限公司 | Aligned drain select level isolation structure for three-dimensional memory device and method of fabricating the same |
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| CN110770913A (en) * | 2017-07-25 | 2020-02-07 | 闪迪技术有限公司 | Aligned drain select level isolation structure for three-dimensional memory device and method of fabricating the same |
| CN108447865A (en) * | 2018-04-19 | 2018-08-24 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
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