KR102302092B1 - Vertical memory devices and methods of manufacturing the same - Google Patents

Abstract

A vertical memory device includes a substrate, channels, gate lines, and a blocking structure. The substrate includes a cell region and a peripheral circuit region. The channels are disposed on the cell region and extend in a first direction perpendicular to the top surface of the substrate. The gate lines surround the outer walls of the channels and are stacked to be spaced apart from each other in the first direction. A blocking structure is disposed between the cell region and the peripheral circuit region. Transmission of stress between the cell region and the peripheral circuit region may be blocked through the blocking structure.

Description

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

The present invention relates to a vertical memory device and a method for manufacturing the same. More particularly, the present invention relates to a nonvolatile vertical type memory device having a channel perpendicular to a top surface of a substrate and a method of manufacturing the same.

Recently, a vertical memory device in which memory cells are vertically stacked from a substrate surface has been developed for high integration of the memory device. In the vertical memory device, a column or cylinder-shaped channel protruding vertically from a top surface of a substrate may be provided, and a plurality of gate lines and insulating layers in contact with the channel may be stacked.

In order to increase the capacity and the degree of integration of the vertical memory device, it is necessary to stack more gate lines and insulating layers in a vertical direction. In this case, stress may be generated as a plurality of layers are stacked, and thus, structural and/or electrical characteristics of the vertical memory device may be defective.

SUMMARY OF THE INVENTION One object of the present invention is to provide a vertical memory device having improved structural stability and operational reliability.

An object of the present invention is to provide a method of manufacturing a vertical memory device having improved structural stability and operational reliability.

However, the problems to be solved by the present invention are not limited to the above problems, and may be variously expanded without departing from the spirit and scope of the present invention.

In order to achieve the above object of the present invention, a vertical memory device according to embodiments of the present invention includes a substrate, channels, gate lines, and a blocking structure. The substrate includes a cell region and a peripheral circuit region. The channels are disposed on the cell region and extend in a first direction perpendicular to the upper surface of the substrate. The gate lines surround outer walls of the channels and are stacked to be spaced apart from each other in the first direction. The blocking structure is disposed between the cell region and the peripheral circuit region.

In example embodiments, the gate lines extend along a second direction parallel to the upper surface of the substrate, and the blocking structure extends along at least a third direction parallel to the upper surface of the substrate and intersecting the second direction. can be

In example embodiments, the blocking structure may include a dummy channel including the same material as the channel.

In example embodiments, the vertical memory device may further include a dielectric film structure surrounding an outer wall of the channel. The blocking structure may include a dummy dielectric layer including the same material as the dielectric layer structure.

In example embodiments, the blocking structure may include an air gap.

In example embodiments, the blocking structure may include one or more dummy channel columns including a plurality of dummy channel structures.

In example embodiments, the dummy channel structure may include a dummy channel having the same shape as the channel.

In example embodiments, the vertical memory device may further include contacts electrically connected to the gate lines on the cell region. The blocking structure may include one or more dummy contact columns including a plurality of dummy contacts.

In example embodiments, the blocking structure may include a dummy conductive line.

In example embodiments, the vertical memory device may further include a common source line disposed on the cell region. The common source line and the dummy conductive line may include the same conductive material.

In example embodiments, at least a portion of the blocking structure may be embedded into the substrate.

In example embodiments, a gate structure may be formed on the peripheral circuit region, and the gate structure may include a gate electrode buried in the substrate.

In order to achieve the above object of the present invention, a vertical memory device according to embodiments of the present invention includes a substrate, channels, gate lines, a common source line, and a blocking structure. The substrate includes a cell region and a peripheral circuit region. The channels are disposed on the cell region and extend in a first direction perpendicular to the upper surface of the substrate. The gate lines surround outer walls of the channels and are stacked to be spaced apart from each other in the first direction. The common source line is disposed on the cell region. The blocking structure is disposed between the cell region and the peripheral circuit region and surrounds the cell region.

In example embodiments, the blocking structure may include a dummy channel including the same material as the channel.

In example embodiments, the blocking structure may include one or more dummy channel columns having the same shape as the channels.

In example embodiments, the blocking structure may include the same material as the common source line.

As described above, according to the vertical memory device according to example embodiments, a blocking structure may be formed between the cell region and the peripheral circuit region. By the blocking structure, it is possible to prevent a phenomenon in which a stress generated when forming a channel, a dielectric layer structure, etc. included in the cell region is transferred to the peripheral circuit region. Accordingly, it is possible to suppress defects such as detachment and malfunction of peripheral circuits that may occur due to the stress.

1 is a plan view illustrating a vertical memory device according to example embodiments.
2 and 3 are cross-sectional views taken along lines II' and II-II' of FIG. 1, respectively.
4 to 17B are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to example embodiments.
18 is a cross-sectional view illustrating a vertical memory device according to example embodiments.
19 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device according to example embodiments.
25 and 26 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
27 to 29B are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to example embodiments.
30 to 32 are plan views and cross-sectional views illustrating vertical memory devices according to example embodiments.
33 to 36C are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to example embodiments.
37 and 38 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
39 and 40 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
41A and 41B are cross-sectional views illustrating a vertical memory device according to example embodiments.
42 to 44 are cross-sectional views illustrating vertical memory devices according to example embodiments.
45A and 45B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
46A to 48 are plan views and cross-sectional views each illustrating a method of manufacturing a vertical memory device according to example embodiments.
49A and 49B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
50A and 50B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.
51 is a block diagram showing a schematic configuration of an information processing system according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In each drawing of the present invention, the dimensions of the structures are enlarged than the actual size for clarity of the present invention.

In the present invention, terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

The terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

In the present invention, each layer (film), region, electrode, pattern or structure is formed “on”, “on” or “under” the object, substrate, each layer (film), region, electrode or pattern. Each layer (film), region, electrode, pattern or structures, when referred to as being, is meant to be formed directly over or beneath the substrate, each layer (film), region, or patterns, or to another layer (film). , other regions, other electrodes, other patterns, or other structures may be additionally formed on the object or substrate.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It should not be construed as being limited to the embodiments described in

That is, since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a vertical memory device according to example embodiments. 2 and 3 are cross-sectional views taken along lines II' and II-II' of FIG. 1, respectively.

1 to 3 , a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions parallel to and crossing the upper surface of the substrate are defined as a second direction and a third direction, respectively. For example, the second direction and the third direction may cross each other substantially perpendicularly. The direction indicated by the arrow in the drawing and the opposite direction thereof will be described as the same direction. The definition of the above-mentioned direction is the same in all drawings hereinafter.

1 to 3 , the vertical memory device may include a plurality of vertical channel structures that protrude from the upper surface of the substrate 100 in the first direction and extend. The vertical channel structure may include a channel 235 , a dielectric film structure 230 surrounding an outer wall of the channel 235 , and a first buried film pattern 240 disposed inside the channel 235 . The vertical memory device includes gate lines 270 disposed on an outer wall of the dielectric layer structure 230 to extend in a second direction and spaced apart from each other in the first direction. In addition, the vertical memory device may include a pad 260 disposed on the channel 235 and the dielectric layer structure 230 and in contact with the channel 235 .

The substrate 100 may include, for example, a semiconductor material such as silicon or germanium. For example, the substrate 100 may function as a p-type well of the vertical memory device.

According to exemplary embodiments, the substrate 100 includes a cell region (I) and a peripheral circuit region (III), and a blocking region (II) defined between the cell region (I) and the peripheral circuit region (III) may include.

The channel 235 is disposed on the cell region I of the substrate 100 to contact the upper surface of the substrate 100 , and may have an empty cylinder shape or a cup shape. The channel 235 may include polysilicon or single crystal silicon, for example, p-type impurities such as boron (B).

A first buried layer pattern 240 having a pillar shape or a hollow cylindrical shape may be formed in the inner space of the channel 235 . The first buried layer pattern 240 may include an insulating material such as silicon oxide. In one embodiment, the channel 235 may have a pillar shape or a solid cylindrical shape. In this case, the first buried layer pattern 240 may be omitted.

The dielectric film structure 230 may be formed on the outer wall of the channel 235 and may have a cup shape or a straw shape with a bottom center portion open substantially.

Although not specifically illustrated, the dielectric film structure 230 may include a tunnel insulating film, a charge storage film, and a blocking film sequentially stacked from the outer wall of the channel 235 . The blocking layer may include silicon oxide or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may include a nitride such as silicon nitride or a metal oxide, and the tunnel insulating layer may include an oxide such as silicon oxide. For example, the stacked structure of the blocking layer, the charge storage layer, and the tunnel insulating layer may have an oxide-nitride-oxide (ONO) structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

In an embodiment, a semiconductor pattern (not shown) disposed between the upper surface of the substrate 100 and the lower surface of the channel 235 may be additionally formed. In this case, the channel 235 may be provided on the upper surface of the semiconductor pattern, and the dielectric film structure 230 may be provided on the periphery of the upper surface of the semiconductor pattern. The semiconductor pattern may include, for example, single crystal silicon or polysilicon.

A pad 260 may be formed on the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 . For example, the pad 260 may have a shape that caps the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 . The pad 260 may include polysilicon or single crystal silicon, and may further include n-type impurities such as phosphorus (P) and arsenic (As).

1 , a plurality of pads 260 may be formed along the second direction to form a pad row, and a plurality of pad rows may be arranged along the third direction. Accordingly, in response to the arrangement of the pads 260 , the channel 235 , the dielectric film structure 230 , and the first buried film pattern 240 are formed in plurality along the second direction to form a channel row. can be formed. In addition, a plurality of the channel rows may be arranged along the third direction.

The gate lines 270 are disposed on the cell region I of the substrate 100 , are formed on the outer wall of the dielectric layer structure 230 , and may be stacked to be spaced apart from each other in the first direction. In example embodiments, each gate line 270 may extend along the second direction while partially surrounding the channels 235 included in the plurality of channel rows.

As shown in FIG. 1 , one gate line 270 may extend to surround the channel rows formed to correspond to, for example, four pad rows. In this case, a gate line structure may be defined by the four channel rows and the gate lines 270 surrounding the same.

The gate line 270 may include a metal or a metal nitride. For example, the gate line 270 may include a metal having a low electrical resistance, such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, platinum, or a metal nitride. According to an embodiment, the gate line 270 may have a multilayer structure in which a barrier layer including a metal nitride and a metal layer including a metal are stacked.

For example, the lowermost gate line 270a may serve as a Ground Selection Line (GSL), and the uppermost gate line 270d may be a String Selection Line (SSL). can be provided as The gate lines 270b and 270c disposed between the GSL and the SSL may be provided as word lines.

In this case, the GSL, the word line, and the SSL may be disposed over one layer, two layers, and one layer, respectively, but is not limited thereto. For example, the GSL and SSL each have a one-layer or two-layer structure, and the word line has 4, 8, or 16 or more layers (eg, 2 x n layers, n is 8). It may have a structure of more than one integer). The number of stacked gate lines 270 may be determined in consideration of a circuit design design and/or the degree of integration of the vertical memory device.

Meanwhile, when the above-described semiconductor pattern is disposed between the channel 235 and the substrate 100 , the GSL 270a may extend while surrounding the outer wall of the semiconductor pattern. In this case, a gate insulating layer (not shown) may be further formed between the GSL 270a and the outer wall of the semiconductor pattern.

1 and 2 , the gate lines 270 are stacked in a shape in which the length or width in the second direction decreases as the distance from the top surface of the substrate 100 in the first direction increases. can In example embodiments, the plurality of gate lines 270 may be stacked in a pyramid shape or a step shape along the first direction. Accordingly, a stepped stacked structure may be formed by the gate lines 270 and the interlayer insulating layer patterns 206 .

Interlayer insulating layer patterns 206 may be provided between the gate lines 270 adjacent in the first direction. The interlayer insulating layer pattern 206 may include an _{oxide-based material such as silicon oxide (SiO 2} ), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF). The gate lines 270 included in the one gate line structure may be insulated from each other by the interlayer insulating layer patterns 206 . In example embodiments, the interlayer insulating layer patterns 206 may be stacked along the first direction in a pyramid shape or a step shape substantially the same as or similar to the gate lines 270 .

3 , a separation layer pattern 275 may be formed between the gate line structures adjacent in the third direction. For example, a plurality of separation layer patterns 275 are disposed along the third direction to separate the gate lines 270 and the interlayer insulating layer patterns 206 , and a plurality of the gates extending in the second direction. Line structures can be defined. In this case, the separation layer pattern 270 may extend along the second direction and function as a gate line cut pattern. The separator pattern 275 may include an insulating material such as silicon oxide.

3 , a second impurity region 105 may be formed on the substrate 100 adjacent to the separation layer pattern 275 . The second impurity region 105 may extend in the second direction and may serve as a common source line (CSL) of the vertical memory device. The second impurity region 105 may include, for example, an n-type impurity such as phosphorus or arsenic. Although not shown, a metal silicide pattern such as a cobalt silicide pattern or a nickel silicide pattern may be formed on the second impurity region 105 .

The mold protection layer 210 is formed over the cell region I, the blocking region II, and the peripheral circuit region III of the substrate 100 , and may cover the side of the step-type stacked structure. The mold protective layer 210 may include, for example, an insulating material such as silicon oxide.

An upper insulating layer 280 may be formed on the uppermost interlayer insulating layer pattern 206e , the pad 260 , the separation layer pattern 275 , and the mold protection layer 210 . The upper insulating layer 280 may include, for example, an insulating material such as silicon oxide.

In example embodiments, the pads 260 may be protected by the upper insulating layer 280 . Wiring structures such as bit lines may be disposed on the upper insulating layer 280 .

A peripheral circuit of the vertical memory device may be disposed on the peripheral circuit region III of the substrate 100 . The peripheral circuit may include, for example, a transistor. The peripheral circuit may be covered by the peripheral circuit passivation layer 152 .

For example, the gate structure 140 in which the gate insulating layer pattern 110 , the gate electrode 120 , and the gate mask 130 are stacked may be disposed on the peripheral circuit region III of the substrate 100 . A first impurity region 103 may be formed on the substrate 100 adjacent to the gate structure 140 . The transistor may be defined by the gate structure 140 and the first impurity region 103 . In this case, the first impurity region 103 may serve as a source/drain region of the transistor. have. In an embodiment, a gate spacer 150 to cover a sidewall of the gate structure 140 may be further formed.

The peripheral circuit passivation layer 152 may be formed on the peripheral circuit region III of the substrate 100 to cover the gate structure 140 , the gate spacer 150 , and the first impurity region 103 . Accordingly, the peripheral circuit may be protected by the peripheral circuit passivation layer 152 .

A blocking structure 250 may be disposed on the blocking region II of the substrate 100 . According to example embodiments, the blocking structure 250 may have a dam shape or a fence shape that penetrates the mold protective layer 210 in the first direction and extends along at least the third direction. can In example embodiments, the blocking structure 250 may have a shape that continuously surrounds the cell region I in the second and third directions. For example, the blocking structure 250 may be formed in the form of a fence that continuously surrounds the cell region I.

In example embodiments, the blocking structure 250 may have a structure in which a dummy dielectric layer 232 , a dummy channel 237 , and a second buried layer pattern 242 are sequentially stacked. The dummy dielectric layer 232 , the dummy channel 237 , and the second buried layer pattern 242 are substantially the same as the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 formed on the cell region I . may contain the same material.

In example embodiments, thermal and/or mechanical stress transferred from the cell region I to the peripheral circuit region III may be blocked by the blocking structure 250 .

For example, a deposition process performed at a high temperature to form the dielectric layer structure 230 , the channel 235 , and the like on the cell region I may be performed. Accordingly, thermal stress may be generated from the deposition process. Also, as a plurality of gate lines 270 and interlayer insulating layer patterns 206 are repeatedly stacked on the cell region I, mechanical stress may occur. When the thermal and/or mechanical stress is excessively accumulated on the cell region I, it may propagate to the peripheral circuit region III and cause a defect in the peripheral circuit. For example, a phenomenon such as a crack, chemical structure change, or dislocation of a portion of the substrate 100 and the gate structure 140 provided as an active region in the peripheral circuit region III may occur. Accordingly, an error in applying and transmitting an electrical signal through the peripheral circuit may occur, thereby deteriorating the operational reliability of the vertical memory device.

However, according to exemplary embodiments, since the blocking structure 250 is interposed between the cell region I and the peripheral circuit region III, transmission and/or diffusion of the thermal and/or mechanical stress may be suppressed. . Accordingly, structural stability and operational reliability in the peripheral circuit region III may be improved.

4 to 17B are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device according to example embodiments. For example, FIGS. 4 to 17B are diagrams for explaining a method of manufacturing the vertical memory device illustrated in FIGS. 1 to 3 .

Specifically, FIGS. 7A, 11A, 14A, and 17A are plan views illustrating a method of manufacturing the vertical memory device. 4 to 6, 7B, 8 to 10, 11B, 12, 13, 15A, and 16A are the lines I-I' shown in FIGS. 7A, 11A, 14A and 17A. are cross-sectional views taken along the first direction. 14B, 15B, 16B, and 17B are cross-sectional views taken along the line II-II' shown in FIGS. 7A, 11A, 14A and 17A in the first direction.

Referring to FIG. 4 , the gate structure 140 and the first impurity region 103 are formed on the substrate 100 .

As the substrate 100 , a semiconductor substrate including a semiconductor material such as single crystal silicon, single crystal germanium, or the like may be used. In addition, the substrate 100 may be divided into a cell region (I), a blocking region (II), and a peripheral circuit region (III). The gate structure 140 and the first impurity region 103 may be formed on the peripheral circuit region III of the substrate 100 .

For example, a gate insulating layer, a gate electrode layer, and a gate mask layer may be sequentially formed on the substrate 100 . The gate mask layer is partially etched to form a gate mask 130, and the gate electrode layer and the gate insulating layer are etched using the gate mask 130 as an etch mask to form a gate electrode 120 and a gate insulating layer pattern ( 110) can be formed. Accordingly, the gate structure 140 including the gate insulating layer pattern 110 , the gate electrode 120 , and the gate mask 130 sequentially stacked on the substrate 100 may be formed.

The gate insulating layer may be formed using silicon oxide or metal oxide. The gate electrode layer may be formed using metal, metal nitride, or doped polysilicon. The gate mask layer may be formed using silicon nitride. The gate insulating layer, the gate electrode layer, or the gate mask layer may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, and a high-density plasma-chemical vapor deposition process, respectively. It may be formed using at least one of a High Density Plasma Chemical Vapor Deposition (HDP-CVD) process, an atomic layer deposition (ALD) process, and a sputtering process. The gate insulating layer may be formed by performing a thermal oxidation process on the upper surface of the substrate 100 .

The first impurity region 103 may be formed on the substrate 100 in the peripheral circuit region III adjacent to the gate structure 140 through an ion implantation process using the gate structure 140 as an ion implantation mask. A transistor disposed in the peripheral circuit region III may be defined by the gate structure 140 and the first impurity region 103 .

In an embodiment, after forming the spacer layer covering the gate structure 140 on the substrate 100 , the spacer layer is anisotropically etched to further form the gate spacer 150 covering the sidewall of the gate structure 140 . can

Thereafter, a peripheral circuit protection layer 152 to protect the transistor may be further formed. For example, after forming a passivation layer covering the first impurity region 103 , the gate structure 140 , and the gate spacer 150 on the substrate 100 , the cell region I and the blocking region II are formed on the substrate 100 . A portion of the formed passivation layer may be removed to form a peripheral circuit passivation layer 152 . The passivation layer may be formed of an oxide layer.

Referring to FIG. 5 , interlayer insulating layers 202 and sacrificial layers 204 are alternately and repeatedly stacked on a substrate 100 to form a mold structure.

In example embodiments, the interlayer insulating layers 202 may be formed using an oxide-based material such as silicon oxide, silicon carbonate, or silicon oxyfluoride. The sacrificial layers 204 have an etch selectivity with respect to the interlayer insulating layer 202 and may be formed using a material that can be easily removed by a wet etching process. For example, the sacrificial layers 204 may be formed using a nitride-based material such as silicon nitride (SiN) or silicon boron nitride (SiBN).

The interlayer insulating layers 202 and the sacrificial layers 204 may be formed through a CVD process, a PECVD process, a spin coating process, or the like. In an embodiment, the lowermost interlayer insulating layer 202a may be formed by performing a thermal oxidation process on the upper surface of the substrate 100 . In this case, the lowermost interlayer insulating layer 202a may be formed to have a thinner thickness than other interlayer insulating layers 202b, 202c, 202d, and 202e.

The sacrificial layers 204 may be removed through a subsequent process to provide a space in which the GSL, the word line, and the SSL are formed. Accordingly, the number of the interlayer insulating layers 202 and the sacrificial layers 204 stacked may vary depending on the stacked number of the GSL, word line, and SSL to be formed later. For example, the GSL and SSL may each be formed in one layer, and the word line may be formed in two layers. In this case, as shown in FIG. 5 , all of the sacrificial layers 204 may be stacked in four layers, and the interlayer insulating layers 202 may be stacked in all five layers. However, the number of the interlayer insulating layers 202 and the sacrificial layers 204 stacked is not particularly limited. For example, the GSL and SSL may each be formed in two layers, and the word line may be formed in four, eight, or 16 layers. In this case, all of the sacrificial layers 204 may be formed of 8, 12, or 20 layers, and all of the interlayer insulating layers 202 may be formed of 9, 13, or 21 layers. The word line may be formed of 16 or more layers, for example, 2 x n layers (n is an integer of 8 or more).

Referring to FIG. 6 , the interlayer insulating layers 202 and the sacrificial layers 204 may be partially etched to form a stepped mold structure 205 .

According to example embodiments, a photoresist pattern (not shown) partially covering the interlayer insulating layer 202e is formed on the uppermost interlayer insulating layer 202e, and the photoresist pattern is used as an etch mask to form an interlayer Both ends of the insulating layers 202e, 202d, 202c, and 202b and the sacrificial layers 204d, 204c, 204b, and 204a may be etched. Thereafter, both ends of the photoresist pattern are partially removed to reduce the width of the photoresist pattern, and then the interlayer insulating layers 202e, 202d, and 202c and the sacrificial layers 204d, 204c, and 204b are used again as an etch mask. ) is etched at both ends. In a similar manner, the step-shaped mold structure 205 as shown in FIG. 6 may be formed by repeating the etching process.

In example embodiments, portions of the interlayer insulating layers 202 and the sacrificial layers 204 formed on the blocking region II and the peripheral circuit region III may be substantially removed. During the etching process for forming the stepped mold structure 205 , the transistor formed on the peripheral circuit region III may be protected by the peripheral circuit passivation layer 152 .

In an embodiment, during the etching process, a portion of the lowermost interlayer insulating layer 202a formed on the blocking region II may remain substantially unetched.

After forming the step-shaped mold structure 205 , a mold protection layer 210 covering the sides or steps of the step-shaped mold structure 205 may be formed on the substrate 200 . For example, an insulating layer covering the stepped mold structure 205 is formed on the substrate 200 through a CVD process or a spin coating process using an insulating material such as silicon oxide. Then, the uppermost insulating layer 202e may be planarized until the uppermost insulating layer 202e is exposed to form the mold protective layer 210 . The planarization process may include a chemical mechanical polishing (CMP) process and/or an etch-back process.

In an embodiment, the mold protective layer 210 may be formed using a material substantially the same as or similar to that of the interlayer insulating layers 202 . In this case, the mold protective layer 210 may be substantially merged with or integrated with the interlayer insulating layers 202 .

7A and 7B , a plurality of channel holes 215 penetrating through the stepped mold structure 205 and a first opening 217 penetrating the mold passivation layer 210 are formed.

According to example embodiments, a hard mask (not shown) is formed on the uppermost interlayer insulating layer 202e and the mold protective layer 210 , and a step type is performed through a dry etching process using the hard mask as an etching mask. A channel hole 215 may be formed by etching the interlayer insulating layers 202 and the sacrificial layers 204 of the mold structure 205 . The channel hole 215 may extend from the upper surface of the substrate 200 in the first direction, and the upper surface of the substrate 200 may be exposed by the channel hole 215 . The hard mask may be formed using, for example, a silicon-based or carbon-based spin-on hard mask (SOH) material or a photoresist material.

7A , a plurality of channel holes 215 may be formed along the second direction to define a channel hole row, and a plurality of channel hole rows may be formed along the third direction. have.

The channel hole rows may be formed such that the channel holes 215 are arranged in a zig-zag shape along the third direction. In example embodiments, the channel holes 215 may be formed on the cell region I of the substrate 100 .

A first opening 217 may be formed on the blocking region II defined between the cell region I and the peripheral circuit region III. In example embodiments, the first opening 217 may be formed substantially simultaneously with the channel hole 215 through the dry etching process for forming the channel hole 215 .

As shown in FIG. 7B , the first opening 217 may pass through the mold protection layer 210 in the first direction, and the upper surface of the substrate 100 may be exposed by the first opening 217 . have. Also, as shown in FIG. 7A , the first opening 217 may have a trench shape or a trench shape extending along the third direction. According to an exemplary embodiment, the first opening 217 may be formed to surround the cell region I and extend in the second and third directions. For example, the first opening 217 may be formed in the form of a fence that continuously surrounds the cell region I.

After the channel hole 215 and the first opening 217 are formed, the hard mask may be removed through an ashing and/or a strip process.

Referring to FIG. 8 , a dielectric layer 220 is formed on the sidewalls and bottom surfaces of the channel holes 215 and the first opening 217 , and the uppermost interlayer insulating layer 202e and the mold protection layer 210 .

According to exemplary embodiments, although not specifically illustrated, the dielectric layer 220 may be formed by sequentially stacking a blocking layer, a charge storage layer, and a tunnel insulating layer. The blocking film may be formed using an oxide such as silicon oxide, the charge storage film may be formed using a nitride such as silicon nitride or a metal oxide, and the tunnel insulating film may be formed using an oxide such as silicon oxide. can According to example embodiments, the dielectric layer 220 may be formed to have an ONO structure. The blocking layer, the charge storage layer, and the tunnel insulating layer may be formed using a CVD process, a PECVD process, or an ALD process, respectively.

Referring to FIG. 9 , a portion of the dielectric layer 220 formed on the bottom surface of the channel hole 215 may be partially etched through, for example, an etch-back process to expose the upper surface of the substrate 100 . A portion of the dielectric layer 220 formed on the uppermost interlayer insulating layer 202e and the mold protection layer 210 may also be substantially removed by the etch-back process. Accordingly, the dielectric layer structure 230 may be formed on the sidewall of the channel hole 215 . The dielectric film structure 230 may have a cylindrical shape or a straw shape in which a bottom center portion is drilled in the channel hole 215 .

A portion of the dielectric layer 220 formed on the bottom surface of the first opening 217 by the etch-back process may also be removed. Accordingly, a dummy dielectric layer 232 may be formed on the sidewall of the first opening 217 .

Referring to FIG. 10 , on the top surface of the substrate 100 exposed by the uppermost interlayer insulating film 202e , the dielectric film structure 230 , the dummy dielectric film 232 , and the channel hole 215 and the first opening 217 . A channel layer 225 may be formed on the upper surface of the junction layer 225 , and a first buried layer 227 filling the remaining portions of the channel hole 215 and the first opening 217 may be formed on the channel layer 225 . In example embodiments, the channel layer 225 may be formed using doped or undoped polysilicon or amorphous silicon. Meanwhile, after forming the channel layer 225 using polysilicon or amorphous silicon, it may be converted into single crystal silicon by heat treatment or laser beam irradiation. When amorphous silicon or polysilicon is converted to single crystal silicon, defects in the channel layer 225 are removed, thereby improving the function of the channel 235 (refer to FIGS. 11A and 11B ). The first buried layer 227 may be formed using an insulating material such as silicon oxide or silicon nitride.

The channel layer 225 and the first buried layer 227 may be formed using, for example, a CVD process, a PECVD process, a spin coating process, a PVD process, or an ALD process.

11A and 11B , the first buried layer 227 and the channel layer 225 may be planarized through, for example, a CMP process until the top surface of the uppermost interlayer insulating layer 202e is exposed. Accordingly, the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 may be sequentially stacked from the sidewall of the channel hole 215 to fill the inside of the channel hole 215 . As the channel 235 is formed in the channel hole 215 , a channel row in which a plurality of the channels are arranged to correspond to the channel hole row may be formed.

Also, a dummy dielectric layer 232 , a dummy channel 237 , and a second buried layer pattern 242 may be sequentially stacked from the sidewall of the first opening 250 to fill the inside of the first opening 217 . Accordingly, the blocking structure 250 including the dummy dielectric layer 232 , the dummy channel 237 , and the second buried layer pattern 242 may be formed inside the first opening 217 .

The channel 235 may have a cup shape, and the first buried layer pattern 240 may have a solid cylindrical shape or a pillar shape. The dielectric layer structure 230 may have a structure in which the tunnel insulating layer, the charge storage layer, and the blocking layer are stacked from the outer wall of the channel 235 .

The blocking structure 250 may have a dam shape or a fence shape extending along the third direction, and may be disposed between the cell region I and the peripheral circuit region III to form a boundary. According to some embodiments, the blocking structure 250 may be formed to surround the cell region I and extend along the second and third directions. For example, the blocking structure 250 may be formed in the form of a fence that continuously surrounds the cell region I.

In an embodiment, when the channel layer 225 is formed to completely fill the channel hole 215 , the first buried layer pattern 240 is not formed, and the channel 235 has a solid cylindrical shape or a pillar shape. can have In this case, the second buried layer pattern 242 may also be omitted, and the dummy channel 237 may fill the remaining portion of the first opening 217 .

In one embodiment, after forming the channel hole 215 shown in FIGS. 7A and 7B , a semiconductor pattern (not shown) filling the bottom of the channel hole 215 is formed before the dielectric layer 220 and the channel layer 225 are formed. can also be formed. The semiconductor pattern may be formed by performing a selective epitaxial growth (SEG) process using the upper surface of the substrate 100 as a seed. Accordingly, the semiconductor pattern may include polysilicon or single crystal silicon. Alternatively, after forming an amorphous silicon film filling the bottom of the channel hole 215, a laser epitaxial growth (LEG) process or a solid phase epitaxi (SPE) process is performed on the amorphous silicon film. This may be performed to form the semiconductor pattern. In this case, the dielectric layer structure 230 and the channel 235 may be formed on the top surface of the semiconductor pattern.

In an embodiment, a dummy semiconductor pattern (not shown) may be formed at the bottom of the first opening 217 at substantially the same time as the semiconductor pattern. In this case, the dummy dielectric layer 232 and the dummy channel 237 may be formed on the top surface of the dummy semiconductor pattern.

12 and 13 , a pad 260 filling an upper portion of the channel hole 215 may be formed.

According to example embodiments, as shown in FIG. 12 , the upper portions of the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 are removed through an etch-back process to form a recess. do. Thereafter, a pad film filling the recess is formed on the first buried film pattern 240 , the channel 235 , the dielectric film structure 230 , and the uppermost interlayer insulating film 202e, and the upper surface of the uppermost interlayer insulating film 202e. The pad 260 may be formed by planarizing the upper portion of the pad layer until this is exposed. In example embodiments, the pad layer may be formed using polysilicon or polysilicon doped with n-type impurities, for example. Alternatively, the pad layer may be formed by forming a preliminary pad layer using amorphous silicon and then crystallizing it. The planarization process may include a CMP process.

In one embodiment, as shown in FIG. 13 , the dummy pad 260a filling the upper portion of the first opening 217 may be formed through a process substantially the same as or similar to the formation of the pad 260 , in this case, The dummy pad may be formed substantially simultaneously with the pad 260 and may have a line shape extending in the third direction.

14A and 14B , the second opening 265 is formed by partially etching the mold structure 205 .

The second opening 265 covers the pads 260 and partially exposes the uppermost interlayer insulating layer 202e and the mold protection layer 210 between some of the channel rows adjacent to each other in the third direction. not), and etching the mold protective layer 210 , the interlayer insulating layers 202 , and the sacrificial layers 204 through a dry etching process using the hard mask as an etching mask. The hard mask may be formed using, for example, a photoresist or an SOH material. Also, the hard mask may be removed through an ashing and/or stripping process after the second opening 265 is formed.

In example embodiments, the second opening 265 may extend along the second direction on the cell region I of the substrate 100 . The second opening 265 may not substantially extend to the blocking region II. In an embodiment, the second opening 265 partially extends to the blocking region II, but may not extend to the blocking structure 250 . In an embodiment, the second opening 265 extends to the blocking region II, but may have a shape in which the extension is stopped by the blocking structure 250 .

The mold structure 205 may be cut by the second opening 265 , and thus the predetermined channel rows may be united or grouped. For example, as shown in FIG. 14A , the second opening 265 may be formed such that one channel row group includes four channel rows. However, the number of the channel rows included in the channel row group may be adjusted in consideration of circuit design and the degree of integration of the vertical memory device.

Meanwhile, as the second opening 265 is formed, the interlayer insulating layers 202 and the sacrificial layers 204 may be converted into the interlayer insulating layer patterns 206 and the sacrificial layer patterns 208 , respectively. In this case, the interlayer insulating layer patterns 206 and the sacrificial layer patterns 208 of each layer may extend in the second direction. Also, a top surface of the substrate 100 may be exposed through the second opening 265 , and sidewalls of the interlayer insulating layer pattern 206 and the sacrificial layer pattern 208 may be exposed.

15A and 15B , the sacrificial layer patterns 208 whose sidewalls are exposed by the second opening 265 are removed. In example embodiments, the sacrificial layer pattern 208 may be removed through a wet etching process using an etchant having an etch selectivity to silicon nitride. For example, an acidic solution such as phosphoric acid or sulfuric acid may be used as the etching solution.

When the sacrificial layer patterns 208 are removed, a gap 267 is formed between the interlayer insulating layer patterns 206 of each layer, and the outer wall of the dielectric layer structure 230 is partially exposed by the gap 267 . can be

16A and 16B , gate lines 270 are formed in the gap 267 of each layer. Accordingly, the sacrificial layer 204 or the sacrificial layer pattern 208 of each layer may be replaced with the gate line 270 .

In example embodiments, the gate electrode is along the exposed outer walls of the dielectric film structure 230 , the surfaces of the interlayer insulating film patterns 206 , the exposed upper surface of the substrate 100 , and the upper surface of the pad 260 . form a film The gate electrode layer may be formed to completely fill the gaps 267 and partially fill the second opening 265 . In addition, the gate electrode layer may cover the mold protection layer 210 and the top surface of the blocking structure 250 .

The gate electrode layer may be formed using a metal or a metal nitride. For example, the gate electrode layer may be formed using a metal or a metal nitride having low electrical resistance and work function, such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, platinum, or the like. According to an embodiment, the gate electrode layer may be formed of a multilayer layer in which a barrier layer including a metal nitride and a metal layer including a metal are stacked. The gate electrode layer may be formed using a CVD process, a PECVD process, an ALD process, a PVD process, or a sputtering process.

In one embodiment, before forming the gate electrode film, along the inner walls of the gaps 267 and the surfaces of the interlayer insulating film patterns 206, using, for example, silicon oxide or metal oxide, an additional blocking film (shown) not) can be further formed.

Thereafter, the gate electrode layer is partially removed to form a gate line 270 in the gap 267 of each layer.

For example, an upper portion of the gate electrode layer is planarized through, for example, a CMP process until the uppermost interlayer insulating layer pattern 206e is exposed. Thereafter, the gate lines 270 may be formed by etching a portion of the gate electrode layer formed inside the second opening 265 and on the upper surface of the substrate 100 . The gate electrode layer may be partially etched through _{, for example, a wet etching process including hydrogen peroxide (H 2} O _{2 ).}

The gate lines 270 may include a GSL, a word line, and an SSL formed sequentially spaced apart from the top surface of the substrate 100 in the first direction. For example, the lowermost gate line 270a may serve as the GSL. The gate lines 2700b and 270c of the second layer on the GSL may serve as the word line. The uppermost gate line 270d above the word line may serve as the SSL.

The gate line 270 of each layer surrounds the dielectric layer structure 230 and the channel 235 and may be formed to extend in the second direction. Also, the gate line 180 of each layer may extend to surround a predetermined number of the channel rows, for example, four channel rows. Accordingly, a gate line structure may be defined by the gate lines 270 that surround a predetermined number of the channel rows, extend in the second direction, and are stacked in the first direction.

17A and 17B , a second impurity region 105 is formed on the substrate 100 exposed by the second opening 265 , and a separation layer pattern 275 filling the second opening 265 is formed. can be formed

According to exemplary embodiments, an ion implantation mask (not shown) covering the upper surface of the pad 260 is formed and an n-type impurity such as phosphorus or arsenic is implanted using the ion implantation mask. Two impurity regions 105 may be formed. The second impurity region 105 may serve as a CSL extending in the second direction. In an embodiment, the resistance of the CSL may be lowered by further forming a metal silicide pattern such as a nickel silicide pattern or a cobalt silicide pattern on the second impurity region 105 .

Thereafter, an isolation insulating layer filling the second opening 275 is formed on the second impurity region 105 , the interlayer insulating layer pattern 206 , the pad 260 , and the mold protection layer 210 , and the uppermost insulating layer is formed over the isolation insulating layer. The separation layer pattern 275 may be formed by planarization through an etch-back process and/or a CMP process until the interlayer insulating layer pattern 206e is exposed. The isolation insulating layer may be formed using an insulating material such as silicon oxide.

An upper insulating layer 280 may be formed on the uppermost interlayer insulating layer pattern 206e , the separation layer pattern 275 , the pad 260 , and the mold protection layer 210 . The upper insulating layer 280 may be formed using an insulating material such as silicon oxide through a CVD process or the like. For convenience of description, illustration of the upper insulating layer 280 is omitted in FIG. 17A .

In an embodiment, a wiring structure such as a bit line may be additionally formed on the upper insulating layer 280 .

18 is a cross-sectional view illustrating a vertical memory device according to example embodiments. The vertical memory device illustrated in FIG. 18 may have a structure and/or configuration substantially the same as or similar to the vertical memory device described with reference to FIGS. 1 to 3 , except for the blocking structure. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

Referring to FIG. 18 , an air gap 251 may substantially function as a blocking structure 252 .

In example embodiments, a first opening 264 penetrating through the mold protection layer 210 and extending in the third direction may be formed on the blocking region II of the substrate 100 . A partial filling layer 281b partially filling the first opening 264 may be formed inside the first opening 264 , and an air gap 251 may be formed inside the partial filling layer 281b .

According to exemplary embodiments, the partial filling layer 281b may be substantially merged with or integrally connected to the upper insulating layer 281a. For example, the partial filling layer 281b may be formed by partially filling the first opening 264 together while the upper insulating layer 281a is formed on the mold protection layer 210 .

The upper insulating layer 281a and the partial filling layer 281b may include silicon oxide such as TetraEthyl OrthoSilicate (TEOS) or CVD oxide having low burying characteristics and/or conformal characteristics. Accordingly, as the upper insulating layer 281a overhangs at the entrance of the first opening 264 , an air gap 251 may be formed in the first opening 264 . The partial filling layer 281b may be formed along sidewalls of the first opening 264 while filling the bottom of the first opening 264 .

According to exemplary embodiments, since the blocking structure 252 includes the air gap 251 , a medium through which stress is transferred from the cell region I to the peripheral circuit region III may be removed. Accordingly, it is possible to more effectively block the stress transfer to the peripheral circuit region III.

19 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device according to example embodiments. For example, FIGS. 19 to 24 illustrate a method of manufacturing the vertical memory device shown in FIG. 18 .

Specifically, FIGS. 22A and 23A are plan views illustrating a method of manufacturing the vertical memory device. 19 to 21 , 22B, 23B and 24 are cross-sectional views taken along the first direction along the line II′ shown in FIGS. 22A and 23A .

Meanwhile, detailed descriptions of processes and/or materials substantially the same as or similar to the processes and/or materials described with reference to FIGS. 4 to 17B will be omitted.

Referring to FIG. 19 , processes substantially the same as or similar to those described with reference to FIGS. 4 to 6 are performed to form the gate structure 140 and the first impurity region ( 103 , and a mold structure 205 may be formed on the cell region I . Thereafter, the mold protection layer 210 covering the side of the mold structure 205 may be formed on the cell region I, the blocking region II, and the peripheral circuit region III of the substrate 100 .

Referring to FIG. 20 , a process substantially similar to the process described with reference to FIGS. 7A and 7B may be performed to form a plurality of channel holes 215 penetrating the mold structure 205 . In this case, the first opening 217 shown in FIGS. 7A and 7B may not be formed.

Referring to FIG. 21 , processes substantially the same as or similar to those described with reference to FIGS. 8 to 12 may be performed. Accordingly, the dielectric film structure 230 filling the channel hole 215 , the channel 235 , and the first buried film pattern 240 may be formed, and the pad 260 capping the upper portion of the channel hole 215 may be formed. have.

22A and 22B , processes substantially the same as or similar to those described with reference to FIGS. 14A to 17B may be performed. Accordingly, the second opening 265 (see FIGS. 14A and 14B ) for cutting the gate line may be formed, and the sacrificial layers 204a may be replaced with the gate lines 270 . Thereafter, a second impurity region 105 (refer to FIG. 17B ) is formed on the substrate 100 exposed through the second opening 265 , and then a separation layer pattern 275 filling the second opening 265 is formed. can do.

23A and 23B , a first opening 264 passing through the mold protection layer 210 may be formed on the blocking region II of the substrate 100 .

In example embodiments, a hard mask (not shown) that covers the cell region I and the peripheral circuit region III of the substrate 100 and exposes a portion of the mold protection layer 210 of the blocking region II ) can be formed. The first opening 264 may be formed by partially etching the mold protective layer 210 using the hard mask as an etching mask.

The first opening 264 may have a trench or trench shape extending in the third direction. Also, the first opening 264 illustrated in FIGS. 23A and 23B may have a smaller width than the first opening 217 illustrated in FIGS. 7A and 7B . According to an exemplary embodiment, the first opening 264 may be formed to surround the cell region I and extend in the second and third directions. For example, the first opening 264 may be formed in the form of a fence that continuously surrounds the cell region I.

Referring to FIG. 24 , an upper insulating layer 281a may be formed on the uppermost interlayer insulating layer pattern 206e , the separation layer pattern 275 , the pads 260 , and the mold protection layer 210 .

According to example embodiments, the upper insulating layer 281a may be formed using a material and process conditions having low filling characteristics and/or conformal characteristics. For example, the upper insulating layer 281a may be formed by using a silicon oxide such as TEOS or CVD oxide, and using a CVD process or a spin coating process having a relatively low buried characteristic.

Accordingly, the upper insulating layer 281a may overhang at the entrance of the first opening 264 , and an air gap 251 may be formed inside the first opening 264 . In an embodiment, as shown in FIG. 26 , a portion of the upper insulating layer 281a may extend into the first opening 264 to form a partial filling layer 281b. The partial filling layer 281b may be formed along sidewalls of the first opening 264 while filling the bottom of the first opening 264 .

Accordingly, the blocking structure 252 including the partial filling layer 281b and the air gap 251 is formed inside the first opening 264 , and the vertical memory device shown in FIG. 18 may be manufactured.

25 and 26 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments. The vertical memory device shown in FIGS. 25 and 26 may have a structure and/or configuration substantially the same as or similar to the vertical memory device shown in FIGS. 1 to 3 , except for the blocking structure. Accordingly, a detailed description of the overlapping structure and/or components will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

25 and 26 , in the vertical memory device, a plurality of dummy channel structures 250a may be disposed on the blocking region II.

The dummy channel structure 250a may include a dummy dielectric layer structure 232a , a dummy channel 237a , and a second buried layer pattern 242a stacked inside the dummy channel hole 216 . A dummy pad 261 capping an upper portion of the dummy channel hole 216 may be formed on the dummy dielectric layer structure 232a, the dummy channel 237a, and the second buried layer pattern 242a.

In example embodiments, the dummy channel hole 216 may have a shape substantially the same as or similar to that of the channel hole 215 formed in the cell region I. In addition, the dummy dielectric film structure 232a, the dummy channel 237a, the second buried film pattern 242a, and the dummy pad 261 each have a dielectric film structure 230, a channel 235, The structure and shape may be substantially the same as or similar to those of the first buried layer pattern 240 and the pad 260 .

25 , a plurality of dummy channel structures 250a may be disposed along the third direction to form a dummy channel column. Also, the plurality of dummy channel columns may be disposed along the second direction. Accordingly, the blocking structure 253 including one or more of the dummy channel columns may be disposed on the blocking region II of the substrate 100 to block the stress propagation of the peripheral circuit region II in the cell region I. . In FIG. 27 , the blocking structure 253 is illustrated to include the two dummy channel columns, but the blocking structure 253 may include three or more dummy channel columns.

In example embodiments, the plurality of dummy channel columns may be arranged such that dummy channel structures 250a belonging to different dummy channel columns are shifted from each other, for example, arranged in a zig-zag form. Accordingly, the density of the dummy channel structures 250a in the blocking region II is increased, so that the stress propagation can be more effectively blocked.

27 to 29B are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to example embodiments. For example, FIGS. 27 to 29B are diagrams for explaining a method of manufacturing the vertical memory device shown in FIGS. 25 and 26 .

Specifically, FIGS. 28A and 29A are plan views illustrating a method of manufacturing the vertical memory device. 27, 28B, and 29B are cross-sectional views taken in the first direction along the line I-I' shown in FIGS. 28A and 29A.

Meanwhile, detailed descriptions of processes and/or materials substantially the same as or similar to the processes and/or materials described with reference to FIGS. 4 to 17B will be omitted.

Referring to FIG. 27 , processes substantially the same as or similar to those described with reference to FIGS. 4 to 6 are performed to form the gate structure 140 and the gate spacer 150 on the peripheral circuit region III of the substrate 100 . And the first impurity region 103 and the peripheral circuit protection layer 152 covering the first impurity region 103 may be formed, and the mold structure 205 may be formed on the cell region I. Thereafter, a mold protection layer 210 covering the side of the mold structure 205 may be formed on the cell region I, the blocking region II, and the peripheral circuit region III of the substrate 100 .

28A and 28B , a plurality of channel holes 215 penetrating through the mold structure 205 in the cell region I by performing a process substantially the same as or similar to the process described with reference to FIGS. 7A and 7B . ) and the blocking region II, a plurality of dummy channel holes 216 penetrating the mold passivation layer 210 may be formed.

28A , in the cell region I, a plurality of channel holes 215 are formed along the second direction to form a row of channel holes, and a plurality of rows of the channel holes are formed along the third direction. can be formed. A plurality of dummy channel holes 216 may be formed in the third direction on the blocking region II to form a dummy channel hole column, and a plurality of dummy channel hole columns may be formed along the second direction.

According to example embodiments, the channel hole 215 and the dummy channel hole 216 may have substantially the same or similar shapes, and may be formed substantially simultaneously by an etching process using a single mask.

29A and 29B , processes substantially the same as or similar to those described with reference to FIGS. 8 to 13 may be performed. Accordingly, the dielectric film structure 230 , the channel 235 , and the first buried film pattern 240 are formed inside the channel hole 215 , and the pad 260 capping the upper portion of the channel hole 215 may be formed. have. A dummy dielectric layer structure 232a , a dummy channel 237a , and a second buried layer pattern 242a are formed inside the dummy channel hole 216 , and a dummy pad 261 capping the upper portion of the dummy channel hole 216 is formed. can be Accordingly, a dummy channel structure 250a including a dummy dielectric layer structure 232a , a dummy channel 237a , a second buried layer pattern 242a , and a dummy pad 261 may be formed inside the dummy channel hole 216 . have.

29A , a plurality of dummy channel structures 250a may be arranged in the third direction on the blocking region II to form a dummy channel column. In addition, one or more of the dummy channel columns may be formed to form the blocking structure 253 . According to an exemplary embodiment, a plurality of dummy channel structures 250a may be arranged along the second and third directions to form a plurality of dummy channel columns and rows. In this case, a blocking structure 253 may be formed in which one or more of the dummy channel columns and rows surround the cell region I in the form of, for example, a fence.

Thereafter, the vertical memory device illustrated in FIGS. 25 and 26 may be manufactured by performing processes substantially the same as or similar to those described with reference to FIGS. 14A to 17B .

For example, the sacrificial layers 204 may be replaced with the gate lines 270 , and a separation layer pattern 275 (refer to FIGS. 17A and 17B ) for separating the gate line structures may be formed. In addition, an upper insulating layer 280 (refer to FIG. 17B ) may be formed on the gate line structure, the mold protection layer 210 , and the blocking structure 253 .

30 to 32 are plan views and cross-sectional views illustrating vertical memory devices according to example embodiments. Specifically, FIG. 30 is a plan view illustrating the vertical memory device. 31 and 32 are cross-sectional views taken along lines II' and II-II' of FIG. 30, respectively.

The vertical memory device illustrated in FIGS. 30 to 32 may have a structure and/or configuration substantially the same as or similar to that of the vertical memory device described with reference to FIGS. 1 to 3 , except for a separator pattern and a blocking structure. . Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

Meanwhile, illustration of the upper insulating layer is omitted in FIG. 30 for convenience of description.

30 to 32 , in the cell region I, on the sidewall of the second opening 265 serving as a gate line cut region for defining the gate line structures, a separation layer for insulating the adjacent gate line structures A pattern 271 may be formed. CSL lines 273 filling the remaining portion of the second opening 265 may be formed on sidewalls of the separation layer pattern 271 . The CSL line 273 may have a shape sandwiched by the separator patterns 271 inside the second opening 265 .

32 , the CSL line 273 may contact the second impurity region 105 formed on the substrate 100 . In an embodiment, a metal silicide pattern may be further formed between the CSL line 273 and the second impurity region 105 to reduce a contact resistance between the CSL line 273 and the second impurity region 105 . .

A first opening 217 penetrating through the mold protection layer 210 and extending in the third direction is formed on the blocking region II, and a dummy separator pattern 271a and a dummy conductive line are formed inside the first opening 217 . A blocking structure 254 including 273a may be disposed.

The dummy separator pattern 271a is formed on the sidewall of the first opening 217 , and the dummy conductive line 273a is formed on the sidewalls of the dummy separator pattern 271a to form the remaining portion of the first opening 217 . can be filled The dummy separator pattern 271a and the dummy conductive line 273a may have a dam shape or a fence shape extending in the third direction. According to an exemplary embodiment, the blocking structure 254 may extend along the second and third directions. For example, the blocking structure 254 may have a fence shape surrounding the cell region I.

In example embodiments, the dummy separator pattern 271a may include substantially the same material as the separator pattern 271 . For example, the separator pattern 271 and the dummy separator pattern 271a may include the same silicon oxide.

In example embodiments, the CSL line 273 and the dummy conductive line 273a may include substantially the same conductive material. For example, the CSL line 273 and the dummy conductive line 273a may include substantially the same metal, metal nitride, or doped polysilicon. In an embodiment, the CSL line 273 and the dummy conductive line 273a may include tungsten (W).

In example embodiments, the dummy conductive line 273a of the blocking structure 254 may include a flexible conductive material such as tungsten. Accordingly, stress generated from the cell region I can be absorbed or more effectively alleviated.

33 to 36C are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to example embodiments. For example, FIGS. 33 to 36C are views for explaining a method of manufacturing the vertical device shown in FIGS. 30 to 32 . Specifically, FIGS. 34A and 36A are plan views illustrating a method of manufacturing the vertical memory device. 33, 34B, 35A, and 36B are cross-sectional views taken along the line I-I' shown in FIGS. 34A and 36A in the first direction. 34C, 35B, and 36C are cross-sectional views taken along the line II-II' shown in FIGS. 34A and 36A in the first direction.

Meanwhile, detailed descriptions of processes and/or materials substantially the same as or similar to the processes and/or materials described with reference to FIGS. 4 to 17C, 19 to 24, or 27 to 29B will be omitted.

Referring to FIG. 33 , processes substantially the same as or similar to those described with reference to FIGS. 19 to 21 may be performed. Accordingly, the gate structure 140 , the gate spacer 150 , the impurity region 103 , and the peripheral circuit protection layer 152 may be formed on the peripheral circuit region III of the substrate 100 . A mold structure 205 may be formed on the cell region I of the substrate 100 , and a mold protection layer 210 covering a side of the mold structure 205 may be formed. Thereafter, a plurality of channel holes 215 passing through the mold structure 205 are formed, and a dielectric film structure 230 , a channel 235 , a first buried film pattern 240 , and a pad are formed in the channel hole 215 . 260) can be formed.

34A to 34C , a process substantially the same as or similar to the process described with reference to FIGS. 14A and 14B is performed to penetrate the mold structure 205 on the cell region I and extend along the second direction second openings 265 may be formed. In example embodiments, a first opening 217 extending in the third direction through the mold passivation layer 210 may be formed on the blocking region II. The upper surface of the substrate 100 may be exposed through the first and second openings 217 and 265 .

In example embodiments, the first and second openings 217 and 265 may be formed by substantially the same etching process using a single mask. In this case, the first and second openings 217 and 265 may be formed substantially simultaneously.

35A and 35B , the sacrificial layer patterns 208 of each layer are replaced with gate lines 270 by performing processes substantially the same as or similar to those described with reference to FIGS. 15A to 16B . can do.

36A to 36C , a blocking structure 254 including a dummy separator pattern 271a and a dummy conductive line 273a is formed inside the first opening 217 , and the blocking structure 254 is formed inside the second opening 265 . A separation layer pattern 271 and a CSL line 273 may be formed.

In example embodiments, the second impurity region 105 may be formed by implanting impurities into the upper portion of the substrate 100 exposed by the second opening 265 . Separation insulating layers are formed on the uppermost layer of the interlayer insulating layer pattern 206e and the top surface of the mold protective layer 210 , and sidewalls and bottom surfaces of the first and second openings 217 and 265 , and first and A portion of the isolation insulating layer formed on the bottom surfaces of the second openings 217 and 265 may be removed. Accordingly, the upper surface of the substrate 100 may be exposed again by the first and second openings 217 and 265 . A conductive layer filling the remaining portions of the first and second openings 217 and 265 may be formed on the isolation insulating layer and the upper surface of the substrate 100 . The upper portions of the insulating insulating layer and the conductive layer are planarized through, for example, a CMP process until the uppermost surface of the uppermost interlayer insulating layer pattern 206e and the mold protective layer 210 is exposed, and the dummy separation layer pattern 271a, the dummy A conductive line 273a , a separation layer pattern 271 , and a CSL line 273 may be formed.

In example embodiments, the conductive layer may be formed through an ALD process or a sputtering process using metal, metal nitride, or doped polysilicon. In an embodiment, the conductive layer may be formed using a metal having a ductility, for example, tungsten. Thereafter, the uppermost interlayer insulating layer pattern 206e, the pad 260, the mold protection layer 210, the dummy separator pattern 271a, the dummy conductive line 273a, the separator pattern 271 and the CSL line 273 are formed on the uppermost layer. An insulating layer 280 may be formed. Accordingly, the vertical memory device shown in FIGS. 30 to 32 may be manufactured.

37 and 38 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments. Specifically, FIG. 38 is a cross-sectional view taken along line I-I' of FIG. 37 . The vertical memory device may have substantially the same or similar structure and/or configuration to that of the vertical memory device described with reference to FIGS. 1 to 3 or 30 to 32 , except for the blocking structure. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

Meanwhile, illustration of the upper insulating layer is omitted in FIG. 37 for convenience of description.

37 and 38 , a first blocking structure 252a and a second blocking structure 254a may be disposed on the blocking region II.

According to example embodiments, the first blocking structure 252a may have a structure and shape substantially the same as or similar to that of the blocking structure 250 of the vertical memory device illustrated in FIGS. 1 to 3 . For example, the first blocking structure 252a penetrates the mold protection layer 210 and extends in the third direction, and the dummy dielectric layer 232 , the dummy channel 237 , and the second buried layer pattern 242 are formed therein. It may have a stacked structure. In example embodiments, the first blocking structure 252a may extend along the second and third directions. For example, the first blocking structure 252a may have a fence shape surrounding the cell region I.

The second blocking structure 254a may have a structure and shape substantially the same as or similar to that of the blocking structure 254 of the vertical memory device illustrated in FIGS. 30 to 32 . For example, the second blocking structure 254a may pass through the mold protection layer 210 and extend in the third direction. The second blocking structure 254a may include a dummy separator pattern 271a and a dummy conductive line 273a. According to an exemplary embodiment, the second blocking structure 254a may extend along the second and third directions. For example, the second blocking structure 254a may have a fence shape surrounding the cell region I.

In example embodiments, the first blocking structure 252a may be formed by a deposition process and/or etching for forming the dielectric layer structure 230 , the channel 235 , and the first buried layer pattern 240 of the cell region (I). can be formed together by a process. The second blocking structure 254a may be formed together by a deposition process and/or an etching process for forming the separation layer pattern 271 and the CSL line 273 of the cell region I.

The vertical memory device illustrated in FIGS. 37 and 38 may be manufactured by combining processes substantially the same as or similar to those described with reference to FIGS. 4 to 17B and 33 to 36C . Accordingly, a detailed description of the method of manufacturing the vertical memory device shown in FIGS. 37 and 38 will be omitted.

39 and 40 are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments. Specifically, FIG. 40 is a cross-sectional view taken along line I-I' of FIG. 39 . The vertical memory device may have substantially the same or similar structure and/or configuration to that of the vertical memory device described with reference to FIGS. 25 and 26 or FIGS. 30 to 32 , except for the blocking structure. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

Meanwhile, illustration of the upper insulating layer is omitted in FIG. 39 for convenience of description.

39 and 40 , a first blocking structure 253a and a second blocking structure 254a may be disposed on the blocking region II of the substrate 100 .

According to example embodiments, the first blocking structure 253a may have a structure and shape substantially the same as or similar to that of the blocking structure 253 of the vertical memory device illustrated in FIGS. 25 and 26 . For example, the first blocking structure 253a may include one or more dummy channel columns formed by arranging a plurality of dummy channel structures 250a. The dummy channel structure 250a may include a dummy dielectric layer structure 232a , a dummy channel 237a , a second buried layer pattern 242a , and a dummy pad 261 . According to an exemplary embodiment, the first blocking structure 253a may be arranged along the second and third directions. For example, the first blocking structure 253a may be arranged in the form of a fence surrounding the cell region I.

The second blocking structure 254a may have a structure and shape substantially the same as or similar to that of the blocking structure 254 of the vertical memory device illustrated in FIGS. 30 to 32 . For example, the second blocking structure 254a passes through the mold protection layer 210 and extends in the third direction, and may include a dummy separator pattern 271a and a dummy conductive line 273a. According to an exemplary embodiment, the second blocking structure 254a may be arranged along the second and third directions. For example, the second blocking structure 254a may have a fence shape surrounding the cell region I.

In example embodiments, the first blocking structure 253a is deposited to form the dielectric layer structure 230 , the channel 235 , the first buried layer pattern 240 , and the pad 260 of the cell region I. It may be formed together by a process and/or an etching process. The second blocking structure 254a may be formed together by a deposition process and/or an etching process for forming the separation layer pattern 271 and the CSL line 273 of the cell region I.

The vertical memory device illustrated in FIGS. 39 and 40 may be formed by combining processes substantially the same as or similar to those described with reference to FIGS. 27 to 29B and 33 to 36C . Accordingly, a detailed description of the method of manufacturing the vertical memory device shown in FIGS. 39 and 40 will be omitted.

As described with reference to FIGS. 37 to 40 , in exemplary embodiments, a blocking structure having a double structure is disposed on the blocking region II, thereby moving from the cell region I to the peripheral circuit region II. stress propagation can be blocked more effectively.

41A and 41B are cross-sectional views illustrating a vertical memory device according to example embodiments. The vertical memory device shown in FIGS. 41A and 41B may have a structure and/or configuration substantially the same as or similar to the vertical memory device described with reference to FIGS. 1 to 3 except for the blocking structure and/or the gate structure. can Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

Referring to FIG. 41A , the blocking structure 107 may have a structure embedded or inserted into the substrate 100 of the blocking region II. According to exemplary embodiments, the trench 101 is formed in the portion of the substrate 100 of the blocking region I, and the blocking structure 107 fills the trench 101 and has a line shape extending in the third direction. can have The blocking structure 107 is formed by forming an insulating layer filling the trench 101 on the substrate 100 using an insulating material such as silicon oxide or silicon nitride, and then forming an upper portion of the insulating layer on the upper surface of the substrate 100 . It can be formed by planarizing until exposed. In example embodiments, the trench 101 and the blocking structure 107 may be formed along the second and third directions. For example, the trench 101 and the blocking structure 107 may have a fence shape surrounding the cell region I.

As the blocking structure 107 is buried in the substrate 100 , the stress generated in the cell region I is transferred to the peripheral circuit region III through the substrate 100 , so that the upper surface of the substrate 100 and the gate structure ( 140) can more effectively block the occurrence of defects such as dislocations and cracks between the bottom surfaces.

1 to 3 , 18 , 25 and 26 , 30 and 31 , 37 and 38 , or 39 in addition to the blocking structure 107 embedded in the substrate 100 in one embodiment And the blocking structures described with reference to FIG. 40 may be formed on the substrate 100 in the blocking region II.

Referring to FIG. 41B , a gate structure having a buried gate structure may be formed in the peripheral circuit region II of the substrate 100 .

For example, after forming the first impurity region 103a on the substrate 100 in the peripheral circuit region III, the upper portion of the substrate 100 in the peripheral circuit region III is etched to form the recess 109 ) can be formed. A gate insulating layer pattern 115 may be formed on sidewalls and a bottom surface of the recess 109 through, for example, a thermal oxidation process. The buried gate 125 may be formed by forming a conductive layer filling the recess 125 on the gate insulating layer pattern 115 , and removing an upper portion of the conductive layer through an etch-back process. Thereafter, for example, a gate mask 135 filling the remaining portion of the recess 109 may be formed on the buried gate 125 by depositing silicon nitride. Accordingly, the buried gate structure 145 including the gate insulating layer pattern 115 , the buried gate 125 , and the gate mask 135 may be formed on the peripheral circuit region of the substrate 100 . In an embodiment, a peripheral circuit protection layer 152a covering the impurity region 103a, the gate insulating layer pattern 115, and the gate mask 135 may be further formed on the substrate 100 of the peripheral circuit region III. have.

As shown in FIG. 41B on the peripheral circuit region III, when the gate structure is buried or inserted into the substrate 100 , a defect phenomenon of the gate structure occurs due to stress transmitted through the substrate 100 . can be However, by forming the blocking structure 107 buried in the substrate 100 on the blocking region II, it is possible to effectively prevent the gate structure from being defective.

42 to 44 are cross-sectional views illustrating vertical memory devices according to example embodiments. For example, FIGS. 42, 43, and 44 are cross-sectional views illustrating modified embodiments of the vertical memory device shown in FIGS. 2, 18, and 31, respectively.

Referring to FIG. 42 , the blocking structure 251 including the dummy dielectric layer 233 , the dummy channel 238 , and the second buried layer pattern 243 passes through the mold protection layer 210 , and It may extend into the substrate 100 so as to be partially buried. For example, when the first opening 217a for forming the blocking structure 251 is formed, a portion of the substrate 100 in the blocking region II is additionally etched so that the first opening 217a is formed into the substrate 100 . can be expanded. Thereafter, the dummy dielectric layer 233 , the dummy channel 238 , and the second buried layer pattern 243 are formed in the first opening 217a through a process substantially the same as or similar to the process described with reference to FIGS. 8 to 11B . This stacked blocking structure 251 may be formed.

Referring to FIG. 43 , the blocking structure 252a includes an air gap 251a , and the air gap 251a may extend into the substrate 100 to extend. For example, when the first opening 264a for forming the blocking structure 251 is formed, a portion of the substrate 100 in the blocking region II is additionally etched so that the first opening 264a is formed into the substrate 100 . can be expanded. Thereafter, as described with reference to FIG. 24 , an upper insulating film 281a is formed on the first opening 264a to partially fill the first opening 264a and into the substrate 100 and the partial filling film 281c. An air gap 251a having an extended length may be formed.

Referring to FIG. 44 , the blocking structure 254b including the dummy separation layer pattern 271b and the dummy conductive line 273b passes through the mold protection layer 210 , and is embedded in a portion of the substrate 100 into the substrate 100 . can be extended For example, when the first opening 217a for forming the blocking structure 254b is formed, a portion of the substrate 100 in the blocking region II is additionally etched so that the first opening 217a is expanded into the substrate 100 . can be Thereafter, through a process substantially the same as or similar to the process described with reference to FIGS. 38A and 38B , the dummy separator pattern 271b and the dummy conductive line 273b extended into the substrate 100 in the inside of the first opening 217a . ) can be formed.

42 to 44 , a buried gate structure 145 may be formed on the peripheral circuit region III as shown in FIG. 41B .

45A and 45B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments.

The vertical memory device shown in FIGS. 45A and 45B has a structure and/or substantially the same as or similar to that of the vertical memory device described with reference to FIGS. Or it may have a configuration. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

45A and 45B , contacts 277 passing through the mold protection layer 210 and the interlayer insulating layer pattern 206 of each layer may be formed on the cell region I of the substrate 100 . The contact 277 may be in contact with the gate line 270 of each layer. For example, the contact 277 may be provided for each step of the word line and GSL belonging to each gate line structure. Wirings 279 electrically connected to the contacts 277 may be formed on the mold passivation layer 210 .

45A , each wiring 279 extends in the third direction and is electrically connected to a plurality of contacts 277 in contact with gate lines 270 belonging to different gate line structures. can

In example embodiments, a plurality of dummy contacts 277a may be disposed on the blocking region II of the substrate 100 . For example, the dummy contact 277a may penetrate the mold passivation layer 210 formed on the blocking region II to contact the substrate 100 .

45A , a plurality of dummy contacts 277a may be disposed along the third direction to define a dummy contact column. Also, the plurality of dummy contact columns may be disposed along the second direction. In some embodiments, the dummy contacts 277a may be arranged to continuously surround the cell region I in the second direction and the third direction.

Accordingly, the blocking structure 278 including one or more of the dummy contact rows may be disposed on the blocking region II of the substrate 100 to block the stress propagation of the peripheral circuit region II in the cell region I. have. In FIG. 45A , the blocking structure 278 is illustrated as including the two dummy contact rows, but the blocking structure 278 may include three or more dummy contact rows.

In example embodiments, the plurality of dummy contact columns may be arranged such that dummy contacts 277a belonging to different dummy contact columns are displaced from each other, for example, arranged in a zig-zag shape. Accordingly, the density of the dummy contacts 277a in the blocking region II is increased, and thus the stress propagation can be more effectively blocked.

In some embodiments, a peripheral circuit contact (not shown) that passes through the mold protection layer 210 and is electrically connected to the first impurity region 103 may be disposed on the peripheral circuit region III. have. A peripheral circuit wiring (not shown) electrically connected to the peripheral circuit contact may be disposed on the mold passivation layer 210 .

The upper insulating layer 280 may be formed on the uppermost interlayer insulating layer pattern 206e , the pad 260 , and the mold protection layer 210 to cover the wirings 279 and the dummy contact 277a . In some embodiments, a bit line designed to apply a signal through the pad 260 may be disposed on the upper insulating layer 280 .

46A to 48 are plan views and cross-sectional views each illustrating a method of manufacturing a vertical memory device according to example embodiments. For example, FIGS. 46A to 48 are diagrams for explaining a method of manufacturing the vertical memory device illustrated in FIGS. 45A and 45B .

Specifically, FIGS. 46A and 47A are plan views illustrating a method of manufacturing the vertical memory device. 46B, 47B, and 48 are cross-sectional views taken in the first direction along the line I-I' shown in FIGS. 46A and 47A.

Meanwhile, detailed descriptions of processes and/or materials substantially the same as or similar to the processes and/or materials described with reference to FIGS. 4 to 17B will be omitted.

46A and 46B , processes substantially similar to those described with reference to FIGS. 4 to 17B may be performed.

Accordingly, interlayer insulating layer patterns 206 , gate lines 270 , and interlayer insulating layer patterns 206 and gate lines 270 alternately and repeatedly stacked on the cell region I of the substrate 100 . ), the gate line structure may be cut by the separation layer pattern 275 formed in the second opening 265 .

A peripheral circuit including a transistor defined by the gate structure 140 and the first impurity region 103 is formed on the peripheral circuit region III of the substrate 100 , and a peripheral circuit protection layer 152 covering the peripheral circuit can be formed.

The mold protection layer 210 may be formed to cover the side portions of the gate line structures, the portion of the substrate 100 of the blocking region II, and the peripheral circuit protection layer 152 .

However, the processes for forming the first opening 217 and the blocking structure 250 described together with reference to FIGS. 7A to 13 may be omitted. Accordingly, the blocking region II may be substantially completely covered by the mold passivation layer II as shown in FIG. 46B .

47A and 47B , the mold protective layer 210 and the interlayer insulating layer pattern 206 on the cell region I are partially etched to form contact holes 276 exposing the gate line 270 of each layer. can do. Meanwhile, a dummy contact hole 276a passing through the mold protection layer 210 may be formed on the blocking region II.

In some embodiments, the contact hole 276 may be formed to expose each step of a word line and a GSL belonging to each gate line structure. A portion of the substrate 100 in the blocking region II may be exposed through the dummy contact hole 276a.

A plurality of dummy contact holes 276a may be formed along the third direction to define a column of dummy contact holes. Also, a plurality of rows of the dummy contact holes may be formed in the second direction. In some embodiments, a plurality of dummy contact holes 276a may be formed to surround the cell region I in the third and second directions.

In example embodiments, the contact hole 276 and the dummy contact hole 276a may be formed through a substantially single etching process using the same etching mask. In some embodiments, on the peripheral circuit region III, a peripheral circuit contact hole (not shown) exposing a peripheral circuit such as, for example, the first impurity region 103 is provided with the contact hole 276 and the dummy contact. It may be formed together with the hole 276a.

Referring to FIG. 48 , a contact 277 and a dummy contact 277a may be formed in the contact hole 276 and the dummy contact hole 276a, respectively.

For example, a first conductive layer sufficiently filling the contact hole 276 and the dummy contact hole 276a may be formed on the mold passivation layer 210 , the exposed gate lines 270 , and the substrate 100 . Thereafter, the upper portion of the first conductive layer may be planarized through a CMP process and/or an etch-back process until the top surface of the mold protective layer 210 is exposed to form contacts 277 and dummy contacts 277a. . As described above, when the peripheral circuit contact hole is formed, a peripheral circuit contact electrically connected to the peripheral circuit may be formed together with the contact 277 and the dummy contact 277a.

According to the arrangement of the contact holes 276 of the contacts 277 , for example, word lines belonging to each gate line structure and each step of the GSL may be in contact. The dummy contact 277a may be formed according to the arrangement of the dummy contact hole 276a to generate, for example, a plurality of dummy contact rows. As shown in FIG. 45A , a blocking structure 278 may be defined on the blocking region II by the plurality of dummy contact rows.

Thereafter, as shown in FIG. 45B , a second conductive layer may be formed on the mold protective layer 210 and patterned to form wirings 279 .

Each wiring 279 may be electrically connected to, for example, contacts 277 extending in the third direction and contacting gate lines 270 of the same level included in different gate line structures. In some embodiments, a peripheral circuit wiring electrically connected to the peripheral circuit contact may be formed together from the second conductive layer.

The first and second conductive layers may be formed through a CVD process, an ALD process, a sputtering process, or the like using a conductive material such as metal, metal nitride, or doped polysilicon.

Thereafter, an upper insulating layer 280 covering the wirings 279 and the dummy contacts 277a may be formed on the uppermost interlayer insulating layer pattern 206e , the pad 260 , and the mold protection layer 210 .

49A and 49B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments. Specifically, FIG. 49B is a cross-sectional view taken along line I-I' of FIG. 49A. The vertical memory device may have substantially the same or similar structure and/or configuration to that of the vertical memory device described with reference to FIGS. 1 to 3 or FIGS. 45A and 45B , except for a blocking structure. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

49A and 49B , a plurality of blocking structures having different structures may be disposed on the blocking region II.

According to exemplary embodiments, the first blocking structure is defined by the dummy contacts 277a described with reference to FIGS. 45A and 45B , and the first blocking structure is defined by the blocking structure 250 described with reference to FIGS. 1 to 3 . 2 blocking structures can be defined. The second blocking structure may include, for example, a dummy dielectric layer 232 continuously extending in the third direction, a dummy channel 237 , and a second buried layer pattern 242 .

Accordingly, the blocking structure has a composite structure including the first blocking structure defined by a dummy contact row, and the second blocking structure in the form of a fence or a ring, and is disposed between the cell region I and the peripheral circuit region III. It is possible to more effectively block the stress propagation in

50A and 50B are a plan view and a cross-sectional view, respectively, for explaining a vertical memory device according to example embodiments. Specifically, FIG. 50B is a cross-sectional view taken along line I-I' of FIG. 50A. The vertical memory device may have substantially the same or similar structure and/or configuration to that of the vertical memory device described with reference to FIGS. 25 and 26 or 45A and 45B except for a blocking structure. Accordingly, a detailed description of the overlapping configuration and/or structures will be omitted. In addition, the same or similar reference numerals are used for the same or similar components.

50A and 50B , a blocking structure having a composite structure of different materials may be disposed on the blocking region II.

According to exemplary embodiments, the first blocking structure is defined by the dummy contacts 277a described with reference to FIGS. 45A and 45B , and is formed in the dummy channel structures 250a described with reference to FIGS. 25 and 26 . A second blocking structure may be defined by The dummy channel structures 250a include, for example, a dummy dielectric layer structure 232a extending in the first direction and penetrating the mold passivation layer 210 , a dummy channel 237a , and a second buried layer pattern 242a. , may further include a dummy pad 261 on the upper portion.

For example, the first blocking structure may include a dummy contact column defined by a plurality of dummy contacts 277a. The second blocking structure may include a dummy channel column defined by a plurality of dummy channel structures 250a.

Although one dummy contact column and one dummy channel column are illustrated in FIG. 50A , respectively, two or more of the dummy contact columns and the dummy channel column may be disposed on the blocking region II. In addition, the dummy contact column and the dummy channel column may be continuously disposed along the second direction and the third direction to surround the cell region (I).

In some exemplary embodiments, the above-described dummy contact column may be provided in combination with various examples of the blocking structure disclosed herein. For example, the dummy contact row may be combined with a blocking structure including an air gap 251 shown in FIG. 24 . In addition, the dummy contact column may be combined with a blocking structure including the dummy conductive line 273a shown in FIG. 30 .

51 is a block diagram showing a schematic configuration of an information processing system according to exemplary embodiments.

Referring to FIG. 51 , the information processing system 300 includes a central processing unit (CPU) 320 electrically connected to a system bus 305 , a RAM 330 , a user interface 340 , It may include a modem (MODEM) 350 and a memory system 310 such as a baseband chipset. The memory system 310 may include a memory device 312 and a memory controller 311 . The memory device 312 may include the vertical memory device according to the above-described exemplary embodiments. Accordingly, it is possible to stably store data processed by the central processing unit 320 or high-capacity data input from the outside. The memory controller 311 is configured to control the memory device 312 . Due to the combination of the memory device 312 and the memory controller 311 , the memory system 310 may be provided as a memory card or a solid state disk (SSD). When the information processing system 300 is a mobile device, a battery for supplying an operating voltage of the system 300 may be additionally provided. Although not shown, the information processing system 300 according to the exemplary embodiments may further include an application chipset, a camera image processor (CIS), a mobile DRAM, and the like.

In the vertical memory device according to exemplary embodiments of the present invention, it is possible to block stress propagation between the cell region and the peripheral circuit region by using blocking structures having various structures and/or shapes. Accordingly, in a highly integrated nonvolatile memory device having an increased number of stacks in the vertical direction, it is possible to implement a highly reliable vertical memory device in which defects due to stress are removed.

Although described with reference to preferred embodiments of the present invention as described above, those of ordinary skill in the art can variously modify and modify the present invention within the scope without departing from the spirit and scope of the present invention described in the claims. You will understand that it can be changed.

I: cell region II: blocking region
III: peripheral circuit area 100: substrate
101: trenches 103, 103a: first impurity region
105: second impurity region 109: recess
110, 115: gate insulating layer pattern 120: gate electrode
125: buried gate 130, 135: gate mask
140: gate structure 145: buried gate structure
150: gate spacer 152: peripheral circuit protective film
202: interlayer insulating film 204: sacrificial film
205: stepped mold structure 206: interlayer insulating film pattern
208: sacrificial layer pattern 210: mold protective layer
215: channel hole 216: dummy channel hole
217, 217a, 264, 264a: first opening
220: dielectric film 225: channel film
227: first buried layer 230: dielectric layer structure
232a: dummy dielectric film structures 232, 233: dummy dielectric film
235: channels 237, 237a, 238: dummy channels
240: first buried layer pattern
242, 242a, 243: second buried layer pattern
107, 250, 251, 252, 252a, 253, 254, 254b, 255: blocking structure
252a, 253a: first blocking structure 254a: second blocking structure
250a: dummy channel structure 251, 251a: air gap
260: pad 260a, 261: dummy pad
264: first opening 265: second opening
267: gap 270: gate line
271, 275: separator pattern 271a, 271b: dummy separator pattern
273a, 273b: dummy conductive line 273: CSL line
276: contact hole 276a: dummy contact hole
277: contact 277a: dummy contact
279: wiring 280, 281a: upper insulating film
281b, 281c: partially filled film

Claims (10)

a substrate including a cell region and a peripheral circuit region;
channels disposed on the cell region and extending in a first direction perpendicular to the upper surface of the substrate;
gate lines surrounding the outer walls of the channels and stacked to be spaced apart from each other in the first direction; and
a blocking structure disposed between the cell region and the peripheral circuit region;
wherein the blocking structure includes a dummy channel including the same material as the channel. The vertical direction of claim 1 , wherein the gate lines extend in a second direction parallel to the upper surface of the substrate, and the blocking structure extends in at least a third direction parallel to the upper surface of the substrate and intersecting the second direction. type memory device. delete According to claim 1, further comprising a dielectric film structure surrounding the outer wall of the channel,
The blocking structure includes a dummy dielectric layer including the same material as the dielectric layer structure. The vertical memory device of claim 1 , wherein the blocking structure includes an air gap. The vertical memory device of claim 1 , wherein the blocking structure includes one or more dummy channel columns including a plurality of dummy channel structures. The method of claim 1 , further comprising: contacts electrically connected to the gate lines on the cell region;
wherein the blocking structure includes one or more dummy contact columns including a plurality of dummy contacts. The vertical memory device of claim 1 , wherein the blocking structure includes a dummy conductive line. The vertical memory device of claim 8 , further comprising a common source line disposed on the cell region, wherein the common source line and the dummy conductive line include the same conductive material. a substrate including a cell region and a peripheral circuit region;
channels disposed on the cell region and extending in a first direction perpendicular to the upper surface of the substrate;
gate lines surrounding the outer walls of the channels and stacked to be spaced apart from each other in the first direction;
a common source line disposed on the cell region; and
a blocking structure disposed between the cell region and the peripheral circuit region and surrounding the cell region;
wherein the blocking structure includes a dummy channel including the same material as the channel.

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