KR20160109989A - Vertical memory devices - Google Patents

Abstract

A vertical memory device includes: a plurality of gate electrodes formed on a plurality of layers respectively which are spaced from each other in a vertical direction vertical to the upper surface of a substrate; a channel extended, on the substrate, in the vertical direction to penetrate the gate electrodes; and a plurality of first contact plugs extended, on the gate electrodes, in the vertical direction to come in contact with the gate electrodes respectively. One or more second contact plugs, extended in the vertical direction, are formed on a first gate electrode among the gate electrodes.

Description

{Vertical Memory Devices}

The present invention relates to a vertical memory device. More particularly, the present invention relates to a vertical non-volatile memory device comprising a step-like word line pad and contacts in contact therewith.

Recently, a vertical type nonvolatile memory device has been developed to increase the degree of integration. In the fabrication of a vertical nonvolatile memory device, after forming a stepped wordline pad, contacts are formed which each contact on the steps of the wordline pad. However, due to the pattern loading effect due to the density difference of the patterns, the contact holes for the contacts formed on the lowest step and the highest step can be formed so as not to expose the step well. As a result, the contacts formed in the contact holes do not contact the word line pad well, and the electrical characteristics may deteriorate.

It is an object of the present invention to provide a vertical memory device having excellent electrical characteristics.

According to an aspect of the present invention, there is provided a vertical memory device including a plurality of gate electrodes formed on a plurality of layers spaced apart from each other along a vertical direction perpendicular to a top surface of a substrate, A plurality of first contact plugs extending in the vertical direction and passing through the gate electrodes, and a plurality of first contact plugs extending in the vertical direction on the gate electrodes and contacting the gate electrodes, respectively. And one or more second contact plugs extending in the vertical direction are further formed on the first gate electrode of the gate electrodes.

In exemplary embodiments, an upper surface of the second contact plug may be formed at a substantially same height as an upper surface of the first contact plugs.

In exemplary embodiments, the second contact plug may contact the first gate electrode.

In the exemplary embodiments, the second contact plug does not contact the first gate electrode, the bottom surface of the second contact plug is higher than the top surface of the first gate electrode, May be lower than the bottom surface of the gate electrode formed immediately above.

In exemplary embodiments, each of the gate electrodes may extend along a first direction parallel to the top surface of the substrate, and the first and second contact plugs may be spaced apart at regular intervals As shown in FIG.

In exemplary embodiments, the second contact plug may be disposed at the earliest or first end of the first and second contact plugs along the first direction.

In exemplary embodiments, the second contact plug may be centered along the first direction among the first and second contact plugs.

In exemplary embodiments, the first and second contact plugs may be arranged in a zigzag shape along the first direction.

In exemplary embodiments, the second contact plug may be disposed at the earliest or first end of the first and second contact plugs along the first direction.

In exemplary embodiments, the gate electrodes may have a stepped shape in which the length in the first direction gradually decreases from the lower layer to the upper layer, and each of the first and second contact plugs may be formed by gate electrodes of the upper layer May be formed on edge portions of the gate electrodes not overlapping each other.

In exemplary embodiments, the first gate electrode may be formed in the lowest layer among the gate electrodes.

In exemplary embodiments, the first gate electrode may be formed on the uppermost one of the gate electrodes.

In exemplary embodiments, the first gate electrode may be formed in the middle layer of the gate electrodes.

In exemplary embodiments, the vertical memory device may include a plurality of the first gate electrodes.

In exemplary embodiments, the first gate electrodes may be formed in the lowermost layer and the uppermost layer, respectively, of the gate electrodes.

In exemplary embodiments, the first contact plugs may further include first wirings that respectively contact the upper surfaces of the first contact plugs, and electrical signals may be applied to the first contact plugs through the first wirings.

In exemplary embodiments, the upper surface of the second contact plug may contact the first wiring formed on the upper surface of the first contact plug contacting the first gate electrode.

In exemplary embodiments, the second contact plug may not be connected to any wiring.

In exemplary embodiments, the gate electrodes may have a stepped shape in which a length in a first direction parallel to the upper surface of the substrate gradually decreases from a lower layer to an upper layer, and a gate electrode formed in the lowest layer among the gate electrodes, The upper surface of the substrate adjacent to the first direction may further include at least one third contact plug extending in the vertical direction and having a top surface at the same height as the top surfaces of the first and second contact plugs.

In exemplary embodiments, the first contact plugs may further include first wirings that respectively contact the upper surfaces of the first contact plugs, and electrical signals may be applied to the first contact plugs through the first wirings.

In exemplary embodiments, an upper surface of the third contact plug may contact a second wiring different from the first wiring.

In the exemplary embodiments, the third contact plug may not be connected to any wiring.

In exemplary embodiments, the gate electrodes may comprise a sequentially selected ground selection line (GSL), a word line, and a string selection line (SSL).

In exemplary embodiments, the first gate electrode may comprise the ground select line or the string select line.

In exemplary embodiments, each of the gate electrodes may include a metal pattern, and a barrier film pattern covering at least upper and lower surfaces of the metal pattern.

In exemplary embodiments, each of the first contact plugs may contact the metal pattern through the barrier film pattern of the corresponding gate electrode.

In exemplary embodiments, each of the first contact plugs may contact the barrier film pattern of the corresponding gate electrode.

In exemplary embodiments, each of the first contact plugs may penetrate the barrier film pattern and the metal pattern of the corresponding gate electrode.

In exemplary embodiments, the second contact plug may contact the barrier film pattern of the corresponding gate electrode.

In exemplary embodiments, the second contact plug may not contact the barrier film pattern of the corresponding gate electrode.

According to another aspect of the present invention, there is provided a vertical memory device including: a memory cell region including a memory cell region and a peripheral region; A plurality of gate electrodes formed in a plurality of layers spaced apart from each other, a channel extending in the vertical direction on the substrate and passing through the gate electrodes, and a plurality of gate electrodes extending in the vertical direction on the gate electrodes, And a plurality of first contact plugs, respectively. In the memory cell region, at least one third contact plug extending in the vertical direction and having a top surface at the same height as the top surface of the first contact plugs is formed on the substrate adjacent to the gate electrode formed in the lowermost layer among the gate electrodes Lt; / RTI >

In exemplary embodiments, each of the gate electrodes may extend along a first direction parallel to the top surface of the substrate, and the first and third contact plugs may be spaced apart at regular intervals As shown in FIG.

In the exemplary embodiments, the gate electrodes may have a stepped shape in which a length in a first direction parallel to the upper surface of the substrate gradually decreases from a lower layer to an upper layer, and the third contact plug may have a stepped shape, And may be formed on the portion of the substrate adjacent to the electrode in the first direction.

In exemplary embodiments, the semiconductor device may further include first wirings that respectively contact the upper surfaces of the first contact plugs, wherein an electrical signal is applied to the first wirings through a second wiring formed in a peripheral region of the substrate .

In exemplary embodiments, the upper surface of the third contact plug may contact the first wiring formed on the upper surface of the first contact plug contacting the gate electrode formed in the lowest layer.

In exemplary embodiments, the third contact plug may be connected to a third wiring different from the first wiring.

In the exemplary embodiments, the third contact plug may not be connected to any wiring.

In exemplary embodiments, one or more second contact plugs may be further formed on the first gate electrode of the gate electrodes, the first contact plugs extending in the vertical direction and having an upper surface of the same height as the upper surfaces of the first contact plugs .

According to another aspect of the present invention, there is provided a vertical memory device including: a channel extending along a vertical direction perpendicular to a top surface of a substrate; a charge storage film structure surrounding an outer wall of the channel; A plurality of gates extending along a first direction parallel to the upper surface of the substrate and spaced from each other along the vertical direction and having a stepped shape gradually decreasing in length in the first direction from the lower layer to the upper layer, Electrodes, and a plurality of first contact plugs extending in the vertical direction in contact with edge portions of the gate electrodes that do not overlap by the gate electrodes of the upper layer. The lengths of the gate electrodes adjacent to each other in the vertical direction in the first direction are reduced to a first width, but a length in the first direction of the first gate electrode among the gate electrodes, The length of the second gate electrode disposed immediately above in the first direction decreases to a second width larger than the first width.

In exemplary embodiments, the second width may be at least twice the first width.

In exemplary embodiments, the first contact plug may further include one or more second contact plugs extending in the vertical direction on the first gate electrode.

In exemplary embodiments, the first and second contact plugs may be disposed at regular intervals along the first direction.

In exemplary embodiments, the upper surface of the second contact plug may be formed at the same height as the upper surface of the first contact plug.

In exemplary embodiments, the vertical memory device may include a plurality of the first gate electrodes.

In exemplary embodiments, the first gate electrode may be formed in the lowest layer among the gate electrodes.

As described above, in the vertical memory device manufacturing method according to the exemplary embodiments, when the first contact plugs are formed to be connected to the gate electrodes formed at the respective steps of the step structure, By further forming the plug, the pattern loading phenomenon can be prevented, and the first contact plugs can be formed to be in contact with the gate electrodes well.

1 to 13 are plan views and sectional views for explaining a vertical memory device according to exemplary embodiments.
14 to 44 are plan views and sectional views for explaining a method of manufacturing the vertical memory device.
45-70 are plan views and cross-sectional views for illustrating a vertical memory device according to exemplary embodiments.

Hereinafter, a vertical memory device and a method of manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. In the accompanying drawings, dimensions of a substrate, a layer (film), an area, patterns or structures are enlarged in actuality for clarity of the present invention. In the present invention, each layer (film), region, electrode, pattern or structure is referred to as being "on", "on", or " Means that each layer (film), region, electrode, pattern, or structure is directly formed or positioned below a substrate, each layer (film), region, structure, or pattern, A layer (film), another region, another electrode, other patterns or other structure may be additionally formed on the substrate. It will also be understood that when a material, layer, region, electrode, pattern or structure is referred to as a "first", "second", "third", and / But only to distinguish each material, layer (membrane), region, electrode, patterns or structures. Thus, "first", "second", "third" and / or "spare" may be used, alternatively or alternatively, for each layer (membrane), region, electrode, patterns or structures.

1 to 13 are plan views and sectional views for explaining a vertical memory device according to exemplary embodiments. 1 is a plan view for explaining regions of a substrate on which the vertical memory device is formed, and FIGS. 2 to 13 are views for the X region of FIG. Specifically, Figures 1, 2, 8 and 13 are plan views, and Figures 3-7 and 9-12 are cross-sectional views. 2 is a cross-sectional view taken along the line B-B 'in FIG. 2, and FIG. 5 is a cross-sectional view taken along the line C-C' FIG. 6 is a cross-sectional view taken along line D-D 'of FIG. 2, and FIG. 7 is a cross-sectional view taken along line E-E' of FIG.

8A is a plan view of a structure of the vertical memory device stacked from the substrate to a fifth interlayer insulating film, and FIG. 8B is a plan view of a structure stacked from the substrate to the sixth interlayer insulating film in the vertical memory device And FIG. 8C is a plan view of a structure of the vertical memory device stacked up from the substrate to the seventh interlayer insulating film. 9A and 9B are cross-sectional views taken along the line B-B 'in FIG. 8A, and FIGS. 10 to 12 are enlarged views of the Y region in FIG. 9A.

In the following description, two directions parallel to the upper surface of the substrate and intersecting with each other are defined as first and second directions, respectively, and a direction substantially perpendicular to the upper surface of the substrate is defined as a third direction. In exemplary embodiments, the first and second directions may be orthogonal to each other.

Referring first to FIG. 1, a substrate 100 on which the vertical memory device is formed may include first through fourth regions I, II, III, and IV. In this case, the first region I may be a memory cell region where memory cells are formed, the second region II may be a region where a row decoder X-decoder is formed, A page buffer and a Y-decoder may be formed, and the fourth region IV may be a peripheral circuit region in which peripheral circuits for driving the memory cells are formed. The second and third regions II and III may form a core region together, and the core region and the peripheral circuit region together may be referred to as a peripheral region.

Hereinafter, for convenience of description, the description will be made with reference to the drawings of the X region which is the one-edge portion in the first region I of the substrate 100. [

Referring to FIGS. 2 to 7, 8A, 8B, 8C and 9A, the vertical memory device includes gate electrodes 310 formed on a substrate 100, a channel 210, a second charge storage film structure First contact plugs 280, and first and second contact plugs 380 and 385.

The vertical memory device includes an insulating film pattern 115 formed on a substrate 100, an insulating pad 127, a semiconductor pattern 160, a filled film pattern 220, a capping film pattern 230, The first and second interlayer insulating films 130, 140, 240, 340, 390, 430, 560 and 630, the common source line (CSL) 330, the second spacer 320, 460, 465, 660, 690, and first through sixth vias 460, 465, 550, 555, 590, 620. The first through sixth vias 460,

The substrate 100 may comprise a semiconductor material such as silicon, germanium, or the like.

The gate electrodes 310 may be formed on the substrate 100 in a plurality of layers so as to be spaced apart from each other along the third direction. At this time, an insulating layer pattern 115 may be interposed between the gate electrodes 310 stacked along the third direction.

Each of the gate electrodes 310 may extend in the first direction, and may be formed along the second direction. The plurality of gate electrodes 310 formed along the second direction may be separated from each other by a common source line (CSL) 330 extending in the first direction and a second spacer 320 formed on both sidewalls thereof. . On the other hand, the impurity region 105 may be formed on the substrate 100 in contact with the common source line (CSL) 330. The impurity region 105 may include an n-type impurity such as phosphorous, arsenic, for example.

The gate electrode 310 and the insulating film pattern 115 which are sequentially stacked in the third direction may constitute one step, and the plurality of steps may be stacked along the third direction to form one step structure . Accordingly, in the present specification, each step constituting the step structure means an entire part including one layer, including not only the part exposed to the outside but also the part covered by the structure formed on the upper part.

The stepped structure may include steps in which the length of the first direction gradually decreases from the lower layer to the upper layer, so that the gate electrodes 310 and the insulating layer patterns 115 formed at the respective steps are also formed from the lower layer to the upper layer, The length of the first direction may gradually decrease. In exemplary embodiments, the stairs along the third direction may be reduced in length in the first direction to a constant width, such that they are not covered or overlapped by the stairs formed in the upper layer in each of the stairs The exposed part may be constant. Similarly, the lengths of the gate electrodes 310 adjacent to each other in the third direction in the first direction may be reduced by a predetermined first width, so that the gate electrodes 310 formed in the upper layer in each of the gate electrodes 310, The portion exposed or covered by or not overlapped with each other 310 may be constant.

However, the length in the first direction of the first step and the length in the first direction of the second step disposed immediately above the first step in the steps are reduced by a second width greater than the first width, can do. In exemplary embodiments, the second width may be at least twice the first width.

Accordingly, the length of the first gate electrode 310 formed in the first step in the first direction and the length of the second gate electrode 310 disposed in the immediately upper layer of the first gate electrode 310 in the first direction May be reduced to a second width greater than the first width and a portion of the first gate electrode 310 that is covered or not overlapped by the gate electrodes 310 of the upper layer may be exposed to the gate May be wider than the portions exposed or covered by the gate electrodes 310 of the upper layer in the electrodes 310. [

In the exemplary embodiments, the first gate electrode 310 may be formed in the lowermost layer among the plurality of gate electrodes 310 stacked. In other embodiments, the first gate electrode 310 may be formed on the uppermost layer among a plurality of the gate electrodes 310 stacked. In still other embodiments, the first gate electrode 310 may be formed in the middle layer among a plurality of the gate electrodes 310 stacked. That is, the first gate electrode 310 may be formed in any layer among the plurality of gate electrodes 310, and may be formed in a plurality of layers in some cases.

The gate electrode 310 may include a ground selection line (GSL), a word line, and a string selection line (SSL) sequentially arranged along the third direction. At this time, each GSL, word line, and SSL may be formed in one or a plurality of layers. In addition, one or more dummy word lines may be formed between the GSL and the word lines and / or between the SSL and the word lines. In exemplary embodiments, the GSL is formed in one layer, the SSL is formed in two layers, and the word line may be formed in even layers between the GSL and the SSL. Thus, in one embodiment, the first gate electrode 310 may be the GSL or the SSL.

The gate electrode 310 may include a gate conductive pattern 300, and a gate barrier film pattern 290 surrounding the top and bottom surfaces and at least some of the sidewalls thereof. The gate conductive pattern 300 may include a low electrical resistance metal, such as, for example, tungsten, titanium, tantalum, platinum, and the like. The gate barrier film pattern 290 may comprise a metal nitride, such as, for example, titanium nitride, tantalum nitride, and the like. Alternatively, the gate barrier film pattern 290 may be comprised of a first layer comprising a metal and a second layer comprising a metal nitride.

On the other hand, the top and bottom surfaces of the gate electrode 310 and some sidewalls may be surrounded by the second blocking film pattern 270. Specifically, the second blocking film pattern 270 can cover the gate barrier film pattern 290 of the gate electrode 310. The second blocking film pattern 270 may comprise an oxide, such as, for example, silicon oxide.

The common source line (CSL) 330 may comprise a metal, a metal nitride and / or a metal suicide, and the second spacer (e.g., 320 may comprise a nitride, such as, for example, silicon nitride.

On the other hand, the insulating pad 127 may be formed on one side wall of each gate electrode 310, and the length of the insulating pad 127 in the second direction may gradually decrease from the lower layer to the upper layer. The insulating pad 127 may comprise a nitride, such as, for example, silicon nitride.

A second structure may be formed through the step structure, and the second structure may contact the upper surface of the substrate 100. That is, the second structure may include a semiconductor pattern 160, a first structure, and a capping pattern 230 that are sequentially stacked on a substrate 100, and the first structure may include a semiconductor pattern 160 A first charge storage film structure 200, a channel 210, and a filler film pattern 220 that are sequentially stacked on the first charge storage film structure 200. The second structure may extend in the third direction and pass through the gate electrodes 310 and the insulating film patterns 115 which are alternately repeatedly stacked.

In exemplary embodiments, the second structure may be formed in plurality along the first and second directions, thereby forming a second structure array. Since each of the second structures includes a channel 210 therein, the second structure array will be replaced with a description of a channel array to be described later.

The semiconductor pattern 160 may comprise monocrystalline silicon or monocrystalline germanium and may optionally be doped with impurities. In the exemplary embodiments, the semiconductor pattern 160 is formed such that the upper surface thereof is positioned between the upper surface and the lower surface of the insulating film pattern 115 formed in the second layer from the upper surface of the substrate 100 in the insulating film patterns 115 . Accordingly, the semiconductor pattern 160 can be formed adjacent to the GSL.

The channel 210 may be formed on the semiconductor pattern 160 and may have a cup shape. The channel 210 may comprise doped or undoped polysilicon or amorphous silicon. The channel 210 may be formed in plural along the first and second directions, thereby forming a channel array.

In exemplary embodiments, the channel array may include a first channel column including a plurality of first channels formed along the first direction, and a plurality of second channels formed along the first direction, And a second channel column spaced apart from the first channel column by a predetermined distance in the second direction. At this time, the first channels may be positioned at an acute angle with the first direction or the second direction from the second channels. Accordingly, the first and second channels may be arranged in a zigzag shape with respect to the first direction as a whole. Thus, as the first and second channels are arranged in a zigzag manner, a greater number of channels 210 can be arranged in a unit area.

The first and second channel columns may be alternately and repeatedly arranged along the second direction. In exemplary embodiments, the first and second channel columns may be alternately arranged twice in the second direction to form one channel block including a total of four channel columns. And the channel blocks may be formed to be spaced apart from each other along the second direction. Hereinafter, four channel columns arranged in each channel block are referred to as first, second, third and fourth channel columns in order from the side adjacent to the edge of the uppermost insulating film pattern 115 to the second direction do. In other words, in FIG. 2, two channel blocks spaced apart from each other along the second direction are shown, and each of the channel blocks includes first, second, third and fourth channels sequentially arranged in the second direction Columns.

Unlike the foregoing, the channel array may comprise a plurality of channels 210 arranged differently from the zigzag arrangement.

A tunnel insulating film pattern 190, a charge storage film pattern 180 and a first blocking film pattern 170 may be sequentially stacked on an outer wall of the channel 210. These may form a first charge storage film structure 200 can do. The first charge storage film structure 200 may contact a portion of the second blocking film pattern 270 that surrounds one side wall of the gate electrode 310 and together they may form a second charge storage film structure 280 have. At this time, the first and second blocking film patterns 170 and 270 may form a blocking film pattern structure together. The first charge storage film structure 200 may have a cup shape with an opening at the center of the bottom.

The tunnel insulating layer pattern 190 may comprise an oxide, such as, for example, silicon oxide, and the charge storage layer pattern 180 may comprise a nitride, such as, for example, silicon nitride, 0.0 > 170 < / RTI > may comprise an oxide, such as, for example, silicon oxide.

The filling film pattern 220 may fill the inner space formed by the cup-shaped channel 210. The filler film pattern 220 may comprise an oxide, such as, for example, silicon oxide.

The first structure comprising the first charge storage film structure 200, the channel 210, and the filler film pattern 220 may be formed adjacent to the word line and the SSL.

A capping layer pattern 230 may be formed on the first structure. The capping layer pattern 230 may include impurity-doped or undoped polysilicon or amorphous silicon.

The first interlayer insulating film 100 may be formed on the substrate 100 to cover the sidewalls of the stepped structure. The second interlayer insulating layer 140 may be formed on the first interlayer insulating layer 130 and the step structure and may cover the side walls of the capping layer pattern 230. The third interlayer insulating layer 240 may be formed on the second interlayer insulating layer 140 and the capping layer pattern 230 and may cover the sidewalls of the common source line 330 and the second spacers 320. The fourth interlayer insulating film 340 may be formed on the third interlayer insulating film 240 and the common source line 330. The first to fourth interlayer insulating films 130, 140, 240, and 340 may include an oxide such as silicon oxide, for example, and some or all of them may be combined into a single film. Also, the first and second interlayer insulating films 130 and 140 may be combined with the insulating film pattern 115.

Referring to FIGS. 10 to 12, each first contact plug 380 includes first to fourth interlayer insulating films 130, 140, 240 and 340, an insulating film pattern 115, The gate conductive film pattern 270, and the gate barrier film pattern 290. That is, each of the first contact plugs 380 includes the first to fourth interlayer insulating layers 130, 140, 240, and 340, an insulating layer pattern 115 formed on each of the uncovered steps of the upper layer, The second blocking film pattern 270 under the portion of the insulating film pattern 115 and the gate barrier film pattern 290 and contact with the gate conductive pattern 300. [ At this time, each first contact plug 380 can contact the gate conductive pattern 300 through the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300, and further, the gate conductive pattern 300 ) Can be partially penetrated.

However, the concept of the present invention is not necessarily limited to this, and all of the first contact plugs 380 may be included in the scope of the present invention at least partially in contact with the gate electrode 310. 10, each of the first contact plugs 380 does not pass through the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300 but contacts only the upper surface thereof, or alternatively, The gate conductive pattern 300 may partially penetrate only the portion of the gate barrier film pattern 290 and not contact the gate conductive pattern 300. 11, each of the first contact plugs 380 penetrates a portion of the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300 and the gate conductive pattern 300, It may contact or partially penetrate the portion of the gate barrier film pattern 290 formed on the bottom of the gate conductive pattern 300. 12, each of the first contact plugs 380 includes a gate conductive pattern 300, a gate barrier film pattern 290 portions formed on an upper surface and a lower surface of the gate conductive pattern 300, So that the bottom surface may be located inside the insulating film pattern 115 inside or below the second blocking film pattern 270. [

However, the first contact plug 380, which exposes the gate electrode 310 formed in the uppermost step, may not pass through the first interlayer insulating film 130.

Each first contact plug 380 may be formed at each step portion that is not covered by the upper step steps. In the exemplary embodiments, the first contact plugs 380 may be formed at regular intervals along the first direction. In one embodiment, the first contact plugs 380 may be formed so as to be collinear with one channel column, for example, the second channel column, in each channel block when viewed from above. 13, the first contact plugs 380 are formed to be arranged along the first direction at a center position in the second direction within each of the channel blocks when viewed from above. . That is, the first contact plugs 380 may be formed to be arranged along the first direction at any position in the second direction within one channel block.

Alternatively, the first contact plugs 380 may be formed in a zigzag shape along the first direction.

In one embodiment, the second contact plug 385 includes first to fourth interlayer insulating films 130, 140, 240 and 340, an insulating film pattern 115, a second blocking film pattern 270, And can contact the gate conductive pattern 300 included in the first gate electrode 310 through the film pattern 290. However, the concept of the present invention is not necessarily limited to this. That is, the second contact plug 385 may contact or partially penetrate the upper surface of the portion of the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300, similarly to the first contact plug 380 And may be in contact with or partially penetrating the gate barrier film pattern 290 formed on the bottom of the gate conductive pattern 300. The gate conductive pattern 300 and the gate barrier film 290 formed on the top and bottom surfaces thereof The bottom surface of the pattern 290 may be located inside the insulating film pattern 115 inside or below the second blocking film pattern 270.

However, unlike the first contact plugs 380, the second contact plugs 385 may not contact the gate electrode 310. 9B, the second contact plug 385 contacts only the upper surface or the inner part of the portion of the second blocking film pattern 270 formed on the upper surface of the gate electrode 310, and does not contact the gate electrode 310 Further, the bottom surface may be located in the upper insulating film pattern 115 and may not contact the second blocking film pattern 270.

In exemplary embodiments, a second contact plug 385 may be formed on the first gate electrode 310 to be adjacent to a first contact plug 380 formed on the first gate electrode 310, The first contact plugs 380 may be spaced apart from the first contact plugs 380 formed in the first direction on the first gate electrode 310 in the same manner as spaced apart from one another along the first direction. That is, the first and second contact plugs 380 and 385 may be formed on the same line at regular intervals along the first direction. Alternatively, when the first contact plugs 380 are formed in a zigzag shape along the first direction, the first and second contact plugs 380 and 385 may also be formed in a zigzag shape along the first direction as a whole .

As described above, the first gate electrode 310 may be formed not only in the lowermost layer step but also in the uppermost layer step, may be formed in any layer step, or may be formed in a plurality of layers. Accordingly, the second contact plug 385 formed on the first gate electrode 310 may also have its bottom surface formed in the lowest step, the uppermost step, or an arbitrary layer step, and further, a plurality of second contact plugs 285 may be formed. A plurality of second contact plugs 385 may be formed on each of the first gate electrodes 310 as well as one second contact plug 385.

Hereinafter, for convenience of description, the case where the first step is the lowest step and only one second contact plug 385 is formed at the first step will be described.

The first contact plug 380 may include a first conductive pattern 370 and a first barrier film pattern 360 surrounding the bottom and side walls of the first contact plug 380 and the second contact plug 385 may include a second conductive pattern 375, and a second barrier film pattern 365 surrounding the bottom and sidewalls thereof. The first barrier layer pattern 360 may include a metal such as titanium nitride, tantalum nitride, tungsten nitride, or the like. The first barrier pattern 360 may include a metal such as tungsten, titanium, tantalum, Nitride. ≪ / RTI > Alternatively, the first barrier film pattern 360 may be formed of a multilayer film composed of a metal film and a metal nitride film.

The fifth to eighth interlayer insulating films 390, 430, 560 and 630 may be sequentially stacked on the fourth interlayer insulating film 340 and the first and second contact plugs 380 and 385, For example, an oxide such as silicon oxide. Accordingly, the fifth to eighth interlayer insulating films 390, 430, 560, and 630 may be partially or wholly merged into a single film, or may be merged with the fourth interlayer insulating film 340 disposed below.

The first through sixth wiring lines 420, 425, 460, 465, 660, 690 and the first through sixth vias 490, 495, 550, 555, 590, 620 each have a conductive pattern, And a barrier film pattern surrounding the sidewalls. The conductive pattern may include a metal such as copper, aluminum, tungsten, titanium, or tantalum. The barrier pattern may include a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride . Alternatively, the barrier film pattern may be formed of a multilayer film composed of a metal film and a metal nitride film.

Specifically, the first and second wirings 420 and 425 may be in contact with the upper surfaces of the first and second contact plugs 380 and 385 through the fifth interlayer insulating film 390. The first wiring 420 may include a third conductive pattern 410 and a third barrier film pattern 400 surrounding the bottom and side walls of the third conductive pattern 410. The second wiring 425 may include a fourth conductive pattern 415, And a fourth barrier film pattern 405 surrounding the bottom and sidewalls thereof.

In the exemplary embodiments, the first wirings 420 may extend in the second direction, and may be formed in plural along the first direction. Also, the second wiring 425 may extend in the first direction. At this time, the first wirings 420 may contact the upper surface of the first contact plug 380, and the second wirings 425 may contact the first and second contact plugs 380 and 385 ) ≪ / RTI >

Each of the first wirings 420 may extend in the second direction so as to contact the upper surface of the first contact plugs 380 formed on a part of the plurality of channel blocks formed along the second direction. In one embodiment, each of the first wirings 420 extends in the second direction and contacts the upper surface of the first contact plugs 380 formed on the four channel blocks adjacent to each other in the second direction . The second wiring 425 may extend in the first direction and may be connected to a wiring (not shown) formed in the second region II so that an electrical signal can be applied.

The third and fourth wirings 460 and 465 may penetrate the upper portion of the sixth interlayer insulating film 430 and the first and second vias 490 and 495 may penetrate the upper portion of the sixth interlayer insulating film 430 And may contact the upper surfaces of the first and second wirings 420 and 425, respectively.

The third wiring 460 may include a fifth conductive pattern 450 and a fifth barrier film pattern 440 surrounding a portion of the side wall and the bottom of the fifth conductive pattern 450. The fourth wiring 465 may include a sixth conductive pattern 450, A second barrier layer pattern 455, and a sixth barrier layer pattern 445 that surrounds a portion of the sidewall and bottom thereof. The first via 490 may include a seventh conductive pattern 480 and a seventh barrier film pattern 470 surrounding the bottom and sidewalls thereof and the second via 495 may include an eighth conductive pattern 485, and an eighth barrier film pattern 475 surrounding the bottom and sidewalls thereof. The sequentially stacked first vias 490 and the third wirings 460 may be integrally formed, and the second vias 495 and the fourth wirings 465 sequentially stacked may also be integrally formed As shown in FIG.

In the exemplary embodiments, the third wiring 460 may extend in the second direction, and may be formed along the first direction. Further, the fourth wiring 465 may extend in the first direction. The third wirings 460 may be electrically connected to the first wirings 420 through the first vias 490 and the fourth wirings 465 may be electrically connected to the first wirings 420 through the second vias 495. [ 1 wirings 420, respectively.

In one embodiment, each of the third wires 460 may extend in the second direction and may be formed on four adjacent channel blocks in the second direction. The fourth wiring 465 may extend in the first direction and may be connected to a wiring (not shown) formed in the second region II, and thus an electrical signal may be applied.

The first and second connection wirings 520 and 525 may penetrate the upper portion of the sixth interlayer insulating film 430 and the third and fourth vias 550 and 555 may penetrate the upper portion of the sixth interlayer insulating film 430. [ 340, and 390, and may contact the upper surface of the capping pattern 230. In this case,

The first connection wiring 520 may include a ninth conductive pattern 510 and a ninth barrier layer pattern 500 surrounding a side wall and a part of the bottom of the ninth conductive pattern 510. The second connection wiring 525 may include a tenth conductive pattern 510, A conductive pattern 515, and a tenth barrier film pattern 505 that surrounds a portion of the side wall and the bottom of the conductive pattern 515. The third vias 550 may include an eleventh conductive pattern 540 and an eleventh barrier layer pattern 530 surrounding the bottom and sidewalls thereof and the fourth via 555 may include a twelfth conductive pattern 545, and a twelfth barrier film pattern 535 surrounding the bottom and sidewalls thereof. However, the third vias 550 and the first connection wirings 520, which are sequentially stacked, may be integrally formed, and the fourth vias 555 and the second connection wirings 525 sequentially stacked may also be formed And can be integrally formed.

The third and fourth vias 550 and 555 may be formed on the capping pattern patterns 230 formed on the channels 210 respectively and the first and second connection wirings 520 and 525 Extend in the second direction, and may be electrically connected to the third and fourth vias 550 and 555, respectively. Accordingly, the first and second connection wirings 520 and 525 are formed by the common source line (CSL) 330 and the channels 210, respectively, included in the two channel blocks spaced from each other in the second direction They can be electrically connected to each other. In the exemplary embodiments, the first connection wiring 520 includes channels 210 included in the third and fourth channel columns of the first channel block, And the channels 210 included in the first and second channel columns of the second channel block may be connected to each other. In addition, the second connection wiring 525 may include channels 210 included in the third and fourth channel columns of the second channel block, and a third channel block, which is spaced apart from the second channel block in the second direction, And the channels 210 included in the first and second channel columns of the first and second channel columns.

The fifth and sixth vias 590 and 620 can be in contact with the upper surface of the third wiring 460 and the first and second connection wirings 520 and 525 through the seventh interlayer insulating film 560 have.

The fifth vias 590 may include a thirteenth conductive pattern 580 and a thirteen barrier film pattern 570 surrounding the sidewalls and the bottom of the thirteenth conductive pattern 580. The sixth via 620 may include a fourteenth conductive pattern 580, 610), and a fourteenth barrier film pattern 600 surrounding the side and bottom surfaces thereof.

The fifth and sixth wirings 660 and 690 may penetrate the eighth interlayer insulating film 630 and contact the upper surfaces of the fifth and sixth vias 590 and 620, respectively.

The fifth wiring 660 may include a fifteenth conductive pattern 650 and a fifteenth barrier film pattern 640 surrounding the sidewalls and the bottom of the fifth wiring 660. The sixth wiring 690 may include a sixteenth conductive pattern 680, and a sixteenth barrier film pattern 670 surrounding the side and bottom surfaces thereof. In the exemplary embodiments, the fifth wiring 660 may extend in the first direction and may be connected to a wiring (not shown) formed in the second region II, whereby an electrical signal may be applied . That is, an electrical signal applied from the wiring in the second region II is electrically connected to the fifth wiring 660, the fifth via 590, the third wiring 460, the first via 490, and the first wiring 420 To the first contact plug 380 through the first contact plug 380. [ In the exemplary embodiments, the sixth wiring 690 may extend in the second direction and may include a sixth via 620, first and second connection interconnections 520 and 525, 4 vias 550, 555, and a capping pattern 230. In this embodiment, At this time, the sixth wiring 690 may perform a bit line function.

As described above, the vertical memory device includes, in addition to the first contact plug 380, a first contact plug 380 on the first gate electrode 310 among the plurality of gate electrodes 310 stacked along the direction perpendicular to the upper surface of the substrate 100, A second contact plug 385 may be further formed. The patterning phenomenon is prevented by the second contact plug 385, as described in the manufacturing method described later, so that each first contact plug 380 can be formed to have a desired size and / or shape, The gate electrode 310 of FIG.

The second contact plug 385 formed in the vertical memory device and the first and second wirings 420 and 425 electrically connected to the second contact plug 385 may be implemented in various forms. This will be described later with reference to FIG.

Hereinafter, a method of manufacturing a vertical type memory device according to exemplary embodiments will be described. Hereinafter, a method of manufacturing the vertical memory device will be described with reference to FIGS. 14 to 44 showing the X region in the first region I shown in FIG.

14 to 44 are plan views and sectional views for explaining a method of manufacturing the vertical memory device. 14, 16, 18, 20, 22, 24, 29, 31, 33, 35, 37 and 42 are plan views and FIGS. 15, 17, 19, 21, 23, 25-28, 30, 32, 34, 36, 38-41 and 43-44 are cross-sectional views. Figs. 15, 17, 19, 21, 23, 25, 27, 30 and 38 are cross-sectional views taken along the line A-A ' 40 is a cross-sectional view taken along the line C-C 'in the corresponding plan view, and FIGS. 41 and 43 are cross-sectional views taken along the line B-B' of corresponding corresponding plan views, And FIG. 44 is a cross-sectional view taken along the line E-E 'in the corresponding plan view.

14 and 15, an insulating film 110 and a sacrificial film 120 are alternately and repeatedly laminated on a substrate 100. [ Accordingly, a plurality of insulating films 110 and a plurality of sacrificial films 120 may be alternately stacked along the third direction. Although FIG. 1 exemplarily shows eight layers of insulating films 110 and seven layers of sacrificial films 120 alternately formed on a substrate 100, an insulating film 110 and a sacrificial layer 120 are not limited thereto, but may be formed in a larger number or a smaller number, respectively.

The substrate 100 may comprise a semiconductor material such as silicon, germanium, or the like.

The insulating layer 110 and the sacrificial layer 120 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition : ALD) process. In particular, in the case of the lowermost insulating film 110 formed directly on the upper surface of the substrate 100, the lower insulating film 110 may be formed by a thermal oxidation process on the upper surface of the substrate 100.

The insulating film 110 may be formed to include silicon oxide such as, for example, PE-TEOS (PE-TEOS), high-density plasma (HDP) oxide, or PEOX. The sacrificial layer 120 may be formed to include a material having an etch selectivity to the insulating layer 110, for example, silicon nitride.

16 and 17, a photoresist pattern (not shown) partially covering the insulating film 110 formed on the uppermost layer is formed on the uppermost insulating film 110, and then the uppermost insulating film 110 And the uppermost sacrificial layer 120 at the lower part thereof are etched. Accordingly, a part of the insulating film 110 formed under the uppermost sacrificial film 120 can be exposed. The uppermost sacrificial layer 120, the exposed insulating layer 110, and the sacrificial layer 110 under the sacrificial layer 110 are etched using an etch mask to reduce the area of the photoresist pattern, And then performing a trimming process to etch again. By repeating the trimming process, a step structure including a plurality of stepped portions each composed of the sequentially stacked sacrificial pattern 125 and the insulating film pattern 115 can be formed.

At this time, the steps included in the step structure may have an area decreasing at a constant rate from the lower layer to the upper layer. Thus, the stairs may be reduced in length in the first and second directions from the lower layer to the upper layer by a predetermined width, and the first, second, And the lengths in the second directions may be constant. However, in exemplary embodiments, the length of each of the first and second directions of the portion that is not covered by the stairs formed in the upper layer at the lowest layer of the stairs, May be formed so as to be larger than the lengths in the first and second directions of the portion exposed without being covered by the steps formed in the upper layer in the steps. This can be realized by adjusting the ratio of reducing the area of the photoresist pattern in the trimming process. In exemplary embodiments, the length in the first direction of the portion exposed at the lowest step may be at least twice the length in the first direction of the portion exposed at each step formed in the remaining layers.

16 and 17 illustrate that the length of the exposed portion of the lowest step is relatively larger than the length of the exposed portion of the step formed on the other layer, but the concept of the present invention is not necessarily limited thereto. 31 and 32) need to be formed in addition to the first contact holes 350 (see FIGS. 31 and 32), the exposure of the step formed in the other layer other than the lowest step And a step having a relatively long length of the relatively exposed portion will be referred to as a first step. In the exemplary embodiments, the first step may be formed in any layer as well as the lowermost layer, or may be formed in plural.

On the other hand, when the number of stacks of the insulating film 110 and the sacrificial film 120 is large, the trimming process may be performed using two or more photoresist patterns (not shown). That is, due to the limitation of the thickness of one photoresist pattern, the trimming process is performed by using the photoresist pattern as an etch mask. Therefore, a plurality of photoresist patterns are sequentially used to perform the trimming process as many times as a whole The insulating film pattern 115 and the sacrificial film pattern 125 may be formed by etching the insulating film 110 and the sacrificial film 120 stacked in a large number.

In the case of using a plurality of photoresist patterns as described above, the ratio of reducing the area of the photoresist pattern at the time of trimming must be at least partially reduced in order to make the length of the exposed portion of the step formed in another layer other than the lowermost layer relatively large. . For example, after the trimming process is performed a plurality of times while reducing the area of the first photoresist pattern to a constant size, a step is formed in which a relatively long portion is exposed by adjusting the area of the second photoresist pattern used next Then, a step structure can be formed by performing a trimming process a plurality of times while reducing the area of the second photoresist pattern to be constant.

18 and 19, a first interlayer insulating film 130 covering the step structure is formed on a substrate 100, and a first interlayer insulating film 130 is formed on the substrate 100 until the upper surface of the uppermost insulating film pattern 115 of the step structure is exposed. The upper surface of the interlayer insulating film 130 is planarized.

At this time, the first interlayer insulating film 130 may be formed to include an oxide such as silicon oxide, for example, and may be combined with the insulating film pattern 115. The planarization process may be performed through a chemical mechanical polishing (CMP) process and / or an etch back process. However, since the first interlayer insulating layer 130 may be relatively high on the portion where the step structure is formed, the planarization process may be performed after the first interlayer insulating layer 130 is etched.

20 and 21, a second interlayer insulating layer 140 is formed on the step structure and the first interlayer insulating layer 130, and then a photolithography process using a photoresist pattern (not shown) is performed . Accordingly, a plurality of channel holes 150 that expose the upper surface of the substrate 100 can be formed through the second interlayer insulating film 140, the insulating film patterns 115, and the sacrificial film patterns 125 have.

At this time, the second interlayer insulating film 140 may be formed to include an oxide such as silicon oxide, for example, and may be incorporated into the first interlayer insulating film 130 and / or the uppermost insulating film pattern 115 .

In the exemplary embodiments, channel holes 150 may be formed along the first and second directions, respectively, so that a channel hole array may be defined. In exemplary embodiments, the channel hole array may include a first channel hole column including a plurality of first channel holes formed along the first direction, and a plurality of second channel hole columns formed along the first direction, And a second channel hole array including two channel holes and spaced apart from the first channel hole column in the second direction by a predetermined distance. At this time, the first channel holes may be located at an acute angle to the first direction or the second direction from the second channel holes. Accordingly, the first and second channel holes may be arranged in a zigzag shape with respect to the first direction as a whole. As the first and second channel holes are arranged in a zigzag manner, a larger number of channel holes 150 can be arranged in a unit area.

The first and second channel hole rows may be alternately and repeatedly arranged along the second direction. In the exemplary embodiments, the first and second channel hole sequences are alternately arranged twice along the second direction to form one channel hole block including a total of four channel hole sequences. And the plurality of channel hole blocks may be spaced apart from each other along the second direction. Hereinafter, the four channel hole arrays arranged in the respective channel hole blocks are arranged in the first, second, third and fourth channel hole arrays in order from the side adjacent to the edge of the uppermost insulating film pattern 115 to the second direction . That is, FIG. 20 shows two channel hole blocks spaced apart from each other along the second direction, and each of the channel hole blocks is divided into first, second, third, and fourth And includes four channel hole rows.

Unlike the above, the channel hole array may include a plurality of channel holes 150 arranged differently from the zigzag arrangement.

Referring to FIGS. 22 and 23, a semiconductor pattern 160 is formed, which partially fills each of the channel holes 150.

Specifically, a selective epitaxial growth (SEG) process using the upper surface of the substrate 100 exposed by the channel holes 150 as a seed is performed to partially fill the channel holes 150 The semiconductor pattern 160 can be formed. Accordingly, the semiconductor pattern 160 may be formed to include monocrystalline silicon or single-crystal germanium depending on the material of the substrate 100, and in some cases, impurities may be doped. Alternatively, after the amorphous silicon film filling the channel holes 150 is formed, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process is performed on the amorphous silicon film The semiconductor pattern 160 may be formed. In the exemplary embodiments, the semiconductor pattern 160 is formed such that the upper surface thereof is positioned between the upper surface and the lower surface of the insulating film pattern 115 formed in the second layer from the upper surface of the substrate 100 in the insulating film patterns 115 .

Thereafter, a first blocking film, a charge storage film, a tunnel insulating film, and a first spacer film (not shown) are formed on the inner walls of the channel holes 150, the upper surface of the semiconductor pattern 160 and the upper surface of the second interlayer insulating film 140 (Not shown) that remains only on the inner walls of the channel holes 150 are formed by anisotropically etching the first spacer film, and then the first spacer is used as an etch mask A tunnel insulating film pattern 190 having a cup-shaped central opening at the bottom of each of the inner walls of the channel holes 150 and the semiconductor pattern 160 by etching the tunnel insulating film, the charge storage film, and the first blocking film, The storage film pattern 180 and the first blocking film pattern 170 may be formed. At this time, the upper portion of the semiconductor pattern 160 can also be partially removed together. The tunnel insulating film pattern 190, the charge storage film pattern 180, and the first blocking film pattern 170 may form the first charge storage film structure 200.

The first blocking film may be formed to include an oxide such as, for example, silicon oxide, and the charge storage film may be formed to include nitride, for example, silicon nitride. The tunnel insulating film may be formed, for example, , An oxide such as silicon oxide, and the first spacer film may be formed to include a nitride such as, for example, silicon nitride.

A channel film is formed on the exposed semiconductor pattern 160, the tunnel insulating film pattern 190 and the second interlayer insulating film 140, and a filling process is performed to fill the remaining portions of the channel holes 150 A film is formed on the channel film.

The channel film may be formed to include impurity-doped or undoped polysilicon or amorphous silicon. When the channel film is formed to include amorphous silicon, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process may be further performed to convert the channel film to crystalline silicon. The filling film may be formed to include an oxide such as, for example, silicon oxide.

Thereafter, the filling film and the channel film are planarized until the upper surface of the second interlayer insulating film 140 is exposed, thereby forming a filling film pattern 220 filling the remaining portions of the respective channel holes 150, The channel film may be converted to channel 210.

Accordingly, the first charge storage film structure 200, the channel 210, and the filling film pattern 220 may be sequentially stacked on the semiconductor pattern 160 in each of the channel holes 150. At this time, the first charge storage film structure 200 may be formed into a cup shape with the center of the bottom thereof being opened, the channel 210 may be formed into a cup shape, and the filling film pattern 220 may be formed into a pillar shape .

The channel holes 150 in which the channel 210 is formed define a channel hole block including the first through fourth channel hole columns and the channel hole array including the plurality of channel hole blocks, Corresponding to this, a channel block and a channel array can be defined.

Thereafter, the upper portion of the first structure consisting of the filler film pattern 220, the channel 210, and the first charge storage film structure 200 is removed to form a trench (not shown) Thereby forming a thin film pattern 230.

Specifically, the upper portion of the first structure is removed through an etch-back process to form the trench, and then a capping layer filling the trench is formed on the first structure and the second interlayer insulating layer 140, The upper portion of the capping layer may be planarized until the upper surface of the insulating layer 140 is exposed to form the capping layer pattern 230. In exemplary embodiments, the capping film may be formed to include polysilicon or amorphous silicon doped with or without doping, and when the capping film is formed to include amorphous silicon, .

Since the capping layer pattern 230 is formed on each of the channels 210, a capping pattern block and a capping pattern array may be formed corresponding to the channel block and the channel array, respectively.

The first structure, the semiconductor pattern 160, and the capping pattern 230 formed in the respective channel holes 150 may define a second structure.

24 to 26, after the third interlayer insulating layer 240 is formed on the second interlayer insulating layer 140 and the capping layer pattern 230, the second and third interlayer insulating layers 140 and 240 are formed, The insulating film patterns 115 and the sacrificial film patterns 125 to expose the upper surface of the substrate 100.

At this time, the third interlayer insulating film 240 may be formed to include an oxide such as silicon oxide, for example, and may be combined with the second interlayer insulating film 140.

According to exemplary embodiments, the openings 250 may be formed to extend along the first direction between the channel blocks, and may be formed along the second direction. Accordingly, although four channel columns may be formed between two adjacent openings 250, the concept of the present invention is not necessarily limited thereto. That is, the number of channel columns formed between adjacent two openings 250 may vary depending on the number of channel columns included in the channel blocks.

Thereafter, the sacrificial film patterns 125 exposed by the openings 250 may be removed to form a gap 260 between the insulation film patterns 115 of each layer, A part of the outer wall of the blocking film pattern 170 and a part of the side wall of the semiconductor pattern 160 may be exposed. According to exemplary embodiments, the sacrificial film patterns 125 exposed by the opening 250 may be removed through a wet etching process using an etchant containing phosphoric acid or sulfuric acid.

However, the portion of the sacrificial film pattern 125 formed in the step portion remote from the opening 250 in the second direction may remain without being removed by the wet etching process, and hereinafter, they may be referred to as an insulating pad 127 .

27 and 28, the outer wall of the exposed first blocking film pattern 170, the sidewall of the exposed semiconductor pattern 160, the inner wall of the gap 260, the surface of the insulating film patterns 115, A second blocking film is formed on the upper surface of the third interlayer insulating film 240 and the upper surface of the third interlayer insulating film 240 and a gate barrier film is formed on the second blocking film and then a gate conductive film Is formed on the gate barrier film.

The second blocking film may be formed to include metal oxides such as aluminum oxide, hafnium oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, and zirconium oxide. The gate conductive film may be formed to include a low electrical resistance metal such as tungsten, titanium, tantalum, and platinum. The gate barrier film may be formed to include, for example, a metal nitride such as titanium nitride, tantalum nitride, or the like. Alternatively, the gate barrier film may consist of a first layer comprising a metal and a second layer comprising a metal nitride.

The gate conductive film and the gate barrier film may be partially removed to form a gate conductive pattern 300 and a gate barrier film pattern 290 in the gap 260, Can be formed. According to exemplary embodiments, the gate conductive film and the gate barrier film can be partially removed through a wet etching process.

In the exemplary embodiments, the gate electrode 310 may extend in the first direction, and may be formed along the second direction. That is, the plurality of gate electrodes 310 extending in the first direction may be spaced apart from each other by the openings 250. Meanwhile, the gate electrode 310 formed at the first step among the plurality of gate electrodes 310 may be referred to as a first gate electrode 310.

The gate electrode 310 may include a GSL, a word line, and a SSL formed sequentially along the third direction. At this time, each GSL, word line, and SSL may be formed in one or a plurality of layers. In addition, one or more dummy word lines may be formed between the GSL and the word line and / or between the SSL and the word line.

In exemplary embodiments, the GSL is formed in one layer, the SSL is formed in two layers, and the word line may be formed in even layers between the GSL and the SSL. Accordingly, the GSL may be formed adjacent to the semiconductor pattern 160, and the word line and the SSL may be formed adjacent to the channel 210.

On the other hand, when the gate conductive film and the gate barrier film are partially removed, the upper surface of the insulating film patterns 115, the upper surface of the substrate 100, the upper surface of the capping film pattern 230 and the upper surface of the third interlayer insulating film 240 The second blocking film portion may be removed together, thereby forming the second blocking film pattern 270 that covers the upper surface, the bottom surface, and at least one side wall of the gate electrode 310. The first and second blocking film patterns 170 and 270 can form a blocking film pattern structure together and the tunnel insulating film pattern 190, the charge storage film pattern 180, A second charge storage film structure 280 may be formed.

Meanwhile, as the gate conductive film, the gate barrier film, and the second blocking film are partially removed, the opening 250 exposing the upper surface of the substrate 100 and extending in the first direction may be formed again.

Referring to FIGS. 29 and 30, the impurity region 105 may be formed by implanting impurities on the exposed substrate 100. According to exemplary embodiments, the impurity may comprise an n-type impurity such as phosphorus, arsenic.

Thereafter, a second spacer film is formed on the upper surface of the impurity region 105, the side wall of the opening 250 and the upper surface of the third interlayer insulating film 240, and then the second spacer film is subjected to anisotropic etching, The second spacers 320 may be formed so that the impurity regions 105 formed on the substrate 100 may be partially exposed. The second spacer film may be formed to include an oxide such as, for example, silicon oxide.

Forming a common source line (CSL) 330 that fills the remaining portion of the opening 250 on the exposed impurity region 105. According to exemplary embodiments, a conductive film filling the opening 250 is formed on the exposed impurity region 105, the second spacer 320, and the third interlayer insulating film 240, and then the third interlayer insulating film 240 (CSL) 330 can be formed by planarizing the upper portion of the conductive film until the upper surface of the common source line (CSL) 330 is exposed. The conductive film may be formed to include a metal, a metal nitride, and / or a metal silicide.

31 and 32A, a fourth interlayer insulating film 340 is formed on the third interlayer insulating film 240 and the common source line (CSL) 330, and a photo using a photoresist pattern (not shown) The first and second contact holes 350 and 355 may be formed by performing an etching process.

Each of the first contact holes 350 includes first through fourth interlayer insulating films 130 140 and 240 340, an insulating film pattern 115, a second blocking film pattern 270, and a gate barrier film pattern 290, So as to expose the gate conductive pattern 300. That is, each of the first contact holes 350 includes the first to fourth interlayer insulating films 130, 140, 240, and 340, a portion of the insulating film pattern 115 formed on each step portion that is not covered by the upper step, The second blocking film pattern 270 under the insulating film pattern 115 and the gate barrier film pattern 290 to expose the gate conductive pattern 300. [ Each of the first contact holes 350 may expose the gate conductive pattern 300 through the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300, The upper part can also partially penetrate.

However, the concept of the present invention is not necessarily limited to this, and all of the first contact holes 350 may be included in the scope of the present invention if they are formed to at least partially expose the gate electrode 310. That is, in one embodiment, each first contact hole 350 does not penetrate the portion of the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300, but expose only the upper surface thereof, The gate conductive pattern 300 may not be exposed by partially penetrating the pattern 290 portion. Each of the first contact holes 350 penetrates through the gate conductive pattern 300 and the portion of the gate conductive film pattern 290 formed on the upper surface of the gate conductive pattern 300, Or may partially penetrate the portion of the gate barrier film pattern 290 that is formed on the gate insulating film pattern 290. In yet another embodiment, each first contact hole 350 may pass through both the gate conductive pattern 300, the top surface of the gate conductive pattern 300, and the gate barrier film pattern 290 portions formed on the bottom surface, The bottom face may be located inside the insulating film pattern 115 inside or below the second blocking film pattern 270.

However, the first contact hole 350 for exposing the gate electrode 310 formed in the uppermost step may not pass through the first interlayer insulating film 130.

Each of the first contact holes 350 may be formed at each step portion that is not covered by the upper step steps. In the exemplary embodiments, the first contact holes 350 may be formed at regular intervals along the first direction. In one embodiment, the first contact holes 350 may be formed so as to be aligned with one channel column, for example, the second channel column, in each channel block when viewed from above. In another embodiment, the first contact holes 350 may be formed to be arranged along the first direction at a center position in the second direction within the respective channel blocks when viewed from above. That is, the first contact holes 350 may be formed to be arranged along the first direction at an arbitrary position in the second direction within one channel block.

Alternatively, the first contact holes 350 may be formed in a zigzag shape along the first direction.

In one embodiment, the second contact hole 355 includes first to fourth interlayer insulating films 130, 140, 240 and 340, an insulating film pattern 115, a second blocking film pattern 270, May be formed to penetrate the film pattern 290 and expose the gate conductive pattern 300 formed in the first step. However, the concept of the present invention is not necessarily limited to this. That is, the second contact hole 355 may expose the upper surface of the gate barrier film pattern 290 formed on the upper surface of the gate conductive pattern 300, or may penetrate a portion thereof, similarly to the first contact hole 350 And may expose or partially penetrate the portion of the gate barrier film pattern 290 formed on the bottom surface of the gate conductive pattern 300. The gate conductive pattern 300 may include a gate conductive pattern 300 and a gate formed on the top and bottom surfaces thereof. The bottom of the barrier film pattern 290 may be entirely penetrated and the bottom of the barrier film pattern 290 may be located in the insulating film pattern 115 inside or below the second blocking film pattern 270.

However, unlike the first contact holes 350, the second contact hole 355 may not expose the gate electrode 310. 32B, the second contact hole 355 partially exposes only the upper surface or the inner part of the portion of the second blocking film pattern 270 formed on the upper surface of the gate electrode 310, and the gate electrode 310 is exposed The bottom surface of the second insulating film pattern 115 may be located in the upper insulating film pattern 115 and may not expose the second blocking film pattern 270.

In exemplary embodiments, a second contact hole 355 may be formed in the first step adjacent to the first contact hole 350 formed in the first step, and the first contact holes 350 may be formed in the first step, And may be spaced apart from the first contact holes 350 formed in the first step in the first direction in the same manner as the spaced apart intervals along the first direction. That is, the first and second contact holes 350 and 355 may be formed at regular intervals in the same direction along the first direction as a whole. Alternatively, when the first contact holes 350 are formed in a zigzag shape along the first direction, the first and second contact holes 350 and 355 may be formed in a zigzag shape along the first direction as a whole .

The first contact holes 350 may be formed by forming a photoresist pattern having holes therein and etching the underlying films using the photoresist pattern as an etching mask. However, due to the difference in density of the patterns to be formed, the patterns formed on the edges may not be formed in the same size and / or shape as the patterns formed in the center, which is known as pattern loading phenomenon. That is, when forming the holes in the photoresist pattern, the holes formed at the edges may have different sizes and / or shapes from the holes formed at the center, for example, smaller than the holes.

The first to fourth interlayer insulating films 130, 140, 240, and 340 are etched using the photoresist pattern having the holes as an etch mask to form first contact holes 350 so as to partly penetrate each step, The first contact holes 350 partially penetrating the lowest step are formed in the first contact holes 350 and the second contact holes 350 in the second contact holes 350. Therefore, It may be difficult to have a desired depth and / or width compared to the first contact holes 350 partially penetrating the steps formed in the layer.

Therefore, when only the first contact holes 350 are formed without forming the second contact holes 355, the first contact holes 350 formed at the edges along the first direction, that is, the uppermost step and the lowermost step The first contact holes 350 formed may be formed to have a desired depth and / or width by the pattern loading phenomenon. In particular, the first contact holes 350 formed at the lowermost step, And / or a width.

However, in exemplary embodiments, a second contact hole 355 may be formed adjacent to the first contact hole 350 formed in the lowest step to prevent the pattern loading phenomenon, The first contact hole 350 may have a desired depth and / or width. Accordingly, the lowest step, that is, the first step, in which the second contact hole 355 is formed in addition to the first contact hole 350, can be formed in a relatively short distance along the first direction as described with reference to FIGS. And can be formed to have a large length. Of course, the first contact hole 350 may be formed in the uppermost step in place of or in addition to the lowest step. However, the second contact hole 355 may be formed to have a size and / or shape different from that of the first contact holes 350 due to the pattern loading phenomenon or the depth difference.

Meanwhile, the first contact holes 350 formed in the middle layer steps as well as the first contact holes 350 formed in the lowest step or the uppermost step may be formed in accordance with a process order or a process condition in the actual etching process. Depth and / or width, and a second contact hole 355 may be further formed in the middle layer steps to prevent this. For example, when the first contact holes 350 are formed without dividing into the upper and lower stepped portions, the first contact holes 350 formed at the middle layer step, as well as the lowest step or the uppermost step, May not have a desired depth and / or width, and thus the second contact hole 355 may be formed in the middle layer step. However, in this case, in one embodiment, the first and second contact plugs 380 and 385, which will be described later, are formed to fill the first and second contact holes 350 and 355 formed in the lower layer steps The first and second contact plugs 380 and 380 are formed so as to form a separate interlayer insulating film (not shown) covering them, and to fill the first and second contact holes 350 and 355 formed in the upper step steps, , And 385 may be formed.

That is, the first step having a relatively large length may include not only the lowest step but also a middle layer step or a plurality of steps, and the second contact holes 355 are formed in the first steps . In the exemplary embodiments, a plurality of second contact holes 355 may be formed in each of the first steps as well as one second contact hole 355.

Hereinafter, for convenience of explanation, only the case where the first step has the lowest step and the second step has a second contact hole 355 will be described.

Referring to FIGS. 33 and 34, first and second contact plugs 380 and 385 are formed to fill the first and second contact holes 350 and 355, respectively.

In the exemplary embodiments, the first and second contact plugs 380 and 385 include portions of the gate electrode 310 exposed by the first and second contact holes 350 and 355, A first barrier film is formed on the inner walls of the contact holes 350 and 355 and on the fourth interlayer insulating film 340 and the remaining portions of the first and second contact holes 350 and 355 are formed on the first barrier film The first conductive film and the first barrier film may be planarized until the upper surface of the fourth interlayer insulating film 340 is exposed after the first conductive film is formed.

The first conductive layer may be formed to include a metal such as tungsten, titanium, or tantalum, and the first barrier layer may be formed to include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like. have. Alternatively, the first barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

A first contact plug 380 filling each first contact hole 350 may be formed to include a first conductive pattern 370 and a first barrier layer pattern 360 surrounding the bottom and side walls of the first conductive pattern 370, A second contact plug 385 filling the second contact hole 355 may be formed to include a second conductive pattern 375 and a second barrier film pattern 365 surrounding the bottom and side walls thereof.

On the other hand, depending on the arrangement shape of the first and second contact holes 350 and 355, the first and second contact plugs 380 and 385 may be similarly arranged. In exemplary embodiments, the height of the bottom surface of the first and second contact plugs 380 and 385 may be different, but the height of the top surface thereof may be substantially the same.

35 and 36, after a fifth interlayer insulating film 390 is formed on the fourth interlayer insulating film 340 and the first and second contact plugs 380 and 385, a fifth interlayer insulating film 390 And the first and second wirings 420 and 425 are formed to contact the upper surfaces of the first and second contact plugs 380 and 385.

The fifth interlayer insulating film 390 may be formed to include an oxide such as, for example, silicon oxide, and may be incorporated into the fourth interlayer insulating film 340. [

The first and second wirings 420 and 425 may include first and second openings (not shown) that penetrate the fifth interlayer insulating film 390 to expose the upper surfaces of the first and second contact plugs 380 and 385 And forming a third barrier film on the exposed upper surfaces of the first and second contact plugs 380 and 385, the inner wall of the first and second openings, and the fifth interlayer insulating film 390 A third conductive film is formed on the third barrier film to fill the remaining portions of the first and second openings and the third conductive film and the third conductive film are formed on the third interlayer insulating film until the upper surface of the fifth interlayer insulating film 390 is exposed. And may be formed by planarizing the barrier film.

The third conductive layer may include a metal such as copper, aluminum, tungsten, titanium, or tantalum, and the third barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like. . Alternatively, the third barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

The first wiring 420 filling the first opening may be formed to include a third conductive pattern 410 and a third barrier film pattern 400 surrounding the bottom and side walls of the third conductive pattern 410, The second wiring 425 may be formed to include a fourth conductive pattern 415 and a fourth barrier film pattern 405 surrounding the bottom and side walls of the fourth conductive pattern 415.

In the exemplary embodiments, the first wirings 420 may extend in the second direction, and may be formed in plural along the first direction. Also, the second wiring 425 may extend in the first direction. At this time, the first wirings 420 may be formed to contact the upper surface of the first contact plug 380, and the second wirings 425 may be formed to contact the first and second contact plugs 380 And 385, respectively.

Alternatively, the second wiring 425 may be formed to include a first portion extending in the first direction and a second portion extending in the second direction, in which case the second wiring 425 And may be formed so as to contact only the upper surface of the first contact plug 380 formed at the first step and not contact the upper surface of the second contact plug 385. Alternatively, when the first and second contact plugs 380 and 385 are formed in a zigzag shape along the first direction, the second wiring 425 extends in the first direction, 1 contact plug 380 and not on the upper surface of the second contact plug 385. [ As such, no electrical signal may be applied to the second contact plug 385 that is not connected to the second wiring 425, and thus may be referred to as a dummy contact plug.

Each of the first wirings 420 may extend in the second direction so as to contact the upper surface of the first contact plugs 380 formed on a part of the plurality of channel blocks formed along the second direction. In one embodiment, each of the first wirings 420 extends in the second direction and contacts the upper surface of the first contact plugs 380 formed on the four channel blocks adjacent to each other in the second direction . The second wiring 425 may extend in the first direction and may be connected to a wiring (not shown) formed in the second region II (see FIG. 1), so that an electrical signal can be applied.

37 to 41, a sixth interlayer insulating film 430 is formed on the fifth interlayer insulating film 390 and the first and second wirings 420 and 425, 495, 550 and 555, third and fourth wirings 460 and 465 and first and second connection wirings 520 and 525 are formed.

The sixth interlayer insulating film 430 may be formed to include an oxide such as silicon oxide, for example, and may be incorporated into the fifth interlayer insulating film 390. [

The third and fourth wirings 460 and 465 and the first and second vias 490 and 495 are formed by removing the upper portion of the sixth interlayer insulating film 430 to form first and second trenches Holes (not shown) are formed to expose the upper surfaces of the first and second wirings 420 and 425 while respectively communicating with the first and second trenches. Then, A fifth interlayer insulating film 430 is formed on the upper surfaces of the exposed first and second wirings 420 and 425, the inner walls of the first and second via holes, the inner walls of the first and second trenches, A fifth conductive film is formed on the fifth barrier film to fill the first and second via-holes and the remaining portions of the first and second trenches, and then the upper surface of the sixth interlayer insulating film 430 And then planarizing the fifth conductive film and the fifth barrier film until exposed. However, before forming the first and second trenches, the first and second via-holes may be formed first.

The fifth conductive layer may include a metal such as copper, aluminum, tungsten, titanium, or tantalum, and the fifth barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like. . Alternatively, the fifth barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

The third wiring 460 filling the first trench may be formed to include a fifth conductive pattern 450 and a fifth barrier film pattern 440 surrounding the side wall and a part of the bottom surface of the fifth conductive pattern 450, The filling fourth wiring 465 may be formed to include a sixth conductive pattern 455 and a sixth barrier film pattern 445 surrounding a part of the side wall and the bottom. The first via 490 filling the first via hole may be formed to include a seventh conductive pattern 480 and a seventh barrier film pattern 470 surrounding the bottom and side walls of the seventh conductive pattern 480, The second via 495 filling the via hole may be formed to include an eighth conductive pattern 485 and an eighth barrier film pattern 475 surrounding the bottom and sidewalls thereof. The sequentially stacked first vias 490 and the third wirings 460 may be integrally formed, and the second vias 495 and the fourth wirings 465 sequentially stacked may also be integrally formed As shown in FIG.

In the exemplary embodiments, the third wiring 460 may extend in the second direction, and may be formed along the first direction. Further, the fourth wiring 465 may extend in the first direction. The third wirings 460 may be electrically connected to the first wirings 420 through the first vias 490 and the fourth wirings 465 may be electrically connected to the first wirings 420 through the second vias 495. [ 1 wirings 420, respectively.

In one embodiment, each of the third wires 460 may extend in the second direction and may be formed on four adjacent channel blocks in the second direction. The fourth wiring 465 may extend in the first direction and may be connected to a wiring (not shown) formed in the second region II (see FIG. 1), so that an electrical signal can be applied.

The first and second connection wirings 520 and 525 and the third and fourth vias 550 and 555 are formed by removing the upper portion of the sixth interlayer insulating film 430 to form third and fourth trenches And third and fourth via-holes (not shown) that respectively expose the top surfaces of the capping pattern patterns 230 while communicating with the third and fourth trenches, respectively, A ninth barrier film is formed on the upper surface of the fringe patterns 230, the inner wall of the third and fourth via-holes, the inner wall of the third and fourth trenches, and the sixth interlayer insulating film 430, The ninth conductive film is formed on the ninth conductive film to fill the fourth via holes and the remaining portions of the third and fourth trenches, and then the ninth conductive film is formed until the upper surface of the sixth interlayer insulating film 430 is exposed. And planarizing the ninth barrier film. However, before forming the third and fourth trenches, the third and fourth via-holes may be formed first.

The ninth conductive layer may include a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride. The ninth conductive layer may include a metal such as copper, aluminum, tungsten, titanium or tantalum. . Alternatively, the ninth barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

The first connection wiring 520 filling the third trench may be formed to include a ninth conductive pattern 510 and a ninth barrier film pattern 500 surrounding a part of the side wall and the bottom of the ninth conductive pattern 510, The second connection wiring 525 filling the tenth conductive pattern 515 may include a tenth conductive pattern 515 and a tenth barrier film pattern 505 surrounding a part of the side wall and the bottom of the tenth conductive pattern 515. The third via 550 filling the third via hole may be formed to include an eleventh conductive pattern 540 and an eleventh barrier film pattern 530 surrounding the bottom and sidewalls thereof, The fourth via 555 filling the via hole may be formed to include a twelfth conductive pattern 545 and a twelfth barrier film pattern 535 surrounding the bottom and side walls thereof. However, the third vias 550 and the first connection wirings 520, which are sequentially stacked, may be integrally formed, and the fourth vias 555 and the second connection wirings 525 sequentially stacked may also be formed And can be integrally formed.

The third and fourth vias 550 and 555 may be formed on the capping pattern patterns 230 formed on the channels 210 respectively and the first and second connection wirings 520 and 525 Extend in the second direction, and may be electrically connected to the third and fourth vias 550 and 555, respectively. Accordingly, the first and second connection wirings 520 and 525 are formed by the common source line (CSL) 330 and the channels 210, respectively, included in the two channel blocks spaced from each other in the second direction They can be electrically connected to each other. In the exemplary embodiments, the first connection wiring 520 includes channels 210 included in the third and fourth channel columns of the first channel block, And the channels 210 included in the first and second channel columns of the second channel block may be connected to each other. In addition, the second connection wiring 525 may include channels 210 included in the third and fourth channel columns of the second channel block, and a third channel block, which is spaced apart from the second channel block in the second direction, And the channels 210 included in the first and second channel columns of the first and second channel columns.

42 to 44, a seventh interlayer insulating film 430 is formed on the sixth interlayer insulating film 430, the third and fourth wirings 460 and 465, and the first and second connection wirings 520 and 525. [ (560), and then fifth and sixth vias 590 and 620 are formed.

The seventh interlayer insulating film 560 may be formed to include an oxide such as, for example, silicon oxide, and may be incorporated into the sixth interlayer insulating film 430. [

The fifth and sixth vias 590 and 620 pass through the seventh interlayer insulating film 560 to form the third wiring 460 and the first and second connection wirings 520 and 525, 5 and sixth via holes (not shown) are formed on the upper surface of the exposed third wiring 460, the upper surface of the exposed first and second connection wirings 520 and 525, A thirteenth barrier film is formed on the inner wall of the sixth via holes and the seventh interlayer insulating film 560 and a thirteenth conductive film filling the remaining portions of the fifth and sixth via holes is formed on the thirteenth barrier film , And the seventh conductive film and the thirteenth barrier film are planarized until the upper surface of the seventh interlayer insulating film 560 is exposed.

The thirteenth conductive layer may include a metal such as copper, aluminum, tungsten, titanium, or tantalum, and the thirteenth conductive layer may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like. . Alternatively, the thirteenth barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

The fifth via hole 590 filling the fifth via hole may be formed to include a thirteenth conductive pattern 580 and a thirteenth barrier film pattern 570 surrounding the side and bottom surfaces of the thirteenth conductive pattern 580, The sixth via 620 filling the first conductive pattern 620 may include the fourteenth conductive pattern 610 and the fourteenth barrier film pattern 600 surrounding the side and bottom surfaces thereof.

The fifth vias 590 may be electrically connected to the third wires 460 and the sixth vias 620 may be electrically connected to the first and second connection wires 520 and 525.

Referring again to FIGS. 2 to 7, after forming an eighth interlayer insulating film 630 on the seventh interlayer insulating film 560 and the fifth and sixth vias 590 and 620, the fifth and sixth Wiring lines 660 and 690 are formed.

The eighth interlayer insulating film 630 may be formed to include an oxide such as, for example, silicon oxide, and thus may be incorporated into the seventh interlayer insulating film 560. [

The fifth and sixth wirings 660 and 690 are connected to third and fourth openings (not shown) through the eighth interlayer insulating film 630 to expose the upper surfaces of the fifth and sixth vias 590 and 620, respectively A fifteenth barrier film is formed on the exposed upper surfaces of the fifth and sixth vias 590 and 620, the inner walls of the third and fourth openings, and the eighth interlayer insulating film 630 , A fifteenth conductive film filling the remaining portions of the fifth and sixth via-holes is formed on the fifteenth barrier film, and the fifteenth conductive film and the ninth interlayer insulating film 15 < / RTI > barrier film.

The fifteenth conductive layer may include a metal such as copper, aluminum, tungsten, titanium, or tantalum, and the fifteenth conductive layer may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like. . Alternatively, the fifteenth barrier film may be formed of a multilayer film composed of a metal film and a metal nitride film.

The fifth wiring 660 filling the third opening may be formed to include a fifteenth conductive pattern 650 and a fifteenth barrier film pattern 640 surrounding the side walls and the bottom surface thereof, The sixth wiring 690 may be formed to include a sixteenth conductive pattern 680 and a sixteenth barrier film pattern 670 surrounding the side walls and the bottom surface thereof.

In the exemplary embodiments, the fifth wiring 660 may extend in the first direction and be connected to a wiring (not shown) formed in the second region II (see FIG. 1), so that an electrical signal . That is, an electrical signal applied from the wiring in the second region II is electrically connected to the fifth wiring 660, the fifth via 590, the third wiring 460, the first via 490, and the first wiring 420 To the first contact plug 380 through the first contact plug 380. [

In the exemplary embodiments, the sixth wiring 690 may extend in the second direction and may include a sixth via 620, first and second connection interconnections 520 and 525, 4 vias 550, 555, and a capping pattern 230. In this embodiment, At this time, the sixth wiring 690 may perform a bit line function.

The vertical memory device can be completed through the above-described processes.

As described above, in the vertical memory device manufacturing method, when the first contact plugs 380 are formed to be connected to the gate electrodes 310 formed at the respective steps of the step structure, By further forming the second contact plug 385, the first contact plugs 380 can be formed so as to contact the gate electrodes 310 well by preventing the pattern loading phenomenon.

45-70 are plan views and cross-sectional views for illustrating a vertical memory device according to exemplary embodiments. 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67 and 69 are plan views and FIGS. 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68 and 70 are sectional views. Here, the cross-sectional views are cross-sectional views taken along line B-B 'of corresponding plan views.

The vertical memory devices shown in the figures are substantially the same as or similar to the vertical memory device shown in Figs. 1 to 13, except for the second contact plug and the upper wiring connected thereto. Accordingly, the same components are denoted by the same reference numerals, and a detailed description thereof will be omitted. For convenience of explanation, as shown in Figs. 8A and 9A, the drawings only show structures stacked from the substrate to the fifth interlayer insulating film.

45 and 46, the first and second contact plugs 380 and 385 may be formed in a zigzag shape along the first direction. Accordingly, the first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the lowest step, and a second wiring (not shown) may be commonly connected to the first and second contact plugs 380 and 385, 425 may include a first portion extending in the first direction and a second portion extending in the second direction.

47 and 48, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. At this time, the first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed at the uppermost step, and the first wirings 420 May extend in the second direction.

Referring to FIGS. 49 and 50A, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. At this time, the first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed at the middle layer step, and the first and second contact plugs 380 and 385, which are commonly connected to the first and second contact plugs 380 and 385, 420 may extend in the second direction.

Referring to FIG. 50B, the first and second contact plugs 380 and 385 may be divided into an upper portion and a lower portion. That is, the first and second wirings 420 and 425 to which the first and second contact plugs 380 and 385 formed in the lower layer steps are connected, and the ninth and tenth Interlayer insulating films 700 and 710 may be separately formed. The first and second contact plugs 380 and 385 formed on the upper layer steps are electrically connected to the first through fifth interlayer insulating layers 130, 140, 240, 340, and 390, and the ninth interlayer insulating layer 700 And the first and second wirings 420 and 425 may be formed through the tenth interlayer insulating film 710 on the upper surfaces thereof.

51 and 52, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the lowest step. The second wire 425 electrically connected to the first contact plug 380 may include a first portion extending in the first direction and a second portion extending in the second direction, It may not contact the upper surface of the substrate 385. Thereby, no electrical signal may be applied to the second contact plug 385, and may be referred to as a dummy contact plug.

Referring to FIGS. 53 and 54, the first and second contact plugs 380 and 385 may be formed in a zigzag shape along the first direction. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the lowest step. The second wiring 425 electrically connected to the first contact plug 380 may extend in the first direction and may not contact the upper surface of the second contact plug 385. Accordingly, the second contact plug 385 may be a dummy contact plug.

55 and 56, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. However, the second contact plug 385 is not formed on the gate electrode 310, but may be formed on the upper surface of the substrate 100 in the first direction at the lowest step. On the other hand, the second wiring 425 electrically connected to the first contact plug 380 may include a first portion extending in the first direction and a second portion extending in the second direction, It may not contact the upper surface of the contact plug 385. Accordingly, the second contact plug 385 may be a dummy contact plug.

Referring to FIGS. 57 and 58, the first and second contact plugs 380 and 385 may be formed in a zigzag shape along the first direction. At this time, the second contact plug 385 is not formed on the gate electrode 310, but may be formed on the top surface of the substrate 100 which is adjacent to the lowermost step in the first direction. On the other hand, the second wiring 425 electrically connected to the first contact plug 380 may extend in the first direction and may not contact the upper surface of the second contact plug 385. Accordingly, the second contact plug 385 may be a dummy contact plug.

59 and 60, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the uppermost step. However, the first wiring 420 electrically connected to the first contact plug 380 may extend in the first direction and may not contact the upper surface of the second contact plug 385. Accordingly, the second contact plug 385 may be a dummy contact plug.

Referring to FIGS. 61 and 62, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the middle layer step. However, the first wiring 420 electrically connected to the first contact plug 380 may extend in the first direction and may not contact the upper surface of the second contact plug 385. Accordingly, the second contact plug 385 may be a dummy contact plug.

63 and 64, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the lowest step. Also, the second contact plug 385 may be formed on the uppermost step of the substrate 100 adjacent to the lowest step in the first direction. The second wiring 425 electrically connected to the first contact plug 380 may include a first portion extending in the first direction and a second portion extending in the second direction, Contact with the upper surface of the second contact plug 385 formed on the substrate 310 but not with the second contact plug 385 formed on the upper surface of the substrate 100. Accordingly, the second contact plug 385 formed on the upper surface of the substrate 100 may be a dummy contact plug.

65 and 66, the first contact plugs 380 and the second contact plugs 385 formed on the gate electrode 310 may be formed on the same line along the first direction, but the substrate 100 The second contact plug 385 formed on the upper surface may be formed to deviate from the line. On the other hand, first and second contact plugs 380 and 385 may be formed on the first gate electrode 310 formed in the lowest step. A second wire 425 electrically connected to the first contact plug 380 and the second contact plug 385 formed on the gate electrode 310 may extend in the first direction, 100 may not contact the upper surface of the second contact plug 385 formed on the upper surface. Accordingly, the second contact plug 385 formed on the upper surface of the substrate 100 may be a dummy contact plug.

67 and 68, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. At this time, the second contact plug 385 may be formed on the first gate electrode 310 formed in the lowest step and the substrate 100 adjacent thereto. The second wire 425 electrically connected to the first contact plug 380 may include a first portion extending in the first direction and a second portion extending in the second direction, It may not contact the upper surface of the sphere 385. Accordingly, the second contact plugs 385 may be dummy contact plugs.

Referring to FIGS. 69 and 70, the first and second contact plugs 380 and 385 may be formed on the same line along the first direction. At this time, the second contact plug 385 may be formed on the upper surface of the substrate 100 adjacent to the lowest step. The second wire 425 electrically connected to the first contact plug 380 may include a first portion extending in the first direction and a second portion extending in the second direction, It may not contact the upper surface of the sphere 385. The second contact plug 385 may be connected to a separate seventh wiring 427 and the third wiring 427 may electrically connect an electrical signal from a wiring (not shown) formed in the second region II To the contact plug 385.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the present invention can be changed.

100: substrate 105: impurity region
110: insulating film 115: insulating film pattern
130, 140, 240, 340, 390, 430, 560, 630, 700, 710: first to tenth interlayer insulating films
150: channel hole 160: semiconductor pattern
170, 270: first and second blocking film patterns 180: charge storage film pattern
190: tunnel insulating film pattern 200: first charge storage film structure
210: channel 220: filling film pattern
230: cap layer pattern 250: opening
260: gap 280: second charge storage film structure
290: gate barrier film pattern 300: gate conductive pattern
310: gate electrode 320: second spacer
330: common source line 350, 355: first and second contact holes
The first to the sixteenth barrier film patterns are formed by patterning the first to the sixteenth barrier film patterns 601, 602, 603, 604, 605, 604, 605,
370, 375, 410, 415, 450, 455, 480, 485, 510, 515, 540, 545, 580, 610, 650, 680:
380, 385: first and second contact plugs
420, 425, 460, 465, 660, 690, 427: first to seventh wiring
490, 495, 550, 555, 590, 620: first to sixth vias

Claims (20)

A plurality of gate electrodes formed in a plurality of layers spaced apart from each other along a vertical direction perpendicular to an upper surface of a substrate;
A channel extending in the vertical direction on the substrate and passing through the gate electrodes; And
And a plurality of first contact plugs extending in the vertical direction on the gate electrodes and contacting the gate electrodes, respectively,
And one or more second contact plugs extending in the vertical direction are further formed on the first gate electrode of the gate electrodes. 2. The vertical memory device of claim 1, wherein an upper surface of the second contact plug is formed at a substantially same height as an upper surface of the first contact plugs. 2. The vertical memory device of claim 1, wherein the second contact plug contacts the first gate electrode. The semiconductor device of claim 1, wherein the second contact plug is not in contact with the first gate electrode, the bottom surface of the second contact plug is higher than the upper surface of the first gate electrode, Is lower than the underside of the gate electrode formed in the vertical memory device. The method of claim 1, wherein each of the gate electrodes extends along a first direction parallel to an upper surface of the substrate,
Wherein the first and second contact plugs are arranged at regular intervals along the first direction when viewed from the top surface. 6. The vertical memory device of claim 5, wherein the second contact plug is disposed at the earliest or last one of the first and second contact plugs along the first direction. 6. The vertical memory device of claim 5, wherein the second contact plug is centered along the first direction among the first and second contact plugs. 6. The vertical memory device of claim 5, wherein the first and second contact plugs are arranged in a zigzag shape along the first direction. 9. The vertical memory device of claim 8, wherein the second contact plug is disposed at the earliest or last one of the first and second contact plugs along the first direction. The semiconductor device according to claim 5, wherein the gate electrodes have a stepped shape in which a length of the gate electrode gradually decreases from a lower layer to an upper layer,
Wherein each of the first and second contact plugs is formed on an edge portion of each of the gate electrodes that is not overlapped by upper gate electrodes. 2. The vertical memory device of claim 1, wherein the first gate electrode is formed in the lowest layer among the gate electrodes. 2. The vertical memory device of claim 1, wherein the first gate electrode is formed on the uppermost one of the gate electrodes. The vertical memory device of claim 1, wherein the first gate electrode is formed in a middle layer of the gate electrodes. 2. The vertical memory device of claim 1, comprising a plurality of said first gate electrodes. 15. The vertical memory device according to claim 14, wherein the first gate electrodes are formed in the lowest layer and the uppermost layer, respectively, of the gate electrodes. A plurality of gate electrodes formed in a plurality of layers spaced apart from each other in a direction perpendicular to the upper surface of the substrate in the memory cell region of the substrate including the memory cell region and the peripheral region;
A channel extending in the vertical direction on the substrate and passing through the gate electrodes; And
And a plurality of first contact plugs extending in the vertical direction on the gate electrodes and contacting the gate electrodes, respectively,
In the memory cell region, at least one third contact plug extending in the vertical direction and having a top surface at the same height as the top surface of the first contact plugs is formed on the substrate adjacent to the gate electrode formed in the lowermost layer among the gate electrodes A further formed vertical memory device. 17. The method of claim 16, wherein each of the gate electrodes extends along a first direction parallel to an upper surface of the substrate,
Wherein the first and third contact plugs are arranged at regular intervals along the first direction when viewed from the top surface. The semiconductor device according to claim 16, wherein the gate electrodes have a stepped shape in which a length in a first direction parallel to the upper surface of the substrate gradually decreases from a lower layer to an upper layer,
And the third contact plug is formed on the portion of the substrate adjacent to the gate electrode formed in the bottom layer in the first direction. A channel extending along a vertical direction perpendicular to the upper surface of the substrate;
A charge storage film structure surrounding an outer wall of the channel;
Each of which extends along a first direction parallel to the upper surface of the substrate and surrounds the charge storage film structure and is spaced apart from each other along the vertical direction and has a step shape in which the length of the first direction gradually decreases from the lower layer to the upper layer A plurality of gate electrodes; And
And a plurality of first contact plugs extending in the vertical direction in contact with edge portions of the respective gate electrodes which are not overlapped by the gate electrodes of the upper layer,
The lengths of the gate electrodes adjacent to each other in the vertical direction in the first direction are reduced to a first width, but a length in the first direction of the first gate electrode among the gate electrodes, Wherein a length of the second gate electrode disposed immediately above in the first direction is reduced to a second width larger than the first width. 20. The vertical memory device of claim 19, wherein the second width is at least two times the first width.

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