JP2012186302A - Method of decreasing number of masks for integrated circuit device having laminated connection level - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of masks of a 3D laminate memory device, in which the required number of masks increases because a separate mask is used for each connection level, by devising the pattern.SOLUTION: A three-dimensional lamination integrated circuit device has a lamination part of connection level in a wiring region. Only N sets of etching mask for forming a wiring connection region containing up to 2levels in the lamination part of connection level are required. In some examples, connection levels of 2are etched by an etching mask of sequential number X, where X=1 in one mask, X=2 in another mask, and the X is given up to X=N. A wiring connection region matching a formation region at the connection level is formed by this method.

Description

  The present invention generally relates to a high-density integrated circuit device, and more particularly to a wiring structure of a multi-level three-dimensional stack device.

  In manufacturing a high-density storage device, the amount of data per unit area on an integrated circuit is the most important factor. As the critical dimension of storage devices approaches the limits of lithographic technology, technology for multi-level stacking of memory cells has also been proposed to earn greater storage capacity density and lower cost per bit.

  For example, thin film transistor technology includes "multilayer stackable thin film transistor NAND flash memory" line, etc., IEEE International Electronic Device Conference, 11-13 DEC 2006 and "stacking single crystal silicon layer on ILD and TANOS structure beyond 30nm node" 3D stacked NAND flash memory technology used "Jan et al., IEEE International Electronic Device Conference, 11-13 DEC 2006, applied to charge trapping memory.

  Cross-point array technology has also been applied to antifuse memories in "512MbPROM with 3D array of diode / antifuse memory cells" Johnson et al., IEEE, Solid Circuit Journal, Vol 38, no 11, Nov. 2003. See also U.S. Pat. No. 7,081,377 entitled Cleave, entitled 3D Memory.

  Another structure that provides vertical NAND cells in charge trapping memory technology is "New 3D structure for ultra-high density flash memory by VRAT and PIPE" Kim et al., VLSI Technology Symposium, Technical Paper Digest, 17-19 June 2008 , 122-123.

  In a three-dimensional stacked memory device, a conductor wiring used to connect a lower level of a memory cell and a decoding circuit is connected to the upper level. The cost of wiring increases with the number of lithography steps required. One approach to reducing the number of lithography steps is "bit cost scalable technology for punch and plug methods for ultra-high density flash memory" Tanaka et al., 2007 VLSI Technology Symposium, Technology Article digest, 12-14 June 2007, pages 14-15.

  However, one drawback with conventional 3D stacked memory devices is that a separate mask is typically used for each connection level. So, for example, if there are 20 connection levels, 20 different masks are required in common, and one connection level requires the creation of a mask for that level and an etching process for that level. It is said.

According to some examples of the invention, only N masks are required to provide access to 2 ^N (2 ^N ) connection level regions. According to some examples, 2 ^x-1 (2 ^x-1 ) connection levels are etched in each mask sequence X times.

A first example of a method used for a three-dimensional stacked integrated circuit device having a connection-level stacked portion in a wiring region is used to create a wiring connection region that matches and is exposed to a formation region in a connection level. Is done. The set of N etching masks is used to create up to and including the 2 ^N (2 ^N ) levels of the wiring connection region in the connection level stack. Each mask has a mask and an etched region. N is an integer equal to at least 2. X is a serial number assigned to the mask, one mask is X = 1, the other one is X = 2, and X = N. At least a portion of any upper layer covering the connection level stack in the wiring region is removed. The wiring region is etched N times in the selected order using the mask. By doing so, connection openings are created that extend from the surface layer to the respective connection levels. The connection opening is aligned with the formation region at each of 2 N power levels (2 ^N ) to provide access. 2 X-1 power (2 ^X-1 ) connection levels are etched during the etching process of each mask with serial number X. The conductor is formed through the connection opening and connected to the formation region at the connection level. Some examples include the following steps. Filling material is applied to the openings to define the via pattern surface. Via portions are opened through the filling material to expose the formation regions of the respective connection levels. A conductive material is laminated in the via portion. In some examples, the access step is performed with N equal to at least 4. In some examples, the removal process is performed using an additional mask that exposes the wiring area, and in other examples, the removal process is performed using a blanket etching process in the wiring area. In some examples, the sidewall material is utilized as one of N etch masks.

  In another example of the method, an electrical connection is provided to a formation region in a stack portion of a connection level of a wiring region for a three-dimensional stacked integrated circuit device. The integrated circuit device is of a type having a wiring region, and the wiring region has an upper layer and a laminated portion of at least first, second, third, and fourth connection levels below the upper layer. At least first and second openings are formed in the upper layer, each opening exposes a surface portion of the first connection level, and the first and second openings are partially upper layer sidewalls. A boundary is formed. Sidewall material is laminated on the sidewalls of the first and second openings and on the respective first portions of the surface portion, leaving the second portion of the surface portion free of sidewall material. The first and second openings are expanded through the second portion of the surface portion to expose the surface of the second connection level at each of the first and second openings. At least some of the sidewall material of each opening is removed to expose some of the first portion of the surface of each opening, and a wiring connection region is formed in the second opening. The wiring connection region of the second opening is aligned with the formation region of the first and second connection levels. Further, the first opening is extended from the exposed first portion of the surface through the first and second connection levels to expose the surface of the third connection level, and the second And the first opening is widened from the exposed surface of the second connection level via the third connection level to expose the surface of the fourth connection level. By doing so, the wiring connection region of the first opening is aligned with the formation region at the third and fourth connection levels. Conductors are formed in the formation regions of the first, second, third, and fourth connection levels. In some examples, in the step of forming the conductor, a filling material is provided to the opening to define a via pattern surface, and the via is opened through the filling material to expose a formation region of each connection level. Then, a conductive material is laminated in the via portion.

An example of a set of masks is used to form a wiring connection region that matches a formation region in a connection level stacking portion of a wiring region for a three-dimensional stacked integrated circuit device, the connection level stacking portion being an upper portion The layer is coated. Each of the masks in the set of N etching masks has a mask and an etching region, and the etching region has 2 N-1 (2 ^N-1 ) connection levels of the wiring region of the three-dimensional stacked integrated circuit device. It is used to form a wiring connection region that matches the previous and including formation region. N is an integer that is at least 3, X is a sequential number assigned to the mask, one mask is X = 1, the other one is X = 2, and X = N. Become. In some examples, the etching mask has a dummy mask region at a corresponding position of some of the etching masks. In some examples, the etch mask has at least one dummy mask region at a corresponding location on the etch mask. In some examples, N is 4 or greater.

The other set of masks is used to form a wiring connection region that matches a formation region in the stacked portion of the connection region of the wiring region for the three-dimensional integrated circuit device. Each mask in the set of N etching masks has a mask and an etching region, and the etching region includes up to 2 ^N (2 ^N ) connection levels of the wiring region of the three-dimensional stacked integrated circuit device. Used to form a wiring connection region that matches the formation region. N is an integer that is at least 2. X is a serial number assigned to the mask. One mask is X = 1, the other one is X = 2, and X = N.

  Other features and advantages of the invention can be ascertained by looking at the drawings, detailed description and claims that follow.

  The description in connection with FIGS. 1-16 is a US patent application Ser. No. 12 / 579,192 filed Oct. 14, 2009 under the name 3D integrated circuit layer wiring having the same assignee as the present assignee. Which is incorporated from the application, the disclosure of which is hereby incorporated by reference.

FIG. 2 is a cross-sectional view of a device including a three-dimensional structure having a small footprint wiring structure 190 in which conductors 180 are extended to various levels 160-1 to 160-4 of the device. The top view of the level 160-1 which shows a formation area is shown. The top view of the level 160-2 which shows a formation area is shown. The top view of the level 160-3 which shows a formation area is shown. The top view of the level 160-4 which shows a formation area is shown. It is sectional drawing which shows a part of three-dimensional laminated integrated circuit device containing 3D wiring structure. FIG. 3B is a cross-sectional view showing a part of a three-dimensional stacked integrated circuit device including a 3D wiring structure, and is a view orthogonal to FIG. 3A. FIG. 4 is a top layout of an embodiment of the device having a wiring structure around two sides of the memory array. FIG. FIG. 6 is a top layout of an embodiment of the device having a wiring structure around four sides of the memory array. FIG. It is a schematic diagram of a part of a memory device having a wiring structure described here. FIG. 6 is a simplified block diagram of an integrated circuit device having a 3D memory device having a wiring structure described herein. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a figure which shows the process of the manufacture order which manufactures the wiring structure demonstrated here. It is a top view of the opening part in the mask which has the width | variety which changes to the variable direction of the formation area on a level in the stepwise shape in a longitudinal direction. 4 is a simplified flow diagram of a method for forming a wiring connection region according to the present invention. FIG. 5 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and a connection level together with an additional mask formed on an upper layer; FIG. FIG. 19 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and an opening in the additional mask of FIG. 18 through an upper layer; The result of etching through the region is shown. FIG. 20 is a diagram illustrating a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and is applied to the connection level stacked unit in FIG. 19. It is a figure which shows a 1st mask. FIG. 6 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and a single connection level using the first mask; It is a figure which shows the result of this etching. FIG. 22 is a diagram illustrating a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and is applied to the connection level stacked unit in FIG. 21; It is a figure which shows a 2nd mask. FIG. 23 is a diagram showing a first example of a method for forming a wiring connection region at several connection levels of a wiring region of a three-dimensional stacked integrated circuit device, and shows an etching process through two connection levels in FIG. It is a figure which shows a result. FIG. 3 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, and includes a second mask at four different connection levels; It is a figure which shows the structure of FIG. 23 which removed and exposed the wiring connection area | region. FIG. 25 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in a wiring region of a three-dimensional stacked integrated circuit device, which is provided on the exposed surface of the structure of FIG. 24. FIG. 25 is a diagram showing the structure of FIG. 24 with an etching stopper layer to be manufactured. FIG. 26 is a diagram showing a first example of a method for forming wiring connection regions at several connection levels in the wiring region of the three-dimensional stacked integrated circuit device, and the structure of FIG. 25 covered with an interlayer dielectric layer; FIG. It is a figure which shows the 1st example of the method for forming the wiring connection area | region in several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device, Comprising: In each wiring connection area | region of the said four connection levels FIG. 27 is a diagram showing the structure of FIG. 26 after an electrical conductor is formed through the interlayer dielectric layer and the etching stopper layer in order to connect to the formation region of FIG. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 2nd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the 3rd example of the method for forming the wiring connection area | region in the several connection levels of the wiring area | region of a three-dimensional laminated integrated circuit device. It is a figure which shows the example of a method of the laminated part of 16 connection levels. It is a figure which shows the etching result of the example of a method of FIG. It is a figure which shows the etching result when a mask has a dummy connection area | region so that a dummy laminated part may be formed between wiring connection areas.

  FIG. 1 is a cross-sectional view of a device including a three-dimensional structure having a wiring structure 190 in a small area where the conductor 180 extends to various levels 160-1 to 160-4 of the device. In the depicted example, four levels 160-1 to 160-4 are shown. More generally, the small interconnect structure 190 described herein may be implemented with structures having levels 0-N, where N is at least 2.

  Conductors 180 are disposed in the wiring structure 190 to connect to the formation areas of the various levels 160-1 to 160-4. As will be described in detail below, each individual level of conductor 180 is connected to formation regions 161-1a, 161-1b, 161-2a, 161-2b, 161-3a, 161-3b, 161-4. To extend through the overlapping level openings. In this example, the conductor 180 is used to connect the connection levels 160-1 to 160-4 to the internal connection wiring 185 of the wiring layer superimposed on the connection levels 160-1 to 160-4.

  The formation area is the part of the connection levels 160-1 to 160-4 used to connect to the conductor 180. The size of the formation region also gives the conductor 180 enough room to connect the conductive formation regions in the formation regions of the various connection levels 160-1 to 160-4 to the overlapped internal connection wiring 185, and at the same time different levels. The formation area is made large enough to solve problems such as misalignment between the openings overlapping the conductor 180.

  Thus, the size of the formation region depends on several factors including the size and number of conductors used and will vary from embodiment to embodiment. In addition, the number of conductors 180 is different in each formation region.

  In the example shown, levels 160-1 through 160-4 are layers of insulating material 165 that separate level conductors 160-1 through 160-4, respectively, from a planar conductor layer of material such as doped polycrystalline silicon. Consists of. Alternatively, levels 160-1 through 160-4 need not be planarly stacked material layers, but instead may be material layers that vary in a vertical dimension.

  The conductors 180 connected to the different levels 160-1 to 160-4 are arranged in a direction extending along the cross section shown in FIG. 1A. This direction, defined by the structure of the conductor 180 connected to the different levels 160-1 to 160-4, is referred to herein as the “longitudinal” direction. The “lateral” direction is the direction perpendicular to the longitudinal direction and is the direction into and out of the illustrated cross section of FIG. 1A. Both the longitudinal direction and the lateral direction are considered to be horizontal dimensions, meaning the direction in the two-dimensional region of the plan view at levels 160-1 to 160-4. The “length” of a structure or feature is the length in the longitudinal direction, and its “width” is the width in the lateral direction.

  The level 160-1 is the lowest level among the plurality of levels 160-1 to 160-4. This level 160-1 is on the insulating layer 164.

  The level 160-1 includes first and second formation regions 161-1a and 161-1b for connection to the conductor 180.

  In FIG. 1, the level 160-1 has two forming regions 161-1a and 161-1b at both ends of the wiring structure 190. In some alternative embodiments, one formation region 161-1a, 161-1b is omitted.

  FIG. 2A is a plan view of a portion of the level 160-1 including the formation regions 161-1a and 161-1b in the region of the wiring structure 190. FIG. The region of the wiring region 190 is close to the width of the via size of the conductor, and has a length that can be made longer than the width. As shown in FIG. 2A, the formation region 161-1a has a width 200 in the lateral direction and a length 201 in the longitudinal direction. The formation region 161-1b has a width 202 in the lateral direction and a length 203 in the longitudinal direction. In the embodiment of FIG. 2A, the formation regions 161-1a, 161-1b may each have a circular, elliptical, square, rectangular, or other somewhat distorted cross-section.

  Since the level 160-1 is the lowest level, the conductor 180 does not need to reach the lower level via the level 160-1. In this example, therefore, the level 160-1 does not have an opening inside the wiring structure 190.

  Returning to FIG. 1, level 160-2 overlies level 160-1. The level 160-2 has an opening 250 that overlaps the formation region 161-1a on the level 160-1. The opening 250 has a distal-side longitudinal side wall 251 a and a proximal-side longitudinal side wall 251 b that define the length 252 of the opening 250. The length 252 of the opening 250 is at least as long as the length 201 of the lower formation region 161-1a, and the conductor 180 in the formation region 161-1a can pass through the level 160-2.

  The level 160-2 also has an opening 255 overlying the formation region 161-1b. Opening 255 has distal and proximal longitudinal side walls 256a, 256b that define length 257 of opening 255. The length 257 of the opening 255 is at least as long as the length 203 of the lower formation region 161-1b, and the conductor 180 in the formation region 161-1b can pass through the level 160-2.

  The level 160-2 also has first and second formation regions 161-1a and 161-1b in the vicinity of the openings 250 and 255, respectively. The first and second formation regions 161-1 a and 161-1 b are portions of the level 160-2 used to connect with the conductor 180.

  FIG. 2B is a plan view of a portion of level 160-2 including first and second formation regions 161-2a and 161-2b and openings 250 and 255 in the region of the wiring structure 190. FIG.

  As shown in FIG. 2B, the opening 250 has longitudinal side walls 251 a and 251 b that define a length 252, and side walls 253 a and 253 b that define a width 254 of the opening 250. The width 254 is at least as large as the width 200 of the lower formation region 161-1a, and the conductor 180 can pass through the opening 250.

  Opening 255 has longitudinal side walls 256 a, 256 b that define a length 257 and lateral side walls 258 a, 258 b that define a width 259. The width 259 is at least as large as the width 202 of the lower formation region 161-1b, and the conductor 180 can pass through the opening 255.

  In the plan view of FIG. 2B, the openings 250 and 255 each have a rectangular cross section. In embodiments, the openings 250, 255 each have a circular, oval, square, rectangular, or some other distorted cross section, depending on the shape of the mask used to form them. May be.

  As shown in FIG. 2B, the formation region 161-2a is in the vicinity of the opening 250 and has a width 204 in the lateral direction and a length 205 in the longitudinal direction. The formation region 161-2b is in the vicinity of the opening 255 and has a width 206 in the lateral direction and a length 207 in the longitudinal direction.

  Returning to FIG. 1, level 160-3 overlies level 160-2. The level 160-3 has an opening 260 that overlaps the formation region 161-1a on the level 160-1 and the formation region 161-2a on the level 160-2. The opening 260 has distal and proximal longitudinal side walls 261a, 261b that define a length 262 of the opening 260. The length 252 of the opening 260 is at least equal to the sum of the lengths 201 and 205 of the lower formation regions 161-1a and 161-2a, and the conductor 180 in the formation regions 161-1a and 161-2a has a level 160. -3.

  As shown in FIG. 1, the front end side long side wall 261a of the opening 260 is aligned vertically with the front end side long side wall 251a of the lower opening 250. In the process embodiment described in detail below, the opening can be formed using a single etching mask opening and one additional mask formed overlying the single etching mask opening, with significant alignment. Etching with that additional mask without going through the process, resulting in the formation of openings having distal longitudinal side walls 261a, 251a along the periphery of a single vertically aligned etching mask Become.

  Level 160-3 also has an opening 265 overlying the formation region 161-1b on level 160-1 and the formation region 161-2b on level 160-2. The opening 265 has outer and inner longitudinal side walls 266a, 266b that define a length 267 of the opening 265. The outer longitudinal sidewall 266a of the opening 265 is aligned vertically with the outer longitudinal sidewall 256a of the lower opening 255.

  The length 267 of the opening 265 is at least as long as the lengths 203 and 207 of the lower formation regions 161-1b and 161-2b, and the conductor 180 in the formation regions 161-1b and 161-2b has a level 160-3. Can pass through.

  The level 160-3 also has first and second formation regions 161-3a and 161-3b in the vicinity of the openings 260 and 265, respectively. The first and second formation regions 161-3a and 161-3b are portions of the level 160-3 used to connect to the conductor 180.

  2C is a plan view of the level 160-3 portion including the first and second formation regions 161-3a and 161-3b and the openings 260 and 265 in the wiring structure 190. FIG.

  As shown in FIG. 2C, the opening 260 has outer and inner longitudinal sidewalls 261a, 261b that define a length 262, and lateral sidewalls 263a, 263b that define the widths 264a, 264b of the opening 260. The width 264a is at least as large as the width 200 of the lower formation region 161-1a, the width 264b is at least as large as the width 204 of the lower formation region 161-2a, and the conductor 180 can pass through the opening 260. .

  In the illustrated embodiment, the widths 264a, 264b are substantially the same. Alternatively, the widths 264a, 264b can be different for different formation regions.

  Opening 265 has outer and inner longitudinal sidewalls 266a, 266b that define a length 267 and lateral sidewalls 268a, 268b that define widths 269a, 269b. The width 269a is at least as large as the width 202 of the lower formation region 161-1b, the width 269b is at least as large as the width 206 of the lower formation region 161-2b, and the conductor 180 can pass through the opening 265. .

  As shown in FIG. 2, the formation region 161-3a is in the vicinity of the opening 260 and has a width 214 in the lateral direction and a length 215 in the longitudinal direction. The formation region 161-3b is in the vicinity of the opening 265 and has a width 216 in the lateral direction and a length 217 in the longitudinal direction.

  Returning to FIG. 1, level 160-4 overlies level 160-3. The level 160-4 has a formation region 161-1a on the level 160-1, a formation region 161-2a on the level 160-2, and an opening 270 that overlaps the formation region 161-3a on the level 160-3. . The opening 270 has longitudinal side walls 271 a and 271 b that define a length 272 of the opening 270. The length 272 of the opening 270 is at least the same as the sum of the lengths 201, 205, and 215 of the lower formation regions 161-1a, 161-2a, and 161-3a, and the formation regions 161-1a, 161-2a, The conductor 180 of 161-3a can pass through the level 160-4. As shown in FIG. 1, the longitudinal side wall 271a of the opening 270 is aligned with the longitudinal side wall 261a of the lower opening 260 in the vertical direction.

  Level 160-4 also has an opening 275 overlying the formation region 161-1b on level 160-1, the formation region 161-2b on level 160-2, and the formation region 161-3b on level 160-3. Have. The opening 275 has longitudinal side walls 276 a, 276 b that define the length 277 of the opening 275. The longitudinal side wall 267a of the opening 275 is aligned with the longitudinal side wall 266a of the lower opening 265 in the vertical direction.

  The length 277 of the opening 275 is at least equal to the sum of the lengths 203, 207, and 217 of the lower formation regions 161-1b, 161-2b, and 161-3b, and the formation regions 161-b, 161-2b, The conductor 180 of 161-3b can pass through the level 160-4.

  Level 160-4 also has a formation region 161-4 between openings 270,275. The formation region 161-4 is a portion of the level 160-4 used to connect with the conductor 180. In FIG. 1, the level 160-4 has one formation region 161-4. Alternatively, level 160-4 may have more than one formation area.

  FIG. 2D is a plan view of a level 160-4 portion including the formation region 161-4 and the openings 270 and 275 in the wiring structure 190.

  As shown in FIG. 2D, the opening 270 has longitudinal side walls 271a, 271b that define a length 272, and lateral sidewalls 273a, 273b that define the widths 274a, 274b, 274c of the opening 270. The widths 274a, 274b, and 274c are at least the same as the widths 200, 204, and 214 of the lower formation regions 161-1a, 161-2a, and 161-3a, and the conductor 180 can pass through the opening 270.

  Opening 275 has outer and inner longitudinal sidewalls 276a, 276b that define a length 277 and lateral sidewalls 278a, 278b that define widths 279a, 279b, 279c. The widths 279a, 279b, and 279c are at least the same as the widths 202, 206, and 216 of the lower formation regions 161-1b, 161-2b, and 161-3b, and the conductor 180 can pass through the opening 275.

  As shown in FIG. 2D, the formation region 161-4 is between the openings 270 and 275 and has a width 224 in the lateral direction and a length 225 in the longitudinal direction.

  Returning to FIG. 1, the distal side long side walls 271a, 261a, 251a of the openings 270, 260, 250 are vertically aligned, and the difference in length of the openings 270, 260, 250 is the side walls 271b, 261b, 251b. This is due to the horizontal offset. As used herein, “vertically aligned” elements and features are substantially coplanar with a virtual plane perpendicular to both the transverse and longitudinal directions. As used herein, the term “substantially coplanar” refers to manufacturing tolerances in the formation of openings using multiple etching processes that result in variations in the plane of the openings and sidewalls in one etch mask. Intended to adapt.

  As shown in FIG. 1, the longitudinal side walls 276a, 266a, 256a of the openings 275, 265, 255 are aligned in the vertical direction.

  Similarly, the side walls of the level opening are also aligned vertically. 2A-2D, the lateral sidewalls 273a, 263a, 253a of the openings 270, 260, 250 are aligned vertically. Further, the lateral side walls 273b, 263b, 253b are aligned in the vertical direction. For the openings 275, 265, 255, the longitudinal side walls 276a, 266a, 256a are aligned in the vertical direction, and the side walls 278b, 268b, 258b are aligned in the vertical direction.

  In the illustrated embodiment, the openings of the various levels 161-1 to 160-4 have substantially the same width in the lateral direction. Alternatively, the width of the opening can be varied along the longitudinal direction, e.g. in a step-like fashion, to accommodate forming regions having different widths.

  The technique for implementing the wiring structure 190 described here significantly reduces the area and footprint required for connection to the plurality of levels 160-1 to 160-4 compared to the prior art. As a result, more space can be provided by implementing various levels 160-1 through 160-4 of storage circuits. This results in higher memory density and lower cost per bit at higher levels compared to the prior art.

  In the cross section of FIG. 1, the opening of the wiring structure 190 provides a level having a stepped pattern on both sides of the formation region 161-4 on the level 160-4. That is, the two openings at each level are symmetric about an axis that is perpendicular to both the longitudinal and lateral directions, and the two formation regions at each level are also symmetric about that axis. As used herein, the term “symmetric” accommodates manufacturing tolerances in the formation of openings using multiple etching processes that result in variations in openings and opening dimensions in one etch mask. Intended.

  In an alternative embodiment where each level has one opening and one forming area, the level has a stepped pattern on only one side.

  In the illustrated example, four levels 160-1 to 160-4 are shown. More generally, the small interconnect structures described herein can be implemented at levels 0 to N (N is at least 2). In general, when (i) is equal to 1 to N, level (i) overlaps level (i-1) and an opening (i) near the formation region (i) above level (i). i). The opening (i) extends above the formation region (i-1) above the level (i-1), and in the case of (i) greater than 1, the adjacent opening at level (i-1) ( extended over i-1). The opening (i) has a distal-side longitudinal side wall aligned with the distal-side longitudinal side wall of the opening (i-1) at the level (i), and determines the length of the opening (i). Have The length of the opening (i) is at least about the same as the length of the opening (i-1) if it is the length of the formation region (i-1). When (i) is greater than 1, the opening (i) has a lateral wall aligned with the lateral wall of the opening (i-1) at level (i), and the width of the formation region (i-1) Define at least the width of the equivalent opening (i).

  Other types of memory cells and shapes can be used in alternative embodiments. Other types of memory cells that can be used include dielectric charge trapping and floating gate memory cells. For example, as another example, a device level is implemented with an access device or access line where the planar memory cell array is separated by an insulating material and formed within the level using thin film transistors and related technologies. obtain. Further, in the wiring structure described herein, conductors that extend to various levels within the device within a small footprint are convenient and can be implemented by other types of three-dimensional stacked integrated circuit devices.

  FIG. 3A is a cross-sectional view of a portion of a three-dimensional stacked integrated circuit device having a memory cell array 110 and a peripheral region 120 with a wiring structure 190 as described herein.

  In FIG. 3A, the memory array area 110 is one-time programmable as described in Lang US Patent Application No. 12 / 430,290, which is shared with the assignee and incorporated herein by reference. It is implemented as a multi-level memory cell. Here, a representative integrated circuit structure capable of implementing the three-dimensional wiring structure described herein will be described.

  The memory array region 110 includes a memory access layer 112 including horizontal field effect transistor access devices 131a and 131b having source regions 132a and 132b and drain regions 134a and 134b on a semiconductor substrate 130. The substrate 130 may comprise a bulk silicon or a silicon layer on an insulating layer in known techniques for supporting integrated circuits. The trench isolation structures 135a and 135b isolate and isolate the region of the substrate 130. The word lines 140a and 140b function as the gates of the access devices 131a and 131b. The connection plugs 142a and 142b extend so as to connect the drain regions 134a and 134b and the bit lines 150a and 150b via the interlayer dielectric 144.

  The connection pads 152a and 152b are connected to the lower connection portions 146a and 146b, and are also connected to the source regions 132a and 132b of the access transistor. The connection pads 152a and 152b and the bit lines 150a and 150b exist in the interlayer dielectric 154.

  In the example shown, the level consists of each planar conductive layer of material such as doped polysilicon. Alternatively, the level need not be a planar stacked material layer, but instead may be such that the layer of material varies in the vertical dimension.

  Insulating layers 165-1 through 165-3 separate levels 160-1 through 160-4 from others. The insulating layer 166 overlaps the levels 160-1 to 160-4 and the insulating layers 165-1 to 165-3.

  The plurality of electrode pillars 171a and 171b are formed on the memory cell access layer 112 and extend through the level. In this figure, the first electrode pillar 171a has a central conductive core 170a made of tungsten or other suitable electrode material, for example, and is surrounded by a polysilicon sheath 172a. A layer 174a of anti-fuse material, or other programmable memory material, is formed between the polysilicon sheath 172a and the plurality of levels 160-1 through 160-4. The levels 160-1 to 160-4 are made of n-type polysilicon having a relatively high concentration in this example, and the polysilicon sheath 172a is made of p-type polysilicon having a relatively high concentration. Preferably, the thickness of the polysilicon sheath 172a is deeper than the depth of the depletion layer formed by the pn junction. The depth of the depletion layer is determined in part by the relative doping concentration of the n-type and p-type polysilicon used to form it. The levels 160-1 to 160-4 and the sheath 172a can be similarly implemented using amorphous silicon. Other semiconductor materials can also be used.

  The first electrode pillar 171a is connected to the pad 152a. The second electrode pillar 171b having the conductive core 170b, the polysilicon sheath 172b, and the anti-fuse material layer 174b is connected to the pad 152b.

  The interface region between the plurality of levels 160-1 to 160-4 and the pillars 171a and 171b includes a memory element having a programmable element connected to a rectifier and a direct current, as will be described in detail below.

  In the initial state, the antifuse material layer 174a of the pillar 171a, which is silicon dioxide, silicon oxynitride, or other silicon oxide, has a high resistance. For example, other antifuse materials such as silicon nitride may be used. After programming by supplying the required voltage to the word line 140, the bit line 150 and the plurality of levels 160-1 to 160-4, the layer 174a of the antifuse material is broken, and the antifuse adjacent to the corresponding level is broken. It is assumed that the active region in the material is in a low resistance state.

  As shown in FIG. 3A, the plurality of conductor layers at levels 160-1 to 160-4 are extended to the peripheral region 120 where the support circuit and conductor 180 are formed at the plurality of levels 160-1 to 160-4. . Various devices are implemented in the peripheral 120 to support the decoding logic and other circuitry of the integrated circuit 100.

  Conductors 180 are formed in the wiring structure 190 to connect to the formation areas of the various levels 160-1 to 160-4. As will be described in detail below, the conductor 180 of each level 160-1 to 160-4 is extended through an opening of a level overlying the wiring layer including the conductor wiring 185. Conductor wiring 185 provides wiring between levels 160-1 through 160-4 and the decoding circuit of peripheral portion 120.

  As represented by broken lines in FIG. 3A, the conductors 180 connected to the different levels 160-1 to 160-4 are formed in the longitudinal direction extending in and out of the cross section shown in FIG. 3A.

  FIG. 3B shows a diagram such as the wiring structure 190 shown in FIG. 3B-Fig. It is sectional drawing of the longitudinal direction along 3B line. As shown in FIG. 3B, each level of conductor 180 extends through an overlying level opening to connect to the formation region.

  In the illustrated example, four levels 160-1 to 160-4 are shown. More generally, the small interconnect structure described here can be implemented at levels 0-N where N is at least 2.

  Other types of memory cells and structures can be used in alternative embodiments. For example, in one alternative, the device level may be implemented as a planar memory cell array separated by insulating material, with access devices and access lines formed in the level using thin film transistors or related techniques. Furthermore, the interconnect structure described herein has conductors 180 that extend to various levels within the device within a small footprint, and is implemented by other types of three-dimensional stacked integrated circuit devices.

  3A and 3B, one wiring structure 190 is shown. Multiple wiring structures can be formed to provide more power supply at various locations within the device surrounding memory array region 110. FIG. 4 shows a top layout of an embodiment of the device 100 having a two series wiring structure with a series in regions 190-1, 190-2 at the periphery 120 on each side of the array. FIG. 5 shows a top layout of an embodiment including four series of wiring structures having series 190-1, 190-2, 190-3, 190-4 on the periphery 120 on all four sides of the array. The exemplary array size has 1000 rows and 1000 columns of cells, has 10 levels, the feature size defining the word line width and bit line width is F, and the size of the formation area on the level is F In the example, the length of the area occupied by one wiring structure is approximately several times the level of about 2F, that is, 20F, and the pitch per word line is about 2F, that is, the width of the array is about 2000F. I understand. Thus, in the following example, approximately 100 wiring structures can be formed in a series such as the series 190-3 along the array width, and as in the series 190-1 along the array length. A similar number of series can be formed.

  In still other alternative embodiments, one or more wiring structures may be formed in the memory array region 110 in addition to or as a replacement for the peripheral 120 wiring structure. Further, the wiring structure can be extended obliquely or in any other direction rather than parallel to the end of the memory array region 110.

  FIG. 6 is a schematic view of a part of a memory device including the wiring structure described here. The first electrode pillar 171a is connected to the access transistor 131a selected using the bit line 150a and the word line 140a. The plurality of memory elements 544-1 to 544-4 are connected to the pillar 171a. Each memory element has a programmable element 548 connected in series with a rectifier 549. Although the antifuse material layer is located at the pn junction, this series structure is representative of the structure shown in FIGS. 3A and 3B. The programmable element 548 is often represented by a symbol that is used to indicate an antifuse. However, it should be understood that other types of programmable resistance materials and structures can be used.

  Further, the rectifier 549 implemented by the pn junction between the conductor plane and the polysilicon of the electrode pillar may be replaced by another rectifier. For example, a solid electrolyte base such as germanium silicide or other suitable material rectifier may be used as the rectifier. See US Pat. No. 7,382,647 for other representative solid electrolyte materials.

  Each of memory elements 544-1 to 544-4 is connected to a corresponding conductor level 160-1 to 160-4. Levels 160-1 to 160-4 are connected to the plane decoder 546 through the conductor 180 and the wiring 185. In response to the address, the plane decoder 546 applies a voltage, such as ground 547, to the selected level so that the rectifier of the memory element becomes forward biased and conducts, and the rectifier of the memory element becomes reverse biased and becomes non-conductive The voltage is applied to the floating unselected level so that

  FIG. 7 is a simplified block diagram of an integrated circuit device 300 having a 3D memory array 360 having a wiring structure described herein. Row decoder 361 is connected to a plurality of word lines 140 arranged along a row of memory array 360. The column decoder 363 is connected to a plurality of bit lines 150 arranged along the columns of the memory array 360, and reads and writes data from the memory cells in the array 360. The plane decoder 546 is connected to the plurality of levels 160-1 to 160-4 of the memory cell 360 through the conductor 180 and the wiring line 185. The address is supplied from the bus 365 to the column decoder 363, the row decoder 361, and the plane decoder 546. The sense amplifier and data-in structure in the block 366 are connected to a column decoder 363 in this example via a data bus 367. Data is supplied from the input / output port on the integrated circuit 300 to the data-in structure of the block 366 via the data-in line 371. In the illustrated embodiment, other circuits 374 may be provided on the integrated circuit 300, such as a general purpose processor, a special purpose application circuit, or a combination of modules that provide system functions on a chip. Data is supplied from the sense amplifier in the block 366 to the input / output port of the integrated circuit 300 via the data-out line 372 or to other data destinations inside and outside the integrated circuit 300.

  The controller using the bias adjustment state device 369 implemented in this example controls the application of the bias adjustment supply voltage generated or provided from the voltage supply unit, or supplies the read and write voltages in the block 368. The controller may be implemented using special purpose logic circuits known in the art. In an alternative embodiment, the controller has a general purpose processor that is implemented on the same integrated circuit and runs a computer program to control the operation of the device. In another embodiment, a special purpose logic circuit and a general purpose processor are combined to help the operation of the controller.

  8A-8C through 15 illustrate the steps of an embodiment of a processing sequence for producing a wiring structure having a very small footprint as described herein.

  8A and 8C are cross-sectional views of the first process in the processing order, and FIG. 8B is a top view of the first process in the processing order. For the purpose of this application, the first step forms a plurality of levels 160-1 to 160-4 overlying the provided memory cell access layer 112. In the illustrated embodiment, the structure illustrated in FIGS. 8A-8C is made using the process described in Lang's shared US patent application Ser. No. 12 / 430,290 and is included by reference above. It is supposed to be.

  In alternative embodiments, the levels can be made by standard processes known in the art, depending on the device in which the wiring structure described herein is implemented, transistors, diodes, word lines, bit lines, source lines, Access devices such as conductor plugs, doped regions in the substrate may be included.

  As noted above, other types of memory cells and structures in the memory array region 110 can be used in alternative embodiments.

  Next, a first mask 800 having an opening 810 is formed over the structure shown in FIGS. 8A-8C, resulting in the structure shown in top and cross-section in FIGS. 9A and 9B, respectively. The first mask 800 can be formed by depositing a layer for the first mask 800, and patterning the layer using a lithography technique to form the opening 810. The first mask 800 may be formed of a hard mask material such as silicon nitride, silicon oxide, or silicon oxynitride.

  The opening 810 of the first mask 800 surrounds the combination of formation regions above the levels 160-1 to 160-4. Thus, the width 192 of the opening 810 is at least as large as the width of the formation region above the levels 160-1 to 160-4, and the subsequently formed conductor 180 can pass through the level opening. The length 194 of the opening 810 is at least as large as the total length of the formation region above the levels 160-1 to 160-4, and the subsequently formed conductor 180 passes through the level opening. it can.

  Next, a second etching mask 900 is formed on the structure illustrated in FIGS. 9A-9B, including the opening 810, and is illustrated in FIGS. 10A and 10B in a top view and a cross-sectional view, respectively. Result in a structure. As shown in the figure, the second etching mask 900 has a length 910 that is shorter than the length 194 of the opening 810 and has a width at least as large as the width 192 of the opening 810.

  In the illustrated embodiment, the second etching mask 900 is composed of a material that can be selectively etched with respect to the material of the first mask 800, and the length of the second mask 900 inside the opening 810 is: It is selectively shortened in the subsequent process steps described below. In other words, the material of the second mask 900 has an etching rate that is greater than the etching rate of the material of the first mask 800 of the process used to reduce the length of the second mask 900. For example, in embodiments where the first mask 800 has a hard mask material, the second mask can be made of photoresist.

  Next, an etching process is performed on the structure shown in FIGS. 10A-10B using the first and second masks 800, 900 as etching masks, and is illustrated in the top and cross-sections of FIGS. 11A-11B. Result in a structure. The etching process can also be performed using a single etch chemistry using, for example, timing mode etching. Alternatively, the etching process may be performed using different etch chemistries that etch through insulating layer 166, level 160-4, insulating material 165-3, and level 160-3, respectively.

  Etching forms an opening 1000 through level 160-4 to expose a portion of level 160-3. Opening 1000 overlies formation area 161-1a above level 160-1. The opening 1000 has a length 1002 that is at least approximately the same as the length of the formation region 161-1a, and has a width 1004 that is at least approximately the same as the width of the formation region 161-1a.

  An opening 1010 is formed by etching and through level 160-4 to expose a portion of level 160-3. Opening 1010 overlies formation area 161-1b above level 160-1. The opening 1010 has a length 1012 that is at least about the same as the length of the formation region 161-1b, and has a width 1014 that is at least about the same as the width of the formation region 161-1b.

  Next, the length 910 of the mask 910 is shortened to form a short length mask 1100 having a length 1110, resulting in the structures illustrated in the top and cross sections of FIGS. 12A and 12B, respectively. In the illustrated embodiment, the mask 900 is made of a photoresist and can be removed using, for example, reactive ion etching with chlorine or hydrogen bromide-based chemicals.

  Next, the etching process is performed on the structure shown in FIGS. 12A and 12B using the first mask 800 and the short-length mask 1100 as an etching mask, and the structure shown in top and cross-section in FIGS. 13A and 13B. Bring.

  The etching process extends to the openings 1000 and 1010 through the level 160-3 and exposes the underlying portion of the level 160-2.

  From the etching, openings 1200 and 1210 are further formed through the portions of the level 160-4 that are no longer covered by the mask 1100 due to the shortening of the length of the mask 1100, and the portions of the level 160-3 are exposed. The opening 1200 is formed in the vicinity of the opening 1000 and overlaps the formation region 161-2a above the level 160-2. The opening 1200 has a length 1202 that is at least approximately the same as the length of the formation region 161-2a, and has a width 1204 that is at least approximately the same as the width of the formation region 161-2a.

  The opening 1210 is formed in the vicinity of the opening 1010 and overlaps the formation region 161-2b above the level 160-2. The opening 1210 has a length 1212 that is at least as large as the length of the formation region 161-2b, and has a width 1214 that is at least as large as the width of the formation region 161-2b.

  Next, the length 1110 of the mask 1110 is shortened to form a short length mask 1300 having a length 1305. The etching process is performed using the first mask 800 and the short length mask 1300 as an etching mask, resulting in the structure shown in FIGS. 14A and 14B in top and cross-section.

  The etching process extends to the openings 1000 and 1010 through the level 160-2 and exposes the formation regions 161-1a and 161-1b above the level 160-1. The etching process extends to the openings 1200 and 1210 through the level 160-3 and exposes the formation regions 161-2a and 161-2b above the level 160-2.

  From etching, openings 1310 and 1320 are further formed through portions of level 160-4 that are no longer covered by the shortening of the length of mask 1300 to expose formation regions 161-3a and 161-3b of level 160-3. To do.

  The opening 1310 is formed in the vicinity of the opening 1200. The opening 1310 has a length 1312 that is at least approximately the same as the length of the formation region 161-3a, and has a width 1314 that is at least approximately the same as the width of the formation region 161-3a.

  The opening 1320 is formed in the vicinity of the opening 1210. The opening 1320 has a length 1322 that is at least as long as the length of the formation region 161-3b, and has a width 1324 that is at least as large as the width of the formation region 161-3b.

  Next, an insulating fill material 1400 is deposited on the structure illustrated in FIGS. 14A-14B, a planarization process such as chemical mechanical polishing (CMP) is performed, the masks 800, 1300 are removed, and the cross-sectional view of FIG. The structure shown in FIG.

  Next, a lithography pattern is formed to define a via portion to the formation region of the conductor 180. Reactive ion etching can be used to form deep and high aspect ratio vias through the insulating fill material 1400, and the vias of the conductor 180 can be provided. After opening the via portion, the via portion is filled with tungsten or other conductive material to form the conductor 180. A metallization process is applied to form wiring 185 to provide wiring between the conductor 185 and the planar decoding circuit. Finally, a back end of line (BEOL) process is applied to complete the integrated circuit, resulting in the structure shown in FIGS.

  The various levels of openings used to pass the conductor through the formation area above the underlying level, using the openings 810 of the single etch mask 800, similarly, without additional critical alignment steps. It is formed by patterning the level using the etching process in FIG. As a result, openings for various levels with vertically aligned sidewalls are formed in a self-aligned manner.

  In the illustrated example described above, the opening 810 of the mask 800 has a rectangular cross section in plan view. As a result, the various levels of openings have substantially the same width along the lateral direction. Alternatively, the openings of the mask 800 may each have a circular, elliptical, square, rectangular, or other somewhat distorted cross section, depending on the shape of the various levels of formation regions.

  For example, the width of the opening of the mask 800 can be changed along the longitudinal direction in accordance with formation regions having different widths. FIG. 16 shows a plan view of the opening 1510 of the mask 800 having different widths stepwise in the longitudinal direction, and the width of the level opening varies accordingly.

  From here on, the present invention will be described mainly with reference to FIGS.

  The following description will typically refer to specific structural embodiments and methods. It should be understood that the invention is not intended to be limited to the specifically disclosed embodiments and methods, although the invention may be practiced using other features, elements, methods, and embodiments. . The preferred embodiments are set forth to illustrate the invention and are not intended to limit the scope thereof as defined by the claims. Those skilled in the art will recognize various equivalent variations of the description that follows. Similar elements in the various embodiments are commonly referred to by similar reference numerals.

  FIG. 17 is a simplified flow diagram for a method 10 for making a wiring connection region 14 according to the present invention. The wiring connection region manufacturing method of FIG. 17 includes obtaining a set of N masks in the acquisition step 12. Further steps of the method 10 shown in FIG. 17 are described below in conjunction with FIGS. 18-27 to illustrate a first example of a method for carrying out the present invention.

  As shown in FIG. 27, the N mask sets produce up to 2N levels of the wiring connection region 14 in the stacked portion 16 of the connection levels 18.1, 18.2, 18.3, and 18.4. The laminated portion 16 is formed in the wiring region 17 of the three-dimensional laminated IC device. The wiring region 17 is typically a peripheral wiring region as shown in FIGS. 4 and 5, but may be located elsewhere. In the three examples of FIGS. 18 to 44, four connection levels are shown on the substrate 19 for simplicity of illustration, and the three-dimensional stacked IC device has more connection levels in common. As will be described below, each mask has a mask and an etched region, and N is an integer equal to at least 2. X is a serial number assigned to the mask, one mask is X = 1, the other one is X = 2, and X = N. If X = 1, one connection level 18 is etched in the etching process for the associated mask. When X = 2, two connection levels are etched in the etching process for the associated mask.

  Next, as shown in FIG. 17, a partial removal step 20 is executed to remove the portion 22 of the upper layer 24 that overlaps the integrated portion 16 at the connection level 18 shown in FIG. In this example, the upper layer 24 has first and second silicon oxide layers 26, 28 and a charge trapping layer 27 typically comprised of silicon nitride therebetween. In this example, this removal is completed using an additional mask 30 having an open region 32, allowing etching of the portion 22 of the upper layer 24 as shown in FIG. In this example, each of the connection levels 18 is typically an upper conductor layer 34, which is a patterned polysilicon layer that forms a conductor such as a word line, and typically a silicon oxide or silicon nitride compound. And a lower insulating layer 36. Reference layer 34 is typically referred to as polysilicon layer 34. However, layer 34 may be formed from other suitable materials such as, for example, metal, metal silicide, and multilayer combinations from polysilicon, metal silicide, more than one of the metals. Etching of the top layer 24 through the dielectric layer 28 is typically controlled using a material selective etching process. For example, if dielectric layer 28 is silicon oxide and layer 34 is polysilicon, the etching is effectively stopped when it reaches layer 34 using reactive ion etching to etch dielectric layer 28. Similar techniques can be used to control the depth of etching in other situations. Other techniques for controlling the depth of etching can also be used. Since the additional mask 30 is used to simply open a space for etching the integration 16 at the connection level 18, the additional mask 30 is not considered part of the set of N masks. In the example described below with respect to FIGS. 28-34, any additional layer 24 is removed from the interconnect connection region using a blanket etch without the need for an additional mask.

  FIG. 20 illustrates the formation of a first mask 38.1 on the connection level 18 stack 16 of FIG. In this example, the first mask 38.1 has photoresist mask elements 40.1, 40.2, 40.3, of which the mask element 40.2 is the center of the first polysilicon layer 34.1. Covering the part 42.1, the mask element 40.3 covers the end part 42.2 of the first polysilicon layer 34.1. FIG. 21 shows the result of an etching process in which the part of the connection level 18.1 that is not covered by the photoresist mask element 40 is etched down to the connection level 18.1. That is, one connection level 18 is etched in this first etching step.

  FIG. 22 illustrates the formation of a second photoresist mask 38.2 on the connection level 18 stack 16 of FIG. The mask 38.2 covers the portions of the polysilicon layers 34.1, 34.2 that will be used later as wiring connection regions 14.1, 14.2, as suggested by the dashed lines in FIG. FIG. 23 shows the result of a second etching step in which two connection levels are etched. In particular, the exposed surface portion 44 of the polysilicon layer 34.2 removes the two layers by etching, exposing a portion 46 of the polysilicon layer 34.4. Further, the exposed portion of the polysilicon layer 34.1 or the two layers are removed by etching to expose the portion 47 of the polysilicon layer 34.3. FIG. 24 shows a second example in which portions of the polysilicon layers 34.1, 34.2, 34.3, 34.4 used as the wiring connection regions 14.1, 14.2, 14.3, 14.4 are left. The result of removing the mask 38.2 is shown. The thin column portion 48 at connection level 18.1 is often referred to as a dummy stack or a partial height dummy stack and can be provided for manufacturing tolerance or as a result.

  In the example of FIGS. 18 to 24, the two masks 38.1 and 38.2 are connected to the formation regions of the four wiring connection regions 14-1 to 14-4 at four different connection levels 18-1 to 18-4. Used to provide access. According to the present invention, the wiring region 17 is etched N times using N masks to produce a wiring connection region 14 for each of the 2N connection levels 18. The wiring connection area 14 is aligned with the formation area 56 and provides access at each of the 2N connection levels, as will be described below with reference to FIG. Each etching step has an etching through 2X-1 connection levels of each mask with serial number X. Refer to the wiring region etching process of FIG.

  FIG. 25 illustrates the optional step of applying an etch stop layer 50 such as silicon nitride over the exposed surface of the etched integration 16 at the connection level 18 when the interlayer insulator is silicon oxide. Results are shown. Thereafter, an interlayer dielectric 52 is deposited on the structure of FIG. 25 by the etching region filling step 53 of FIG. 17 as shown in FIG. This continues to form the electrical conductor 54 via the interlayer dielectric 52 and the etch stop layer 50 so as to conduct to the electrically conductive formation region 56 in the wiring connection region 14. Conductor 54 may be formed using a tungsten plug process, which includes forming a via portion through a dielectric fill that provides an opening to a formation region above a selected layer, and includes CVD. Alternatively, by using a PVD process, an adhesive layer is formed in the via portion, and tungsten is deposited to fill the via portion, thereby forming the vertical conductor 54 in the formation region. This is illustrated in FIG. 27 and shown as the electrical conductor formation step 60 of FIG.

  A second example will be described with reference to FIGS. 28-34 with like reference numerals referring to like elements of the first example of FIGS. The stacked portion 16 at the connection level 18 in the wiring region 17 in FIG. 28 has the same basic structure as that in FIG. In this example, the dielectric layer 26 and charge trapping layer 27 of the top layer 24 are removed by a blanket etch process, eliminating the need for an additional mask 30. A first mask 38.1 is formed on the dielectric layer 28 and has an opening area 41.1 between the mask elements 40.1, 40.2 and an opening area between the mask elements 40.2, 40.3. Formed with 41.2. This is followed by the first etching step shown in FIG. 31, where the openings 62, 63 are formed between the openings 41.1 between the mask elements 40.1, 40.2 and the mask elements 40.2, 40.3. An opening 41.2 is formed between the dielectric layer 28 and the polysilicon layer 34.1. Such an etching process can be continued up to the polysilicon layer 34.2, but there is no need to prove the reason as described with reference to FIGS. Second mask 38.2 includes mask elements 40.4, 40.5, with mask element 40.5 covering opening 63, and dielectric layer 28 between opening 62 and openings 62, 63. The portion 64 is not covered.

  FIG. 33 illustrates the result of a second etching step in which two connection levels are etched. In particular, opening 62 is etched to oxide layer 36.3 and portion 64 of dielectric layer 28 is etched to oxide layer 36.2 by two connection levels. The second mask 38.2 is then removed and an interlayer dielectric 52 is deposited over the etched structure shown in FIG. This is because the interlayer dielectric 52 and the oxide layer 28 covering the polysilicon layers 34-1 to 34-4 for connection to the formation regions 56.1 to 56.4 of the wiring connection regions 14-1 to 14-4 are formed. , 36.1, 36.2, 36.3 followed by formation of conductors 54.1-54.4.

  Like the example of FIGS. 18-24, in the example of FIGS. 28-34, the two masks 38.1, 38.2 have four wiring connection regions 14 at four different connection levels 18.1 to 18.4. Used to provide access to the formation areas 56.1 to 56.4 of .1 to 14.4. According to the present invention, the wiring region 17 is etched N times using N masks to produce a wiring connection region 14 at each connection level 18. The wiring connection area 14 is aligned with the formation area 56 of each of the 2N connection levels and provides access. Again, the etching step comprises an etching process through 2x-1 connection levels of each mask with serial number X.

  FIGS. 35-44 illustrate a third example of a method of practicing the invention again with like reference numbers referring to like elements. The first mask 38.1 is formed on the stacked portion 16 of the connection level 18 between the upper layer 24 and the wiring region 17. Photoresist mask elements 40.1, 40.2, 40.3 have an open area 66.between mask elements 40.1 and 40.2 and between mask elements 40.2 and 40.3 as shown in FIG. 1 and 66.2 are formed. Below the open regions 66.1, 66.2, a portion of the upper layer 24 is the first connection level 18 poly that creates the first and second openings 68.1, 68.2 of the upper layer 24. The silicon layer 34.1 is etched. Openings 68.1, 68.2 expose surface portions 70.1, 70.2 of first polysilicon layer 34.1.

  FIG. 38 shows the result of depositing sidewall material 72.1, 72.2 on the sidewalls of the first and second openings 68.1, 68.2. This can be completed in different ways, for example by depositing a blanket layer of insulating material such as silicon nitride on the wafer by CVD or sputtering, except in the region adjacent to the vertical sidewall where the sidewall spacer remains. Anisotropic etching is performed until material is removed from the horizontal plane of the wafer. The sidewall material 72.1, 72.2 covers the first portions 74.1, 74.2 of the surface portions 70.1, 70.2, respectively, 2 parts 76.1, 76.2 are not covered.

  The structure of FIG. 38 then reduces the size of the sidewall material 72.1, 72.2 without attacking the sidewall material and exposes the polysilicon layer 34.2 first through one connection level, Etching is performed by, for example, anisotropic reactive ion etching for extending the second openings 68.1 and 68.2. See FIG. 39. Then, as in FIG. 40, the sidewall material 72.1, 72.2 is removed, exposing the first portions 74.1, 74.2 of the surface portions 70.1, 70.2. FIG. 41 shows a second mask 38.2 over the structure of FIG. 40 filling the second opening 68.2. The first opening 68.1 includes a portion 78 of the third polysilicon layer 34.3 below the first portion 74.1 and a fourth polysilicon layer 34 below the second portion 76.1. It is assumed that two connection levels have been etched to expose the portion 80 of .4.

  The second mask 38.2 is then removed and the structure of FIG. 42 is covered by an interlayer dielectric 52 as shown in FIG. FIG. 44 shows a result of forming the conductors 54-1 to 54-4 connected to the formation regions 56-1 to 56-4 in the wiring connection regions 14-1 to 14.4.

  The method illustrated in FIGS. 35-44 is particularly suitable when a relatively thick upper layer 24 is used over the stack 16 at the connection level 18. The SiN layer 50 used in the examples of FIGS. 18 to 27 can also be used in the second and third examples.

  FIG. 45 illustrates a manufacturing method example of 16 connection levels 18. According to the invention, for each of the 16 connection levels 18, the wiring connection area 14 can be accessed using only 4 masks 38. In this example, the first mask 38.1 has eight photoresist mask elements 40 labeled 1, 3, 5,..., Labeled 2, 4, 6,. Continuing to the opening etching area 41 formed. In this example, each mask element 40 and each end of the region 41 have a dimension in the longitudinal direction for one unit. One layer is etched for the first mask 38.1. The second mask 38.2 has four photoresist mask elements labeled 1/2, 5/6, ... and labeled 3/4, 7/8, ... Following the opening etch region, each has a longitudinal dimension of two units. The two layers are etched using the second mask 38.2. The third mask 38.3 has two photoresist mask elements labeled 1-4, 9-12, followed by an opening etch area labeled 5-8, 13-16, respectively. Has longitudinal dimensions for four units. The four layers are etched using the third mask 38.3. The fourth mask 38.4 has one photoresist mask element labeled 1-8, followed by an opening etch region labeled 9-16, each of which is 8 units long. Have the dimensions of The eight layers are etched using a fourth mask 38.4.

As described above, when x is 1 and the first mask 38.1 is used, the single layer 18 is etched (2 ^x-1 = 2 ⁰ = 1). When the second mask 38.2 is used, the two layers 18 are etched (2 ^x-1 = 2 ¹ = 2). When the third mask 38.3 is used, the four layers 18 are etched (2 ^x-1 = 2 ² = 4). When the fourth mask 38.4 is used, the eight layers 18 are etched (2 ^x-1 = 2 ³ = 8). Thus, any number of connection levels 18 between 1 and 16 can be accessed using several combinations of one level etch, two level etch, four level etch, and eight level etch. it can. Another way of thinking about this is that the four masks represent four-digit binary numbers corresponding to decimal numbers 1 to 16, ie 0000, 0001, 0010,. For example, to access the wiring connection region 14 at connection level 18, it is necessary to etch 12 connection levels, which includes the third mask 38.3 (etching 4 connection levels) and the fourth It can be completed with the opening area 41 for the mask 38.4 (etching 8 connection levels). FIG. 46 shows the result of using the masks 38.1 to 38.4 of FIG. Conventional methods typically require 16 different masks, resulting in increased cost of manufacturing and increased potential for defects to achieve resistance.

  The example of FIGS. 45 and 46 provides a continuous and open process area of the wiring connection area 14 that is aligned with the formation area 56. FIG. 47 shows 16 connection level 18 integrated portions 16 in which four masks 38 have a total height dummy integrated portion 82 between each interconnect connection region 14 and an integrated portion 84 at the total height boundary adjacent to the connection regions 14, 16. An example is shown that is configured to fabricate. This is obtained by providing the dummy mask region 86 for each mask 38 when the dummy integrated portion 82 is to be produced anywhere. In this example, a dummy integrated portion 82 is disposed between each wiring connection region 14. However, in some examples, one or more dummy integration portions 82 may be omitted. Further, the dimension in the longitudinal direction of the dummy accumulation portion 82 need not be the same.

  The masks 38 need not be used in the order of the number of connection levels 18 etched with each mask. That is, the mask 38.2 can be used before the mask 38.1. However, the masks are preferably used in ascending order of the number of connection levels to be etched, because this is a larger process window, the mask used to etch one connection level is first, This is because the mask used to etch the connection level is second.

  In the example of FIG. 47, the dummy mask region 86 is disposed at a corresponding position of each mask 38 such that the resulting dummy integrated portion 82 becomes a full height dummy integrated portion. 24 can be fabricated by forming dummy mask regions 38 at corresponding positions on one or more, but not all, masks 38, such as the thin column portion 48 of FIG. .

  17 to 44 is described with reference to N = 2 and FIGS. 45 to 47 with reference to N = 4. However, the number of masks may be other than 3, and N may be larger than 4. A set of N masks can be used to create 2N levels of wire connection regions, and can also be used to make up to and including 2N levels of wire connection regions. be able to. For example, when N is equal to 4, four masks can be used to create a level of the wiring connection region that is less than 16 levels of the wiring connection region, eg, 13, 14, 15 levels.

  Although the present invention has been described by reference to the preferred embodiments and examples described above, it should be understood that these examples are intended to be described rather than in a limiting sense. Modifications and combination examples are easily generated by those skilled in the art, and these modification examples and combination examples are within the scope of the present invention and are within the scope of the following claims.

  The disclosures of any and all patents, patent applications, and printed publications referred to above are hereby incorporated by reference.

Claims (27)

A method used to form a wiring connection region that is aligned with and exposed to a formation region at the connection level in a three-dimensional stacked integrated circuit device having a connection level stacked portion in the wiring region, the method comprising:
Using a set of N etching masks that create and include up to 2 ^N (2 ^N ) levels of wiring connection regions in the connection level stack, where each mask has a mask and an etching region; N is an integer that is at least 2, X is a sequential number assigned to the mask, one mask is X = 1, the other one is X = 2, and X = N,
Removing at least part of the upper layer overlying the connection level stack of the wiring region;
In order to selectively form connection openings extending from the surface layer to the connection level, the wiring region is etched N times using the mask, where the connection openings are 2 N (2 ^N ) shall be aligned to provide access to the formation area at each of the connection levels,
The etching process etches up to 2X-1 power (2 ^X-1 ) connection levels of each mask of serial number X,
A method wherein a conductor can be formed to connect to the connection level formation region via the connection opening. The method of claim 1, comprising:
Furthermore, in order to define the via pattern surface, a filling material is given to the opening,
Opening the via portion through the filling material to expose the formation region of each connection level,
A method of laminating a conductive material in the via portion. The method of claim 1, wherein the accessing step is performed with a mask having a dummy mask region in at least one of the masks. The method of claim 1, wherein the accessing step is performed with a mask having dummy mask regions at least at some corresponding positions of the mask. 2. The method of claim 1, wherein the accessing step is performed with a mask having at least one dummy mask region at each corresponding position of the mask. The method of claim 1, wherein the accessing step is performed with N equal to at least four. The method according to claim 1, wherein the performing steps are performed in the order of a serial number X. 2. The method according to claim 1, wherein the removing step is performed using an additional mask that exposes a wiring region. The method according to claim 1, wherein the removing step is performed using a blanket etching step in a wiring region. The method according to claim 1, wherein in the removing step, an opening part of which a sidewall is partially bounded is formed in the upper layer exposing the upper surface part of the first connection level,
In the etching process of the wiring region,
A second portion of the upper surface portion is left without a sidewall material, and a sidewall material is laminated on the sidewall of the opening and on the first portion of the upper surface portion,
Expanding the opening through the second portion of the upper surface to provide access to the upper surface of the lower connection level;
At least some of the sidewall material is removed to expose some of the first portion of the upper surface to form a wiring connection region that is aligned with and provides access to the first and lower connection level formation regions. And
The method wherein the sidewall material is utilized as one of N etching masks. 12. The method of claim 10, wherein the sidewall material removal step is performed to expose the formation region. 11. The method of claim 10, wherein the sidewall material removal step is performed by removing substantially all of the sidewall material. 11. The method of claim 10, wherein the opening forming step is performed on a layer that is an upper layer, and the selected connection level is a first connection level. The method according to claim 1, wherein in the removing step, first and second openings are formed in an upper layer exposing an upper surface portion of a first connection level in each opening,
In the etching process of the wiring region,
A second portion of each upper surface portion is left without a sidewall material, and a sidewall material is laminated on the sidewall of the opening and on the upper surface portion,
Expanding each of the first and second openings through the second portion of the upper surface portion to expose the upper surface of the second connection level at each opening;
At least some of the sidewall material is removed to expose some of the first portion of the upper surface portion, forming a wiring connection region in the second opening, and the wiring connection region of the second opening Is aligned with and provides access to the formation regions of the first and second connection levels;
Further, the first opening is expanded from the exposed first portion of the upper surface portion through the first and second connection levels to expose the upper surface of the third connection level, and the second And the first opening is expanded from the exposed upper surface of the second connection level via the third connection level to expose the upper surface of the fourth connection level, and the wiring connection of the first opening Regions are aligned with and provide access to the formation regions at the third and fourth connection levels;
The method wherein the sidewall material is utilized as one of N etching masks. A method of arranging electrical connection in a formation region in a connection portion of a connection region of a wiring region for a type of three-dimensional stacked integrated circuit device having a wiring region, wherein the wiring region includes an upper layer and the upper layer Having a stack of at least first, second, third and fourth connection levels below the layer, the method comprising:
At least first and second openings are formed in the upper layer, each opening exposes a surface portion of the first connection level, and the first and second openings are partially upper layer sidewalls. A boundary is formed,
A second portion of the surface portion remains without a sidewall material, and a sidewall material is laminated on the sidewalls of the first and second openings and on the respective first portions of the surface portion,
Expanding the first and second openings, respectively, through the second portion of the surface portion to expose the surface of the second connection level at each of the first and second openings;
At least some of the sidewall material of each opening is removed to expose some of the first portion of the surface of each opening to form a wiring connection region in the second opening, The wiring connection region of the two openings is aligned with the formation region of the first and second connection levels;
Further, the first opening is extended from the exposed first portion of the surface through the first and second connection levels to expose the surface of the third connection level, and the second And extending the first opening from the exposed surface of the second connection level through the third connection level to expose the surface of the fourth connection level, and The wiring connection region is aligned with the formation region at the third and fourth connection levels;
Forming a conductor in the formation region of the first, second, third, and fourth connection levels; The method according to claim 15, wherein in the step of forming the conductor, a filling material is further applied to the opening to define a via pattern surface,
Opening the via portion through the filling material to expose the formation region of each connection level,
A method of laminating a conductive material in the via portion. 16. The method according to claim 15, wherein the forming step of the first and second openings is performed so as to expose an upper surface portion of the first connection level, and further, in the expanding step, the third and second openings are formed. 4. A method which is carried out so as to expose a formation region of four connection levels. A set of masks used to form a wiring connection region that matches a formation region in a connection portion of a connection area of a wiring region for a three-dimensional stacked integrated circuit device, wherein the connection portion stack portion is an upper layer And the set of masks is
A set of N etching masks, each mask having a mask and an etching region, and the etching region is a power of 2 ^N-1 (2 ^N-1 ) wiring regions of the three-dimensional stacked integrated circuit device; N is an integer that is at least 3, X is a sequential number assigned to the mask, and one mask is X = 1, the other mask is X = 2, and X = N. A set of masks. 19. The mask set of claim 18, wherein the sidewall material is utilized as one of N etching masks. 19. The mask set of claim 18, wherein the etching mask has at least one dummy mask region on the etching mask. 19. The mask set according to claim 18, wherein the etching mask has a dummy mask region at a position corresponding to some of the etching masks. 19. The mask set of claim 18, wherein the etching mask has at least one dummy mask region at a corresponding position of the etching mask. 19. A mask set according to claim 18, wherein the longitudinal dimensions of the etching regions of the selected etching mask are substantially equal. 19. The mask set of claim 18, wherein the mask and the etched region have a longitudinal dimension, and the etched region of the selected mask and the selected mask have substantially the same longitudinal dimension. A set of masks. 19. The mask set of claim 18, wherein the mask and the etched region have longitudinal dimensions, and the mask and the etched regions of all masks have substantially the same longitudinal dimension. Pairs. 19. A mask set according to claim 18, wherein N is equal to or greater than four. A set of masks used to form a wiring connection region that matches a formation region in a stacked portion of a connection level of a wiring region for a three-dimensional stacked integrated circuit device, the mask set comprising:
A set of N etching masks, each mask having a mask and an etching region, and the etching region up to 2 ^N (2 ^N ) connection levels of the wiring region of the three-dimensional stacked integrated circuit device And N is an integer that is at least 2, X is a sequential number assigned to the mask, and one mask is X = 1. A set of masks, wherein another mask is X = 2 and X = N.