CN110071112A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN110071112A CN110071112A CN201910247660.2A CN201910247660A CN110071112A CN 110071112 A CN110071112 A CN 110071112A CN 201910247660 A CN201910247660 A CN 201910247660A CN 110071112 A CN110071112 A CN 110071112A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The manufacturing method of the 3D memory device includes: that the first laminated construction and the channel hole through the first laminated construction is formed on the substrate, and first laminated construction includes the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；Barrier layer and channel column are formed in the channel hole, barrier layer is between the sacrificial layer and channel column；The multiple sacrificial layer is replaced using multiple gate conductor layers, forms laminated construction；And form the conductor channel for running through the laminated construction.The application forms high-K dielectric layer in channel hole before forming channel column and is separated from each other grid conductor and channel column, to reduce the depositing operation difficulty of high-K dielectric layer, improve the spreadability and uniformity of high-K dielectric layer film, expand the process window in channel hole, it avoids destroying high-K dielectric layer film when sacrificial layer removes in grid line gap, to improve the yield and reliability of 3D memory device.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductor system
The characteristic size for making technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
The memory device (that is, 3D memory device) of three-dimensional structure is developed.3D memory device includes stacking along vertical direction
Multiple storage units can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technologies point
It Cai Yong not NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but speed is written
Degree is fast, and erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it adopts
It is had been widely used with the 3D memory device of NAND structure.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor are provided using laminated construction
Pole conductor, using interconnection that run through laminated construction and the conductive channel realization memory cell string with laminated construction insulation.It is typical
3D memory device manufacturing process as shown in Fig. 1 a- Fig. 1 c, multiple dielectric layers are deposited on the substrate 1 of usually Si and are stacked
The laminated construction 2 (such as oxide and the alternate structure of nitride) of composition；By anisotropic etching technics to substrate 1
Upper multi-layer laminate structure 2 is etched and is formed along the distribution of memory cell wordline (WL) extending direction, perpendicular to substrate surface
Multiple channel holes 2 (CH) (can go directly substrate surface or have certain over etching)；The materials such as deposit polycrystalline silicon in channel hole 2
Material forms column channel (being not shown below)；The groove of through substrate is formed along the direction WL etching multi-layer laminate structure 2
(i.e. grid line gap GLS), exposing are enclosed in multilayer laminated around column channel；Wet process removes a certain class profile in lamination
Expect (such as hot phosphoric acid goes silicon nitride or HF to remove silicon), the protrusion knot of cross direction profiles is left around column channel
Structure；The side wall deposition gate dielectric layer 3 (such as high K medium material) and 4 (example of grid conducting layer of raised structures in the trench
Such as Ti, W, Cu, Mo) grid conducting layer is formed, for example including bottom selection grid polar curve, dummy gate electrode line, wordline, top choosing
Select grid line；Grid conducting layer except perpendicular magnetic anisotropy etching removal protrusion side plane, until exposing protrusion side
Gate dielectric layer；Etching stack structure forms source and drain and contacts and complete back end fabrication.
In the prior art, the high-K dielectric layer film of the 3D memory device for 128 layers and higher than 128 layers, deposition covers
Lid is poor, uneven thickness, and the performance of device is caused to decline.It is expected that being further improved structure and its manufacturer of 3D memory device
Method, to improve the yield and reliability of 3D memory device.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, wherein is forming channel column
It forms high-K dielectric layer in channel hole before to be separated from each other grid conductor and channel column, to reduce the heavy of high-K dielectric layer
Product technology difficulty, improves the coverage rate and uniformity of high-K dielectric layer, expands the process window in channel hole.
According to an aspect of the present invention, a kind of manufacturing method of 3D memory device is provided, comprising:
Be formed on the substrate the first laminated construction, first laminated construction include the multiple sacrificial layers being alternately stacked and
Multiple interlayer insulating films；
The channel hole for running through the first laminated construction is formed, the channel hole extends to substrate interior；
Barrier layer is formed in the channel hole and channel column, the barrier layer are located at the sacrificial layer and channel column
Between；
The multiple sacrificial layer is replaced using multiple gate conductor layers, forms laminated construction；And
Form the conductor channel for running through the laminated construction.
Preferably, the barrier layer is high-K dielectric layer.
Preferably, it is being formed between barrier layer further include: in channel inner hole deposition product separation layer.
Preferably, the separation layer is oxide skin(coating).
Preferably, the step of forming laminated construction includes: the grid line gap to be formed through first laminated construction；It is logical
It crosses grid line gap and removes the multiple sacrificial layer in first laminated construction, to be formed and the grid line gap area
Cavity；Metal layer is filled in the grid line gap and the cavity by grid line gap；And the metal layer is lost
It carves, grid line gap is re-formed, so that the metal layer to be divided into the multiple grid conductor of different level.
Preferably, between the step of forming cavity and the step of filling metal layer, further includes: stitched via the grid line
Gap forms stratum nucleare on the surface of the multiple interlayer insulating film.
Preferably, in the step of re-forming grid line gap, the grid conductor of same level is divided in the grid line gap
It is cut into a plurality of grid line.
Preferably, the lower part of the conductive channel is formed with polysilicon layer and the conductive layer around the polysilicon layer.
Preferably, before forming conductive channel further include:
Barrier layer is deposited in the grid line gap.
According to another aspect of the present invention, a kind of 3D memory device is provided, comprising: substrate；Lamination above substrate
Structure, the laminated construction include the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；Multiple channel columns, are passed through
Wear the laminated construction；Barrier layer is isolated by multiple gate conductor layers with the channel column；Conductive channel runs through the lamination
Structure.
Preferably, the barrier layer is high-K dielectric layer.
Preferably, the 3D memory device further include: separation layer, each other with the barrier layer by the gate conductor layer
It separates, the separation layer is oxide skin(coating).
Preferably, the bottom end of the multiple channel column forms common source connection via the substrate, and the conductive channel mentions
The conductive path of source electrode line is connected to for the common source, the lower part of the conductive channel is polysilicon layer and surrounds described more
The conductive layer of crystal silicon layer.
Preferably, the 3D memory device further includes the doped region in the substrate, the conductive channel with it is described
Doped region contact.
Preferably, the 3D memory device further include: stratum nucleare, on the surface of the interlayer insulating film.
Preferably, the 3D memory device further includes grid line gap, and the laminated construction is run through in the grid line gap, from
And the multiple grid conductor is divided into a plurality of grid line, the conductive channel is located in the grid line gap.
Preferably, the separation layer is located on the side wall in the grid line gap, and the conductive channel fills the grid line seam
Gap, the barrier layer is between the separation layer and the conductive channel.
Preferably, the 3D memory device further includes barrier layer, between the gate conductor layer and conductive channel.
Preferably, a part on the barrier layer is located between interlayer insulating film adjacent in the laminated construction.
Preferably, the channel column includes the channel layer formed around center stack, tunneling medium layer, charge storage layer
And gate dielectric layer.
3D memory device provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
Grid conductor and interlayer insulating film laminated construction, not only formed run through the laminated construction channel column, but also formed run through
The conductive channel of the laminated construction.The conductive channel is located in grid line gap, is connected to leading for source electrode line for providing common source
Power path.Compared with the conductive channel formed in dedicated wiring region, the conductive channel formed in grid line gap be can reduce
Chip area footprints.The conductive channel is easy to implement the connection between 3D memory device and CMOS chip, and is easy to co-occurrence
Some technique is integrated, especially after the thickness of laminated construction is continuously increased, is formed without etching laminated construction for source electrode
The conductive channel that line is drawn, is conducive to the realization of technique and the continuous improvement of integrated level.
Further, formed in channel hole before forming channel column high-K dielectric layer by grid conductor and channel column that
This is separated, to reduce the depositing operation difficulty of high-K dielectric layer, improves the spreadability and uniformity of high K medium layer film,
The process window for expanding channel hole avoids destroying high-K dielectric layer film when sacrificial layer removes in grid line gap, to improve 3D
The yield and reliability of memory device.
Further, the tungsten of conductive channel lower part is replaced using polysilicon layer, thus it is possible to vary the angularity of chip becomes
It measures (wafer bow), the steam in conductive channel can also be avoided to enhance the stability of conductive channel to the influence of conductive column.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 a to Fig. 1 c shows the sectional view in each stage of 3D memory device manufacturing method according to prior art；
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 2 a and Fig. 2 b；
Fig. 3 shows the perspective view of 3D memory device；
Fig. 4 a to Fig. 4 h shows the section in each stage of 3D memory device manufacturing method according to an embodiment of the present invention
Figure.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " directly in order to describe located immediately at another layer, another region above scenario
... above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture memory device
The general designation of conductor structure, including all layers formed or region.It is described hereinafter of the invention many specific thin
Section, such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as ability
The technical staff in domain it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 2 a and Fig. 2 b.In the reality
Apply the situation that memory cell string shown in example includes 4 storage units.It is appreciated that the invention is not limited thereto, storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
As shown in Figure 2 a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection
Line SSL, the grid of the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 connects respectively
It is connected to the respective word of wordline WL1 to WL4.
As shown in Figure 2 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include 122 He of gate conductor layer
123, memory transistor M1 to M4 respectively includes gate conductor layer 121.Gate conductor layer 121,122 and 123 and memory cell string
The stacking order of transistor in 100 is consistent, is separated each other using interlayer insulating film between adjacent gate conductor layer, thus
Form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 and rhythmic structure of the fence phase
Neighbour runs through rhythmic structure of the fence.In the middle section of channel column 110, accompanied between gate conductor layer 121 and channel layer 111
Tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.In channel column
110 both ends accompany gate dielectric layer 114 between gate conductor layer 122 and 123 and channel layer 111, to form selection crystal
Pipe Q1 and Q2.
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and gate dielectric layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride of the particle comprising metal or semiconductor, gate conductor layer 121,122 and 123 are made of metal,
Such as tungsten.Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping class of channel layer 111
Type is identical as selection transistor and the control type of transistor.For example, selection transistor and control transistor for N-type, ditch
Channel layer 111 can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112, charge storage layer 113
The laminated construction for surrounding core wall is formed with gate dielectric layer 114.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114, which are formed, surrounds semiconductor
The laminated construction of layer.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public 111 and of channel layer
Gate dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the reality of substitution
Apply in example, can use step independent of one another, be respectively formed semiconductor layer and the gate dielectric layer of selection transistor Q1 and Q2 with
And the semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, selection transistor Q1's and Q2 is partly led
Body layer and the semiconductor layer of memory transistor M1 to M4 are electrically connected to each other.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, and wordline WL2 is inclined
It is placed in program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor
The word line voltage of M2 is higher than tunneling voltage, therefore, the electronics of the channel region of memory transistor M2, via tunneling medium layer 112
Charge storage layer 113 is reached, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.It is with memory transistor M2
Example, wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2
It is related to its threshold voltage, i.e., it is related to the quantity of electric charge in charge storage layer, thus according to the conducting shape of memory transistor M2
State may determine that data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, memory cell string 100 is led
Logical state depends on the on state of memory transistor M2.Control circuit is according to the telecommunications detected on bit line BL and source electrode line SL
Number the on state of memory transistor M2 is judged, to obtain the data stored in memory transistor M2.
Fig. 3 shows the perspective view of 3D memory device.For the sake of clarity, it is not shown in Fig. 3 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string respectively includes respective channel column 110 and public grid is led
Body layer 121,122 and 123.The stacking order one of transistor in gate conductor layer 121,122 and 123 and memory cell string 100
It causes, is separated each other using interlayer insulating film between adjacent gate conductor layer, to form rhythmic structure of the fence 120.In figure not
Interlayer insulating film is shown.
The internal structure of channel column 110 is as shown in Figure 2 b, is no longer described in detail herein.In the centre of channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and grid inside part, gate conductor layer 121 and channel column 110
Dielectric layer 114 together, forms memory transistor M1 to M4.At the both ends of channel column 110, gate conductor layer 122 and 123 and ditch
Channel layer 111 and gate dielectric layer 114 inside road column 110 together, form selection transistor Q1 and Q2.
Channel column 110 runs through rhythmic structure of the fence 120, and is arranged in array, and the of multiple channel columns 110 of same row
One end is commonly connected to same bit line (i.e. one of bit line BL1 to BL4), and second end is commonly connected to substrate 101, second end
Common source connection is formed via substrate 100.
The grid conductor 122 of string select transistor Q1 is divided into different by grid line gap (gate line slit) 102
Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely
One of SSL4).
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap 161, then the grid line of same level is via each
From conductive channel 131 reach interconnection layer 132, thus interconnected amongst one another, be then connected to same word via conductive channel 133
Line (i.e. one of wordline WL1 to WL4).
The grid conductor of ground selection transistor Q2 links into an integrated entity.If the grid conductor 123 of ground selection transistor Q2 by
Grid line gap 161 is divided into different grid lines, then grid line reaches interconnection layer 132 via respective conductive channel 131, thus that
This interconnection, then via with the being connected to same selection line GSL of conductive channel 133.
Fig. 4 a to Fig. 4 h shows the section in each stage of 3D memory device manufacturing method according to an embodiment of the present invention
Figure.The sectional view is intercepted along the AA line in Fig. 3.
This method starts from having been formed the semiconductor structure of channel hole (CH), as shown in fig. 4 a.
Interlayer insulating film 151 is formed on substrate 101 and sacrificial layer 152 is alternately stacked the laminated construction 150 to be formed, with
And form the channel hole for running through laminated construction 150.As described below, sacrificial layer 152 will be substituted for grid conductor.In the implementation
In example, substrate 101 is, for example, monocrystalline substrate, and interlayer insulating film 151 is for example made of silica, and sacrificial layer 152 is for example by nitrogen
SiClx composition.
Further, barrier layer 141 and channel column 110 are formed in the channel hole, as shown in Figure 4 b.
Barrier layer 141 is formed using channel hole as deposition channels.In the present embodiment, barrier layer 141 is high K dielectric
Layer, is made, including but not limited to aluminium oxide, hafnium oxide, lanthana, yttrium oxide and/or tantalum oxide of high-k dielectric material, can have
Effect prevents electric leakage from generating.
Preferably, etch-back (etch back) is carried out, plasticity is carried out to the barrier layer 141 in channel hole, wherein barrier
Layer 141 forms certain thickness on the side wall in channel hole.Then channel column is formed in channel hole.
For the sake of clarity, the internal structure of channel column 110 is not shown in fig. 4b.Referring to Fig. 1 b, in channel column 110
Middle section, channel column 110 includes the channel layer 111, tunneling medium layer 112, charge storage layer 113 and the grid that stack gradually
Dielectric layer 114, at the both ends of channel column 110, channel column 110 includes the channel layer 111 and gate dielectric layer 114 stacked gradually.
It is also deposition channels, shape using channel hole CH before forming barrier layer 141 in a preferred embodiment
At separation layer 142, as shown in Figure 4 b.
In this embodiment, separation layer 142 can be identical with the material of interlayer insulating film 151, such as by silica group
At.In other embodiments, separation layer 142 and the material of interlayer insulating film 151 can also be different.
Further, such as on the surface of semiconductor structure photoresist mask is formed, anisotropy is then carried out
Etching forms grid line gap 161, as illustrated in fig. 4 c in laminated construction 150.
Anisotropic etching can use dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, swash
Light ablation.For example, by control etching period, so that the surface for being etched in substrate 101 nearby stops.Pass through after the etching
Removal photoresist mask is dissolved or is ashed in a solvent.
In this embodiment, grid line gap 161 is applied not only to for grid conductor to be divided into a plurality of grid line, and is used for shape
The conductive channel connected at source electrode.For this purpose, grid line gap 161 reaches substrate 101 through laminated construction 150.
Preferably, via grid line gap 161 carry out ion implanting, in substrate 101 formed N-type (use N type dopant,
Such as P, As) or p-type (use P-type dopant, such as B) doped region 102.The contact that doped region 102 is connected as common source
Area, for reducing the contact resistance between the conductive channel and substrate 101 subsequently formed.
Further, using grid line gap 161 as etchant channel, laminated construction is removed using isotropic etching
Sacrificial layer 152 in 150 is to form cavity 162, as shown in figure 4d.
Isotropic etching can be using the wet etching or gas phase etching of selectivity.Etching is used in wet etching
Solution is as etchant, wherein in the etch solution by semiconductor structure submergence.Made in gas phase etching using etching gas
For etchant, wherein semiconductor structure to be exposed in etching gas.151 He of interlayer insulating film in laminated construction 150
It, can be using phosphoric acid solution as erosion in wet etching in the case of sacrificial layer 152 is made of silica and silicon nitride respectively
Agent is carved, it can be using one of C4F8, C4F6, CH2F2 and O2 or a variety of in gas phase etching.In an etching step, it loses
It carves agent and is full of grid line gap 161.The end of sacrificial layer 152 in laminated construction 150 is exposed in the opening in grid line gap 161,
Therefore, sacrificial layer 152 touches etchant.Etchant is from the opening in grid line gap 161 gradually to the inside of laminated construction 150
Etch sacrificial layer 152.Due to the selectivity of etchant, which goes relative to the interlayer insulating film 151 in laminated construction 150
Except sacrificial layer 152.
Preferably, it after above-mentioned wet etch step, can be removed using additional etching step in layer insulation
The etch products (such as silica) adhered on layer 151, so that exposed surface of the interlayer insulating film 151 in cavity 162 is flat
It is whole.
Preferably, after above-mentioned wet etch step, using atomic layer deposition (ALD), in interlayer insulating film 151
Exposed surface on formed stratum nucleare 153, as shown in fig 4e.
In this embodiment, stratum nucleare 153 is for example made of the silicide of tungsten or nitride.
Further, it is stitched using atomic layer deposition (ALD) in grid line using grid line gap 161 as deposit channel
Metal layer 154 is filled in gap 161 and cavity 162, as shown in fig. 4f.
In this embodiment, metal layer 154 is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example,
Tungsten hexafluoride WF6, the reducing gas of use are, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, benefit
Tungsten material, which is obtained, with the chemisorption of tungsten hexafluoride WF6 and the reaction product of silane SiH4 realizes deposition process.
Metal layer 154 is formed on the surface of stratum nucleare 153, and forerunner source is on the surface during can improving atomic layer deposition
Chemisorptive properties, and adhesive strength of the metal layer 154 on interlayer insulating film 151 can be improved.
Further, etch-back (etch back) is carried out, grid line gap 161 is re-formed in metal layer 154, such as schemed
Shown in 4g.
The etch-back uses sulfur fluoride, nitrogen and chlorine as etchant, to remove the tungsten material in the grid line gap 161.Into one
Step ground, metal layer 154 is not only separated into different levels by grid line gap 161, to form grid conductor 121,122 and
123, and the grid conductor of each level is separated into a plurality of grid line.On the side wall in grid line gap 161, grid conductor
121, the end exposure in 122 and 123 adjacent grid line gaps 161.
Grid conductor 121,122 and 123 and the interlayer insulating film 151 formed in this step is alternately stacked, to be formed
Laminated construction 120.Compared with laminated construction 150, the grid conductor 121,122 and 123 in laminated construction 120 has replaced lamination
Sacrificial layer 152 in structure 150.
Further, using grid line gap 161 as deposit channel, barrier layer 162 is formed, as shown in figure 4h.It is described
162 part of barrier layer is located between interlayer insulating film 151 adjacent in the laminated construction.
In this embodiment, barrier layer 162 can be identical with the material of interlayer insulating film 151, such as by silica group
At.In other embodiments, barrier layer 162 and the material of interlayer insulating film 151 can also be different.
Preferably, etch-back (etch back) is carried out, plasticity is carried out to the barrier layer 162 in grid line gap 161,
In, barrier layer 162 forms certain thickness on the side wall in grid line gap 161.
Further, conductive channel 163 is formed in grid line gap 161, as shown in figure 4h.
In this embodiment, the lower part of the conductive channel 163 is formed with polysilicon layer 163a and around the polysilicon
The conductive layer 163b of layer 163a, the top of the conductive channel are formed with conductive column 163c and around the conductive column 163c
Conductive layer 163b.It is separated between conductive channel 163 and grid conductor 121,122 and 123 by barrier layer 162.Conductive channel
The first end of 163 conductive layer 163b is connected with substrate 101, and second end extends to the top of laminated construction 120.Preferred
Embodiment in, conductive channel 163 via conductive layer 163b contact substrate 101 in doped region 102, thus realize and substrate
Connection between 101.The tungsten of conductive channel lower part is replaced using polysilicon layer 163a, thus it is possible to vary the angularity of chip
Variable (wafer bow) can also avoid influence of the steam to conductive column 163c in conductive channel, enhance conductive channel
Stability.
It is connected as described above, channel column 110 forms common source via substrate 100, conductive channel 163 provides common source and connects
It is connected to the conductive path of source electrode line SL.
The embodiment of the present invention forms high-K dielectric layer for grid conductor and channel before forming channel column in channel hole
Column is separated from each other, to reduce the depositing operation difficulty of high-K dielectric layer, improves the spreadability and uniformly of high-K dielectric layer film
Property, expand the process window in channel hole, avoid destroying high-K dielectric layer film when sacrificial layer removes in grid line gap, to improve
The yield and reliability of 3D memory device.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It is it will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.Separately
Outside, in order to form same structure, those skilled in the art can be devised by not fully identical with process as described above
Method.In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment is not
Use can be advantageously combined.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that,
And it is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This is not departed from
The range of invention, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the present invention
Within the scope of.
Claims (19)
1. a kind of manufacturing method of 3D memory device, comprising:
The first laminated construction is formed on the substrate and through the channel hole of first laminated construction, first laminated construction
Including the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；
Barrier layer and channel column are formed in the channel hole, the barrier layer is between the sacrificial layer and channel column；
The multiple sacrificial layer is replaced using multiple gate conductor layers, forms laminated construction；And
Form the conductor channel for running through the laminated construction.
2. the manufacturing method according to claim 1, wherein the barrier layer is high-K dielectric layer.
3. the manufacturing method according to claim 1, wherein formed between barrier layer further include:
In channel inner hole deposition product separation layer.
4. manufacturing method according to claim 3, wherein the separation layer is oxide skin(coating).
5. the manufacturing method according to claim 1, wherein formed laminated construction the step of include:
Form the grid line gap for running through first laminated construction；
The multiple sacrificial layer in first laminated construction is removed by grid line gap, is connected with being formed with the grid line gap
Logical cavity；
Metal layer is filled in the grid line gap and the cavity by grid line gap；And
The metal layer is etched, grid line gap is re-formed, so that the metal layer to be divided into the institute of different level
State multiple grid conductors.
6. manufacturing method according to claim 5, wherein the step of forming cavity and filling metal layer the step of it
Between, further includes: via the grid line gap, stratum nucleare is formed on the surface of the multiple interlayer insulating film.
7. manufacturing method according to claim 5, wherein in the step of re-forming grid line gap, the grid line seam
The grid conductor of same level is divided into a plurality of grid line by gap.
8. manufacturing method according to claim 5, wherein the lower part of the conductive channel is polysilicon layer and surrounds described
The conductive layer of polysilicon layer.
9. the manufacturing method according to claim 1, before forming conductive channel further include:
Barrier layer is deposited in the grid line gap.
10. a kind of 3D memory device, comprising:
Substrate；
Laminated construction above substrate, the laminated construction include the multiple gate conductor layers and multiple interlayers being alternately stacked
Insulating layer；
Multiple channel columns run through the laminated construction；
Barrier layer is isolated by multiple gate conductor layers with the channel column；
Conductive channel runs through the laminated construction.
11. 3D memory device according to claim 10, wherein the barrier layer is high-K dielectric layer.
12. 3D memory device according to claim 10, wherein further include:
The gate conductor layer and the barrier layer are separated from each other by separation layer, and the separation layer is oxide skin(coating).
13. 3D memory device according to claim 10, wherein the bottom end of the multiple channel column is via the substrate shape
It is connected at common source, the conductive channel provides the conductive path that the common source is connected to source electrode line, the conductive channel
Lower part is polysilicon layer and the conductive layer around the polysilicon layer.
14. 3D memory device according to claim 10, wherein it further include the doped region in the substrate, it is described
Conductive channel is contacted with the doped region.
15. 3D memory device according to claim 10, further includes: stratum nucleare, on the surface of the interlayer insulating film.
16. 3D memory device according to claim 10, wherein further include grid line gap, institute is run through in the grid line gap
Laminated construction is stated, so that the multiple grid conductor is divided into a plurality of grid line, the conductive channel is located at the grid line gap
In.
17. 3D memory device according to claim 15, wherein further include barrier layer, be located at the gate conductor layer and
Between conductive channel.
18. 3D memory device according to claim 17, wherein a part on the barrier layer is located at the laminated construction
In between adjacent interlayer insulating film.
19. 3D memory device according to claim 10, wherein the channel column includes the ditch formed around center stack
Channel layer, tunneling medium layer, charge storage layer and gate dielectric layer.
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