CN108807410A - 3D memory devices and its manufacturing method - Google Patents
3D memory devices and its manufacturing method Download PDFInfo
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- CN108807410A CN108807410A CN201810779005.7A CN201810779005A CN108807410A CN 108807410 A CN108807410 A CN 108807410A CN 201810779005 A CN201810779005 A CN 201810779005A CN 108807410 A CN108807410 A CN 108807410A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
This application discloses a kind of 3D memory devices and its manufacturing methods.The 3D memory devices include：Substrate；Laminated construction above substrate, laminated construction include the multiple grid conductors being alternately stacked and multiple interlayer insulating films；Through multiple raceway groove columns of laminated construction；And the conductive channel through laminated construction, conductive channel are connected to the bottom end of multiple raceway groove columns via substrate, wherein the top of conductive channel includes conductive column, and lower part includes insulating core and the conductive layer around insulating core.By making insulating core in the lower part of conductive channel, the ratio for adjusting conductive channel shared by insulating core and conductive column arranges, and the purpose by positive negative regulator by silicon wafer warpage degree may be implemented.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory devices and its manufacturing method.
Background technology
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductor manufacturing
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory devices) of three-dimensional structure.3D memory devices include stacked along vertical direction it is multiple
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory devices are mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structures.Compared with NOR memory devices, the reading speed in nand memory part is slightly slow, but writing speed
Soon, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory devices of NAND structures have been widely used.
In the 3D memory devices of NAND structures, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor, using the interconnection for realizing memory cell string through the conductive channel of laminated construction.However, conductive channel can stick up chip
Curvature (wafer bow) has an impact, and in the prior art, the angularity of chip is very high, and cannot change the warpage of chip
The variable (wafer △ bow) of degree.
Invention content
The object of the present invention is to provide a kind of improved 3D memory devices and its manufacturing methods, wherein under conductive channel
Portion is insulating core and the conductive layer around insulating core.
According to an aspect of the present invention, a kind of 3D memory devices are provided, including:Substrate；Lamination above substrate
Structure, the laminated construction include the multiple grid conductors being alternately stacked and multiple interlayer insulating films；Through the laminated construction
Multiple raceway groove columns；And the conductive channel through the laminated construction, the conductive channel are connected to institute via the substrate
State the bottom end of multiple raceway groove columns, wherein the lower part of the conductive channel is insulating core and the conduction around the insulating core
Layer.
Preferably, the conductive layer is selected from single conductive layer or lamination conductive layer.
Preferably, the lamination conductive layer includes at least one of viscous glutinous layer, metal layer, polysilicon layer.
Preferably, the top of the conductive channel is conductive column and the conductive layer around the conductive column, described to lead
Electric layer includes viscous glutinous layer, and the cylinder of the conductive column is contacted with the viscous glutinous layer.
Preferably, the conductive layer is selected from the single conductive layer, the lower surface of the conductive column and the insulating core
Contact.
Preferably, the conductive layer is selected from the lamination conductive layer, and the lamination conductive layer further includes：The metal layer,
Around the insulating core, the viscous glutinous layer surrounds the metal layer.
Preferably, the lower surface of the conductive column is contacted with the insulating core and the metal layer.
Preferably, the conductive layer is selected from the lamination conductive layer, and the lamination conductive layer further includes：The polysilicon
Layer surrounds the insulating core；And the metal layer, the polysilicon layer is surrounded, the viscous glutinous layer surrounds the metal layer.
Preferably, the first surface of the conductive column and the insulating core, the polysilicon layer and the metal layer
Contact.
According to another aspect of the present invention, a kind of method of manufacture 3D memory devices is provided, including：It is formed on substrate
First laminated construction, first laminated construction include the multiple sacrificial layers being alternately stacked and multiple interlayer insulating films；Formation is passed through
Wear multiple raceway groove columns of first laminated construction；The multiple sacrificial layer is replaced using multiple grid conductors, it is folded to form second
Layer structure；And form the conductive channel for running through second laminated construction, wherein the lower part of the conductive channel is formed with absolutely
Edge core and conductive layer around the insulating core.
Preferably, the step of forming the conductive layer include：It forms single conductive layer or forms lamination conductive layer.
Preferably, the step of forming the lamination conductive layer include：Form viscous glutinous layer, metal layer, polysilicon layer at least
It is a kind of.
Preferably, the step of forming the conductive channel include：It is formed through the grid line gap of second laminated construction,
To be divided into the multiple grid conductor of different level；The conduction is formed on the bottom in the grid line gap and side wall
Layer；The insulating core is filled in the grid line gap；And the etching insulating core, so that the insulating core is reached pre-
If length；Wherein, the conductive layer surrounds the insulating core.
Preferably, the step of forming the conductive layer include：It is formed on the bottom in the grid line gap and side wall viscous
Glutinous layer, wherein the viscous glutinous layer surrounds the insulating core.
Preferably, the step of forming the conductive channel further include：Opening in the grid line gap forms conductive column,
The cylinder of the conductive column is contacted with the viscous glutinous layer, and the lower surface of the conductive column is contacted with the insulating core.
Preferably, the step of forming the conductive layer include：It is formed on the bottom in the grid line gap and side wall viscous
Glutinous layer；And form metal layer on the bottom of the viscous glutinous layer and side wall, wherein the metal layer surrounds the insulating core
Portion, the viscous glutinous layer surround the metal layer.
Preferably, the step of forming the conductive channel further include：Opening in the grid line gap forms conductive column,
The cylinder of the conductive column is contacted with the viscous glutinous layer, the lower surface of the conductive column and the insulating core and the metal
Layer contact.
Preferably, the step of forming the conductive layer include：It is formed on the bottom in the grid line gap and side wall viscous
Glutinous layer；Metal layer is formed on the bottom of the viscous glutinous layer and side wall；And on the bottom of the metal layer and side wall
Form polysilicon layer, wherein the doped polysilicon layer surrounds the insulating core, and the metal layer surrounds the doped polycrystalline
Silicon, the viscous glutinous layer surround the metal layer.
Preferably, the step of forming the conductive channel further include：Opening in the grid line gap forms conductive column,
The cylinder of the conductive column is contacted with the viscous glutinous layer, the first surface of the conductive column and the insulating core, the doping
Polysilicon layer and metal layer contact.
3D memory devices provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
The laminated construction of grid conductor and interlayer insulating film, and formed through the laminated construction conductive channel, the conductive channel it is upper
Portion is conductive column and the conductive layer around conductive column, and lower part is insulating core and the conductive layer around insulating core, by leading
The lower part of electric channel makes insulating core, and the ratio for adjusting conductive channel shared by insulating core and conductive column arranges, and may be implemented will be brilliant
The angularity of piece by positive negative regulator purpose.
Further, the cylinder of conductive column is contacted with the viscous glutinous layer in conductive layer, provides common source being connected to source electrode
The conductive path of line.
Further, conductive layer further includes the metal layer around insulating core, which can enhance conductive channel
Electric conductivity.
Further, conductive layer further includes the doped polycrystalline layer around insulating core, which can with metal layer
Influence to avoid the steam in conductive channel to conductive column enhances the stability of conductive channel.
In addition, the insulating core using oxide fills conductive channel, production cost is saved.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory devices is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory devices.
Fig. 3 a to Fig. 3 l show cutting for each stage of 3D memory device manufacturing methods according to a first embodiment of the present invention
Face figure.
Fig. 4 a to Fig. 4 e show cutting for each stage of 3D memory device manufacturing methods according to a second embodiment of the present invention
Face figure.
Fig. 5 a to Fig. 5 e show cutting for each stage of 3D memory device manufacturing methods according to a third embodiment of the present invention
Face figure.
The sectional view of 3D memory devices according to prior art is shown respectively in Fig. 6 and 7.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If in order to describe located immediately at another layer, another region above scenario, it will use " directly exist ... herein
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to formed in each step of manufacture memory device entire and partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the present invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory devices is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be it is any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, including：First choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to the ground selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes raceway groove column 110.Raceway groove column 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section of raceway groove column 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of raceway groove column 110, grid
Gate dielectric layer 114 is accompanied between pole conductor layer 122 and 123 and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
Such as include the silicon nitride of the particle of metal or semiconductor, gate conductor layer 121,122 and 123 is made of metal, such as tungsten.Ditch
Channel layer 111 is used to provide the channel region of control selection transistor and controlling transistor, doping type and the selection crystal of channel layer 111
Pipe is identical with the type of controlling transistor.For example, for the selection transistor and controlling transistor of N-type, channel layer 111 can be
The polysilicon of n-type doping.
In this embodiment, the core of raceway groove column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction around core wall.In alternate embodiments, the core of raceway groove column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In raceway groove column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of replacement
Example in, step independent of one another may be used, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In raceway groove column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 is write data into using FN tunneling effects in memory transistor M1 to M4
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL is grounded, ground selection line SGS is biased to greatly
About zero volts so that the selection transistor Q2 for corresponding to ground selection line SGS is disconnected, and string selection line SGD is biased to high voltage
VDD so that correspond to the selection transistor Q1 conductings of string selection line SGD.Further, bit line BL2 is grounded, wordline WL2 biasings
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, to which data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, memory cell string 100 is led according to the selected memory transistor in memory transistor M1 to M4
The quantity of electric charge in logical condition adjudgement charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The conducting state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the conducting state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conduction state always, and therefore, the conducting state of memory cell string 100 takes
Certainly in the conducting state of memory transistor M2.Control circuit judges storage according to the electric signal detected on bit line BL and source electrode line SL
The conducting state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory devices.For the sake of clarity, it is not shown in fig. 2 each in 3D memory devices
A insulating layer.
The 3D memory devices shown in this embodiment include that 4*4 amounts to 16 memory cell strings 100, each storage unit
String 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that this hair
Bright without being limited thereto, 3D memory devices may include any number of memory cell strings, for example, 1024, in each memory cell string
Number of memory cells can be it is any number of, for example, 32 or 64.
In 3D memory devices, memory cell string respectively includes respective raceway groove column 110 and public gate conductor layer
121,122 and 123.Gate conductor layer 121,122 and 123 is consistent with the stacking order of the transistor in memory cell string 100, phase
It is separated each other using interlayer insulating film between adjacent gate conductor layer, to form rhythmic structure of the fence 120.It is being not shown in figure layer
Between insulating layer.
The internal structure of raceway groove column 110 is as shown in Figure 1 b, is no longer described in detail herein.In the centre of raceway groove column 110
Part, gate conductor layer 121 and channel layer 111, tunneling medium layer 112, charge storage layer 113 and the grid inside raceway groove column 110
Dielectric layer 114 together, forms memory transistor M1 to M4.At the both ends of raceway groove column 110, gate conductor layer 122 and 123 and raceway groove
Channel layer 111 and gate dielectric layer 114 inside column 110 together, form selection transistor Q1 and Q2.
Raceway groove column 110 runs through rhythmic structure of the fence 120, and is arranged in array, and the first of multiple raceway groove columns 110 of same row
End is commonly connected to same bit line (i.e. one of bit line BL1 to BL4), and second end is commonly connected to substrate 101, second end via
Substrate 100 forms common source connection.
The grid conductor 122 of string select transistor Q1 is divided into different grid by grid line gap (gate line slit)
Line.With multiple raceway groove columns 110 of a line grid line be commonly connected to same string selection line (i.e. go here and there selection line SGD1 to SGD4 it
One).
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap, then the grid line of same level is via respective
Conductive channel 131 reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline is connected to via conductive channel 133 (i.e.
One of wordline WL1 to WL4).
The grid conductor of ground selection transistor Q2 links into an integrated entity.If the grid conductor 123 of ground selection transistor Q2 by
Grid line gap is divided into different grid lines, then grid line reaches interconnection layer 132 via respective conductive channel 131, to mutually
Even, then via with the being connected to same selection line SGS of conductive channel 133.
Fig. 3 a to Fig. 3 l show cutting for each stage of 3D memory device manufacturing methods according to a first embodiment of the present invention
Face figure.The sectional view is intercepted along the AA lines in Fig. 2.
This method starts from having been formed the semiconductor structure of raceway groove column 110, as shown in Figure 3a.
Interlayer insulating film 151 is formed on substrate 101 and sacrificial layer 152 is alternately stacked the laminated construction 150 to be formed, and
Form the raceway groove column 110 through laminated construction 150.As described below, sacrificial layer 152 will be substituted for grid conductor.In the implementation
In example, substrate 101 is, for example, monocrystalline substrate, and interlayer insulating film 151 is for example made of silica, and sacrificial layer 152 is for example by nitrogen
SiClx forms.
For the sake of clarity, the internal structure of raceway groove column 110 is not shown in fig. 3 a.Referring to Fig. 1 b, in raceway groove column 110
Middle section, raceway groove column 110 include channel layer 111, tunneling medium layer 112, charge storage layer 113 and the gate medium stacked gradually
Layer 114, at the both ends of raceway groove column 110, raceway groove column 110 includes the channel layer 111 stacked gradually and gate dielectric layer 114.
Further, such as on the surface of semiconductor structure photoresist mask is formed, anisotropy is then carried out
Etching forms grid line gap 161, as shown in Figure 3b in laminated construction 150.
Dry etching may be used in anisotropic etching, such as ion beam milling etching, plasma etching, reactive ion etching, swashs
Light ablation.For example, by controlling etching period so that the surface for being etched in substrate 101 nearby stops.After the etching by
Removal photoresist mask is dissolved or is ashed in solvent.
In this embodiment, grid line gap 161 is applied not only to grid conductor being divided into a plurality of grid line, and is used to form
The conductive channel of source electrode connection.For this purpose, grid line gap 161 reaches substrate 101 through laminated construction 150.
Further, using grid line gap 161 as etchant channel, laminated construction is removed using isotropic etching
Sacrificial layer 152 in 150 is to form cavity 162, as shown in Figure 3c.
Preferably, via grid line gap 161 carry out ion implanting, in substrate 101 formed N-type (use N type dopant,
Such as P, As) or p-type (use P-type dopant, such as B) doped region 102.The contact that doped region 102 is connected as common source
Area, for reducing the contact resistance between the conductive channel and substrate 101 subsequently formed.
Selective wet etching or gas phase etching may be used in isotropic etching.It is molten using etching in wet etching
Liquid is as etchant, wherein in the etch solution by semiconductor structure submergence.Use etching gas as erosion in gas phase etching
Carve agent, wherein semiconductor structure is exposed in etching gas.Interlayer insulating film 151 in laminated construction 150 and sacrificial layer
In the case of 152 are made of silica and silicon nitride respectively, phosphoric acid solution may be used in wet etching as etchant,
C may be used in gas phase etching4F8、C4F6、CH2F2And O2In it is one or more.In an etching step, etchant is full of grid line
Gap 161.The end of sacrificial layer 152 in laminated construction 150 is exposed in the opening in grid line gap 161, therefore, sacrificial layer
152 touch etchant.Etchant is from the opening in grid line gap 161 gradually to the etched inside sacrificial layer of laminated construction 150
152.Due to the selectivity of etchant, which removes sacrificial layer 152 relative to the interlayer insulating film 151 in laminated construction 150.
Preferably, after above-mentioned wet etch step, additional etching step removal may be used in layer insulation
The etch products (such as silica) adhered on layer 151 so that exposed surface of the interlayer insulating film 151 in cavity 162 is smooth.
Preferably, after above-mentioned wet etch step, using atomic layer deposition (ALD), in interlayer insulating film 151
The first viscous glutinous layer 153 is formed on exposed surface, as shown in Figure 3d.
In this embodiment, the first viscous glutinous layer 153 is for example made of the silicide of tungsten or nitride.
Further, using grid line gap 161 as deposit channel, using atomic layer deposition (ALD), in grid line gap
161 and cavity 162 in fill metal layer 154, as shown in Figure 3 e.
In this embodiment, metal layer 154 is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, six
Tungsten fluoride WF6, the reducing gas of use is, for example, silane SiH4Or diborane B2H6.In the atomic layer deposition the step of, six are utilized
Tungsten fluoride WF6With silane SiH4Reaction product chemisorption obtain tungsten material realize deposition process.
Metal layer 154 is formed on the surface of the first viscous glutinous layer 153, and forerunner source is in table during can improving atomic layer deposition
Chemisorptive properties on face, and adhesive strength of the metal layer 154 on interlayer insulating film 151 can be improved.
Further, photoresist mask is formed on the surface of semiconductor structure, then carries out etch-back (etch
Back), grid line gap 161 is re-formed in metal layer 154, as illustrated in figure 3f.
The etch-back uses sulfur fluoride, nitrogen and chlorine as etchant, to remove the tungsten material in the grid line gap 161.Into one
Step ground, metal layer 154 is not only separated into different levels by grid line gap 161, to form grid conductor 121,122 and 123,
And the grid conductor of each level is separated into a plurality of grid line.On the side wall in grid line gap 161, grid conductor 121,122
With the end exposure in 123 adjoining grid line gaps 161.
Grid conductor 121,122 and 123 and the interlayer insulating film 151 formed in this step is alternately stacked, to be formed
Laminated construction 120.Compared with laminated construction 150, the grid conductor 121,122 and 123 in laminated construction 120 has replaced lamination knot
Sacrificial layer 152 in structure 150.
Further, covering 120 upper surface of laminated construction forms the first insulating layer 155, and profit with 161 side wall of grid line gap
Expand the opening in grid line gap 161 with etching technics, as shown in figure 3g.
Further, the first insulating layer of covering 155 forms the second viscous glutinous layer 141a with grid line gap 161, wherein in grid line
In gap 161, the second viscous glutinous layer 141a completely covers side wall and the bottom in grid line gap 161, as illustrated in figure 3h.
In this embodiment, the second viscous glutinous layer 141a is electrically conductive, and the second viscous glutinous layer 141a is for example carried out by the oxide of aluminium
Atomic layer deposition forms (AL OX ALD DEP), or is deposited and formed (TiN DEP) by titanium nitride.
Further, insulating core 142a is formed using the viscous glutinous layer 141a of chemical vapor deposition method (CVD) covering second,
Wherein, in grid line gap 161, insulating core 142a is filled with the inside in grid line gap 161, as shown in figure 3i.
In the present embodiment, the material of insulating core 142a is oxide.
Further, the insulating core of 120 top of covering laminated construction is removed using dry etch process (dry each)
The insulating core 142a of 142a and removal from 161 opening of grid line gap to bottom definite length extended, as shown in Fig. 3 j.When
After the oxide deposits on wafer, the compression stress less than 0 can be brought to wafer.It is determined according to the wafer bow of wafer
The predetermined length specifically, chooses the oxide (OX) and tungsten of a series of ratios to which stress is adjusted to a certain predetermined value
(W), angularity is recorded respectively, as basic data data base, if it is desired to by wafer bow to negative regulator to a certain value,
It can be based on equation (1), and the ratio of reference data base selective oxidations objects (OX) and tungsten (W),
BOW=0.58*Stress*THK (1)
Wherein, BOW is angularity, and Stress is stress, and THK is thickness, and thickness unit is micron.It is predetermined about the extension
The setting of length and stress, those skilled in the art can determine as needed.
Further, the viscous glutinous layer 141a and remaining insulating core 142a of covering second forms conductive column 143a, wherein leads
The material of electric column 143a is tungsten, as shown in figure 3k.
Further, the second insulating layer stacked on laminated construction 120 is removed using chemical machinery polishing technique (CMP)
155, the second viscous glutinous layer 141a, 120 upper surface conductive column 143a and laminated construction partial insulative layer 151, ultimately form the
The memory construction of one embodiment, as shown in Fig. 3 l.
In the present embodiment, the second viscous glutinous layer 141a, insulating core 142a and conductive column 143a constitute the confession of memory
Source conductive channel, conductive channel run through laminated construction 120, wherein the second viscous glutinous layer 141a constitutes single conductive layer, and conduction is logical
The top in road is conductive column 143a and the second viscous glutinous layer 141a around conductive column 143a, and lower part is insulating core 142a and surrounds
The viscous glutinous layer 141a of the second of insulating core 142a, the first surface of conductive column 143a are contacted with insulating core, conductive column 143a's
Cylinder is contacted with the second viscous glutinous layer 141a.The first end of conductive channel is connected with substrate 101, and second end extends to laminated construction
120 top.In a preferred embodiment, the doped region 102 in the first end in contact substrate 101 of conductive channel, to realize
With the connection between substrate 101.
It is connected as described above, raceway groove column 110 forms common source via substrate 100, conductive channel provides common source and is connected to
The conductive path of source electrode line SL.In the present embodiment, the etch amount of adjusting insulating core 142a, i.e. insulating core 142a can be passed through
The purpose by silicon wafer warpage degree by positive negative regulator is realized with the ratio of conductive channel shared by conductive column 143a.
Fig. 4 a to Fig. 4 d show cutting for each stage of 3D memory device manufacturing methods according to a second embodiment of the present invention
Face figure.The sectional view is intercepted along the AA lines in Fig. 2.In the present embodiment, since manufacture craft is similar with first embodiment,
Fig. 3 a to Fig. 3 g can be shared with first embodiment, are not described in detail herein, be described more fully below with first embodiment not
Same place.
As shown in fig. 4 a, covering second insulating layer 155 forms the second viscous glutinous layer 141b, covering second with grid line gap 161
Viscous glutinous layer 141b forms conductive layer 142b, wherein in grid line gap 161, the second viscous glutinous layer 141b completely covers grid line seam
The side wall of gap 161 and bottom.
In this embodiment, the second viscous glutinous layer 141b is electrically conductive, and the second viscous glutinous layer 141b is for example by the silicide of tungsten or nitrogen
Compound forms, and the material of conductive layer 142b is tungsten.
Further, insulating core 143b is formed using chemical vapor deposition method (CVD) covering conductive layer 142b,
In, in grid line gap 161, insulating core 143b is filled with the inside in grid line gap 161, as shown in Figure 4 b.
Further, using the conductive layer 142b of dry etch process (dry each) removal laminated construction 120 top with
Insulating core 143b and removal extend the conductive layer 142b and insulating core of certain length from 161 opening of grid line gap to bottom
Portion 143b, as illustrated in fig. 4 c.About the setting of the development length, those skilled in the art can determine as needed.
Further, the viscous glutinous layer 141b and remaining conductive layer 142b of covering second, insulating core 143b form conductive column
144b, wherein the material of conductive column 144b is tungsten, as shown in figure 4d.
Further, first stacked on covering laminated construction 120 is removed using chemical machinery polishing technique (CMP) absolutely
The viscous glutinous layer 141b of edge layer 155, second, 120 upper surface conductive column 144b and laminated construction partial insulative layer 151, most end form
At the memory construction of second embodiment, as shown in fig 4e.
In the present embodiment, the second viscous glutinous layer 141b, metal layer 142b, insulating core 143b and conductive column 144b are constituted
Memory for source electrode conductive channel, conductive channel runs through laminated construction 120, wherein the second viscous glutinous layer 141b and metal layer
142b constitutes lamination conductive layer, and the top of conductive channel is conductive column 144b and the second viscous glutinous layer around conductive column 144b
141b, lower part are that insulating core 143b, the metal layer 142b around insulating core 143b and second around metal layer 142b are viscous
The first surface of glutinous layer 141b, conductive column 144b are contacted with insulating core 143b, metal layer 142b, the cylinder of conductive column 144b and
Second viscous glutinous layer 141b contacts.The first end of conductive channel is connected with substrate 101, and second end extends to laminated construction 120
Top.In a preferred embodiment, the doped region 102 in the first end in contact substrate 101 of conductive channel, to realization and substrate
Connection between 101.
It is connected as described above, raceway groove column 110 forms common source via substrate 100, conductive channel provides common source and is connected to
The conductive path of source electrode line SL.In the present embodiment, the etch amount of adjusting insulating core 143b, i.e. insulating core 143b can be passed through
The purpose by wafer bow by positive negative regulator is realized with the ratio of conductive channel shared by conductive column 144b.In addition, metal layer
142b can enhance the electric conductivity of conductive channel.
Fig. 5 a to Fig. 5 e show cutting for each stage of 3D memory device manufacturing methods according to a third embodiment of the present invention
Face figure.The sectional view is intercepted along the AA lines in Fig. 2.In the present embodiment, since manufacture craft is similar with first embodiment,
Fig. 3 a to Fig. 3 g can be shared with first embodiment, are not described in detail herein, be described more fully below with first embodiment not
Same place.
As shown in Figure 5 a, the first insulating layer of covering 155 forms the second viscous glutinous layer 141c with grid line gap 161, wherein in grid
In linear slit gap 161, the second viscous glutinous layer 141c completely covers side wall and the bottom in grid line gap 161, the viscous glutinous layer of covering second
141c forms metal layer 142c, and covering metal layer 142c forms doped polycrystalline layer 143c.
In this embodiment, the second viscous glutinous layer 141c is electrically conductive, and the second viscous glutinous layer 141c is for example by the silicide of tungsten or nitrogen
Compound forms, and the material of conductive layer 142b is tungsten, and the material of doped polycrystalline layer 143c is polysilicon.
Further, doped polycrystalline layer 143c shapes are covered using spin coating process (Spin On Dielectric, SOD)
At insulating core 144c, wherein in grid line gap 161, insulating core 144c is filled with the inside in grid line gap 161, such as schemes
Shown in 5b.
Further, the metal layer of 120 stacked on top of laminated construction is removed using dry etch process (dry each)
142c, doped polycrystalline layer 143c, insulating core 144c and removal extend certain length from 161 opening of grid line gap to bottom
Insulating core 144c, doped polycrystalline layer 143c and metal layer 142c, as shown in Figure 5 c.About the setting of the development length,
Those skilled in the art can determine as needed.
Further, the viscous glutinous layer 141c of covering second and remaining metal layer 142c, doped polycrystalline layer 143c, insulating core
144c forms conductive column 145c, wherein the material of conductive column 145c is tungsten, as fig 5d.
Further, using the first insulating layer stacked on CMP process (CMP) removal laminated construction 120
155, the second viscous glutinous layer 141c, 120 upper surface conductive column 145c and laminated construction partial insulative layer 151, ultimately form the
The memory construction of two embodiments, as depicted in fig. 5e.
In the present embodiment, second glues glutinous layer 141c, metal layer 142c, doped polycrystalline layer 143c, insulating core 144c, leads
Electric column 145c constitute memory for source electrode conductive channel, conductive channel runs through laminated construction 120.Wherein, the second viscous glutinous layer
141c, metal layer 142c and doped polycrystalline layer 143c constitute lamination conductive layer, the top of conductive channel be conductive column 145c and
Around the second viscous glutinous layer 141c of conductive column 145c, lower part is insulating core 144c, around the doped polycrystalline of insulating core 144c
The viscous glutinous layer 141c of layer 143c, the metal layer 142c around doped polycrystalline layer 143c and second around metal layer 142c, conductive column
The first surface of 145c is contacted with insulating core 144c, doped polycrystalline layer 143c and metal layer 142c, the column of conductive column 145c
Face is contacted with the second viscous glutinous layer 141c.The first end of conductive channel is connected with substrate 101, and second end extends to laminated construction
120 top.In a preferred embodiment, the doped region 102 in the first end in contact substrate 101 of conductive channel, to realize
With the connection between substrate 101.
It is connected as described above, raceway groove column 110 forms common source via substrate 100, conductive channel provides common source and is connected to
The conductive path of source electrode line SL.In the present embodiment, the etch amount of adjusting insulating core 144c, i.e. insulating core 144c can be passed through
The purpose by wafer bow by positive negative regulator is realized with the ratio of conductive channel shared by conductive column 145c.In addition, metal layer
142c can enhance the electric conductivity of conductive channel.Polysilicon layer 143c and metal layer 142c can be to avoid the water in conductive channel
Influence of the vapour to conductive column 145c, enhances the stability of conductive channel.
The sectional view of 3D memory devices according to prior art is shown respectively in Fig. 6 and 7.
As shown in fig. 6, the conductive channel through laminated construction 120 is only made of conductive column 141d, the material of conductive column 141d
Material is tungsten, causes the angularity of chip very high, and cannot change the angularity variable (wafer △ bow) of chip.
As shown in fig. 7, the conductive channel through laminated construction 120 sticks layer 141e, polycrystalline core 142e and conduction by viscous
Column 143e is constituted, and the material of polycrystalline core 142e is polysilicon, and the material of conductive column 143e is tungsten, with polycrystalline core 142e
Although the angularity variable (wafer △ bow) of chip, polycrystalline core can be changed instead of the tungsten of conductive channel lower part
142e easy tos produce crack in forming process so that the degree of etching is difficult to control.
And 3D memory devices provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
Grid conductor and interlayer insulating film laminated construction, and formed through the laminated construction conductive channel, the conductive channel
Top is conductive column and the conductive layer around conductive column, and lower part is insulating core and the conductive layer around insulating core, by
The lower part of conductive channel makes insulating core, adjusts ratio row of the insulating core with conductive channel shared by conductive column, may be implemented by
The angularity of chip by positive negative regulator purpose.
Further, the cylinder of conductive column is contacted with the viscous glutinous layer in conductive layer, provides common source being connected to source electrode
The conductive path of line.
Further, conductive layer further includes the metal layer around insulating core, which can enhance conductive channel
Electric conductivity.
Further, conductive layer further includes the doped polycrystalline layer around insulating core, which can with metal layer
Influence to avoid the steam in conductive channel to conductive column enhances the stability of conductive channel.
In addition, the insulating core using oxide fills conductive channel, production cost is saved.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all be fallen the present invention's
Within the scope of.
Claims (19)
1. a kind of 3D memory devices, including:
Substrate；
Laminated construction above the substrate, the laminated construction include the multiple grid conductors being alternately stacked and multiple layers
Between insulating layer；
Through multiple raceway groove columns of the laminated construction；And
Through the conductive channel of the laminated construction, the conductive channel is connected to the multiple raceway groove column via the substrate
Bottom end,
Wherein, the lower part of the conductive channel includes insulating core and the conductive layer around the insulating core.
2. 3D memory devices according to claim 1, wherein the conductive layer is selected from single conductive layer or lamination is conductive
Layer.
3. 3D memory devices according to claim 2, wherein the lamination conductive layer includes viscous glutinous layer, metal layer, polycrystalline
At least one of silicon layer.
4. 3D memory devices according to claim 2, wherein the top of the conductive channel include conductive column and surround institute
The conductive layer of conductive column is stated,
The conductive layer includes viscous glutinous layer, and the cylinder of the conductive column is contacted with the viscous glutinous layer.
5. 3D memory devices according to claim 4, wherein the conductive layer is selected from the single conductive layer,
The lower surface of the conductive column is contacted with the insulating core.
6. 3D memory devices according to claim 4, wherein the conductive layer is selected from the lamination conductive layer, described folded
Layer conductive layer further include：The metal layer surrounds the insulating core,
The viscous glutinous layer surrounds the metal layer.
7. 3D memory devices according to claim 6, wherein the lower surface of the conductive column and the insulating core and
The metal layer contact.
8. 3D memory devices according to claim 4, wherein the conductive layer is selected from the lamination conductive layer, described folded
Layer conductive layer further include：
The polysilicon layer surrounds the insulating core；And
The metal layer surrounds the polysilicon layer,
The viscous glutinous layer surrounds the metal layer.
9. 3D memory devices according to claim 8, wherein the first surface of the conductive column and the insulating core,
The polysilicon layer and metal layer contact.
10. a kind of method of manufacture 3D memory devices, including：
The first laminated construction is formed on substrate, and first laminated construction includes the multiple sacrificial layers being alternately stacked and multiple layers
Between insulating layer；
Form multiple raceway groove columns through first laminated construction；
The multiple sacrificial layer is replaced using multiple grid conductors, forms the second laminated construction；And
The conductive channel through second laminated construction is formed,
Wherein, the lower part of the conductive channel is formed with insulating core and the conductive layer around the insulating core.
11. according to the method described in claim 10, wherein, the step of forming the conductive layer, includes：Form single conductive layer
Or form lamination conductive layer.
12. according to the method for claim 11, wherein the step of forming the lamination conductive layer include：The viscous glutinous layer of formation,
At least one of metal layer, polysilicon layer.
13. according to the method described in claim 10, wherein, the step of forming the conductive channel, includes：
It is formed through the grid line gap of second laminated construction, to be divided into the multiple grid conductor of different level；
The conductive layer is formed on the bottom in the grid line gap and side wall；
The insulating core is filled in the grid line gap；And
The insulating core is etched, the insulating core is made to reach preset length；
Wherein, the conductive layer surrounds the insulating core.
14. according to the method for claim 13, wherein the step of forming the conductive layer include：In the grid line gap
Bottom and side wall on form viscous glutinous layer,
Wherein, the viscous glutinous layer surrounds the insulating core.
15. according to the method for claim 14, wherein the step of forming the conductive channel further include：In the grid line
The opening in gap forms conductive column, and the cylinder of the conductive column is contacted with the viscous glutinous layer, the lower surface of the conductive column and
The insulating core contact.
16. according to the method for claim 15, wherein the step of forming the conductive layer include：
Viscous glutinous layer is formed on the bottom in the grid line gap and side wall；And
Metal layer is formed on the bottom of the viscous glutinous layer and side wall,
Wherein, the metal layer surrounds the insulating core, and the viscous glutinous layer surrounds the metal layer.
17. according to the method for claim 16, wherein the step of forming the conductive channel further include：In the grid line
The opening in gap forms conductive column, and the cylinder of the conductive column is contacted with the viscous glutinous layer, the lower surface of the conductive column and
The insulating core and metal layer contact.
18. according to the method for claim 15, wherein the step of forming the conductive layer include：
Viscous glutinous layer is formed on the bottom in the grid line gap and side wall；
Metal layer is formed on the bottom of the viscous glutinous layer and side wall；And
Polysilicon layer is formed on the bottom of the metal layer and side wall,
Wherein, the doped polysilicon layer surrounds the insulating core, and the metal layer surrounds the DOPOS doped polycrystalline silicon, described viscous
Glutinous layer surrounds the metal layer.
19. according to the method for claim 18, wherein the step of forming the conductive channel further include：In the grid line
The opening in gap forms conductive column, and the cylinder of the conductive column is contacted with the viscous glutinous layer, the first surface of the conductive column
It is contacted with the insulating core, the doped polysilicon layer and the metal layer.
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