CN109148459A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109148459A CN109148459A CN201810892033.XA CN201810892033A CN109148459A CN 109148459 A CN109148459 A CN 109148459A CN 201810892033 A CN201810892033 A CN 201810892033A CN 109148459 A CN109148459 A CN 109148459A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: the first array structure, and the first array structure includes the first substrate, the first rhythmic structure of the fence on the first substrate and multiple first channel columns through the first rhythmic structure of the fence；Second array structure, it is stacked on above the first array structure, second array structure includes the second substrate, the second rhythmic structure of the fence on the second substrate and multiple second channel columns through the second rhythmic structure of the fence, and interconnection structure, between the first array structure and second array structure and including multiple bit lines, wherein, the multiple second channel column is each passed through second substrate and is connected to the multiple bit lines, and the corresponding channel column in the multiple first channel column is connected to via the multiple bit lines.Bit line in the 3D memory device doubles as the interconnection between the array structure for different level, so as to reduce the size of 3D memory device and improve product yield.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the array structure of many levels can be stacked to improve storage density.Example
Such as, it for the storage unit of 128 levels, can be stacked using two array structures, each array structure includes multiple
The memory cell string of (such as 32 or 64) level, the memory cell string of two array structures are interconnected amongst one another.Each array structure
Including laminated construction and through the channel column of laminated construction, the grid of selection transistor and memory transistor are provided using laminated construction
Pole conductor provides the channel layer and gate medium lamination of selection transistor and memory transistor using channel column, and uses and run through
The conductive channel of laminated construction realizes the interconnection of memory cell string.Grid conductor and conductive channel mutual distance in laminated construction
It is close, it is separated by insulating layer therebetween.
It is expected that being further improved the structure and its manufacturing method of 3D memory device, the storage for not only improving 3D memory device is close
Degree, and it is further simplified manufacturing process, manufacturing cost is reduced, yield and reliability are improved.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, wherein in an interconnection structure
Bit line is formed, so that bit line doubles as the interconnection between the array structure for different level, so as to simplify manufacturing process and subtract
The size of small 3D memory device.
According to the first aspect of the invention, a kind of 3D memory device is provided, comprising: the first array structure, described first gust
Array structure includes the first substrate, the first rhythmic structure of the fence on first substrate and through first gate stack
Multiple first channel columns of structure；Second array structure is stacked on above first array structure, the second array structure
Including the second substrate, the second rhythmic structure of the fence on second substrate and through second rhythmic structure of the fence
Multiple second channel columns and interconnection structure between first array structure and the second array structure and wrap
Including multiple bit lines, wherein the multiple second channel column is each passed through second substrate and is connected to the multiple bit lines, and
The corresponding channel column being connected to via the multiple bit lines in the multiple first channel column.
Preferably, first rhythmic structure of the fence and second rhythmic structure of the fence respectively include the multiple grid being alternately stacked
Pole conductor layer and multiple interlayer insulating films, and the multiple gate conductor layer is patterned step-like, to form stepped region
Domain provides the electrical connection area of wordline in the stepped area.
Preferably, in first array structure, the multiple first channel column is located at first rhythmic structure of the fence
Intermediate region, in the second array structure, the multiple second channel is located at the centre of second rhythmic structure of the fence
Region.
Preferably, first array structure further includes the multiple first pseudo- channel columns positioned at the stepped area, described
It a part of gate conductor layer of multiple first pseudo- channel columns in first rhythmic structure of the fence and is not connected to described a plurality of
Bit line, the second array structure further include the multiple second pseudo- channel columns positioned at the stepped area, and the multiple second is pseudo-
A part of gate conductor layer of the channel column in second rhythmic structure of the fence and it is not connected to the multiple bit lines.
Preferably, further includes: the cmos circuit in first substrate.
Preferably, further includes: the first insulating layer, for surrounding insulating regions, first rhythmic structure of the fence and described the
Two rhythmic structure of the fence are located at the outside of the insulating regions；First insulating laminate structure and the second insulating laminate structure are located at institute
The inside of insulating regions is stated, and corresponding with first rhythmic structure of the fence and second rhythmic structure of the fence respectively；And
First conductive channel is upwardly extended positioned at the inside of the insulating regions from first substrate, sequentially passes through described first absolutely
Edge laminated construction, second substrate, the second insulating laminate structure, reach the top of the second array structure, wherein
First conductive channel provides being electrically connected between the cmos circuit and peripheral circuit.
Preferably, first conductive channel includes the array of multiple conductive column compositions.
Preferably, further includes: the second conductive channel positioned at the outside of the insulating regions, including conductive column and surrounds
The second insulating layer of conductive column, second conductive channel are upwardly extended from first substrate, sequentially pass through the first grid
Laminated construction, second substrate, second rhythmic structure of the fence, reach the top of the second array structure, wherein described
Second conductive channel provides being electrically connected between first substrate and public source zone and source electrode line in second substrate.
Preferably, further includes: grid line gap, being used for will be in first rhythmic structure of the fence and second rhythmic structure of the fence
Grid conducting layer be divided into a plurality of grid line.
Preferably, second conductive channel is located in the grid line gap.
Preferably, multiple gate conductor layers in first rhythmic structure of the fence and the multiple first channel column are formed more
A selection transistor and multiple memory transistors, multiple gate conductor layers in second rhythmic structure of the fence and the multiple the
Two channel columns form multiple selection transistors and multiple memory transistors.
Preferably, the interconnection structure further include: third insulating layer, the multiple bit lines are formed in the third insulating layer
In；And third conductive channel, the third conductive channel passes through the third insulating layer, so that the multiple bit lines are via institute
It states in the corresponding channel column that third conductive channel is connected in the multiple first channel column.
Preferably, every bit line in the multiple bit lines is connected in the multiple first channel column one group of channel column
The bottom end of another group of channel column in top and the multiple second channel column.
Preferably, the multiple first channel column is aligned with corresponding one in the multiple second channel column respectively.
According to the second aspect of the invention, a kind of method for manufacturing 3D memory device is provided, comprising: form the first array junctions
Structure, first array structure include the first substrate, the first rhythmic structure of the fence on first substrate and through institute
State multiple first channel columns of the first rhythmic structure of the fence；Second array structure is formed, the second array structure includes the second lining
Bottom, the second rhythmic structure of the fence on second substrate and multiple second ditches through second rhythmic structure of the fence
Road column；Interconnection structure is formed between the first array structure and second array structure, the interconnection structure includes multiple bit lines,
In, the multiple first channel column is commonly connected to a plurality of position to corresponding one in the multiple second channel column respectively
A corresponding bit line in line.
Preferably, the step of forming the first array structure includes: that the first insulating laminate knot is formed on first substrate
Structure, the first insulating laminate structure include the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；It will be the multiple sacrificial
Domestic animal pattern layers are step-like；The multiple sacrificial layer is replaced as multiple gate conductor layers, so that it is folded to form the first grid
Layer structure.
Preferably, the step of forming second array structure includes: that the second insulating laminate knot is formed on second substrate
Structure, the second insulating laminate structure include the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；It will be the multiple sacrificial
Domestic animal pattern layers are step-like；The multiple sacrificial layer is replaced as multiple gate conductor layers, so that it is folded to form the first grid
Layer structure.
Preferably, further includes: form cmos circuit in first substrate；The first insulating layer is formed, described first absolutely
Edge layer surrounds a part of the first insulating laminate structure and the second insulating laminate structure, to form insulating regions；
And the first conductive channel is formed in the inside of the insulating regions, first conductive channel prolongs upwards from first substrate
It stretches, sequentially passes through the first insulating laminate structure, second substrate, the second insulating laminate structure, reach described the
The top of two array structures, wherein first conductive channel provides being electrically connected between the cmos circuit and peripheral circuit.
Preferably, first conductive channel includes the array of multiple conductive column compositions.
Preferably, further includes: form public source zone in first substrate and second substrate；In the insulation layer
The external of domain forms the second conductive channel, and second conductive channel is upwardly extended from first substrate, sequentially passes through described
First rhythmic structure of the fence, second substrate, second rhythmic structure of the fence, reach the top of the second array structure,
In, second conductive channel provides the electricity between public source zone and source electrode line in first substrate and second substrate
Connection.
Preferably, further includes: form grid line gap, be used for first rhythmic structure of the fence and the second gate stack knot
Grid conducting layer in structure is divided into a plurality of grid line.
Preferably, second conductive channel is located in the grid line gap.
Preferably, second conductive channel includes conductive column and the second insulating layer around conductive column.
Preferably, the step of forming interconnection structure includes: the formation third insulating layer on first array structure；Institute
State formation third conductive channel in third insulating layer；And the multiple bit lines are formed in the third insulating layer, wherein institute
It states in the corresponding channel column that multiple bit lines are connected in the multiple first channel column via the third conductive channel.
Preferably, form first array structure and the step of the second array structure in, by the multiple the
One channel column is aligned with corresponding one in the multiple second channel column respectively.
3D memory device according to an embodiment of the present invention and its manufacturing method, interconnection structure are located at first array structure
Between the second array structure, and interconnection structure includes multiple bit lines.The multiple bit lines double as different level
Interconnection between array structure, the bit line can provide the alignment mark between the first array structure and second array structure, and
And the bit line has biggish surface area, so that the alignment of the first array structure and the channel column in second array structure be allowed to hold
Difference.
Unlike the prior art, the 3D memory of the embodiment of the present invention is logical as the conduction in interconnection structure using bit line
Road not only can reduce 3D memory to realize the interconnection between the channel column in the first array structure and second array structure
The size of part, and can simplify manufacturing process, reduce the manufacturing cost of 3D memory device.
Further, bigger conductive path sectional area can be obtained as interconnection structure using bit line, and reduced mutual
Link the defects of structure quantity, to reduce interconnection resistance, improves the performance of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device.
Fig. 3 a to 3h shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to the first source electrode
Selection line SSL, the grid of the second selection transistor Q2 are connected to the second control gate selection line GSL.Memory transistor M1 is to M4's
Grid is respectively connected to the respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included
Gate conductor layer 109b and 109c, memory transistor M1 to M4 respectively include gate conductor layer 109a.Gate conductor layer 109a,
109b and 109c is consistent with the stacking order of transistor in memory cell string 100, adopts each other between adjacent gate conductor layer
It is separated with interlayer insulating film, to form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel
Column 110 is adjacent with rhythmic structure of the fence or runs through rhythmic structure of the fence.In the middle section of channel column 110, gate conductor layer 109a
Tunneling medium layer 112, charge storage layer 113 and block media layer 114 are accompanied between channel layer 111, so that it is brilliant to form storage
Body pipe M1 to M4.Block media is accompanied between the both ends of channel column 110, gate conductor layer 109b and 109c and channel layer 111
Layer 114, to form first choice transistor Q1 and the second selection transistor Q2.
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride and silicon oxynitride of the particle comprising metal or semiconductor, gate conductor layer 109a, 109b and 109c
It is made of metal, such as tungsten.Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, channel layer 111
Doping type and selection transistor and the control type of transistor it is identical.For example, the selection transistor and control for N-type are brilliant
Body pipe, channel layer 111 can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used
Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors
And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed
The semiconductor layer and block media layer of two selection transistor Q2 and the semiconductor layer and block media of memory transistor M1 to M4
Layer.In channel column 110, the semiconductor layer and memory transistor M1 of first choice transistor Q1 and the second selection transistor Q2 are extremely
The semiconductor layer of M4 is electrically connected to each other.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, the second control gate selection line GSL
(Gate Selective Line) is biased to about zero volts, so that the selection corresponding to the second control gate selection line GSL is brilliant
Body pipe Q2 is disconnected, and the first drain selection line SSL (Source Selective Line) is biased to high voltage VDD, so that corresponding to
The selection transistor Q1 of first drain selection line SSL is connected.Further, bit line BIT2 is grounded, and wordline WL2 is offset to programming electricity
VPG, such as 20V or so are pressed, remaining wordline is offset to low-voltage VPS1.Due to the word line voltage of only selected memory transistor M2
Higher than tunneling voltage, therefore, the electronics of the channel region of memory transistor M2 reaches charge storage via tunneling medium layer 112
Layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes the first array structure stacked and second array structure.
Each array structure includes that 3*3 amounts to 9 memory cell strings 100, and each memory cell string 100 includes 4 storage units, thus
It is respectively formed the memory array that 3*3*4 amounts to 36 storage units.The first array structure and second in 3D memory device 200
Array structure is total to form 72 storage units.It is appreciated that the invention is not limited thereto, 3D memory device may include any more
A memory cell string, for example, 1024, the number of memory cells in each memory cell string can be it is any number of, for example, 32
It is a or 64.
By taking the first array structure in 3D memory device 200 as an example, the first rhythmic structure of the fence is formed on substrate 101 and is passed through
Wear multiple channel columns 110 of first rhythmic structure of the fence.In the first rhythmic structure of the fence, adjacent gate conductor layer 109 it
Between separated each other using interlayer insulating film.Interlayer insulating film is being not shown in the figure.The internal structure of channel column 110 such as Fig. 1 b institute
Show, is no longer described in detail herein.
Memory cell string in first array structure respectively includes respective channel column 110 and public grid conductor
Layer 109.Gate conductor layer 109 is consistent with the stacking order of transistor in memory cell string 100.In the centre of channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and resistance inside part, gate conductor layer 109 and channel column 110
It keeps off dielectric layer 114 together, forms memory transistor M1 to M4.At the both ends of channel column 110, gate conductor layer 109 and channel column
Channel layer 111 and block media layer 114 inside 110 together, form first choice transistor Q1 and the second selection transistor Q2.
Second array structure and the first array structure are essentially identical, form the second rhythmic structure of the fence on substrate 201 and pass through
Wear multiple channel columns 210 of the rhythmic structure of the fence.In the second rhythmic structure of the fence, between adjacent gate conductor layer 209 that
This is separated using interlayer insulating film.
Interconnection structure is between the first array structure and second array structure.Interconnection structure includes multiple bit lines 302.The
One array architecture and second array structure share multiple bit lines 302.As shown, channel column 110 in the first array structure from
Substrate 101 extends upwardly to corresponding bit line 302, and the channel column 210 in second array structure passes through substrate 201 and extends downward into
Corresponding bit line 302.
In this embodiment, the channel column 210 in the channel column 110 and second array structure in the first array structure is distinguished
The common bit lines 302 for being arranged in array, extending not only through respective rhythmic structure of the fence, and be connected in interconnection layer.Further,
Channel column 110 in first array structure is commonly connected to substrate 101, forms common source connection, the ditch in second array structure
Road column 210 is commonly connected to substrate 201, forms common source connection.
First array structure can also include pseudo- channel column 140, and second array structure can also include pseudo- channel column 240.
Pseudo- channel column 140 and 240 can be identical with the internal structure of channel column 110 and 210, and at least across in rhythmic structure of the fence
At least part grid conductor.However, pseudo- channel column 140 and 240 is not connected with bit line 302, to be provided solely for machinery
Supporting role, without being used to form selection transistor and memory transistor.Therefore, pseudo- channel column 140 and 240 is not also formed
Effective storage unit.
The grid conductor of first array structure and the string select transistor in second array structure is by grid line gap (gate
Line slit) it is divided into different grid lines.Grid line with multiple channel columns of a line is commonly connected to the choosing of the first source electrode of same
Select line (i.e. one of first drain selection line).
The grid conductor of first array structure and the memory transistor in second array structure is distinguished according to different levels
It links into an integrated entity.If the grid conductor of memory transistor is divided into different grid lines, the grid of same level by grid line gap
Line reaches interconnection layer via respective conductive channel, thus it is interconnected amongst one another, then same wordline is connected to via conductive channel
(i.e. wordline one).
The grid conductor of ground selection transistor in first array structure and second array structure links into an integrated entity.If ground
The grid conductor of selection transistor is divided into different grid lines by grid line gap, then grid line reaches mutual via respective conductive channel
Even layer, thus it is interconnected amongst one another, then same the second control gate selection line is connected to via conductive channel.
Further, which includes multiple conductive channels.For example, in the substrate 101 of the first array structure
For example including cmos circuit, conductive channel 123 provides being electrically connected between cmos circuit and peripheral circuit, and conductive channel 130 mentions
For being electrically connected between the public source and source electrode line of memory string.
For example, the first array structure and second array structure include the insulating regions surrounded by separation layer 121, in the region
In, different from rhythmic structure of the fence, which still maintains insulating laminate structure, wherein multiple sacrificial layers and multiple interlayers are exhausted
Edge layer is alternately stacked.In insulating regions, conductive channel 123 is, for example, the array of multiple conductive column compositions, respectively from first gust
The substrate 101 of array structure upwardly extends, and sequentially passes through the insulating laminate structure of the first array structure, the substrate of second array structure
201, the insulating laminate structure of second array structure reaches the top of second array structure.
For example, conductive channel 130 includes conductive column and the insulation around conductive column in the region of neighbouring channel column
Layer.Conductive channel 130 is upwardly extended from the substrate 101 of the first array structure, sequentially passes through the gate stack knot of the first array structure
Structure, the substrate 201 of second array structure, second array structure rhythmic structure of the fence, reach second array structure top.
In this embodiment, conductive channel 130 is adjacent with channel column, and is formed in the access opening similar with channel hole
Conductive column and insulating layer.In alternate embodiments, can be formed directly in grid line gap conductive channel 130 conductive column and
Insulating layer, so as to save the step of forming access opening.It should be noted that forming independent access opening is still preferred implementation
Example.The conductive channel 130 run through the first array structure and second array structure insulating laminate structure, with pass through second array knot
The 201 grid line gap of substrate of structure is compared, and independent access opening can reduce the open-mouth ruler in the substrate 201 of second array structure
It is very little, to maintain the mechanical strength of 3D memory device.
Fig. 3 a to 3h shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.Institute
Sectional view is stated to intercept along the AA line in Fig. 2.
This method starts from the first array structure L01 that insulating laminate structure is formed on substrate 101, such as Fig. 3 a institute
Show.
First array structure L01 includes substrate 101 and insulating laminate structure thereon.The insulating laminate structure includes alternating
The multiple interlayer insulating films 108 and multiple sacrificial layers 122 stacked.In this embodiment, substrate 101 is, for example, monocrystalline substrate,
Interlayer insulating film 108 is for example made of silica, and sacrificial layer 122 is for example made of silicon nitride.
As described below, sacrificial layer 122 will be substituted for grid conductor, and grid conductor is further attached to wordline.For shape
At the conductive channel for reaching wordline from grid conductor, multiple sacrificial layers 122 are for example patterned step-like, that is, each sacrificial layer
122 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 122
Later, insulating laminate structure can be covered using insulating layer.In fig. 3 a by the interlayer insulating film between multiple sacrificial layers 122
108 integrally show with the interlayer insulating film for covering insulating laminate structure.However, the invention is not limited thereto, it can be using multiple only
Vertical deposition step is formed between multiple sacrificial layers 122 and its interlayer insulating film of top.
For the ease of being programmed operation to the storage unit in 3D memory device, multiple well regions are formed in substrate 101
And the cmos circuit (not shown) for driving selection transistor and memory transistor.The multiple well region is for example including deep N
Trap 102, the high pressure p-well 103 in deep N-well 102 and high pressure N trap 105, the P+ doped region 104 in high pressure p-well 103, position
N+ doped region 106 in high pressure N trap 105.In this embodiment, public source zone of the high pressure p-well 103 as channel column, high pressure N
For trap 105 for the precharge to public source zone, P+ doped region 104 and N+ doped region 106 reduce contact respectively as contact zone
Resistance.Public source zone of the high pressure p-well 103 as multiple channel columns, therefore it is located at the lower section of insulating laminate structure.
Further, corresponding with intermediate region (the core region) of insulating laminate structure in the first array structure L01
In the A01 of first area, the channel column 110 for running through insulating laminate structure is formed, in the stepped area (stair- of insulating laminate structure
Step region) in corresponding second area A02, the pseudo- channel column 140 for running through insulating laminate structure is formed, as shown in Figure 3b.
The lower part of channel column 110 includes semiconductor layer 116.Further, channel column 110 includes that half is extended to from upper part
The channel layer 111 of conductor layer 116.As shown, channel column 110 includes being sequentially stacked on ditch in the middle section of channel column 110
Tunneling medium layer 112, charge storage layer 113 and block media layer 114 in channel layer 111, at the both ends of channel column 110, channel
Column 110 includes the block media layer 114 being stacked on channel layer 111 or semiconductor layer 116.The lower end of channel column 110 and substrate
High pressure p-well 103 (public source zone) in 101 is in contact.In final 3D memory device, the upper end of channel column 110 and bit line
It is connected, to form effective storage unit.
The internal structure of pseudo- channel column 140 and channel column 110 can be identical or different, and at least across rhythmic structure of the fence
In at least part grid conductor.In final 3D memory device, pseudo- channel column 140 is not connected with bit line, thus
It is provided solely for mechanical support effect, without being used to form selection transistor and memory transistor.Therefore, pseudo- channel column 140 does not have
To form effective storage unit.
In this embodiment, channel column 110 further includes the insulating layer 115 as core, channel layer 111, tunneling medium layer
112, charge storage layer 113 and block media layer 114 form the laminated construction for surrounding core.In alternate embodiments, channel
Insulating layer 115 can be saved in column 110.
Further, interconnection structure L03 is formed on the first array structure L01, as shown in Figure 3c.
Interconnection structure L03 includes interlayer insulating film 301, the multiple bit lines 302 in interlayer insulating film 301, and
Connect the conductive channel 303 of bit line 302 and the channel layer 111 in corresponding channel column 110.The multiple bit lines 302 are along
One direction (i.e. perpendicular to the direction of paper) extends, so that the upper end of multiple channel columns 110 link together respectively.In the reality
It applies in example, interlayer insulating film 301 is for example made of silica, and bit line 302 and conductive channel 303 are for example made of Ti/TiN or W.
Further, second array structure L02 is formed on interconnection structure L03, as shown in Figure 3d.
Second array structure L02 includes substrate 201 and insulating laminate structure thereon.The insulating laminate structure includes alternating
The multiple interlayer insulating films 208 and multiple sacrificial layers 222 stacked.In this embodiment, substrate 201 is, for example, monocrystalline substrate,
Interlayer insulating film 208 is for example made of silica, and sacrificial layer 222 is for example made of silicon nitride.
As described below, sacrificial layer 222 will be substituted for grid conductor, and grid conductor is further attached to wordline.For shape
At the conductive channel for reaching wordline from grid conductor, multiple sacrificial layers 222 are for example patterned step-like, that is, each sacrificial layer
222 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 222
Later, insulating laminate structure can be covered using insulating layer.In Fig. 3 d by the interlayer insulating film between multiple sacrificial layers 222
208 integrally show with the interlayer insulating film for covering insulating laminate structure.However, the invention is not limited thereto, it can be using multiple only
Vertical deposition step is formed between multiple sacrificial layers 222 and its interlayer insulating film of top.
It is similar with structure shown in FIG. 1, form multiple well regions in substrate 201, such as deep N-well 202, be located at deep N-well 202
In high pressure p-well 203 and high pressure N trap 205, the P+ doped region 204 in high pressure p-well 203, the N+ in high pressure N trap 205
Doped region 206.In this embodiment, public source zone of the high pressure p-well 203 as channel column, high pressure N trap 205 are used for common source
The precharge in area, P+ doped region 204 and N+ doped region 206 are respectively as contact zone to reduce contact resistance.The high pressure p-well 203
As the public source zone of multiple channel columns, therefore it is located at the lower section of insulating laminate structure.
Further, corresponding with intermediate region (the core region) of insulating laminate structure in second array structure L02
In the A01 of first area, the channel column 210 for running through insulating laminate structure is formed, in the stepped area (stair- of insulating laminate structure
Step region) in corresponding second area A02, the pseudo- channel column 240 for running through insulating laminate structure is formed, as shown in Figure 3 e.
Channel column 210 in second array structure L02 is substantially aligned with the channel column 110 in the first array structure L01, and two
The internal structure of person is identical, and this will not be detailed here.
The lower end of channel column 210 is in contact with the high pressure p-well 103 (public source zone) in substrate 201.Under channel column 210
End further extends on the bit line 302 of interconnection structure L03, and the channel layer in channel column 210 is connected with bit line 302, thus
Form effective storage unit.
The internal structure of pseudo- channel column 240 and channel column 210 can be identical or different, and at least across rhythmic structure of the fence
In at least part grid conductor.Pseudo- channel column 240 is not connected with bit line, so that it is provided solely for mechanical support effect,
Without being used to form selection transistor and memory transistor.Therefore, pseudo- channel column 240 does not form effective storage unit.
Further, separation layer 121 is formed in the first array structure L01 and second array structure L02, such as Fig. 3 f institute
Show.
Separation layer 121 is upwardly extended from the substrate 101 of the first array structure L01, sequentially passes through the first array structure L01's
The insulating laminate structure of insulating laminate structure, the substrate 201 of second array structure L02, second array structure L02 reaches second
The top of array structure.In the plan view perpendicular to stacking direction, separation layer 121 surrounds a part of insulating laminate structure
Region forms insulating regions A03.In this embodiment, separation layer 121 is for example made of silica.
Further, grid line seam is formed in the insulating laminate structure of the first array structure L01 and second array structure L02
Gap via the sacrificial layer 122 and 222 in the insulating laminate outside grid line gap removal insulating regions to form cavity, and is adopted
With metal layer filling cavity to form gate conductor layer 109 and 209, as shown in figure 3g.
When forming grid line gap, anisotropic etching can be used, for example, by using dry etching, as ion beam milling etching,
Plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in substrate 101 and 201
Surface nearby stop.
In this embodiment, grid line gap is applied not only to for grid conductor to be divided into a plurality of grid line.For this purpose, grid line gap is passed through
Wear the insulating laminate structure of the first array structure L01 and second array structure L02.
When forming cavity, using grid line gap as etchant channel, insulating laminate is removed using isotropic etching
Sacrificial layer 122 and 222 in structure is to form cavity.Isotropic etching can be using the wet etching or gas phase of selectivity
Etching.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.?
Use etching gas as etchant in gas phase etching, wherein semiconductor structure is exposed in etching gas.
In the case of interlayer insulating film and sacrificial layer in insulating laminate structure are made of silica and silicon nitride respectively,
In wet etching can using phosphoric acid solution as etchant, in gas phase etching can use C4F8, C4F6, CH2F2 and
One of O2 or a variety of.In an etching step, etchant is full of grid line gap.The end of sacrificial layer in insulating laminate structure
It is exposed in the opening in grid line gap, therefore, sacrificial layer touches etchant.Etchant is from the opening in grid line gap gradually to exhausted
The etched inside sacrificial layer of edge laminated construction.Due to the selectivity of etchant, the etching is relative to the layer in insulating laminate structure
Between insulating layer remove sacrificial layer.
When forming gate conductor layer, using grid line gap as deposit channel, using atomic layer deposition (ALD),
Metal layer is filled in grid line gap and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, six are utilized
The chemisorption of the reaction product of tungsten fluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
After forming the gate conductor, inside insulating regions A03, still maintain insulating laminate structure, wherein multiple
Sacrificial layer and multiple interlayer insulating films are alternately stacked.Outside insulating regions A03, insulating laminate structure is replaced with into gate stack knot
In structure, wherein multiple gate conductor layers and multiple interlayer insulating films are alternately stacked.
In the first array structure L01 and second array structure L02, it is respectively formed selection transistor and memory transistor.
Ditch by taking the first array structure L01 as an example, in the middle section of channel column 110, inside gate conductor layer 109 and channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 together, form memory transistor.In channel
Channel layer 111 (or semiconductor layer 116) and block media inside the both ends of column 110, gate conductor layer 109 and channel column 110
Layer 114 together, forms selection transistor.
Further, multiple conductive channels 123 and 130 are formed, cmos circuit and peripheral circuit in substrate are provided respectively
Between electrical connection and public source zone and source electrode line between be electrically connected, as illustrated in figure 3h.
Inside insulating regions A03, conductive channel 123 is, for example, the array of multiple conductive column compositions, respectively from first gust
The substrate 101 of array structure upwardly extends, and sequentially passes through the insulating laminate structure of the first array structure, the substrate of second array structure
201, the insulating laminate structure of second array structure reaches the top of second array structure.
Outside insulating regions A03, conductive channel 130 includes conductive column 133 and the insulating layer around conductive column 133
132.Conductive channel 130 is upwardly extended from the substrate 101 of the first array structure, sequentially passes through the gate stack knot of the first array structure
Structure, the substrate 201 of second array structure, second array structure rhythmic structure of the fence, reach second array structure top.
Preferably, using ion implanting, N-type (using N type dopant, such as P, As) or p-type are formed in substrate 101
The doped region 131 of (using P-type dopant, such as B).The contact zone that doped region 131 is connected as common source, for reducing conduction
Contact resistance between channel and public source zone.
In this embodiment, the conductive column 133 in conductive channel 123 and conductive channel 130 is for example by Ti/TiN or W group
At insulating layer 132 is for example made of silica.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (25)
1. a kind of 3D memory device, comprising:
First array structure, first array structure include the first substrate, the first gate stack on first substrate
Structure and multiple first channel columns through first rhythmic structure of the fence；
Second array structure is stacked on above first array structure, and the second array structure includes the second substrate, is located at
The second rhythmic structure of the fence on second substrate and multiple second channel columns through second rhythmic structure of the fence, with
And
Interconnection structure, between first array structure and the second array structure and including multiple bit lines,
Wherein, the multiple second channel column is each passed through second substrate and is connected to the multiple bit lines, and via institute
State the corresponding channel column that multiple bit lines are connected in the multiple first channel column.
2. 3D memory device according to claim 1, wherein first rhythmic structure of the fence and the second gate stack knot
Structure respectively includes the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked, and the multiple grid conductor layer pattern
It turns to step-like, to form stepped area, provides the electrical connection area of wordline in the stepped area.
3. 3D memory device according to claim 2, wherein in first array structure, the multiple first ditch
Road column is located at the intermediate region of first rhythmic structure of the fence, in the second array structure, the multiple second channel position
In the intermediate region of second rhythmic structure of the fence.
4. 3D memory device according to claim 2, wherein first array structure further includes being located at the stepped region
The pseudo- channel column of multiple the first of domain, a part of grid of the multiple first pseudo- channel column in first rhythmic structure of the fence
Conductor layer and the multiple bit lines are not connected to, the second array structure further includes positioned at multiple the second of the stepped area
Pseudo- channel column, a part of gate conductor layer of the multiple second pseudo- channel column in second rhythmic structure of the fence and does not connect
It is connected to the multiple bit lines.
5. 3D memory device according to claim 2, further includes: the cmos circuit in first substrate.
6. 3D memory device according to claim 5, further includes:
First insulating layer, for surrounding insulating regions, first rhythmic structure of the fence and second rhythmic structure of the fence are located at institute
State the outside of insulating regions；
First insulating laminate structure and the second insulating laminate structure, positioned at the inside of the insulating regions, and respectively with it is described
First rhythmic structure of the fence and second rhythmic structure of the fence are corresponding；And
First conductive channel is upwardly extended positioned at the inside of the insulating regions from first substrate, sequentially passes through described
One insulating laminate structure, second substrate, the second insulating laminate structure, reach the top of the second array structure,
Wherein, first conductive channel provides being electrically connected between the cmos circuit and peripheral circuit.
7. 3D memory device according to claim 6, wherein first conductive channel includes what multiple conductive columns formed
Array.
8. 3D memory device according to claim 2, further includes:
Second conductive channel, positioned at the outside of the insulating regions, including conductive column and around the second insulating layer of conductive column,
Second conductive channel is upwardly extended from first substrate, sequentially passes through first rhythmic structure of the fence, second lining
Bottom, second rhythmic structure of the fence, reach the top of the second array structure,
Wherein, second conductive channel provide public source zone in first substrate and second substrate and source electrode line it
Between electrical connection.
9. 3D memory device according to claim 8, further includes: grid line gap is used for first rhythmic structure of the fence
A plurality of grid line is divided into the grid conducting layer in second rhythmic structure of the fence.
10. 3D memory device according to claim 9, wherein second conductive channel is located in the grid line gap.
11. 3D memory device according to claim 2, wherein multiple grid conductors in first rhythmic structure of the fence
Layer forms multiple selection transistors and multiple memory transistors with the multiple first channel column, in second rhythmic structure of the fence
Multiple gate conductor layers and the multiple second channel column form multiple selection transistors and multiple memory transistors.
12. 3D memory device according to claim 2, wherein the interconnection structure further include:
Third insulating layer, the multiple bit lines are formed in the third insulating layer；And
Third conductive channel, the third conductive channel passes through the third insulating layer, so that the multiple bit lines are via described
Third conductive channel is connected in the corresponding channel column in the multiple first channel column.
13. 3D memory device according to claim 12, wherein every bit line in the multiple bit lines is connected to described
In multiple first channel columns in the top of one group of channel column and the multiple second channel column another group of channel column bottom end.
14. 3D memory device according to claim 2, wherein the multiple first channel column is respectively with the multiple
A corresponding alignment in two channel columns.
15. a kind of method for manufacturing 3D memory device, comprising:
The first array structure is formed, first array structure includes the first substrate, the first grid on first substrate
Laminated construction and multiple first channel columns through first rhythmic structure of the fence；
Second array structure is formed, the second array structure includes the second substrate, the second gate on second substrate
Laminated construction and multiple second channel columns through second rhythmic structure of the fence；
Interconnection structure is formed between the first array structure and second array structure, the interconnection structure includes multiple bit lines,
Wherein, the multiple second channel column is each passed through second substrate and is connected to the multiple bit lines, and via institute
State the corresponding channel column that multiple bit lines are connected in the multiple first channel column.
16. according to the method for claim 15, wherein formed the first array structure the step of include:
Form the first insulating laminate structure on first substrate, the first insulating laminate structure include be alternately stacked it is more
A sacrificial layer and multiple interlayer insulating films；
The multiple sacrificial layer is patterned step-like；
The multiple sacrificial layer is replaced as multiple gate conductor layers, to form first rhythmic structure of the fence.
17. according to the method for claim 16, wherein formed second array structure the step of include:
Form the second insulating laminate structure on second substrate, the second insulating laminate structure include be alternately stacked it is more
A sacrificial layer and multiple interlayer insulating films；
The multiple sacrificial layer is patterned step-like；
The multiple sacrificial layer is replaced as multiple gate conductor layers, to form first rhythmic structure of the fence.
18. according to the method for claim 17, further includes:
Cmos circuit is formed in first substrate；
The first insulating layer is formed, first insulating layer surrounds the first insulating laminate structure and the second insulating laminate knot
A part of structure, to form insulating regions；And
The first conductive channel is formed in the inside of the insulating regions, first conductive channel prolongs upwards from first substrate
It stretches, sequentially passes through the first insulating laminate structure, second substrate, the second insulating laminate structure, reach described the
The top of two array structures,
Wherein, first conductive channel provides being electrically connected between the cmos circuit and peripheral circuit.
19. according to the method for claim 18, wherein first conductive channel includes the battle array of multiple conductive column compositions
Column.
20. according to the method for claim 18, further includes:
Public source zone is formed in first substrate and second substrate；
External in the insulating regions forms the second conductive channel, and second conductive channel prolongs upwards from first substrate
It stretches, sequentially passes through first rhythmic structure of the fence, second substrate, second rhythmic structure of the fence, reach described second gust
The top of array structure,
Wherein, second conductive channel provide public source zone in first substrate and second substrate and source electrode line it
Between electrical connection.
21. according to the method for claim 20, further includes:
Grid line gap is formed, for dividing the grid conducting layer in first rhythmic structure of the fence and second rhythmic structure of the fence
It is cut into a plurality of grid line.
22. according to the method for claim 20, wherein second conductive channel is located in the grid line gap.
23. according to the method for claim 20, wherein second conductive channel includes conductive column and around conductive column
Second insulating layer.
24. according to the method for claim 15, wherein formed interconnection structure the step of include:
Third insulating layer is formed on first array structure；
Third conductive channel is formed in the third insulating layer；And
The multiple bit lines are formed in the third insulating layer,
Wherein, the multiple bit lines are connected to corresponding one in the multiple first channel column via the third conductive channel
In channel column.
25. according to the method for claim 15, in the step for forming first array structure and the second array structure
In rapid, the multiple first channel column is aligned with corresponding one in the multiple second channel column respectively.
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