CN109003982B

CN109003982B - 3D memory device and method of manufacturing the same

Info

Publication number: CN109003982B
Application number: CN201810796632.1A
Authority: CN
Inventors: 张勇; 陶谦; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-07-19
Filing date: 2018-07-19
Publication date: 2021-10-26
Anticipated expiration: 2038-07-19
Also published as: CN109003982A

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a substrate; first and second stacked structures stacked over the substrate, the first and second stacked structures respectively including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; and a plurality of channel pillars penetrating the first and second stacked structures, the channel pillars including a channel layer and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer interposed between a plurality of gate conductors and the channel layer, at least the channel layer of the channel pillars continuously extending through a boundary of the first and second stacked structures. In the 3D memory device, the laminated structure part at the joint of the two laminated structures is disconnected and covered by the channel layer, so that a leakage source formed by the damaged laminated structure at the joint can be avoided, the continuity of the channel layer is also ensured, and the yield and the reliability of the 3D memory device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to a memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In the 3D memory device of the NAND structure, gate conductors of the select transistor and the memory transistor are provided using a stacked structure, and the storage of the memory cell string is achieved using a channel pillar penetrating the stacked structure. For a stacked structure with a high number of layers, the formation of channel columns is difficult, and the stacked structure is realized by stacking two to multiple stacked structures, but the channel columns of the upper layer and the lower layer are staggered, so that the channel columns at the corners of the joints of the layers are damaged when SNON (selective non-conducting) drilling is performed, and a leakage source is formed if the SNON drilling is not performed, so that the 3D memory device is failed.

It is desirable to further improve the structure of the 3D memory device and the method of fabricating the same to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

The invention aims to provide an improved 3D memory device and a manufacturing method thereof, wherein a laminated structure part at the joint of two laminated structures is disconnected and covered by a channel layer, so that the laminated structure at the joint can be prevented from being damaged to form a leakage source, and the continuity of the channel layer is also ensured, thereby improving the yield and the reliability of the 3D memory device.

According to a first aspect of the present invention, there is provided a 3D memory device comprising: a substrate; first and second stacked structures stacked over the substrate, the first and second stacked structures respectively including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; and a plurality of channel pillars penetrating through the first and second stacked structures, the channel pillars including a channel layer, and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer interposed between the plurality of gate conductors and the channel layer, wherein at least the channel layer in the channel pillars continuously extends at a position where at least one of the tunneling dielectric layer, the charge storage layer, and the gate dielectric layer is disconnected.

Preferably, the position of the disconnection is a boundary of the first stacked structure and the second stacked structure.

Preferably, the 3D memory device further includes: an isolation layer between the first and second stacked structures, the channel layer extending continuously through the isolation layer.

Preferably, an epitaxial layer is formed between the channel pillar and the substrate, and the channel layer partially covers the epitaxial layer.

Preferably, the channel pillar of the first stacked structure and the channel pillar of the second stacked structure are offset from each other by a certain distance at a junction of the first stacked structure and the second stacked structure, thereby forming a channel window at the junction.

Preferably, a portion of the epitaxial layer directly covered by the channel layer vertically corresponds to the channel window.

Preferably, the interlayer insulating layers of the first and second stacked structures are in contact to form an isolation layer.

Preferably, in the structure of the tunneling dielectric layer, the charge storage layer and the gate dielectric layer, which are in contact with the isolation layer, the tunneling dielectric layer and the charge storage layer are partially disconnected.

Preferably, the tunneling dielectric layer, the charge storage layer and the gate dielectric layer partially cover the epitaxial layer and are in contact with the channel layer partially covering the epitaxial layer.

Preferably, bottom ends of the plurality of channel pillars form a common source connection via the epitaxial layer.

Preferably, the plurality of channel pillars form a plurality of memory transistors with a plurality of first gate conductors of the plurality of gate conductors, and form a first select transistor and a second select transistor with a second gate conductor and a third gate conductor of the plurality of gate conductors, respectively.

Preferably, the third gate conductor comprises a layer of the gate conductor located closest to the epitaxial layer in the first stacked structure; the second gate conductor comprises a layer of the gate conductor located farthest from the epitaxial layer in the second stacked structure; the first gate conductor is located between the second gate conductor and the third gate conductor.

According to a second aspect of the present invention, there is provided a method of manufacturing a 3D memory device, comprising: forming a first stacked structure on a substrate; forming a first pillar through the first laminate structure; forming a second stacked structure on the first stacked structure; forming a second post penetrating through the second lamination; removing a part of the first cylinder and the second cylinder to form a channel hole; and forming a channel layer in the channel hole, wherein at least the channel layer in the channel hole continuously extends at a position where at least one of the tunneling dielectric layer, the charge storage layer and the gate dielectric layer is disconnected.

Preferably, before the step of forming the first stacked structure, the method further comprises: and depositing an epitaxial layer on the substrate, wherein the epitaxial layer is in contact with the first cylinder.

Preferably, the step of forming the first lamination and the first pillar and the second lamination and the second pillar includes: alternately depositing a plurality of grid conductors and a plurality of interlayer insulating layers on the substrate to form a first laminated structure, and etching the first laminated structure to form a plurality of first columns penetrating through the first laminated structure; and alternately depositing a plurality of grid conductors and a plurality of interlayer insulating layers on the first laminated structure to form a second laminated structure, and etching the second laminated structure to form a plurality of second cylinders penetrating through the second laminated structure.

Preferably, the step of forming the channel hole further comprises forming a channel pillar before: the first cylinder is communicated with the second cylinder; sequentially depositing along the inner walls of the first cylinder and the second cylinder to form a continuous gate dielectric layer, a charge storage layer and a tunneling dielectric layer; and depositing a sacrificial layer along the surface of the tunneling dielectric layer.

Preferably, the first and second columns are offset from each other by a distance at a junction of the first and second laminations, thereby forming a channel window at the junction.

Preferably, the channel hole forming step includes: punching a hole along the top to the bottom of the channel column through the channel window to form a through hole penetrating through the bottom of the channel column so as to expose part of the epitaxial layer; partially etching the damaged charge storage layer and the tunneling dielectric layer at the joint of the first laminated structure and the second laminated structure; partially etching the damaged charge storage layer and the tunneling dielectric layer at the connection position of the epitaxial layer and the channel column; and etching the sacrificial layer completely.

Preferably, the step of forming a channel layer in the channel hole includes: and depositing on the surfaces of the gate dielectric layer, the charge storage layer and the tunneling dielectric layer along the inner wall of the channel column to form a continuous channel layer, wherein the channel layer completely covers the gate dielectric layer, the charge storage layer and the tunneling dielectric layer, covers the exposed surface of the epitaxial layer and is in contact with the epitaxial layer.

Preferably, the plurality of gate conductors are formed from a metal layer using atomic layer deposition.

Preferably, the metal layer is composed of at least one selected from tungsten, platinum, titanium, or an alloy thereof.

According to the 3D memory device and the manufacturing method thereof provided by the embodiment of the invention, the laminated structure comprising the gate conductors and the interlayer insulating layers which are alternately stacked is formed above the substrate, the channel column penetrating through the laminated structure is formed, and the channel column comprises the laminated structure clinging to the inner wall of the channel column and the channel layer positioned on the surface of the laminated structure. The 3D memory device adopts a stacking structure with at least two layers of stacking structures, SONO punching is carried out on the channel column, the damaged stacking structure at the joint of the at least two layers of stacking structures is partially etched, and a leakage source is prevented from being formed, so that the yield and the reliability of the 3D memory device are improved; and because the connection does not function as a word line, the etching does not affect the normal storage function of the storage device.

Furthermore, an epitaxial layer is formed between the channel column and the substrate, when SONO punching is carried out, a through small hole is formed in the laminated structure on the surface of the epitaxial layer, the laminated structure is damaged at the corner where the epitaxial layer is connected with the inner wall of the channel column, the damaged laminated structure is partially etched to form a discontinuous laminated structure, a continuous channel layer is formed on the surface of the laminated structure, and the channel layer covers the exposed surfaces of the laminated structure and the epitaxial layer, so that the continuity of the channel layer is ensured, and the normal storage performance of the storage device is ensured.

Furthermore, before punching, the surface of the laminated structure is covered with a sacrificial layer, after punching, the sacrificial layer is broken, the sacrificial layer is etched and then used as a channel layer, the sacrificial layer can protect the laminated structure, important structures such as a grid structure of a storage device can be prevented from being damaged during punching, and accordingly yield and reliability of the 3D storage device are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 shows a perspective view of a 3D memory device.

Fig. 3a to 3e respectively show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Fig. 4a and 4b show schematic structural views of channel pillars of the 3D memory device corresponding to fig. 3b and 3e, respectively.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include gate conductor layers 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductor layers 121, respectively. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers. In an alternative embodiment, the core of channel pillar 110 is a hollow structure, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122 and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other with an interlayer insulating layer, thereby forming a gate conductor 120 of a gate stack structure. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 form the selection transistors Q1 and Q2 together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110.

The channel pillars 110 penetrate through the gate conductor 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 100.

The gate conductor 122 of the first select transistor, i.e., the string select transistor Q1, is divided into different gate lines by a gate line slit (gate line slit). The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are split into different gate lines by the gate line slit, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via a conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is slit into different gate lines by the gate line, the gate lines reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

Fig. 3a to 3e respectively show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

The 3D memory device 300 of the present embodiment includes at least a two-layer stacked structure 150, and the present embodiment is exemplified by a two-layer stacked structure, that is, a substrate 101, and a stacked structure 150' and a stacked structure 150 stacked over the substrate 101. The stacked structure 150 ' and the stacked structure 150 include a plurality of gate conductors and a plurality of interlayer insulating layers, respectively, which are alternately stacked, and a plurality of channel pillars, which include the channel layer 111, penetrating the stacked structure 150 ' and the stacked structure 150, of which at least the channel layer 111 continuously extends through the boundary of the stacked structure 150 ' and the stacked structure 150.

As shown in fig. 3a, there is shown a basic structure of a 3D memory device manufacturing method according to an embodiment of the present invention, the structure forming step includes: alternately depositing a plurality of interlayer insulating layers 140 ' and a plurality of gate conductors 120 ' on the substrate 101 to form a stacked structure 150 '; the stack 150 ' is etched to form pillars 10 ' extending through the stack 150 '. A plurality of gate conductors 120 and a plurality of interlayer insulating layers 140 are alternately deposited on the stacked structure 150' to form a second stacked structure 150, and the stacked structure 150 is etched to form a plurality of pillars 10 penetrating the stacked structure 150.

In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, and the interlayer insulating layer 140' is, for example, composed of silicon oxide. Further, an epitaxial layer 102 is grown on the substrate 101, and an epitaxial deposition growth of silicon is performed at the contact of the substrate 101 and the pillar 10' to form a silicon epitaxial layer (SEG).

As shown in fig. 3b, a schematic diagram of a trench pillar is shown. The channel pillar of the present embodiment includes a channel sidewall structure ONO closely attached to the inner walls of the channel pillars 110 and 110', and a sacrificial layer 116 on the surface of the channel sidewall structure ONO, and the ONO includes a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 stacked. The formation process of the channel pillars 110 and 110' includes: the column 10' is communicated with the column 10; sequentially depositing along the inner walls of the cylinder 10' and the cylinder 10 to form a continuous gate dielectric layer 114, a charge storage layer 113 and a tunneling dielectric layer 112; and sacrificial layer 116 is deposited along the surface of tunnel dielectric layer 112. Tunnel dielectric layer 112, charge storage layer 113, gate dielectric layer 114 and sacrificial layer 116 are all uniform and continuous layer structures, and sacrificial layer 116 is, for example, polysilicon.

The pillar 10 of the upper laminated structure 150 is communicated with the pillar 10 ' of the lower laminated structure 150 ', and due to the process, the communicated pillars 10 and 10 ' of the upper and lower laminated structures 150 and 150 ' are staggered by a certain distance at the joint of the laminated structure 150 and the laminated structure 150 ', so that a channel window 160 is formed at the joint; and because the upper-layer pillar 10 and the lower-layer pillar 10 'are influenced by the characteristics of silicon when being formed, the channel pillars 110 and 110' are in a shape of a pillar with a thick upper part and a thin lower part, and the aperture of the channel window 160 at the connection part is small. Tunnel dielectric layer 112, charge storage layer 113 and gate dielectric layer 114, and sacrificial layer 116 are each a continuous layer structure that covers the entire two layers of channel pillars 110 and 110'.

At this time, the bottom of the channel pillar 110 ' of the 3D memory device 300, that is, the surface of the epitaxial layer 102, is covered by the tunneling dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114, which are not favorable for the subsequent communication between the channel layer 110 ' and the epitaxial layer 102, so that the SONO punching operation is performed on the bottom of the channel pillar 110 ' along the top of the channel pillar 110 through the channel window 160 along the direction L as shown by a set of solid lines in the figure.

As shown in fig. 3c, the channel pillars 110 and 110 ' are vertically punched, and since the channel pillars 110 and 110 ' and the ONO and sacrificial layer 116 on the inner wall are inclined structures and the channel window 160 is small in size, the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114, and the sacrificial layer 116 may be strongly impacted by the high deviation of the punching and damaged in the punching process in the stacked structures 150 and 150 ' located at the junction of the two-layered stacked structures 150 and 150 ' and the junction of the surface of the substrate 101 and the pillar 10 '.

Tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114, and sacrificial layer 116 on the surface of substrate 101 are punched to form a via through the bottom of channel pillar 110' to partially expose epitaxial layer 102 for subsequent connection to channel layer 111. After punching, the exposed portions of epitaxial layer 102, i.e., the vias, are positioned in vertical correspondence with channel windows 160.

The ONO and sacrificial layer 116 at the corner where the stacked structure 150 and the stacked structure 150 'are connected and the ONO and sacrificial layer 116 at the corner where the substrate 101 surface and the channel pillar 110' are connected may cause leakage source and affect the memory performance due to the damage caused by punching if not processed in time. The damaged tunnel dielectric layer 112, charge storage layer 113 and gate dielectric layer 114 are partially etched in this embodiment.

Specifically, the interlayer insulating layer 140 of the stacked structure 150 is in contact with the interlayer insulating layer 140 'of the stacked structure 150', forming an isolation layer. The ONO (tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114) contacting the isolation layer at the junction does not correspond to the gate conductor 120 and does not function as a wordline, and at this time, even if the ONO is discontinuous, the storage performance of the memory device is not affected, so the ONO at the damaged portion is partially etched. For example, the tunnel dielectric layer 112 and the charge storage layer 113 at the two connecting corners are etched, and the gate dielectric layer 114 is not processed and still protects the outer structure, thereby forming an ONO structure that is not completely continuous and is deposited along the inner surface of the channel pillars 110 and 110'. The sacrificial layer 116 is also damaged by the punching, and thus has a discontinuous layer structure.

In the punching process, the protruding portion of the lower channel pillar 110' at the channel window 160 is impacted and damaged, so that the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 on one side are etched and disconnected in the cross-sectional view, and actually, etching is suitable for the damaged portion. Etched portions of tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 on the surface of substrate 101 may be communicated with the via holes to form larger via holes.

Next, forming the channel layer 111, as shown in fig. 3d, etching away all the damaged sacrificial layer 116 after punching, exposing the discontinuous tunnel dielectric layer 112, the charge storage layer 113, the gate dielectric layer 114 and the through hole, and forming a channel layer on their surfaces.

As shown in fig. 3e, a continuous channel layer 111 is deposited on the surfaces of the gate dielectric layer 114, the charge storage layer 113 and the tunneling dielectric layer 112 along the inner walls of the channel pillars 110 and 110', wherein the channel layer 111 completely covers the exposed surfaces of the gate dielectric layer 114, the charge storage layer 113, the tunneling dielectric layer 112 and the epitaxial layer 102, i.e., the channel layer 111 is continuous and extends through the corresponding etched portion of the isolation layer, and the channel layer 111 is in conduction with the epitaxial layer 102 through a via, and the epitaxial layer 102 is connected to a common source region. Finally, the plurality of channel pillars 110' form a common source connection via the epitaxial layer 102 on the substrate 101.

Preferably, the plurality of gate conductors 120 are formed of a metal layer using Atomic Layer Deposition (ALD). The metal layer is composed of at least one selected from tungsten, platinum, titanium, or an alloy thereof, for example.

Thereby, the manufacturing method of the 3D memory device is completed.

Fig. 4a and 4b show schematic structural views of channel pillars of the 3D memory device corresponding to fig. 3b and 3e, respectively. Fig. 4a and 4b show a three-dimensional structure of the channel pillar 110.

As shown in fig. 4a, and described in conjunction with fig. 3 a-3 e, punch damage is formed at a junction a of stacked structure 150 and stacked structure 150 ', and at a corner B where substrate 101 is joined to pillar 110', which requires partial etching of gate dielectric layer 114, charge storage layer 113, and tunnel dielectric layer 112 at a and B.

After etching the sacrificial layer 116, a new channel layer 111 is deposited, as shown in fig. 4 b. At the etching part A, the charge storage layer 113 and the tunneling dielectric layer 112 are discontinuous and do not have the function of a word line; at the etching position B, the charge storage layer 113 and the tunneling dielectric layer 112 are discontinuous, and the third gate conductor 123 and the channel column 110' form a selection transistor GSL; on top of the channel pillar 110, only the channel layer 111 and the gate dielectric layer 114, the second gate conductor 122 and the channel pillar 110 form a select transistor SSL; the first gate conductor 121 between the second gate conductor 122 and the third gate conductor 123 and the channel pillars 110 and 110 ' form a memory transistor connected to word lines WL1-WL4, WL1 ' -WL4 '.

Here, only 4 word lines per layer are taken as an example, and there may be different numbers of word lines, such as 32, 64, etc. The above embodiments are only some preferred embodiments, but the embodiments of the present invention are not limited thereto.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device comprising:

a substrate;

first and second stacked structures stacked over the substrate, the first and second stacked structures respectively including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; and

a plurality of channel pillars extending through the first and second stacked structures, the channel pillars including a channel layer and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer sandwiched between a plurality of gate conductors and the channel layer,

wherein at least one of the tunneling dielectric layer, the charge storage layer and the gate dielectric layer is disconnected, at least the channel layer in the channel column continuously extends,

the tunneling dielectric layer and the charge storage layer which are positioned at the joint of the first laminated structure and the second laminated structure are disconnected and partially etched, and the gate dielectric layer protects the outer side structure;

and the tunneling dielectric layer and the charge storage layer which are positioned at the connecting corner of the substrate surface and the channel column are disconnected and partially etched, and the gate dielectric layer, the channel layer and the corresponding gate conductor form a selection transistor.

2. The 3D memory device of claim 1, wherein the location of the disconnection is a boundary of the first and second stacked structures.

3. The 3D memory device of claim 2, further comprising: an isolation layer between the first and second stacked structures, the channel layer extending continuously through the isolation layer.

4. The 3D memory device of claim 3, wherein an epitaxial layer is formed between the channel pillar and the substrate, the channel layer partially covering the epitaxial layer.

5. The 3D memory device of claim 4, wherein the channel pillar of the first stacked structure and the channel pillar of the second stacked structure are offset from each other by a distance at a junction of the first stacked structure and the second stacked structure, thereby forming a channel window at the junction.

6. The 3D memory device of claim 5, wherein a portion of the epitaxial layer directly covered by the channel layer vertically corresponds to the channel window.

7. The 3D memory device of claim 3, wherein the interlayer insulating layers of the first and second stacked structures are in contact to form an isolation layer.

8. The 3D memory device of claim 4, wherein the tunneling dielectric layer, charge storage layer, and gate dielectric layer partially overlie the epitaxial layer and are in contact with the channel layer partially overlying the epitaxial layer.

9. The 3D memory device of claim 4, wherein bottom ends of the plurality of channel pillars form a common source connection via the epitaxial layer.

10. The 3D memory device of claim 4, wherein the plurality of channel pillars form a plurality of memory transistors with a first plurality of gate conductors of the plurality of gate conductors and form a first select transistor and a second select transistor with a second gate conductor and a third gate conductor of the plurality of gate conductors, respectively.

11. The 3D memory device of claim 10, wherein the third gate conductor comprises a layer of the gate conductor located closest to the epitaxial layer in the first stacked structure; the second gate conductor comprises a layer of the gate conductor located farthest from the epitaxial layer in the second stacked structure; the first gate conductor is located between the second gate conductor and the third gate conductor.

12. A method of manufacturing a 3D memory device, comprising:

forming a first stacked structure on a substrate;

forming a first pillar through the first laminate structure;

forming a second stacked structure on the first stacked structure;

forming a second post penetrating through the second lamination;

removing a part of the first cylinder and the second cylinder to form a channel hole; and

forming a channel layer in the channel hole,

wherein at least the channel layer in the channel hole extends continuously at a position where at least one of the tunneling dielectric layer, the charge storage layer and the gate dielectric layer is disconnected,

the tunneling dielectric layer and the charge storage layer which are positioned at the joint of the first laminated structure and the second laminated structure are disconnected and partially etched, and the gate dielectric layer protects the outer side structure; and the tunneling dielectric layer and the charge storage layer which are positioned at the connecting corner of the substrate surface and the channel column are disconnected and partially etched, and the gate dielectric layer, the channel layer and the corresponding gate conductor form a selection transistor.

13. The manufacturing method according to claim 12, wherein before the step of forming the second stacked structure, further comprising: and depositing an epitaxial layer on the substrate, wherein the epitaxial layer is in contact with the first cylinder.

14. The manufacturing method of claim 13, wherein the step of forming the first lamination and the first pillar and the second lamination and the second pillar comprises:

alternately depositing a plurality of grid conductors and a plurality of interlayer insulating layers on the substrate to form a first laminated structure, and etching the first laminated structure to form a plurality of first columns penetrating through the first laminated structure; and

and alternately depositing a plurality of grid conductors and a plurality of interlayer insulating layers on the first laminated structure to form a second laminated structure, and etching the second laminated structure to form a plurality of second cylinders penetrating through the second laminated structure.

15. The method of manufacturing of claim 14, wherein the step of forming the channel hole is preceded by forming a channel post:

the first cylinder is communicated with the second cylinder;

sequentially depositing along the inner walls of the first cylinder and the second cylinder to form a continuous gate dielectric layer, a charge storage layer and a tunneling dielectric layer; and

and depositing a sacrificial layer along the surface of the tunneling medium layer.

16. The method of manufacturing of claim 15, wherein the first and second pillars are offset from each other at a junction of the first and second laminations to form a channel window at the junction.

17. The manufacturing method according to claim 16, wherein the forming of the channel hole includes:

punching a hole along the top to the bottom of the channel column through the channel window to form a through hole penetrating through the bottom of the channel column so as to expose part of the epitaxial layer;

partially etching the damaged charge storage layer and the tunneling dielectric layer at the joint of the first laminated structure and the second laminated structure;

partially etching the damaged charge storage layer and the tunneling dielectric layer at the connection position of the epitaxial layer and the channel column; and

and etching the whole sacrificial layer.

18. The manufacturing method of claim 17, wherein the step of forming a channel layer in the channel hole comprises:

depositing on the surfaces of the gate dielectric layer, the charge storage layer and the tunneling dielectric layer along the inner wall of the channel column to form a continuous channel layer,

the channel layer completely covers the gate dielectric layer, the charge storage layer and the tunneling dielectric layer, covers the exposed surface of the epitaxial layer and is in contact with the epitaxial layer.

19. The method of manufacturing of claim 18, wherein bottom ends of the plurality of channel pillars form a common source connection via the epitaxial layer.

20. The method of manufacturing of claim 18, wherein the plurality of gate conductors are formed from a metal layer using atomic layer deposition.

21. The manufacturing method according to claim 19, wherein the metal layer is composed of at least one selected from tungsten, platinum, titanium, or an alloy thereof.