CN109346473B - 3D memory device and method of manufacturing the same - Google Patents

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of conductive lines on the first and second surfaces of the laminated structure; and CMOS circuits adjacent to the first and second surfaces of the stacked structure, wherein the plurality of conductive lines on the first surface are connected to the CMOS circuits adjacent to the first surface, and the plurality of conductive lines on the second surface are connected to the CMOS circuits adjacent to the second surface. The 3D memory device adopts the CMOS circuits which are respectively adjacent to the first surface and the second surface of the 3D memory device stacking structure, so that the wiring density can be reduced, the wiring width can be increased, the parasitic resistance and the parasitic capacitance can be reduced, the storage density and the access speed can be improved, and the yield and the reliability of the 3D memory device can be improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In the 3D memory device of the NAND structure, gate conductors of the selection transistor and the memory transistor are provided in a stacked structure, and electrical connection of the transistors to the CMOS circuit is provided using a large number of metal wirings. It is desirable to further improve the structure of the 3D memory device and the method of fabricating the same to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method of fabricating the same, in which common source lines and bit lines are located at first and second surfaces of a stacked structure, respectively, thereby reducing wiring density to improve yield and reliability of the 3D memory device.

According to an aspect of the present invention, there is provided a 3D memory device, comprising: a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of conductive lines on the first and second surfaces of the laminated structure; and CMOS circuits adjacent to the first and second surfaces of the stacked structure, wherein the plurality of conductive lines on the first surface are connected to the CMOS circuits adjacent to the first surface, and the plurality of conductive lines on the second surface are connected to the CMOS circuits adjacent to the second surface.

Preferably, the plurality of conductive lines includes a plurality of bit lines on one of a first surface and a second surface of the stacked structure and a common source line on the other of the first surface and the second surface of the stacked structure.

Preferably, the method further comprises the following steps: a plurality of channel pillars penetrating the stacked structure, one ends of the plurality of channel pillars being respectively connected to corresponding bit lines among the plurality of bit lines, and the other ends being commonly connected to the common source line.

Preferably, the plurality of channel pillars include a first group of channel pillars and a second group of channel pillars adjacent to each other, the plurality of bit lines connected by the first group of channel pillars are located on the first surface of the stacked structure, the common source line connected by the first group of channel pillars is located on the second surface of the stacked structure, the plurality of bit lines connected by the second group of channel pillars are located on the second surface of the stacked structure, and the common source line connected by the second group of channel pillars is located on the first surface of the stacked structure. 5. The 3D memory device of claim 1, further comprising: a substrate contiguous with the first and second surfaces, the CMOS circuit being formed on the substrate.

Preferably, the method further comprises the following steps: a connection structure through which the CMOS circuit is bonded to the first and second surfaces.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; forming a plurality of conductive lines on the first surface and the second surface of the laminated structure; and forming CMOS circuits adjacent to the first surface and a second surface of the stacked structure, wherein the plurality of conductive lines on the first surface are connected to the CMOS circuits adjacent to the first surface, and the plurality of conductive lines on the second surface are connected to the CMOS circuits adjacent to the second surface.

Preferably, the method further comprises the following steps: forming a plurality of channel pillars penetrating the stacked structure, one ends of the plurality of channel pillars being respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends being commonly connected to the common source line.

According to the 3D memory device and the manufacturing method thereof provided by the invention, the common source line and the bit line which are respectively positioned on the first surface and the second surface of the 3D memory device stacking structure are adopted, compared with single-side wiring, the wiring density can be reduced, the wiring width is increased, the parasitic resistance and the parasitic capacitance are reduced, the storage density and the access speed are improved, and therefore, the yield and the reliability of the 3D memory device are improved.

In the related art, a large number of Through Silicon Vias (TSVs) and Through Array Contacts (TACs) are used to implement double-sided wiring of a 3D memory device. Compared with the prior art, the 3D memory provided by the embodiment of the invention adopts the common source line and the bit line which are respectively positioned on the first surface and the second surface of the 3D memory device stacking structure, and the common source line and the bit line can be directly connected with an external circuit through metal wires, so that the requirements of silicon through holes and penetrating array contact parts are reduced, the manufacturing process is simplified, and the yield and the reliability of the 3D memory device are improved.

Further, in the 3D memory device, a plurality of first common source lines and a plurality of second common source lines which are respectively located at the upper side and the lower side of the 3D memory device stacked structure and are distributed in a staggered manner, and a plurality of first bit lines and a plurality of second bit lines which are respectively located at the upper side and the lower side of the 3D memory device stacked structure and are distributed in a staggered manner are adopted, so that staggered double-sided wiring can be achieved.

Further, in the 3D memory device, the CMOS circuits respectively located at the upper and lower sides of the 3D memory device are used, and the CMOS circuits at the upper and lower sides are connected to the drains at the upper and lower sides, respectively, not only is the wiring density reduced, but also the operating speed of the 3D memory device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3a and 3b respectively show cross-sectional views of a 3D memory device according to an embodiment of the present invention.

Fig. 4a to 4t show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Fig. 5 illustrates a cross-sectional view of a 3D memory device according to a first embodiment of the present invention.

Fig. 6 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the 3D memory device of the NAND structure, gate conductors of the selection transistor and the memory transistor are provided in a stacked structure, and electrical connection is provided using a large number of metal wirings. The increase in metal wiring density will not only increase the process cost and process complexity, but also create problems of short circuit, increased parasitic capacitance, increased parasitic resistance, etc. In addition, the wirings distributed on one side may cause an increase in complexity of the CMOS circuit, thereby reducing an operation speed of the 3D memory device, affecting yield and reliability of the 3D memory device.

The inventors of the present application have noticed the above-mentioned problems affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductors 121, 122, and 123. The gate conductors 121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

In this embodiment, the channel pillars include a plurality of first group channel pillars 110a and a plurality of second group channel pillars 110b which are alternately distributed, and the internal structure of the channel pillars 110a and 110b is shown in fig. 1b and will not be described in detail herein. The channel pillars 110a and 110b penetrate the gate stack structure 120 and are arranged in an array. A first common source line 103a (not shown) is located on the substrate 101 and a second common source line 103b is located over the semiconductor structure. First ends of the plurality of first group channel pillars 110a are commonly connected to the first common source line 103a, and second ends of the plurality of first group channel pillars 110a are commonly connected to the plurality of first bit lines BL 1. Second ends of the plurality of second group channel pillars 110b are commonly connected to the second common source line 103b, and first ends of the plurality of second group channel pillars 110b are commonly connected to the plurality of first bit lines BL 1.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 161. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 3).

The gate conductors 121 of memory transistors M1 and M4 are each connected to a corresponding word line. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths to be interconnected with each other, and then are connected to the same word line via the conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via respective conductive paths to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive paths.

Further, a dummy channel pillar (not shown) may be included in this embodiment, and the dummy channel pillar may have the same internal structure as the channel pillar 110 and pass through at least a portion of the gate conductor in the gate stack structure. However, the dummy channel pillar is not connected to the bit line, thereby providing only a mechanical support function, and is not used for forming the select transistor and the memory transistor. Therefore, the dummy channel pillar also does not form an effective memory cell.

Fig. 3a and 3b respectively show cross-sectional views of a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken perpendicular to the stacking direction.

As shown in fig. 3a, the second common source line 103b and the plurality of first bit lines BL1 are alternately distributed on the second surface of the stacked structure as viewed from top to bottom in the semiconductor structure in a direction perpendicular to the stacking direction. The second common source line 103b is connected to second ends of the plurality of second group channel pillars 110b, and the plurality of first word lines BL1 are connected to second ends of the plurality of first group channel pillars 110 a.

As shown in fig. 3b, the first common source line 103a and the plurality of second bit lines BL2 are alternately distributed on the first surface of the stacked structure as viewed from below in the semiconductor structure in a direction perpendicular to the stacking direction. The first common source line 103a is connected to first ends of the plurality of first group channel pillars 110a, and the plurality of second bit lines BL2 is connected to first ends of the plurality of second group channel pillars 110 b.

Fig. 4a to 4q illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

The method starts with a semiconductor structure having formed a plurality of well regions on a substrate 101, as shown in fig. 4 a. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate.

In this embodiment, in order to facilitate a program operation on a memory cell in the 3D memory device, a plurality of well regions are formed in the substrate 101. The plurality of well regions include, for example, a deep N-well 102, a high-voltage P-well 103 located in the deep N-well 102, a high-voltage N-well 105 adjacent to the high-voltage P-well 103, a P + doped region 104 located in the high-voltage P-well 103, and an N + doped region 106 located in the high-voltage N-well 105. In this embodiment, the high voltage P well 103 serves as a common source line of the channel column, the high voltage N well 105 serves to pre-charge the common source line, and the P + doped region 104 and the N + doped region 106 serve as contact regions, respectively, to reduce contact resistance. As described later, after the high voltage P well 103 is etched, the common source line 103a, which is a plurality of first group channel pillars, is located below the insulating stacked structure.

Further, a mask, for example a photoresist mask, is formed on the surface of the semiconductor structure, and then an anisotropic etch is performed to form trenches 160 in the substrate 101, as shown in fig. 4b and 4 c. In this embodiment, the anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etch time such that the etch stops near the bottom of the deep N-well 102.

Further, the photoresist mask is removed after etching by dissolving or ashing in a solvent, as shown in fig. 4 d.

Further, a first insulating region 153 is formed in the trench 160, as shown in fig. 4 e. In this embodiment, the first insulating region 153 is composed of, for example, silicon oxide.

Further, an insulating stack structure is formed on the substrate 101, as shown in fig. 4 f. The insulating stack structure includes a plurality of interlayer insulating layers 151 and a plurality of sacrificial layers 152 alternately stacked. In this embodiment, the interlayer insulating layer 151 is composed of, for example, silicon oxide, and the sacrificial layer 152 is composed of, for example, silicon nitride.

As described below, sacrificial layer 152 will be replaced with a gate conductor 122, which gate conductor 122 is further connected to a word line. To form a conductive path from the gate conductor 122 to the word line, the plurality of sacrificial layers 152 are, for example, patterned in a step shape, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, the insulating stack structure may be covered with an insulating layer. In fig. 4f, the interlayer insulating layer 151 between the plurality of sacrificial layers 152 and the interlayer insulating layer covering the insulating laminated structure are collectively shown. However, the present invention is not limited thereto, and the interlayer insulating layer between and over the plurality of sacrificial layers 152 may be formed using a plurality of independent deposition steps.

Further, a channel hole 161 is formed in the middle region (core region) of the insulation stack structure, as shown in fig. 4 g. In this embodiment, a trench hole 161 is formed in the insulating stack structure, for example, by forming a photoresist mask on the surface of the semiconductor structure and then performing anisotropic etching. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching stops near below the first common source line 103a, and the etching stops near below the first insulating region 153. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

Further, channel pillars 110 are formed in the channel holes 161, as shown in fig. 4 h. The lower portion of channel pillar 110 includes a semiconductor layer 116, semiconductor layer 116 being, for example, a silicon selective epitaxial growth layer. Further, the channel pillar 110 includes a channel layer 111 extending from an upper portion thereof to the semiconductor layer 116. As shown, in the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 sequentially stacked on the channel layer 111, and at both ends of the channel pillar 110, the channel pillar 110 includes the blocking dielectric layer 114 stacked on the channel layer 111 or the semiconductor layer 116. The lower end of the channel pillar 110 is in contact with the high voltage P-well 103 in the semiconductor substrate 101. In the final 3D memory device, the upper end of the channel pillar 110 is connected to a bit line, thereby forming an effective memory cell. The channel pillar 110 has a structure such as ONOP (oxide-nitride-oxide-polysilicon)

Further, a gate line slit 161 (see fig. 2) is formed in the insulating stack structure, the sacrificial layer 152 is removed by etching through the gate line slit 161 using the plurality of interlayer insulating layers 151 as an etch stop layer to form a cavity, and the cavity is filled with a metal layer to form the gate conductor 122, wherein the plurality of gate conductors 122 and the plurality of interlayer insulating layers 151 are alternately stacked such that the plurality of channel pillars 110 penetrate the gate stack structure, as shown in fig. 4 i.

In forming the gate line slit 161, anisotropic etching, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, or laser ablation may be used. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101.

In this embodiment, the gate line slit 161 divides the gate conductor 122 into a plurality of gate lines. For this, the gate line slit 161 penetrates the insulating laminated structure.

In forming the cavity, the sacrificial layer 152 in the insulating stacked structure is removed using isotropic etching using the gate line slit 161 as an etchant channel to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the insulating stacked layer structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor phase etching. In the etching step, the gate line slit 161 is filled with an etchant. The end portion of the sacrificial layer 152 in the insulation stack structure is exposed in the opening of the gate line slit 161, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 161 toward the inside of the insulating stacked structure. The etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the insulating stack structure due to the selectivity of the etchant.

When the gate conductor 122 is formed, the gate line slit 161 and the cavity are filled with a metal layer by Atomic Layer Deposition (ALD) using the gate line slit 161 as a deposition channel.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

In the semiconductor structure, a selection transistor and a memory transistor are formed. In the middle portion of channel pillar 110, gate conductor 122 forms a memory transistor with channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 inside channel pillar 110. At both ends of channel pillar 110, gate conductor 122 forms a select transistor together with channel layer 111 (or semiconductor layer 116) and blocking dielectric layer 114 inside channel pillar 110.

Further, a groove 162 is formed in the insulating layer above the first group of channel pillars 110a above the first common source line 103a, as shown in fig. 4 j. In this embodiment, a photoresist mask is formed on the surface of the semiconductor structure, for example, and then anisotropic etching is performed to form a recess 162 in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching stops at a distance inside the surface of the first group of channel pillars 110a above the first common source line 103 a. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

Further, a conductor layer 171a is formed in the groove 162, as shown in fig. 4 k. In this embodiment, a conductive layer 171a provides electrical connection between the channel pillar and the bit line, and the conductive layer 171a is, for example, tungsten.

Further, recesses 163 are formed over the second set of channel pillars 110b located over the first insulating region 153, as shown in fig. 4l and 4 m. In this embodiment, a photoresist mask is formed on the surface of the semiconductor structure, for example, and then anisotropic etching is performed to form a recess 163 in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time such that the etching stops at a distance inside the surface of the second set of channel pillars 110 b. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

Further, a second common source line 103b is formed in the recess 163 as shown in fig. 4 n. In this embodiment, the second common source line 103b is, for example, a high voltage p-well.

Further, a plurality of first bit lines BL1 are formed on the conductor layer 171a, and a pad 182 is formed on the second common source line 103b, second ends of the plurality of first group channel pillars 110a are commonly connected to the first bit line BL1, and an insulating material 183 is filled around the plurality of first bit lines BL1 and the second common source line 103b to fix the plurality of first bit lines BL1 and the second common source line 103b and smooth a surface of the insulating material 183, as shown in fig. 4 o. The first bit line BL1 and the pad 182 are made of Ti/TiN or W, for example, and the insulating material 183 is silicon oxide, for example. A method of smoothing the surface of the insulating material 183 is, for example, chemical mechanical polishing.

Further, the semiconductor structure is flipped and the substrate is thinned, as shown in fig. 4 p. For example, the substrate is thinned by grinding and/or etching, including dry etching or wet etching, the etching being stopped on the oxide material by controlling the etching time.

Further, a conductor layer 171b is formed over the second set of channel pillars 110b, as shown in fig. 4 q. The conductor layer 171b provides electrical connection between the channel pillar and the bit line, and the conductor layer 171 is, for example, tungsten.

Further, a plurality of second bit lines BL2 are formed on the conductor layer 171b, and a pad 182 is formed on the first common source line 103a, and first ends of the plurality of second group channel pillars 110b are commonly connected to the second bit line BL2, as shown in fig. 4 r. The second bit line BL2 and the pad 182 are composed of Ti/TiN or W, for example.

Further, a plurality of conductive vias are formed on the gate stack structure of the semiconductor structure, as shown in fig. 4 s. The plurality of conductive vias in the 3D memory device respectively include a conductive pillar 131 as a core and an insulating layer 134 as an isolation layer, the insulating layer 134 for isolating the conductive pillar 131 and a surrounding conductive material from each other. The plurality of conductive channels includes, for example, conductive channels SL1, HV 1. Conductive vias SL1 and HV1 contact P + doped region 104 and N + doped region 106, respectively, providing electrical connections between the common source line and the high voltage N-well and external circuitry.

Further, in order to facilitate a programming operation of a memory cell in the 3D memory device, in this embodiment, the 3D memory device further includes a CMOS circuit 200 for driving the selection transistor and the memory transistor, as shown in fig. 4 t. The CMOS circuit 200 is formed, for example, directly in the substrate, or directly on or over the array, or formed separately and then bonded into a semiconductor structure.

In this embodiment, the step of separately forming CMOS circuitry and then connecting to the semiconductor structure comprises: the bonding interface is formed by aligning the interconnect layer 232 of the CMOS circuit 200 with the interconnect layer 132 of the semiconductor structure and then bringing the interconnect layer 232 of the CMOS circuit 200 and the interconnect layer 132 of the semiconductor structure into contact with each other and performing a bonding process. The bonding process, for example, includes a plasma treatment process, a wet process, and/or a thermal treatment process, such that the surface of interconnect layer 232 of CMOS circuit 200 forms a physical or chemical bond with the surface of interconnect layer 132 of the semiconductor structure. In some embodiments, the interconnect layer 132 of the semiconductor structure is, for example, a silicon oxide layer, and the interconnect layer 232 of the CMOS circuit 200 is, for example, a silicon nitride layer. In some embodiments, interconnect layer 132 of the semiconductor structure and interconnect layer 232 of CMOS circuit 200 both comprise copper, for example.

Fig. 5 illustrates a cross-sectional view of a 3D memory device according to a first embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 5, the CMOS circuit 200 is, for example, located above or below the semiconductor structure, and the drains located on the upper and lower sides of the semiconductor structure are electrically connected through a plurality of conductive vias, and then bonded to an external CMOS circuit 200. In this embodiment, the drain includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2, the plurality of conductive channels respectively include conductive pillars 131 as a core and insulating layers 134 as isolation layers, the insulating layers 134 are used to isolate the conductive pillars 131 from surrounding conductive materials, and the CMOS circuit 200 can simultaneously operate a transistor having a first group of channel pillars 110a and a gate stack structure and a transistor having a second group of channel pillars 110b and a gate stack structure.

Fig. 6 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 6, the CMOS circuit 300 and the CMOS circuit 200 are, for example, respectively located above and below the semiconductor structure, and the drains located on the upper and lower sides of the semiconductor structure are connected to the CMOS circuit 300 and the CMOS circuit 200, respectively. In this embodiment, the drain includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2, the plurality of conductive channels respectively include conductive pillars 131 as a core and insulating layers 134 as isolation layers, the insulating layers 134 are used to isolate the conductive pillars 131 from surrounding conductive material, the CMOS circuit 300 controls the transistors of the first set of channel pillars 110a and the gate stack structure, and the CMOS circuit 200 controls the transistors of the second set of channel pillars 110b and the gate stack structure. The two-sided distribution of the CMOS circuits reduces the wiring density and the separate control of the two sets of CMOS circuits over the two sets of transistors further increases the operating speed of the 3D memory device.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (7)

1. A 3D memory device, comprising:

a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

a plurality of conductive lines on the first and second surfaces of the laminated structure; and

CMOS circuitry adjacent to the first and second surfaces of the stacked structure,

wherein the plurality of conductive lines at the first surface are connected to CMOS circuitry adjacent to the first surface,

the plurality of conductive lines at the second surface are connected to CMOS circuitry adjacent the second surface,

wherein the plurality of conductive lines includes a plurality of bit lines and a common source line,

the plurality of bit lines and the common source line are located on a first surface and a second surface of the stacked structure.

2. The 3D memory device of claim 1, further comprising: a plurality of channel pillars extending through the stacked structure,

one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line.

3. The 3D memory device of claim 2, wherein the plurality of channel pillars includes a first set of channel pillars and a second set of channel pillars adjacent to each other,

the plurality of bit lines to which the first set of channel pillars are connected are located on the first surface of the stacked structure, the common source line to which the first set of channel pillars are connected is located on the second surface of the stacked structure,

the plurality of bit lines to which the second group of channel pillars are connected are located on the second surface of the stacked structure, and the common source line to which the second group of channel pillars is connected is located on the first surface of the stacked structure.

4. The 3D memory device of claim 1, further comprising: a substrate contiguous with the first and second surfaces, the CMOS circuit being formed on the substrate.

5. The 3D memory device of claim 1, further comprising: a connection structure through which the CMOS circuit is bonded to the first and second surfaces.

6. A method of manufacturing a 3D memory device, comprising:

forming a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

forming a plurality of conductive lines on the first surface and the second surface of the laminated structure; and

forming CMOS circuitry adjacent the first and second surfaces of the stacked structure,

wherein the plurality of conductive lines at the first surface are connected to CMOS circuitry adjacent to the first surface,

the plurality of conductive lines at the second surface are connected to CMOS circuitry adjacent the second surface,

wherein the plurality of conductive lines includes a plurality of bit lines and a common source line,

the plurality of bit lines and the common source line are located on a first surface and a second surface of the stacked structure.

7. The manufacturing method according to claim 6, further comprising:

forming a plurality of channel pillars through the stacked structure,

one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line.

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