CN109390303B

CN109390303B - Method for manufacturing three-dimensional memory structure

Info

Publication number: CN109390303B
Application number: CN201811140658.7A
Authority: CN
Inventors: 胡斌; 肖莉红
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2022-01-04
Anticipated expiration: 2038-09-28
Also published as: CN109390303A

Abstract

Disclosed is a method of fabricating a three-dimensional memory structure, including: forming a CMOS circuit, wherein the CMOS circuit comprises a first silicon substrate and a first insulating layer positioned on the first silicon substrate, and the first insulating layer is provided with a plurality of first external bonding pads; forming a through-silicon-via penetrating the first insulating layer and the first silicon substrate, a second end of the through-silicon-via being exposed at a bottom of the first silicon substrate; forming a first wiring layer on the first insulating layer, the first end of the through-silicon via being connected to the first wiring layer and electrically connected to the first external pad via the first wiring layer; forming a memory cell array including a second silicon substrate and a second insulating layer on the second silicon substrate, the second insulating layer having a plurality of second external pads and a plurality of second wiring layers therein; and bonding the CMOS circuit and the memory cell array into a three-dimensional memory structure. The embodiment of the invention can reduce the wiring density.

Description

Method for manufacturing three-dimensional memory structure

Technical Field

The invention relates to the technical field of memories, in particular to a through silicon via process and a manufacturing method of a three-dimensional memory structure.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the aperture of a semiconductor manufacturing process becomes smaller, the memory density of a memory device becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a three-dimensional memory structure) has been developed. The three-dimensional memory structure includes a plurality of memory cells stacked in a vertical direction, can increase the integration level by a multiple on a unit area of a wafer, and can reduce the cost.

In the three-dimensional memory structure of the NAND structure, one is to form a CMOS circuit first and then form a memory cell array over the CMOS circuit. Because of the high temperature processes in the process of the memory cell array, the electrical property and the reliability of the CMOS device are greatly influenced, and the process period is longer.

Another is to form a CMOS circuit using a semiconductor substrate, form a memory cell array using a stacked structure including a gate conductor of a selection transistor and a memory transistor, and then bond the CMOS circuit over the memory cell array. In the three-dimensional memory structure, a Through Array Contact (Through Array Contact) occupies a larger chip area, so that the area of a core area is reduced, and the storage density is reduced; in addition, a large number of metal wires are used to provide electrical connection between the CMOS circuitry and the memory cell array, and the increased wire density will affect the yield and reliability of the three-dimensional memory structure.

Disclosure of Invention

In view of the foregoing problems, an object of the present invention is to provide a through silicon via process and a method for manufacturing a three-dimensional memory structure, in which a through silicon via is formed on a first wafer, a first end of the through silicon via is connected to a first metal layer on a CMOS circuit, and a second end of the through silicon via is bonded to a second metal layer of a second wafer to achieve electrical connection between the first wafer and the second wafer, thereby reducing the wiring density.

According to an aspect of the present invention, there is provided a through silicon via process, including:

providing a first wafer, wherein the first wafer comprises a first silicon substrate and a first insulating layer located on the first silicon substrate, and the first insulating layer is provided with a plurality of first metal layers; forming a through silicon via penetrating through the first insulating layer and the first silicon substrate, wherein a first end of the through silicon via is electrically connected with the first metal layer, and a second end of the through silicon via is exposed at the bottom of the first silicon substrate;

providing a second wafer, wherein the second wafer comprises a second silicon substrate and a second insulating layer located on the second silicon substrate, and the second insulating layer is provided with a plurality of second metal layers;

and bonding the first wafer to the second wafer, wherein the first silicon substrate and the second insulating layer are in contact with each other, and the silicon through hole is bonded with the second metal layer, so that the first wafer and the second wafer are electrically connected.

Preferably, the forming of the through-silicon via penetrating the first insulating layer and the first silicon substrate includes:

etching the first insulating layer at the periphery of the first metal layer to form a groove, wherein the groove extends to the inside of the first silicon substrate;

and depositing a glue layer and/or a barrier layer and a metal layer in the groove in sequence.

Preferably, the forming of the through-silicon via penetrating the first insulating layer and the first silicon substrate further includes:

electrically connecting a first end of the through-silicon via with the first external pad.

and after the first wafer is turned over, thinning the first silicon substrate to expose the second end of the through silicon via.

Preferably, the first wafer further includes a first wiring layer, the second wafer includes a second wiring layer, and the first wiring layer and the second wiring layer extend laterally.

Preferably, the through-silicon via is electrically connected to the first metal layer through a first wiring layer.

According to another aspect of the present invention, there is provided a method of fabricating a three-dimensional memory structure, including:

forming a CMOS circuit comprising a first silicon substrate and a first insulating layer on the first silicon substrate, the first insulating layer having a plurality of first external pads therein;

forming a through-silicon-via penetrating through the first insulating layer and the first silicon substrate, a first end of the through-silicon-via being electrically connected with the first external pad, and a second end being exposed at the bottom of the first silicon substrate;

forming a memory cell array including a second silicon substrate and a second insulating layer on the second silicon substrate, the second insulating layer having a plurality of second external pads therein;

and bonding the CMOS circuit and the memory cell array into the three-dimensional memory structure, wherein the first silicon substrate of the CMOS circuit and the second insulating layer of the memory cell array are in contact with each other, and the through silicon via and the second external pad are bonded with each other, so that the CMOS circuit and the memory cell array are electrically connected.

etching the first insulating layer to form a groove, wherein the groove extends to the inside of the first silicon substrate;

depositing a glue layer and/or a barrier layer and a metal layer in the groove in sequence;

electrically connecting a first end of the through-silicon-via with the first external pad;

and thinning the first silicon substrate to expose the second end of the through silicon via.

Preferably, the step of forming the CMOS circuit further comprises:

forming a plurality of transistors in the first silicon substrate;

forming a plurality of contact pads connected to the plurality of transistors in the second insulating layer;

wherein the first outer pad and the first conductive via are located in the first insulating layer;

the plurality of contact pads are connected to the respective through-silicon vias via the plurality of first outer pads and the plurality of first conductive vias.

Preferably, the step of forming the memory cell array further comprises:

forming a common source region in the second silicon substrate;

forming a gate stack structure on the second silicon substrate, the gate stack structure comprising a plurality of levels of gate conductors;

forming a plurality of channel columns penetrating through the gate stack structure;

forming a plurality of contact pads on the gate stack structure; and

covering a second insulating layer on the gate level structure;

wherein first ends of the plurality of channel pillars extend to the common source region and second ends are connected to respective contact pads,

the gate conductors of the multiple layers are respectively connected to corresponding contact pads;

the second outer pad and the second conductive via are in the second insulating layer.

According to the through silicon via process and the manufacturing method of the three-dimensional memory structure, the silicon through hole is formed on the first wafer, the first end of the silicon through hole is connected with the first metal layer on the CMOS circuit, and the second end of the silicon through hole is bonded with the second metal layer of the second wafer so as to achieve electric connection between the first wafer and the second wafer. The first wafer is a CMOS circuit, and the second wafer is a memory cell array. The three-dimensional memory structure does not need a Through Array Contact (TAC) structure, so that the area of a memory cell array is saved, and the memory density is improved; in addition, wiring is performed on both sides of the CMOS circuit, reducing wiring density.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIGS. 1a and 1b show a circuit diagram and a structural schematic, respectively, of a memory cell string of a three-dimensional memory structure;

FIGS. 2a and 2b show perspective and overall perspective views, respectively, of the internal structure of a three-dimensional memory structure according to an embodiment of the invention;

FIG. 3 illustrates a cross-sectional view of a three-dimensional memory structure according to an embodiment of the invention;

fig. 4a to 4i show cross-sectional views of various stages of a method of fabricating a three-dimensional memory structure according to an embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The term "above" as used herein means above the plane of the substrate, and may refer to direct contact between materials or spaced apart.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

In the embodiment of the invention, the CMOS circuit and the memory cell array are wafer chips, and the external bonding pad, the contact bonding pad and the like are metal layers. The CMOS circuit is a first wafer, the memory cell array is a second wafer, the first external bonding pad is a first metal layer, and the second external bonding pad is a second metal layer.

Fig. 1a and 1b show a circuit diagram and a schematic structural diagram, respectively, of a memory cell string of a three-dimensional memory structure. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory cells M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of memory cells M1-M4 are connected to corresponding ones of word lines WL 1-WL 4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include the second conductor layer 122 and the third conductor layer 123, respectively, and the memory cells M1 to M4 include the first conductor layer 121, respectively. The first, second, and third conductor layers 121, 122, and 123 are stacked in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent conductor layers are separated from each other by an insulating layer, thereby forming a gate stack structure.

Further, the memory cell string 100 includes a memory string 110. The memory string 110 is adjacent to or through the gate stack structure. In the middle portion of the memory string 110, the first conductor layer 121 and the channel layer 111 sandwich the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114, thereby forming memory cells M1 through M4. At both ends of the memory string 110, the gate dielectric layer 114 is sandwiched between the second conductor layers 122 and 123 and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

The channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the first conductor layer 121, the second conductor layer 122, and the third conductor layer 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of memory string 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of the memory string 110 is an additional insulating layer, and the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory cells M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the memory string 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory cells M1 to M4, respectively, may be formed in separate steps from each other. In the memory string 110, semiconductor layers of the first and second selection transistors Q1 and Q2 and semiconductor layers of the memory cells M1 to M4 are electrically connected to each other.

In a write operation, memory cell string 100 writes data to a selected memory cell of memory cells M1-M4 using FN tunneling efficiency. Taking the memory cell M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the second selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since the word line voltage of only the selected memory cell M2 is higher than the tunneling voltage, electrons in the channel region of the memory cell M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory cell M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer according to the on-state of a selected one of the memory cells M1 through M4, thereby obtaining data indicative of the amount of charge. Taking cell M2 as an example, word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory cell M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory cell M2. The memory cells M1, M3 and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory cell M2. The control circuit determines the conductive state of the memory cell M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory cell M2.

Fig. 2a and 2b illustrate a perspective view and an overall perspective view of an internal structure of a three-dimensional memory structure according to an embodiment of the present invention, respectively, and fig. 3 illustrates a cross-sectional view of a three-dimensional memory structure according to an embodiment of the present invention.

For the sake of clarity, only the internal structure of the three-dimensional memory structure is shown in fig. 2a, wherein the semiconductor substrate of the memory cell array and the CMOS circuitry and insulating layers in the memory cell array are not shown, and only the external structure of the 3D memory is shown in fig. 2 b.

The three-dimensional memory structure 200 shown in this embodiment includes CMOS circuitry 210 and a memory cell array 220, the CMOS circuitry 210 being stacked above the memory cell array 220.

The CMOS circuit 210 includes a first silicon substrate 201, a plurality of contact pads 261 on the first silicon substrate 201, a plurality of first wiring layers 263 on the plurality of contact pads 261, a plurality of first outer pads 264 on the plurality of first wiring layers 263, and conductive vias 262 providing interconnection in a direction perpendicular to a surface of the first silicon substrate 201. In the present embodiment, the first insulating layer 202 is an interlayer insulating layer. Although not shown, it is understood that a plurality of transistors are formed in the first silicon substrate 201. The plurality of first wiring layers 263 are spaced apart from each other, and the plurality of first wiring layers 263 and the contact pads 261 and the first outer pads 264 are spaced apart from each other with an interlayer insulating layer, and are electrically connected to each other with conductive vias 262 penetrating the interlayer insulating layer. The interlayer insulating layer is not shown in fig. 2 a.

The CMOS circuit 210 further includes a through-silicon-via 265 penetrating the first insulating layer 202 and the first silicon substrate 201, a first end of the through-silicon-via 265 being electrically connected to the first external pad 264, and a second end being exposed at a bottom of the first silicon substrate 201.

In the CMOS circuit 210, a contact pad 261 is electrically connected to a transistor in the first silicon substrate 201, the contact pad 261 being connected to a first wiring layer 263 via a conductive via 262 and then connected to a first external pad 264 via the conductive via 262; the first outer pad 264 is connected to the through-silicon via 265 via the via 262 and the first wiring layer 263. The through silicon vias 265 provide electrical connections between the transistors within the CMOS circuit 210 and the memory cell array 220.

The memory cell array 220 includes 4 × 3 and 12 memory cell strings, each including 4 memory cells, thereby forming a memory array having 48 memory cells in total, 4 × 3. It is to be understood that the present invention is not limited thereto and that the three-dimensional memory structure may include any number of memory cell strings, for example, 1024, and that the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

The memory cell array 220 includes a second silicon substrate 101, a gate stack structure on the second silicon substrate 101, a channel pillar 110 penetrating the gate stack structure, and an interconnect structure on the gate stack structure. The interconnect structure includes a plurality of second conductive vias 161, a plurality of contact pads 162 that are in contact with the plurality of second conductive vias 161, respectively, a plurality of second wiring layers 164 on the plurality of contact pads 162, a plurality of second external pads 165 on the plurality of second wiring layers 164, and conductive vias 163 that provide interconnections in a direction perpendicular to the surface of the second silicon substrate 101. The gate stack structure includes, for example,

gate conductors

121, 122, and 123. The plurality of gate conductors in the gate stack structure are, for example, stepped to provide space for the second conductive path 161 to extend to reach the respective gate conductor.

In the memory cell array 220, the memory cell strings respectively include the respective channel pillars 110, and the

common gate conductors

121, 122, and 123. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. The interlayer insulating layer is not shown in fig. 2 a.

In this embodiment, the internal structure of the trench pillar 110 is shown in fig. 1b, and will not be described in detail. The channel pillars 110 penetrate the gate stack structure and are arranged in an array. The semiconductor substrate is located above the gate stack structure, wherein a common source region (not shown) is formed. First ends of the channel pillars 110 are commonly connected to the common source region, and second ends of the channel pillars 110 are connected to the respective second external pads 165 via conductive paths and wirings. The conductive channel and the wiring layer here function as the bit line BL.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 151. The gate lines of the plurality of channel pillars 110 of the same row are connected to the corresponding second external pads 165 via conductive channels and wirings, respectively. For clarity, a portion of the conductive vias and wiring layers between the gate conductor 122 and the contact pad are not shown in the figures. The conductive vias and wiring layers here function the same as the string select lines SSL.

The gate conductors 121 of memory transistors M1 and M4 are each connected to a corresponding word line. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 151, the gate lines of the same layer are connected to the corresponding second external pads 165 via conductive channels and wirings, respectively. For clarity, a portion of the conductive path and wiring layers between the gate conductor 121 and the contact pad are not shown in the figures. The conductive paths and wiring layers here function the same as the word lines WL1 to WL 4.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 151, the gate lines are connected to the corresponding second external pads 165 via conductive paths and wirings, respectively. The conductive vias and wiring layers here function the same as the ground select lines GSL.

Preferably, a dummy channel pillar 130 may be further included in this embodiment, and the dummy channel pillar 130 may have the same inner structure as the channel pillar 110 and pass through at least a portion of the gate conductor in the gate stack structure. However, the dummy channel pillar 130 is not connected to the second external pad 165, thereby providing only a mechanical supporting function, and is not used for forming the select transistor and the memory transistor. Therefore, the dummy channel pillar 130 does not form an effective memory cell.

Preferably, the conductive via 141 and the insulating liner 142 may be further included in this embodiment, and are insulated from each other by the insulating liner 142 from the gate stack structure. A conductive via 141 has a first end extending into the semiconductor substrate above the gate stack to the common source region and a second end connected to the wiring layer. The conductive path and the wiring layer here function as the source line GL.

After the CMOS circuitry 210 and the memory cell array 220 are formed, they are bonded to each other into the three-dimensional memory structure 200. Referring to fig. 2b, according to the three-dimensional memory structure 200 of this embodiment, the conductive vias and wiring layers of the CMOS circuit 210 are located in at least one first insulating layer 202, and the conductive vias and wiring layers of the memory cell array 220 are located in at least one second insulating layer 102. The bonding surfaces of the CMOS circuit 210 and the memory cell array 220 are surfaces of the first silicon substrate 201 and the second insulating layer 102, respectively, which are opposite to each other. Further, the through-silicon via 265 of the CMOS circuit 210 and the second external pad 165 of the memory cell array 220 are exposed on the respective bonding surfaces, respectively, and are disposed opposite to each other. Accordingly, when the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the three-dimensional memory structure 200, the through-silicon via 265 of the CMOS circuit 210 and the second external pad 165 of the memory cell array 220 contact each other, thereby achieving electrical connection between the CMOS circuit 210 and the memory cell array 220. A large number of wires of the CMOS circuit 210 and the memory cell array 220 are located near the respective bonding surfaces.

Fig. 4a to 4g show cross-sectional views of stages of a method of fabricating a three-dimensional memory structure according to an embodiment of the present invention, wherein fig. 4a to 4e show fabrication steps of a CMOS circuit, fig. 4f and 4h show fabrication steps of a memory cell array, and fig. 4i shows bonding of a CMOS to the memory cell array. The cross-sectional view is taken along line AA in fig. 2 a.

The method starts with a semiconductor structure in which transistors (not shown) of a CMOS circuit have been formed in a first silicon substrate 201, in this embodiment the first silicon substrate 201 is, for example, a monocrystalline silicon substrate. To form a transistor, a plurality of doped regions are formed in the first silicon substrate 201. For example, the first silicon substrate 201 includes source and drain regions of a plurality of transistors.

As shown in fig. 4a, an interconnect structure is formed on the first silicon substrate 201.

The semiconductor structure formed at this step is a CMOS circuit 210 in which the doped regions of a plurality of transistors formed in the first silicon substrate 201 provide external electrical connections via an interconnect structure.

The interconnect structure includes a plurality of contact pads 261 on the first silicon substrate 201, a plurality of routing layers 263 on the plurality of contact pads 261, a plurality of first outer pads 264 on the plurality of routing layers 263, and conductive vias 262 providing interconnections in a direction perpendicular to the surface of the first silicon substrate 201. The plurality of first wiring layers 263 are separated from each other, and the plurality of first wiring layers 263 and the contact pads 261 and the first outer pads 264 are separated from each other with the first insulating layer 202, and are electrically connected to each other with the conductive vias 262 in the first insulating layer 202.

As shown in fig. 4b, a recess 266 is formed in the CMOS circuit 210 through the first insulating layer 202 and extending into the interior of the first silicon substrate 201.

In this step, for example, a photoresist mask is formed on the surface of the first insulating layer 202, and then anisotropic etching is performed to form a groove 266 in the first insulating layer 202. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching stops at a distance inside the surface of the first insulating layer 202. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

As shown in fig. 4c, a glue layer and/or barrier layer and a metal layer are sequentially deposited within recess 266 to form a through-silicon-via 265.

In this embodiment, the glue layer is, for example, made of Ti/TiN. Barrier layer 265a is, for example, comprised of Ti/TiN. The metal layer 265b is made of tungsten, for example. The metal layer is deposited by Atomic Layer Deposition (ALD) using a precursor such as tungsten hexafluoride WF6 and a reducing gas such as silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

As shown in fig. 4d, a first end of the through-silicon via 265 is electrically connected to a first external pad 264.

Specifically, a first wiring layer 263 is formed on the first insulating layer 202 so that the through-silicon via 265 is electrically connected to the first outer pad 264, and a protective layer is covered over the first wiring layer 263.

As shown in fig. 4e, the first silicon substrate 201 of the CMOS circuit 210 is thinned to expose the second end of the through-silicon via 265.

Specifically, the CMOS circuit 210 is turned over, and then the first silicon substrate 201 is subjected to thinning processing.

As shown in fig. 4f, a plurality of well regions are formed in the second silicon substrate 101, and an insulating stack structure is formed on the second silicon substrate 101.

To facilitate a programming operation of memory cells in the three-dimensional memory structure, a plurality of well regions are formed in the second silicon substrate 101. For example, the second silicon substrate 101 includes a common source region of a plurality of channel pillars.

The insulating stack structure includes a plurality of sacrificial layers 152 stacked, with adjacent sacrificial layers 152 separated from each other by a second insulating layer 102. In this embodiment, the second insulating layer 102 is composed of, for example, silicon oxide, and the sacrificial layer 152 is composed of, for example, silicon nitride.

As described below, sacrificial layer 152 is replaced with gate conductors 121-123, gate conductor 121 being connected to the string select line in one step, gate conductor 123 being connected to the ground select line in one step, and gate conductor 122 being connected to the word line in one step. To form a conductive path from the gate conductors 121 to 123 to the word lines, the plurality of sacrificial layers 152 are, for example, patterned in a step shape, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, the insulating stack structure may be covered with an insulating layer. An interlayer insulating layer between the plurality of sacrificial layers 152 and an interlayer insulating layer covering the insulating laminated structure are collectively shown as a second insulating layer 102 in fig. 4 a. However, the present invention is not limited thereto, and a plurality of interlayer insulating layers between and over the plurality of sacrificial layers 152 may be formed using a plurality of independent deposition steps.

Further, a channel hole is formed in the insulating laminated structure. In this embodiment, a trench hole is formed in the insulating stack structure, for example, by forming a photoresist mask on the surface of the semiconductor structure and then performing anisotropic etching. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time such that the etching stops near below the common source region and the etching stops near below the first insulating region. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

Further, a channel pillar 110 is formed in the channel hole. The lower portion of the channel pillar 110 includes a semiconductor layer. Further, the channel pillar 110 includes a channel layer extending from an upper portion thereof to the semiconductor layer. For clarity, the internal structure of the channel pillar 110 is not shown in fig. 4 a. Referring to fig. 1b, in the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially stacked on the channel layer, and at both ends of the channel pillar 110, the channel pillar 110 includes a blocking dielectric layer stacked on the channel layer or the semiconductor layer. The lower end of the channel pillar 110 is in contact with a common source region in the second silicon substrate 101. In the final three-dimensional memory structure, the upper end of the trench pillar 110 is connected to a wiring layer, thereby forming an effective memory cell. The channel pillar 110 is, for example, ONOP (oxide-nitride-oxide-polysilicon).

Preferably, dummy channel pillars 130 are formed in the channel holes. Dummy channel pillar 130 may be identical in internal structure to channel pillar 110 and may pass through at least a portion of the gate conductor in the gate stack structure. However, in the final three-dimensional memory structure, the upper ends of the dummy channel pillars 130 are not connected to the wiring layer, thereby providing only a mechanical supporting function without being used for forming the selection transistors and the memory transistors.

Preferably, a through hole is formed in the insulating stacked structure, and the conductive via 141 and the insulating liner 142 are formed in the through hole. The conductive vias 141 pass through the insulating stack and are separated from the insulating stack by an insulating liner 142. One end of the conductive via 141 extends into the second silicon substrate 101 under the insulating stacked structure to reach the common source region, and the other end is to be connected to the wiring layer.

As shown in fig. 4g, in the insulating stack structure, the sacrificial layer 152 is replaced with the gate conductors 121 to 123 to form a gate stack structure.

In this step, a gate line slit 151 (see fig. 2a) is formed in the insulating stack structure, the sacrificial layer 152 is removed by etching through the gate line slit 151 using the second insulating layer 102 as an etch stop layer to form a cavity, and the cavity is filled with a metal layer to form gate conductors 121 to 123, wherein the plurality of gate conductors 121 to 123 and the second insulating layer 102 are alternately stacked. Accordingly, a plurality of channel pillars 110 penetrate the gate stack structure.

In forming the gate line slit 151, anisotropic etching, for example, dry etching such as ion mill etching, plasma etching, reactive ion etching, or laser ablation may be used. For example, by controlling the etching time so that the etching is stopped near the surface of the second silicon substrate 101. In this embodiment, the gate line slit 151 divides the gate conductors 121 to 123 into a plurality of gate lines.

In forming the cavity, the sacrificial layer 152 in the insulating stacked structure is removed using isotropic etching using the gate line slit 151 as an etchant path to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the second insulating layer 102 and the sacrificial layer 152 in the insulating stacked structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor phase etching. In the etching step, the gate line gap 151 is filled with an etchant. The end portion of the sacrificial layer 152 in the insulation stack structure is exposed in the opening of the gate line slit 151, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 151 toward the inside of the insulating stacked structure. The etching removes the sacrificial layer 152 with respect to the second insulating layer 102 in the insulating stack structure due to the selectivity of the etchant.

In forming the gate conductors 121 to 123, the gate line slit 151 and the cavity are filled with a metal layer using Atomic Layer Deposition (ALD) using the gate line slit 151 as a deposition path.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

Above the gate stack structure, an interconnect structure is formed, as shown in fig. 4 h.

The interconnect structure includes a plurality of conductive vias 161 located above the gate stack structure, a plurality of contact pads 162 respectively contacting the plurality of conductive vias 161, a plurality of wiring layers 164 located on the plurality of contact pads 162, a plurality of external pads 165 located on the plurality of wiring layers 164, and conductive vias 163 providing interconnections in a direction perpendicular to the surface of the second silicon substrate 101.

The semiconductor structure formed at this step is a memory cell array 220 in which the gate stack structure together with the channel pillar forms a select transistor and a memory transistor. In the middle portion of the channel pillar 110, the gate conductors 121 to 123 form a memory transistor together with the channel layer, the tunneling dielectric layer, the charge storage layer, and the blocking dielectric layer inside the channel pillar 110. At both ends of the channel pillar 110, gate conductors 121 to 123 form a selection transistor together with a channel layer (or a semiconductor layer) and a blocking dielectric layer inside the channel pillar 110.

The

gate conductors

121, 122 and 123 in the gate stack structure are, for example, stepped to provide space for the conductive vias 161 to extend to reach the respective gate conductors. The conductive vias and wiring layers of the memory cell array 220 are located in the at least one second insulating layer 102. As described above, the second insulating layer 102 is shown as a single layer in the drawing, however, the second insulating layer 102 may actually be composed of a plurality of interlayer insulating layers including a plurality of interlayer insulating layers for separating the

gate conductors

121, 122, and 123 and a plurality of interlayer insulating layers for separating different wiring layers. In addition, the contact pad 162 and the external pad 165 may also be located on a separate interlayer insulating layer.

Further, the first ends of the channel pillars 110 are commonly connected to a common source region in the second silicon substrate 101, and the second ends of the channel pillars 110 are connected to the contact pads 162 via conductive paths 161 and then connected to the corresponding external pads 165 via conductive paths and wirings. The conductive vias 141 extend to a common source region in the second silicon substrate 101 at a first end and are connected to contact pads 162 via conductive vias 161 and then to corresponding external pads 165 via conductive vias and wiring.

The bonding surface of the memory cell array 220 is a first surface of the second insulating layer 102. In this step, the first surface is an exposed free surface. The contact surface of the external pad 165 is exposed on the first surface.

As shown in fig. 4i, the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the three-dimensional memory structure 200.

When the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the three-dimensional memory structure 200, the through-silicon via 265 of the CMOS circuit 210 and the external pad 165 of the memory cell array 220 contact each other, thereby achieving electrical connection between the CMOS circuit 210 and the memory cell array 220.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, certain steps are not required and thus may be omitted or replaced with other steps.

The semiconductor structure formed by the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory device.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of fabricating a three-dimensional memory structure, comprising:

forming a through-silicon-via penetrating the first insulating layer and the first silicon substrate;

forming a first wiring layer on the first insulating layer, a first end of the through-silicon via being connected to the first wiring layer and electrically connected to the first external pad via the first wiring layer, a second end of the through-silicon via being exposed at a bottom of the first silicon substrate;

forming a memory cell array including a second silicon substrate and a second insulating layer on the second silicon substrate, the second insulating layer having a plurality of second external pads and a plurality of second wiring layers therein; and

bonding the CMOS circuit and the memory cell array into the three-dimensional memory structure, wherein the first silicon substrate of the CMOS circuit and the second insulating layer of the memory cell array are in contact with each other, and the second end of the through silicon via and the second external pad are bonded with each other, so that the CMOS circuit and the memory cell array are electrically connected;

the through silicon vias are located on two sides of the CMOS circuit, the first wiring layer and the second wiring layer extend transversely, and the first wiring layer is covered with a protection layer.

2. The method of claim 1, wherein forming a through-silicon-via through the first insulating layer and the first silicon substrate comprises:

3. The method of claim 2, wherein forming a through-silicon-via through the first insulating layer and the first silicon substrate further comprises:

and after the CMOS circuit is turned over, thinning the first silicon substrate to expose the second end of the through silicon via.

4. The method of claim 1, wherein the step of forming the CMOS circuit further comprises:

forming a plurality of transistors in the first silicon substrate;

forming a plurality of contact pads connected to the plurality of transistors in the first insulating layer;

wherein the first outer pad and first conductive via are located in the first insulating layer;

the plurality of contact pads are connected to the respective through-silicon vias via the plurality of first outer pads and the plurality of first conductive vias and the first wiring layer.

5. The method of claim 1, wherein the step of forming the memory cell array further comprises:

forming a common source region in the second silicon substrate;

forming a plurality of contact pads on the gate stack structure; and

covering a second insulating layer on the gate stack structure;

the second outer pad and second conductive via are in the second insulating layer.