CN109390349B

CN109390349B - 3D memory device and method of manufacturing the same

Info

Publication number: CN109390349B
Application number: CN201811242026.1A
Authority: CN
Inventors: 吴林春; 蒲月强; 刘藩东; 华文宇; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-10-24
Filing date: 2018-10-24
Publication date: 2020-11-13
Anticipated expiration: 2038-10-24
Also published as: CN109390349A

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a semiconductor substrate; a gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked, over the semiconductor substrate; and a plurality of channel pillars penetrating the gate stack structure, the channel pillars including: the epitaxial layer is positioned at the bottom of the channel column and is in contact with the semiconductor substrate; the protective layer is positioned above the epitaxial layer and is in contact with the epitaxial layer; and the channel layer is positioned above the protective layer and is in contact with the protective layer. According to the 3D memory device, the protective layer is arranged above the epitaxial layer to serve as the etching stop layer, the epitaxial layer is protected by the protective layer and cannot be removed, and therefore the breakdown voltage of the 3D memory device is improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to a memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In the 3D memory device with the NAND structure, the 3D memory device mainly comprises a gate stack structure, a channel column penetrating through the gate stack structure and a conductive channel, wherein the gate stack structure is used for providing gate conductors of a selection transistor and a storage transistor, the channel column is used for providing channel layers and gate dielectric stacks of the selection transistor and the storage transistor, and the conductive channel is used for realizing interconnection of memory cell strings. However, for the channel column with a large size, when the channel layer is in contact with the epitaxial layer, a part of the epitaxial layer may be removed, which results in non-uniform thickness of the surface of the epitaxial layer from the sidewall of the epitaxial layer, and the thickness of the epitaxial layer near the gate conductor portion is very thin.

It is desirable to further improve the structure of the 3D memory device and the method of fabricating the same so as to improve the reliability of the 3D memory device.

Disclosure of Invention

An object of the present invention is to provide an improved 3D memory device and a method of manufacturing the same, in which an epitaxial layer is protected from being removed by providing a protective layer as an etch stop layer over the epitaxial layer, thereby improving the breakdown voltage of the 3D memory device.

According to an aspect of the present invention, there is provided a 3D memory device including: a semiconductor substrate; a gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked over the semiconductor substrate; and a plurality of channel pillars penetrating the gate stack structure, the channel pillars comprising: the epitaxial layer is positioned at the bottom of the channel column and is in contact with the semiconductor substrate; the protective layer is positioned on the upper surface of the epitaxial layer, is in contact with the epitaxial layer and is used for protecting the epitaxial layer; and a channel layer over and in contact with the protective layer.

Preferably, the channel pillar further includes a contact layer on a sidewall of the channel pillar and in contact with the protective layer.

Preferably, the material of the protective layer comprises a metal.

Preferably, the epitaxial layer comprises contact regions, which are located at two sides of the epitaxial layer, and the gate conductor close to the semiconductor substrate is in contact with the contact regions.

Preferably, the other of said gate conductors is in contact with said contact layer.

Preferably, the gate stack structure has: a core region; and a step region surrounding the core region.

Preferably, some of the channel pillars are located in the core region, and the other channel pillars are located in the step region.

Preferably, the size of the channel pillar located in the step region is larger than the size of the channel pillar located in the core region.

Preferably, the semiconductor substrate includes a peripheral circuit.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a gate stack structure on a semiconductor substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; and forming a plurality of channel pillars penetrating through the gate stack structure, the step of forming the channel pillars comprising: forming a plurality of channel holes through the gate stack structure and a portion of the semiconductor substrate; forming an epitaxial layer at the bottom of the channel hole, wherein the epitaxial layer is in contact with the semiconductor substrate; and forming a protective layer at the bottom and the side wall of the channel hole, wherein the protective layer is positioned above the epitaxial layer and is in contact with the epitaxial layer, and the protective layer is used as an etching stop layer.

Preferably, after the protective layer is formed, the step of forming the channel pillar further includes covering the bottom and the sidewall of the channel hole, and sequentially forming a blocking dielectric layer, a charge storage layer, a tunneling dielectric layer, and a channel layer.

Preferably, after forming the channel layer, the step of forming the channel pillar further includes etching the channel layer, the tunneling dielectric layer, the charge storage layer, and the blocking dielectric layer at the bottom of the channel hole to expose a portion of the protective layer, wherein the etching is stopped when the protective layer is reached.

Preferably, after exposing a portion of the protective layer, the step of forming the channel pillar further includes reforming the channel layer over the protective layer, the channel layer being in contact with the protective layer.

Preferably, the step of forming the gate stack structure comprises: forming an insulating laminated structure on the semiconductor substrate, wherein the insulating laminated structure comprises a plurality of interlayer insulating layers and a plurality of sacrificial layers which are alternately stacked; patterning the plurality of sacrificial layers to be step-shaped; replacing the plurality of sacrificial layers with a plurality of gate conductors to form the insulating stack structure.

Preferably, before forming the plurality of gate conductors, the step of forming the gate stack structure further includes removing the plurality of sacrificial layers to form a plurality of cavities exposing portions of the protective layer and portions of the epitaxial layer, wherein the protective layer exposed in the cavities is oxidized to form a contact layer and the epitaxial layer exposed in the cavities is oxidized to form a contact region.

Preferably, the gate conductor near the semiconductor substrate is in contact with the contact region, and the other gate conductors are in contact with the contact region.

Preferably, after the plurality of sacrificial layers are replaced by the plurality of gate conductors, the plurality of gate conductors are stepped to form a stepped region of the gate stack structure, and the stepped region surrounds a core region.

Preferably, some of the channel pillars are located in the core region, and other channel pillars are located in the step region.

Preferably, the material of the protective layer comprises a metal.

According to the 3D memory device and the manufacturing method thereof, the protective layer is arranged above the epitaxial layer to serve as the etching stop layer, the epitaxial layer is protected by the protective layer and cannot be removed, and when the channel layer is formed above the protective layer, the channel layer is uniformly distributed on the protective layer and is in contact with the epitaxial layer through the protective layer, so that the breakdown voltage of the 3D memory device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3 to 15 show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Fig. 16a, 16b show schematic diagrams of effect analysis of a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a Bit Line (BL), and a second terminal is connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The Gate of the first select transistor Q1 is connected to a string select line (SGD), and the Gate of the second select transistor Q2 is connected to a Source select line (SGS). The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.

As shown in fig. 1b, the select transistors Q1 and Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 through M4 include 4 gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a first channel pillar 110. The first channel pillar 110 is adjacent to or extends through the gate stack structure. In the middle portion of the first channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the

gate conductors

122 and 123 and the channel layer 111 at both ends of the first channel column 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the first channel pillar 110 is a channel layer 111, and the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure surrounding the sidewall of the core. In an alternative embodiment, the core of the first channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the first channel column 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the first channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling. Taking memory transistor M2 as an example, while the source line SL is grounded, the source select line SGS is biased to approximately zero volts such that select transistor Q2 corresponding to source select line SGS is turned off, and the string select line SGD is biased to a high voltage VDD such that select transistor Q1 corresponding to string select line SGD is turned on. Further, the bit line BL is grounded, the word line WL2 is biased at the programming voltage VPG, e.g. around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2. The 3D memory device shown in this embodiment includes 4 x 4 and 16 memory cell strings 100 in total, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a to 2, in the 3D memory device, memory cell strings respectively include respective first channel pillars 110, and

common gate conductors

121, 122, and 123. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in fig. 2.

The gate stack structure 120 is stepped and has a core region and a step region surrounding the core region. The first channel pillar 110 is located in the core region, and the dummy channel pillar 130 is located in the step region. The dummy channel pillar 130 located at the stepped region has a size greater than that of the first channel pillar 110 located at the core region.

The internal structure of the first channel pillar 110 and the dummy channel pillar 130 is shown in fig. 1b, and will not be described in detail. In the middle portion of the first channel pillar 110, the gate conductor 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the first channel pillar 110. At both ends of the first channel column 110,

gate conductors

122 and 123 form select transistors Q1 and Q2, along with the channel layer 111 and gate dielectric layer 114 inside the first channel column 110.

The first channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, first ends of a plurality of first channel pillars 110 in a same column are commonly connected to a same bit line, second ends are commonly connected to the substrate 101, and the second ends form a common source connection through the substrate 100.

The gate conductor 122 of the string selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit). The gate lines of the plurality of first channel pillars 110 in the same row are commonly connected to the same string selection line.

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit, the gate lines of the same level reach the interconnection layer via respective conductive paths to be interconnected with each other, and then are connected to the same word line via the conductive paths.

The gate conductors of the source select transistors Q2 are connected in one piece. If the gate conductor 123 of the source select transistor Q2 is divided into different gate lines by the gate line slit, the gate lines reach the interconnect layer via respective conductive channels to be interconnected with each other, and then are connected to the same source select line SGS via the conductive channels.

Peripheral circuits, such as CMOS circuits, are preferably included in the substrate semiconductor substrate 101. Conductive vias are used to provide electrical connections between the CMOS circuitry and external circuitry.

Fig. 3 to 15 are sectional views illustrating stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention, wherein fig. 3 to 11, 13, and 15 are sectional views taken along line a-a of fig. 2, and fig. 12 and 14 are sectional views taken along line B-B of fig. 2. The method of fabricating the memory structure of the invention will be described in detail with reference to fig. 3 to 15.

The method of fabricating the 3D memory device of the present embodiment starts with a semiconductor substrate 101, and forms an insulating stack structure 130 on the semiconductor substrate 101, as shown in fig. 3.

In this step, an interlayer insulating layer 131 and a sacrificial layer 132 may be stacked on the semiconductor substrate 101 using a deposition process, wherein the material of the interlayer insulating layer 131 is selected from oxide, and the material of the sacrificial layer 132 is selected from nitride, such as silicon nitride.

Further, the insulating stack structure 130 is patterned to step the insulating stack structure 130, as shown in fig. 4.

In this step, the insulating stacked structure may be etched using an etching process such that the sizes of the sacrificial layer 132 and the interlayer insulating layer 131 are sequentially decreased from the semiconductor substrate 101 upward, thereby forming the core region 10 and the step region 20 surrounding the core region 10.

Further, a dielectric layer 133 is formed overlying the insulating stack structure 130, as shown in fig. 5.

Further, a plurality of first channel holes 102 and a plurality of second channel holes 103 are formed through the dielectric layer 133, the insulating stacked structure 130 and a portion of the semiconductor substrate 101, and a first epitaxial layer 115 and a second epitaxial layer 115' are formed at the bottom of the first channel holes 102 and the bottom of the plurality of second channel holes 103, respectively, as shown in fig. 6.

In this step, a plurality of first channel holes 102 and a plurality of second channel holes 103, and a first epitaxial layer 115 and a second epitaxial layer 115' may be formed by using an etching process and a deposition process, wherein the first channel holes 102 are located in the core region, the second channel holes 103 are located in the step region, and the size of the second channel holes 103 is larger than that of the first channel holes 102.

Due to the larger size of the second channel hole 103, the second epitaxial layer 115 'is located at a deeper depth in the semiconductor substrate 101, and the second epitaxial layer 115' facilitates formation of the void 104 at the sidewall of the second channel hole 103 at the semiconductor substrate 101.

Further, a first passivation layer 116 and a second passivation layer 116' are formed to cover the bottom and the sidewall of the first channel hole 102 and the second channel hole 103, respectively, as shown in fig. 7.

In this step, the first protection layer 116 covers the sidewalls and the bottom of the first channel hole 102 and contacts the first epitaxial layer 115, and the second protection layer 116 ' covers the sidewalls and the bottom of the second channel hole 103 and contacts the second epitaxial layer 115 ', wherein the materials of the first protection layer 116 and the second protection layer 116 ' include a metal material.

Further, in the first channel hole 102, a first blocking dielectric layer 114, a first charge storage layer 113, a first tunneling dielectric layer 112, and a first channel layer 111 are sequentially formed covering the bottom and the sidewall, and in the second channel hole 103, a second blocking dielectric layer 114 ', a second charge storage layer 113', a second tunneling dielectric layer 112 ', and a second channel layer 111' are sequentially formed covering the bottom and the sidewall, as shown in fig. 8.

Further, the first channel layer 111 in the first channel hole 102 is removed, and a portion of the first blocking dielectric layer 114, the first charge storage layer 113, and the first tunneling dielectric layer 112 at the bottom of the first channel hole 102 are removed, thereby exposing a portion of the first protection layer 116, the second channel layer 111 ' in the second channel hole 103 is removed, and a portion of the second blocking dielectric layer 114 ', the second charge storage layer 113 ', and the second tunneling dielectric layer 112 ' at the bottom of the second channel hole 103 is removed, thereby exposing a portion of the second protection layer 116 ', as shown in fig. 9.

In this step, the first channel hole 102 and the bottom structure of the second channel hole 103 may be etched by a silicon-oxide-nitride-oxide (SONO) etching process, wherein the etching is stopped when the first protection layer 116 and the second protection layer 116' are reached.

Further, in the first channel hole 102, the first channel layer 111 is reformed covering the bottom and the sidewall, and in the second channel hole 103, the second channel layer 111' is reformed covering the bottom and the sidewall, as shown in fig. 10.

In this step, the first channel layer 111 is newly formed to be in contact with the protection layer 116 at the bottom of the first channel hole 102, and the second channel layer 111 'is newly formed to be in contact with the protection layer 116' at the bottom of the second channel hole 103.

Further, the first insulating core 117 is filled in the first channel hole 102, and the first plug structure 118 is formed on the upper portion of the first channel hole 102 covering the first insulating core 117, the second insulating core 117 ' is filled in the second channel hole 103, and the second plug structure 118 ' is formed on the upper portion of the second channel hole 103 covering the second insulating core 117 ', as shown in fig. 11.

In this step, a deposition process may be used to fill the first channel hole 102 with an insulating material, the first channel layer 111, the first tunneling dielectric layer 112, and the first charge storage layer 113 on the top of the first channel hole 102 are removed by an etching process and a mechanochemical polishing process, and finally the first insulating core 117, the first channel layer 111, the first tunneling dielectric layer 112, and the first charge storage layer 113 are covered by the deposition process to form a first plug structure 118, where the first plug structure 118 is in contact with the first channel layer 111, the first tunneling dielectric layer 112, the first charge storage layer 113, and the first blocking dielectric layer 114, respectively, and the material of the first plug structure 118 is the same as that of the first channel layer 111. Similarly, the second insulating core 117 'is formed in the same process as the second plug structure 118', and thus, the description thereof is omitted.

Further, the sacrificial layer 132 is removed by isotropic etching using the gate line slit 105 as an etchant path to form the cavity 106, as shown in fig. 12.

In this step, the isotropic etching may employ selective wet etching or vapor phase etching. In wet etchingWherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the interlayer insulating layer 131 and the sacrificial layer 132 in the insulating stacked structure 130 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and C may be used in vapor phase etching₄F₈、C₄F₆、CH₂F₂And O₂One or more of (a). In the etching step, the gate line slit 105 is filled with an etchant. The end portion of the sacrificial layer 132 in the insulation stack structure 130 is exposed in the opening of the gate line slit 105, and thus, the sacrificial layer 132 is contacted to the etchant. The etchant gradually etches the sacrificial layer 132 from the opening of the gate line slit 105 toward the inside of the insulating stacked structure 130. The etching removes the sacrificial layer 132 with respect to the interlayer insulating layer 131 in the insulating stack structure 130 due to the selectivity of the etchant.

Further, the first protective layer 116 and the second protective layer 116 'exposed in the cavity 106 are oxidized by using the gate line slit 105 and the cavity 106 as an oxidation path to form a first contact layer 119 and a second contact layer 119', respectively, and the first epitaxial layer 115 and the second epitaxial layer 115 'exposed in the cavity 106 are oxidized by using the gate line slit 105 and the cavity 106 as an oxidation path to form a first contact region 107 and a second contact region 107', respectively, as shown in fig. 13.

In this step, the first and second protection layers 116 and 116 'are oxidized to a high dielectric constant (high-k) material, thereby forming first and second contact layers 119 and 119'.

Further, the gate line slit 105 is used as a deposition channel, and Atomic Layer Deposition (ALD) is used to fill metal in the gate line slit 105 and the cavity 106 to form

gate conductors

121, 122, and 123, and then etching back (etch back) is performed to re-form the gate line slit 105, as shown in fig. 14 and 15.

In this step, the metal is composed of, for example, tungsten. The

gate conductors

121, 122, 123 are stepped in place of the sacrificial layer 132 in the insulating stack 130, thereby forming the gate stack 120.

The plug structure 118, the first blocking dielectric layer 114, the contact layer 119 and the uppermost gate conductor 122 on the top of the first channel column 110 form an upper selection transistor, the first epitaxial layer 115 on the bottom of the first channel column 110, the contact regions 107 on two sides of the first epitaxial layer 115 and the gate conductor 123 close to the semiconductor substrate 101 form a lower selection transistor, and the first channel layer 111, the first tunneling dielectric layer 112, the first charge storage layer 113, the first blocking dielectric layer 114, the contact layer 119 and the gate conductor 121 in the middle of the first channel column 110 form a storage transistor.

Fig. 16a, 16b illustrate effect analysis diagrams of a 3D memory device according to an embodiment of the present invention.

In an ideal process, for a larger channel pillar, such as the dummy channel 130, after the bottom of the dummy channel 130 is etched by using a SONO etching process to expose the second epitaxial layer 115 ', the second channel layer 111 ' is deposited on the second epitaxial layer 115 ' by using a deposition process, so that the second channel layer 111 ' is in contact with the second epitaxial layer 115 '. However, when the bottom of the dummy trench 130 is etched, a portion of the second epitaxial layer 115 'may be removed to form a void like a sphere, resulting in non-uniform thickness of the sidewall of the second epitaxial layer 115', and a portion of the second epitaxial layer 115 'near the gate conductor may be thin, and when the second channel layer 111' is formed, the thickness of the second channel layer 111 'contacting the second epitaxial layer 115' may be non-uniform, and the portion of the second channel layer 111 'near the gate conductor may also be thin, and may be easily broken down after power is applied to the portion of the second channel layer 111' after the portion of the second epitaxial layer 115 'near the gate conductor is oxidized to form the contact region 107'.

As shown in fig. 15, in the 3D memory device according to the embodiment of the invention, by disposing the second protection layer 116 ' above the second epitaxial layer 115 ' as an etch stop layer, the second epitaxial layer 115 ' is protected by the second protection layer 116 ' and cannot be removed, and when the second channel layer 111 ' is formed above the second protection layer 116 ', the second channel layer 111 ' is uniformly distributed on the second protection layer 116 ' and is in contact with the second epitaxial layer 115 ' through the second protection layer 116 ', because there is no spherical void in the second epitaxial layer 115 ' as shown in fig. 16a and 16b, and the second channel layer 111 ' is located on the second protection layer 116 ', the second channel layer 111 ' and the second epitaxial layer 115 ' are uniformly distributed at the gate conductor 123, so that the breakdown voltage of the 3D memory device is increased.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device comprising:

a semiconductor substrate;

a gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked over the semiconductor substrate; and

a plurality of channel pillars extending through the gate stack structure, the channel pillars comprising:

the epitaxial layer is positioned at the bottom of the channel column and is in contact with the semiconductor substrate;

the protective layer is positioned on the upper surface of the epitaxial layer, is in contact with the epitaxial layer and is used for protecting the epitaxial layer; and

a channel layer over and in contact with the protective layer,

wherein the channel layer and the epitaxial layer are separated by the protective layer, and the protective layer and the epitaxial layer are used for forming electrical connection of the channel layer and the semiconductor substrate.

2. The 3D memory device of claim 1, wherein the channel pillar further comprises a contact layer on a sidewall of the channel pillar and in contact with the protective layer.

3. The 3D memory device of claim 1, wherein the material of the protective layer comprises a metal.

4. The 3D memory device of claim 2, wherein the epitaxial layer includes a contact region on both sides of the epitaxial layer, the gate conductor near the semiconductor substrate being in contact with the contact region.

5. The 3D memory device of claim 4, wherein the other of the gate conductors is in contact with the contact layer.

6. The 3D memory device of any one of claims 1-5, wherein the gate stack structure has:

a core region; and

a stepped region surrounding the core region.

7. The 3D memory device of claim 6, wherein some of the channel pillars are located at the core region and other of the channel pillars are located at the step region.

8. The 3D memory device of claim 7, wherein a size of the channel pillar at the step region is larger than a size of the channel pillar at the core region.

9. The 3D memory device of any one of claims 1-5, wherein the semiconductor substrate includes peripheral circuitry.

10. A method of fabricating a 3D memory device, comprising:

forming a gate stack structure on a semiconductor substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; and

forming a plurality of channel pillars through the gate stack structure, the step of forming the channel pillars comprising:

forming a plurality of channel holes through the gate stack structure and a portion of the semiconductor substrate;

forming an epitaxial layer at the bottom of the channel hole, wherein the epitaxial layer is in contact with the semiconductor substrate;

forming a protective layer at the bottom and the side wall of the channel hole, wherein the protective layer is positioned above the epitaxial layer and is in contact with the epitaxial layer;

sequentially forming a blocking dielectric layer, a charge storage layer, a tunneling dielectric layer and a channel layer which cover the surface of the protective layer and the side wall of the channel hole;

etching the channel layer, the tunneling dielectric layer, the charge storage layer and the blocking dielectric layer which partially cover the surface of the epitaxial layer at least through the channel hole, wherein the etching is stopped when the protective layer is reached; and

reforming the channel layer over the protective layer, the channel layer being in contact with the protective layer,

the protective layer is used for protecting the epitaxial layer, and the protective layer and the epitaxial layer are used for forming electric connection between the channel layer and the semiconductor substrate.

11. The method of claim 10, wherein forming the gate stack structure comprises:

forming an insulating laminated structure on the semiconductor substrate, wherein the insulating laminated structure comprises a plurality of interlayer insulating layers and a plurality of sacrificial layers which are alternately stacked;

patterning the plurality of sacrificial layers to be step-shaped;

replacing the plurality of sacrificial layers with a plurality of gate conductors to form the insulating stack structure.

12. The method of claim 11, wherein, prior to forming the plurality of gate conductors, forming the gate stack further comprises removing the plurality of sacrificial layers to form a plurality of cavities exposing portions of the protective layer and portions of the epitaxial layer,

wherein the protective layer exposed in the cavity is oxidized to form a contact layer, and the epitaxial layer exposed in the cavity is oxidized to form a contact region.

13. The method of claim 12, wherein the gate conductor proximate the semiconductor substrate is in contact with the contact region,

the other of the gate conductors is in contact with the contact layer.

14. The method of claim 13, wherein, after replacing the plurality of sacrificial layers with a plurality of gate conductors, the plurality of gate conductors are stepped, forming a stepped region of the gate stack structure,

the stepped region surrounds a core region.

15. The method of claim 14, wherein some of the channel pillars are located in the core region and other of the channel pillars are located in the step region.

16. The method of claim 15, wherein the channel pillars at the step regions are larger in size than the channel pillars at the core region.

17. The method of any of claims 10-16, wherein the material of the protective layer comprises a metal.