CN109887920A - Three-dimensional storage - Google Patents
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- CN109887920A CN109887920A CN201910124420.3A CN201910124420A CN109887920A CN 109887920 A CN109887920 A CN 109887920A CN 201910124420 A CN201910124420 A CN 201910124420A CN 109887920 A CN109887920 A CN 109887920A
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Abstract
The present invention provides a kind of three-dimensional storage, comprising: semiconductor structure, the semiconductor structure have substrate, the stacked structure on substrate and the first source electrode line in the substrate；It is alternately arranged across the first channel hole of the stacked structure and the second channel hole, first channel hole with second channel hole；The first vertical channel structure in first channel hole and the second vertical channel structure in second channel hole；Second source electrode line is formed in top of the stacked structure far from the substrate；Across the first plug and the first separation layer of second source electrode line；Across the second plug and the second separation layer of first source electrode line.
Description
Technical field
The invention mainly relates to field of semiconductor manufacture more particularly to a kind of three-dimensional storages.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry, which has been researched and developed and has been mass produced, has three-dimensional (3D) structure
Memory device, improve integration density by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core with vertical channel structure
The heart area (core) and the stepped region with hierarchic structure are separated by grid line gap between multiple storage arrays.Vertical-channel knot
It is configured in the channel hole through the stack layer (stack) of three-dimensional storage part.The plug that vertical channel structure passes through top
It is electrically connected to bit line, the read-write operation to storage array may be implemented by bit line.
In order to improve storage density and capacity, it will usually reduce channel hole critical size (Critical Dimension,
CD).With the reduction of channel hole critical size, the density for the bit line being electrically connected with vertical channel structure in channel hole will be more next
It is bigger, it will short circuit risk and parasitic capacitance and metal Coupling effect between raising adjacent bit lines.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of three-dimensional storages, can reduce the density of bit line, reduce phase
Short circuit risk and parasitic capacitance and metal Coupling effect between the line of ortho position.
In order to solve the above technical problems, the present invention provides a kind of three-dimensional storages, comprising: semiconductor structure, described half
Conductor structure has substrate, the stacked structure on substrate and the first source electrode line in the substrate；Across described
The the first channel hole and the second channel hole, first channel hole of stacked structure are alternately arranged with second channel hole；It is located at
The first vertical channel structure in first channel hole and the second vertical channel structure in second channel hole；The
Two source electrode lines are formed in top of the stacked structure far from the substrate；Across second source electrode line the first plug and
First separation layer, first plug are electrically connected to first vertical channel structure, and first separation layer is by described first
Plug and second source electrode line insulate；It is inserted across the second plug and the second separation layer of first source electrode line, described second
Plug is electrically connected to second vertical channel structure, and second separation layer is exhausted by second plug and first source electrode line
Edge.
In one embodiment of this invention, first channel hole replaces with one, second channel hole interval or multirow
Arrangement.
In one embodiment of this invention, first plug is electrically connected to the first peripheral circuit, the second plug electricity
It is connected to the second peripheral circuit.
In one embodiment of this invention, first plug is electrically connected to a peripheral circuit, and second plug passes through
The peripheral circuit is electrically connected to through array hole.
In one embodiment of this invention, the bottom in first channel hole includes silicon epitaxy layer, first channel hole
Ecto-entad successively includes barrier layer, electric charge capture layer, tunnel layer and channel layer.
In one embodiment of this invention, second channel hole ecto-entad successively include barrier layer, electric charge capture layer,
Tunnel layer and channel layer, the barrier layer, electric charge capture layer, tunnel layer and channel layer contact second source electrode line.
In one embodiment of this invention, using the first channel hole described in atomic layer deposition normal direction or second channel hole
It is sequentially depositing barrier layer, electric charge capture layer, tunnel layer and channel layer.
In one embodiment of this invention, the side wall in first channel hole or second channel hole and the barrier layer
Between include high k dielectric constant material.
In one embodiment of this invention, using atomic layer deposition method in first channel hole or second channel hole
Side wall and the barrier layer between deposit high k dielectric constant material.
In one embodiment of this invention, the high k dielectric constant material is silicon nitride, silicon oxynitride, titanium oxide or nitrogen
Change titanium.
Compared with prior art, the invention has the following advantages that the present invention provides a kind of three-dimensional storage, by by position
The two sides of substrate are arranged in line, can reduce the density of bit line, reduce short circuit risk and parasitic capacitance between adjacent bit lines, with
And metal Coupling effect；It, can be in addition, the plug of the channel hole vertical structure of substrate the same side is bigger for the space of arrangement
It arranges large-sized plug, significantly reduces the technique requirement between metal liner layers and channel hole.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is a kind of diagrammatic cross-section of three-dimensional storage.
Fig. 2 is the flow chart of the method for the formation three-dimensional storage of an embodiment according to the present invention；
Fig. 3 A-3J is the core of the example process of the method for the formation three-dimensional storage of an embodiment according to the present invention
Area's diagrammatic cross-section；
Fig. 4 is the diagrammatic cross-section of the three-dimensional storage of an embodiment according to the present invention；
Fig. 5 is the top view of the three-dimensional storage of an embodiment according to the present invention；
Fig. 6 is the diagrammatic cross-section of three-dimensional storage according to another embodiment of the present invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
Fig. 1 is a kind of diagrammatic cross-section of three-dimensional storage.Refering to what is shown in Fig. 1, the three-dimensional storage includes core array
Area 11 and stepped region 12.Core array area 11 includes the storage unit with vertical channel structure by array distribution.Each
Vertical channel structure is electrically connected to bit line 13 by the plug on top, and the behaviour of the read-write to storage array may be implemented by bit line 13
Make.Stepped region 12 is arranged in around core array area 11, for drawing contact portion for the grid layer 14 in each layer of storage array.
These wordline of grid layer 14 as storage array execute the operation such as programming, erasable, reading.In order to improve storage density and appearance
The number of plies (tier) of amount, three-dimensional storage constantly increases, such as 96 layers, 128 layers or more are risen to from 64 layers, and stores single
Member is also constantly being reduced with bitline dimensions, and under this trend, the arrangement that will lead to storage unit is more and more crowded, corresponding to depositing
The bit lines of storage unit also can be more and more crowded, the short circuit risk being likely to result between adjacent bit lines, generates metal Coupling
Effect and parasitic capacitance.
The present invention provides a kind of methods for forming three-dimensional storage, the density of bit line distribution can be reduced, to reduce
Bit line is distributed overstocked bring risk.
Fig. 2 is the flow chart of the method for the formation three-dimensional storage of an embodiment according to the present invention.Fig. 3 A-3J is basis
The core space diagrammatic cross-section of the example process of the method for the formation three-dimensional storage of one embodiment of the invention.Below with reference to
The method of the formation three-dimensional storage of description the present embodiment shown in Fig. 2-3J.
In step 202, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for follow-up process to ultimately form three-dimensional storage part.Partly lead
Body structure may include array area, and array area may include core space and wordline bonding pad.Fig. 3 A-3J mainly shows the semiconductor structure
Core space.
With reference to shown in Fig. 3 A, which can have substrate 310, the stacked structure 320 on substrate 310 and be formed
The first source electrode line 311 in substrate 310.Stacked structure 320 can be alternately stacked folded for first material layer and second material layer
Layer.First material layer can be grid layer or grid sacrificial layer.
In an embodiment of the present invention, the material of substrate 310 is, for example, silicon.First material layer and second material layer are, for example,
The combination of silicon nitride and silica.It, can be using chemical vapor deposition (CVD), original by taking the combination of silicon nitride and silica as an example
Sublayer deposits (ALD) or other suitable deposition methods, successively replaces deposited silicon nitride on substrate 310 and silica forms heap
Stack structure 320.Silicon nitride layer can be used as grid sacrificial layer.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.For example, can basis in substrate
Need to form various well regions.In addition, the material for each layer illustrated is only exemplary, such as substrate 310 can also be it
His siliceous substrate, such as SOI (silicon-on-insulator), SiGe, Si:C etc..Grid layer can also be other conductive layers, such as gold
Belong to tungsten, cobalt, nickel etc..Second material layer can also be other dielectric materials, such as aluminium oxide, hafnium oxide, tantalum oxide etc..
In an embodiment of the present invention, the first source electrode line 311 is located on substrate 310, stacked structure 320 be formed in this
On source line 311.The first source electrode line 311 can be formed on substrate 310 by the way of doping.First source electrode line 311
Material can be DOPOS doped polycrystalline silicon, such as n-type doping polysilicon.
In step 204, the first channel hole CH1 and the second channel hole CH2 across stacked structure 320 are formed.First ditch
Road hole CH1 is alternately arranged with the second channel hole CH2.With reference to shown in Fig. 3 B, in some embodiments, a first channel hole CH1
It is alternately arranged with channel hole the second channel hole CH2.In other examples, one or more first channel holes be can be
CH1 is alternately arranged with the second channel hole CH2 of one or more, for example, a first channel hole CH1 and two the second channel holes
CH2 is alternately arranged or two the first channel hole CH1 and two the second channel hole CH2 are alternately arranged.
The method for forming the first channel hole CH1 and the second channel hole CH2, which may is that, carries out pattern control by exposure mask, according to
It is secondary to carry out hard mask deposition, photoresist spin coating and baking, exposure and dry etching, from the top of stacked structure 320 up to running through
Substrate 310 forms channel hole.
In step 206, the opening of the second channel hole CH2 is closed, the first channel hole CH1 of filling forms the first vertical-channel
Structure 331.
Wherein, the step of opening of the second channel hole CH2 of closing may include:
Firstly, being covered on the upper surface of stacked structure 320, the first channel hole CH1 and the second channel hole CH2 with sacrificial layer.
The sacrificial layer may include such as silicon nitride layer, silicon oxynitride layer, polysilicon layer or polysilicon germanium layer.The sacrificial layer can be by example
Such as the methods of CVD formation.In one embodiment of this invention, using polysilicon as sacrificial layer fast deposition in stacked structure
320 upper surface.In this deposition process, a part of polysilicon is fallen into the first channel hole CH1 and the second channel hole CH2.
Secondly, covering etching barrier layer on sacrificial layer 361.The etching barrier layer may include hard mask layer.The hard mask
Layer may include the nitrogen oxidation as dielectric antireflective coatings (DARC, Dielectric Anti-Reflection Coating)
Silicon, and agraphitic carbon (a-C) layer as pattern layer.It in some embodiments, can also be again in the top of the hard mask layer
Deposit one layer of bottom antireflective coating (BARC, Bottom Anti-Reflection Coating) and photoresist layer (PR,
Photo Resist)。
Finally, removal the first channel hole CH1 in and its top sacrificial layer, thus closing the second channel hole opening.It can
It by the pattern of etching barrier layer, is optionally removed in the first channel hole CH1 and its sacrificial layer of top, to form difference
The first channel hole CH1 and the second channel hole CH2 be alternately arranged structure.For example, can by a kind of etch stopper layer pattern,
So that the interval a line that is alternately arranged of the first channel hole CH1 and the second channel hole CH2 is alternately arranged.In another example can be by another
A kind of etch stopper layer pattern, so that the first channel hole CH1 replaces row with the interval multirow that is alternately arranged of the second channel hole CH2
Column.With reference to shown in Fig. 3 C, in the first channel hole CH1 and its etching barrier layer and sacrificial layer of top have been removed, the second channel
The opening of hole CH2 is sacrificed layer 361 and is covered, to enclose the opening of the second channel hole CH2.In this step, Ke Yitong
The method combination hard mask for crossing wet etching removes in the first channel hole CH1 and its sacrificial layer 361 of top, later to the first ditch
Road hole carries out necessary cleaning.
In step 206, the step of the first channel hole CH1 of filling forms the first vertical channel structure 331 includes: first
The bottom deposit silicon epitaxy layer 371 of channel hole CH1, and to the first channel hole CH1 be sequentially depositing barrier layer, electric charge capture layer,
Tunnel layer and channel layer.
With reference to shown in Fig. 3 D, there is silicon epitaxy layer 371 in the bottom deposit of the first channel hole CH1.In some embodiments, may be used
To be formed using selective epitaxial growth (SEG, Selective Epitaxial Growth) in the bottom of the first channel hole CH1
Identical height is filled out in the first channel hole bottom CH1 by silicon epitaxy layer 371, to guarantee the devices such as threshold voltage uniformity
Characteristic.Above the silicon epitaxy layer 371, barrier layer, charge-trapping have been sequentially depositing to center from the side wall of the first channel hole CH1
Layer, tunnel layer and channel layer, these layer-by-layer structures constitute the first vertical channel structure 331.
It in some embodiments, further include in the first ditch after carrying out above-mentioned deposition and filling to the first channel hole CH1
Road hole CH1 bottom opening, is refilled with channel layer, to be connected to the first channel hole CH1 and silicon epitaxy layer 371.Further, to be situated between
It is electrically isolated material and fills channel hole core, channel hole core can also give over to air gap (Air gap).
In one embodiment of this invention, barrier layer can be aluminium oxide, silica, the single layer of the materials such as silicon oxynitride or
The wide-band gap materials such as lamination or mixed layer.Electric charge capture layer can be silicon nitride, the single layer or lamination of the materials such as silicon oxynitride or
The wide-band gap materials such as mixed layer.Tunnel layer can be silica, the single layer of silicon oxynitride or the broad stopbands such as lamination or mixed layer material
Material.Channel layer can be polysilicon.Dielectric spacer material can be silica.
With reference to shown in Fig. 3 D, at this time also with some in the opening for closing the second channel hole CH2 inside the second channel hole CH2
When into the second channel hole CH2 361 material of sacrificial layer.
In a step 208, the opening of the second channel hole CH2 is opened, the second channel hole CH2 of filling forms the second vertical-channel
Structure 332, and the second source electrode line 312 is formed far from the top of substrate 310 in stacked structure 320.
With reference to shown in Fig. 3 E, in this step, the method for opening the opening of the second channel hole CH2 can pass through hard mask figure
Case control method opens the opening of the second channel hole CH2.That is it is hard a pattern layers to be covered in the top of stacked structure 320
Mask layer, then the opening by the second channel hole CH2 of etching opening.
The hard mask layer may include the silicon oxynitride as dielectric antireflective coatings, and as the unformed of pattern layer
Carbon (a-C) layer.In some embodiments, the top of the hard mask layer can with redeposited one layer of bottom antireflective coating and
Photoresist layer.
With reference to shown in Fig. 3 E, the material of a part of sacrificial layer 361 is still had in the inside of the second channel hole CH2 at this time.
Therefore, before being filled to the second channel hole CH2, need to remove the material of the partial sacrificial layer 361, and to the second channel
Hole CH2 carries out necessary cleaning.The second channel hole CH2 after cleaning is as illustrated in Figure 3 F.
Filling the step of the second channel hole CH2 forms the second vertical channel structure 332 in this step includes: to the second ditch
Road hole CH2 is sequentially depositing barrier layer, electric charge capture layer, tunnel layer and channel layer.Unlike the first channel hole CH1 of filling,
Silicon epitaxy layer is not necessarily formed in the bottom of the second channel hole CH2.In this way, the second vertical channel structure 332 can be follow-up process
In required plug structure to be formed form bigger space, can be in the corresponding location arrangements of the second vertical channel structure 332
Large-sized plug, so as to significantly reduce the requirement of the technique between metal liner layers and channel hole.
With reference to shown in Fig. 3 G, to the second channel hole CH2 filling finish to be formed the second vertical channel structure 332 and then
The second source electrode line 312 is formed far from the top of substrate 310 in stacked structure 320.Second source electrode line 312 and the second channel hole
Barrier layer, electric charge capture layer, tunnel layer and channel layer in CH2 are in contact.
Before forming the second source electrode line 312, planarization process can also be carried out to the top of stacked structure 320.
In some embodiments, can be formed by way of the top depositing doped polysilicon in stacked structure 320
Two source electrode lines 312.
In step 210, the first plug 341 and the first separation layer 351 across the second source electrode line 312 are formed.Wherein, should
First plug 341 is electrically connected to the first vertical channel structure 331, and first separation layer 351 is by the first plug 341 and the second source electrode
Line 312 insulate.
In some embodiments, it is possible, firstly, to by way of the deposited hard mask layer on the second source electrode line 312, right
It should be performed etching in the position of the first vertical channel structure 331 and necessary cleaning；Secondly, in the first vertical channel structure
The insulation spacer as the first separation layer 351 is formed in the space at 331 tops, which can be using such as ALD or existing
Field steam generates the mode deposition oxide of (ISSG, In-Situ Steam Generation) to be formed；Again, in the insulation
Form aperture on gasket and form the first plug 341 wherein, first plug 341 can by the way of polysilicon deposition shape
At；Finally, the top to the stacked structure 320 carries out planarization process.It is appreciated that the first separation layer 351 and the first plug
341 formation sequence is without being limited thereto, is also possible to be initially formed the first plug 341, re-forms the first separation layer 351.
In some embodiments, the step of the first plug 341 and the first separation layer 351 are formed in the second source electrode line 312
Later further include: the first plug 341 is electrically connected to the first peripheral circuit by conductive contact 381.
With reference to shown in Fig. 3 H, by being formed with first at the top of the first vertical channel structure 331 and inserting after step 210
Plug 341.And the first separation layer 351 is formed with around the first plug 341.First separation layer 351 makes the first plug 341
It insulate with the second source electrode line 312.
In the step 212, the second plug 342 and the second separation layer 352 across the first source electrode line 311 are formed.
In some embodiments, before executing step 212, first three-dimensional storage is spun upside down, makes substrate 310 and
Source line 311 is transformed into top side from original bottom side.After overturning, substrate 310 can be carried out thinning processing, and to it
The surface being located above carries out planarization process.
With reference to shown in Fig. 3 I, by after spinning upside down, the first source electrode line 311 of the three-dimensional storage has been positioned at top
Side, and above the second vertical channel structure 332 corresponding to position form the second plug 342 and the second separation layer 352.
Second plug 342 is electrically connected to the second vertical channel structure 332 of its corresponding position, and second separation layer 352 is by second
Plug 342 and the first source electrode line 311 insulate.
The shape of the forming method of second plug 342 and the second separation layer 352 and the first plug 341 and the first separation layer 351
It is similar at method.
In some embodiments, the step of the second plug 342 and the second separation layer 352 are formed in the first source electrode line 311
Later further include: the second plug 342 is electrically connected to the second peripheral circuit by conductive contact 382.
Wherein, with reference to shown in Fig. 3 I, the first plug 341 passes through conductive contact 381 and the first peripheral circuit (not shown) phase
Connection.The step can also carry out after step 210, that is to say, that form the second plug 342 and the second separation layer 352
It carries out, and/or is carried out before being spun upside down three-dimensional storage before.
Here the first peripheral circuit and the second peripheral circuit respectively refers to mutually independent peripheral circuit.
In the present embodiment, the first peripheral circuit and the second peripheral circuit are located at the two sides of three-dimensional storage.At it
In his embodiment, the first peripheral circuit and the second peripheral circuit can also be positioned at the same sides of three-dimensional storage.
With reference to shown in Fig. 3 J, after above step is finished, the first plug 341 passes through conductive contact 381 and first
Peripheral circuit is connected, and the second plug 342 is connected by conductive contact 382 with the second peripheral circuit.
It is understood that in these embodiments, for the first plug 341 is electrically connected to the first peripheral circuit 381
There is no the limitation of sequencing with two steps that the second plug 342 is electrically connected to the second peripheral circuit 382.
In some embodiments, the step of the second plug 342 and the second separation layer 352 are formed in the first source electrode line 311
Later further include:
First plug 341 is electrically connected to a peripheral circuit 380；And
By the second plug 342 by being electrically connected to the peripheral circuit 380 through array hole.
In these embodiments, the first plug 341 and the second plug 342 are connected to the same peripheral circuit.The periphery
Circuit 380 can be located at the side of three-dimensional storage.
Fig. 4 is the diagrammatic cross-section of the three-dimensional storage of an embodiment according to the present invention.Refering to what is shown in Fig. 4, the three-dimensional
Memory includes semiconductor structure, which has substrate 410, the stacked structure 420 on substrate 410 and position
The first source electrode line 411 in substrate 410.
The three-dimensional storage further includes the first channel hole CH1 and the second channel hole CH2 across stacked structure 420, and first
Channel hole CH1 is alternately arranged with the second channel hole CH2；And the first vertical channel structure 431 in the first channel hole CH1
With the second vertical channel structure 432 being located in the second channel hole CH2.
In the embodiment shown in fig. 4, an a first channel hole CH1 and second channel hole CH2 is alternately arranged.At it
In his embodiment, it is also possible to the first channel hole CH1 of one or more with the second channel hole CH2 of one or more and replaces row
Column.Such as a first channel hole CH1 is alternately arranged with two the second channel hole CH2 or two the first channel hole CH1 and two
A second channel hole CH2 is alternately arranged.
In some embodiments, the first channel hole CH1 of three-dimensional storage is filled to form the first vertical-channel
Structure 431.The bottom of the first channel hole CH1 is set to form silicon epitaxy layer, the first channel hole CH1 ecto-entad successively includes stopping
Layer, electric charge capture layer, tunnel layer and channel layer.The method that the first channel hole CH1 is filled to form the first vertical channel structure 431
It can be with reference to description hereinbefore.
In some embodiments, the second channel hole CH2 of three-dimensional storage is filled to form the second vertical-channel
Structure 432.Making the second channel hole CH2 ecto-entad successively includes barrier layer, electric charge capture layer, tunnel layer and channel layer.With
It fills unlike the first channel hole CH2, not necessarily forms silicon epitaxy layer, the second channel structure in the bottom of the second channel hole CH2
Barrier layer, electric charge capture layer, tunnel layer and channel layer in 432 and it is formed in top of the stacked structure 420 far from substrate 410
Second source electrode line 412 is in contact.
The three-dimensional storage further includes (scheming not across the first plug 441 of the second source electrode line 412 and the first separation layer 451
Show).First plug 441 is electrically connected to the first vertical channel structure 431, and the first separation layer 451 is by the first plug 441 and second
Source electrode line 412 insulate.
The three-dimensional storage further includes (scheming not across the second plug 442 of the first source electrode line 411 and the second separation layer 452
Show), which is electrically connected to the second vertical channel structure 432, and the second separation layer 452 is by the second plug 442 and first
Source electrode line 411 insulate.
In some embodiments, refering to what is shown in Fig. 4, the first plug 441 in the three-dimensional storage is electrically connected to outside first
Circuit 481 is enclosed, the second plug 442 is electrically connected to the second peripheral circuit 482.First peripheral circuit 481 and the second peripheral circuit
482 are located at the two sides of three-dimensional storage.
It is understood that the first plug 441 and the second plug 442 are all to be respectively connected to the first periphery electricity by bit line
Road 481 and the second peripheral circuit 482.Therefore, bit line is made to be distributed in the two of three-dimensional storage using three-dimensional storage of the invention
Side can reduce the density of bit line.
Fig. 5 is the top view of the three-dimensional storage of embodiment illustrated in fig. 4.Refering to what is shown in Fig. 5, in the first source electrode line 411
The array formed by the second plug 442 is distributed with.Wherein the second plug 442 of each row corresponds to shown in Fig. 4 alternately
The second plug 442 at the top of several second channels hole CH2 of arrangement；Second plug 442 of each perpendicular column corresponds to institute in Fig. 4
Show the second plug 442 at the top of all second channels hole CH2 in the column where each second channel hole CH2.Each second
It is surrounded by the second separation layer 452 around plug 442, makes 411 mutually insulated of the second plug 442 and the first source electrode line.
Distance between two the second plugs of column 442 indicates the bottom of the first channel hole CH1, rather than with the first vertical furrow
The first plug 441 that road structure 431 is connected.Therefore, the embodiment of the present invention can reduce three-dimensional storage in this side
Bit line density.
Fig. 6 is the diagrammatic cross-section of three-dimensional storage according to another embodiment of the present invention.Refering to what is shown in Fig. 6, the reality
The three-dimensional storage for applying example has similar structure with the three-dimensional storage in embodiment illustrated in fig. 4, the difference is that:
First, the three-dimensional storage of the embodiment, which has, runs through array hole 601, the second plug 642 can be run through by this
Array hole 601 is electrically connected to peripheral circuit 680；
Second, the first plug 641 is also electrically connected to the peripheral circuit 680；
Third, the peripheral circuit 680 of the embodiment is located at the same side of the three-dimensional storage part.
It is understood that, however it is not limited to by the way that second plug 642 is electrically connected to peripheral circuit 680 through array hole 601,
The second plug 642 can be electrically connected to peripheral circuit 680 by silicon perforation.
For the three-dimensional storage of the present embodiment, all second plugs 642 corresponding to the second channel hole CH2 can be with
It is connected by bit line or other outer on lines, then by being connected to peripheral circuit 680 through array hole 601, that is to say, that
Bit line corresponding to second plug 642 is distributed in the side where the second plug 642, bit line corresponding to the first plug 641 point
It is distributed in the other side where the first plug 641, therefore the bit line density of three-dimensional storage the same side can be reduced, reduces adjacent bit
Short circuit risk and parasitic capacitance and metal Coupling effect between line.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also be done in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (10)
1. a kind of three-dimensional storage, comprising:
Semiconductor structure, the semiconductor structure have substrate, the stacked structure on substrate and are located in the substrate
The first source electrode line；
Across the first channel hole and the second channel hole of the stacked structure, first channel hole and second channel hole are handed over
For arrangement；
The first vertical channel structure in first channel hole and the second vertical furrow in second channel hole
Road structure；
Second source electrode line is formed in top of the stacked structure far from the substrate；
Across the first plug and the first separation layer of second source electrode line, it is vertical that first plug is electrically connected to described first
Channel structure, first separation layer insulate first plug and second source electrode line；
Across the second plug and the second separation layer of first source electrode line, it is vertical that second plug is electrically connected to described second
Channel structure, second separation layer insulate second plug and first source electrode line.
2. three-dimensional storage according to claim 1, which is characterized in that first channel hole and second channel hole
One, interval or multirow are alternately arranged.
3. three-dimensional storage according to claim 1, which is characterized in that first plug is electrically connected to the first periphery electricity
Road, second plug are electrically connected to the second peripheral circuit.
4. three-dimensional storage according to claim 1, which is characterized in that first plug is electrically connected to a periphery electricity
Road, second plug is by being electrically connected to the peripheral circuit through array hole.
5. three-dimensional storage according to claim 1, which is characterized in that the bottom in first channel hole includes silicon epitaxy
Layer, first channel hole ecto-entad successively includes barrier layer, electric charge capture layer, tunnel layer and channel layer.
6. three-dimensional storage according to claim 1, which is characterized in that second channel hole ecto-entad successively includes
Barrier layer, electric charge capture layer, tunnel layer and channel layer, the barrier layer, electric charge capture layer, tunnel layer and channel layer contact described in
Second source electrode line.
7. three-dimensional storage according to claim 5 or 6, which is characterized in that using described in atomic layer deposition normal direction first
Channel hole or second channel hole are sequentially depositing barrier layer, electric charge capture layer, tunnel layer and channel layer.
8. three-dimensional storage according to claim 5 or 6, which is characterized in that first channel hole or second ditch
It include high k dielectric constant material between the side wall in road hole and the barrier layer.
9. three-dimensional storage according to claim 8, which is characterized in that using atomic layer deposition method in first channel
High k dielectric constant material is deposited between hole or the side wall and the barrier layer in second channel hole.
10. three-dimensional storage according to claim 8, which is characterized in that the high k dielectric constant material be silicon nitride,
Silicon oxynitride, titanium oxide or titanium nitride.
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| CN201910124420.3A CN109887920A (en) | 2019-02-19 | 2019-02-19 | Three-dimensional storage |
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