CN108140645A - The 3D semicircle vertical nand strings in the inactive semiconductor channel section with recess - Google Patents

The 3D semicircle vertical nand strings in the inactive semiconductor channel section with recess Download PDF

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CN108140645A
CN108140645A CN201680055146.3A CN201680055146A CN108140645A CN 108140645 A CN108140645 A CN 108140645A CN 201680055146 A CN201680055146 A CN 201680055146A CN 108140645 A CN108140645 A CN 108140645A
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memory
side wall
pair
layer
dielectric medium
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CN108140645B (en
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西川昌利
H.井内
M.宫本
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract

Including each memory be open in every grade of dual memory cell vertical memory device can have be projected into memory opening in memory heap stack structure towards a pair of sidewalls in dielectric separator dielectric medium structure.Laterally it is recessed from control gate electrode towards the inactive part of a pair of the vertical semiconductor raceway groove of dielectric separator dielectric medium structure.Due to dielectric separator dielectric medium structure, the control of the threshold voltage to this vertical memory device can be enhanced.Due to the increased distance between control gate electrode and the inactive part of vertical semiconductor raceway groove, the fringe field from control gate electrode is weaker.The convex side wall that memory heap stack structure can have the recessed side wall of contact dielectric separator dielectric medium structure and be protruded towards control gate electrode.

Description

The 3D semicircle vertical nand strings in the inactive semiconductor channel section with recess
Cross reference to related applications
This application claims enjoy in the U.S. Provisional Application No. 62/257,885 submitted on November 20th, 2015 and in The benefit of priority of U.S. non-provisional application sequence number 15/008,744 that on January 28th, 2016 submits, the whole of above-mentioned application Content is incorporated herein by reference.
Technical field
The disclosure relates generally to field of semiconductor devices, and more particularly to three dimensional nonvolatile storage component part, all Such as vertical nand string and other three-dimension devices and the method for manufacturing the device.
Background technology
Recently, it has been proposed that use sometimes referred to as scalable (Bit Cost Scalable, the BiCS) frame of bit cost The Ultra High Density Memory part of three-dimensional (3D) stacked storage stacked structure of structure.For example, 3D NAND stacked storage devices Part can be formed by the array of alternate conductive layer and dielectric layer.Memory opening is formed by layer to define many storages simultaneously Device layer.Then NAND string is formed by using suitable material filling memory opening.Straight NAND string is opened in a memory Extend in mouthful, and tubular or U-shaped NAND string (p-BiCS) includes a pair of vertical memory cell columns.The control of memory cell Grid can be provided by conductive layer.
Invention content
According to one aspect of the disclosure, a kind of storage component part is provided, including：Insulating layer above substrate With being alternately stacked for conductive layer；A pair of separated device dielectric medium structure extends through described be alternately stacked and along the first transverse direction Direction extends transversely with；And memory heap stack structure, memory heap stack structure include memory film and extend through alternately heap Folded vertical semiconductor raceway groove, memory heap stack structure have a pair first of the side wall of contact a pair of separated device dielectric medium structure Side wall, and with along outwardly projecting a pair of of the second sidewall of the second horizontal direction.The first side wall is from the base of a pair of of second sidewall Vertical edge is laterally inwardly recessed in sheet.
According to another aspect of the present disclosure, a kind of method for manufacturing memory device is provided.Insulating layer is formed on substrate With being alternately stacked for sacrificial material layer.Multiple separator dielectric medium structures are formed by being alternately stacked, multiple separator electricity is situated between Matter structure is arranged along the first horizontal direction and is stored by opening and is laterally spaced.With than surrounding memory opening The higher etch-rate of side wall of multiple separator dielectric medium structures is laterally recessed the side wall of insulating layer.It is replaced with conductive layer sacrificial Domestic animal material layer.The memory heap stack structure for including memory film and vertical semiconductor raceway groove is formed in each memory opening.
Description of the drawings
Fig. 1 is the exemplary device structures according to an embodiment of the present disclosure for including 3D NAND stacked storage devices Vertical cross-section.
Fig. 2A is showing after the formation being alternately stacked of insulating layer and semiconductor layer according to an embodiment of the present disclosure The vertical view of example property device architecture.
Fig. 2 B are the vertical cross-sections of the exemplary device structures of Fig. 2A.
Fig. 3 A are the exemplary device structures according to an embodiment of the present disclosure after the formation for the groove being laterally extended Vertical view.
Fig. 3 B are the vertical cross-sections of the exemplary device structures of Fig. 3 A.
Fig. 4 A are the exemplary means knots according to an embodiment of the present disclosure after the formation of separator dielectric medium structure The vertical view of structure.
Fig. 4 B are the vertical cross-sections of the exemplary device structures of Fig. 4 A.
Fig. 5 A are bowing for the exemplary device structures after the formation according to an embodiment of the present disclosure being open in memory View.
Fig. 5 B are the vertical cross-sections of the exemplary device structures of Fig. 5 A.
Fig. 6 A are the exemplary devices after the selectivity according to an embodiment of the present disclosure being open in memory is extending transversely The vertical view of part structure.
Fig. 6 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Fig. 6 A.
Fig. 6 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Fig. 6 B.
Fig. 7 A are bowing for the exemplary device structures according to an embodiment of the present disclosure after the removal of sacrificial material layer View.
Fig. 7 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Fig. 7 A.
Fig. 7 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Fig. 7 B.
Fig. 8 A are the horizontal plane A-A' according to an embodiment of the present disclosure along Fig. 8 B in continuous conduction material layer The vertical cross-section of exemplary device structures after deposit.
Fig. 8 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Fig. 8 A.
Fig. 8 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Fig. 8 B.
Fig. 9 A are that the horizontal plane A-A' according to an embodiment of the present disclosure along Fig. 9 B removals out of memory opening connect The vertical cross-section of exemplary device structures after the part of continuous conductive material layer.
Fig. 9 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Fig. 9 A.
Fig. 9 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Fig. 9 B.
Figure 10 A are in accordance with an embodiment of the present disclosure along the memory heap stack structure and electricity of the horizontal plane A-A' of Figure 10 B The vertical cross-section of exemplary device structures after the formation of dielectric core.
Figure 10 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Figure 10 A.
Figure 10 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Figure 10 B.
Figure 11 A be the drain region of the horizontal plane A-A' according to an embodiment of the present disclosure along Figure 11 B formation it The vertical cross-section of exemplary device structures afterwards.
Figure 11 B are the vertical cross-sections along the vertical plane B-B' of the exemplary device structures of Figure 11 A.
Figure 11 C are the horizontal cross-sectional views along the exemplary device structures of the horizontal plane C-C' of Figure 11 B.
Figure 12 is memory heap stack structure and a pair of separated device electricity in example arrangement according to an embodiment of the present disclosure The amplification horizontal cross-sectional view of dielectric structure.
Figure 13 shows the etch-rate of the silica material deposited in buffered hydrofluoric acid by different deposition process.
Figure 14 is the circuit diagram of the array region of the first exemplary device structures.
Figure 15 is the second exemplary device structures after the formation of bit line according to second embodiment of the present disclosure Vertical cross-section.
Figure 16 is showing for the global shape for the various assemblies for showing exemplary device structures according to an embodiment of the present disclosure The perspective plan view of example property device architecture.
Figure 17 is the perspective view of the array region of exemplary device structures according to an embodiment of the present disclosure.
Specific embodiment
As described above, this disclosure relates to three dimensional nonvolatile storage component part (such as vertical nand string and other three-dimensional devices Part) and its manufacturing method, various aspects be described below.Embodiment of the disclosure may be used and various partly led to be formed Body device, such as the three dimensional monolithic memory array device including multiple nand memory strings.Attached drawing is not necessarily to scale.It removes The repetition there is no element is non-clearly described or has clearly dictated otherwise, otherwise multiple examples of element can show element Single instance in the case of be replicated.The ordinal number of such as " first ", " second " and " third " is only used for identifying similar element, And different ordinal numbers can be used across instant disclosed specification and claims.
Monolithic three dimensional memory array is that plurality of storage level is formed on single substrate (such as semiconductor wafer) Just and without the array of intermediate substrate.Term " monolithic " means that the layer of each grade (level) of array is deposited directly on array It is each below (underlying) grade layer on.On the contrary, two-dimensional array can be respectively formed, and it is then encapsulated in together To form non-monolithic memory part.For example, as Serial No. 5,915,167, the U.S. of entitled " three-D structure memory " are special Described in profit, non-monolithic is built by forming storage level on separate substrates and being vertically stacked storage level Stacked memory.Substrate can be thinned or be removed before the adhesive is set from storage level, but since storage level is initially being divided From substrate on formed, so this memory is not real monolithic three dimensional memory array.Substrate can be included on it The integrated circuit of manufacture, such as the drive circuit of storage component part
The various three dimensional memory devices of the disclosure include monolithic three dimensional NAND string storage component part, and this may be used Various embodiments described in text manufacture.Monolithic three dimensional NAND string is located at the monolithic three dimensional array of the NAND string above substrate In.At least one of first device level of the cubical array of NAND string memory cell is located at the of the cubical array of NAND string On another memory cell in two device levels.
With reference to figure 1, exemplary device structures according to an embodiment of the present disclosure are shown, including 3D NAND stacks Storage component part.Exemplary device structures may be used to be incorporated to the memory stacking for being used to form and being shown in subsequent attached drawing The embodiment of structure 55 and separator dielectric medium structure (not shown in figure 1).Each memory heap stack structure 55 can include at least Memory film 50, semiconductor channel 60 and the feelings that the whole volume in memory film is optionally not filled in semiconductor channel 60 Include dielectric core 62 under condition.
Exemplary device structures include substrate 8, can be Semiconductor substrates.It can be using methods known in the art On substrate 8 or 8 top of substrate forms various semiconductor devices.For example, storage component part battle array can be formed in device area 100 Row, and at least one peripheral components 20 can be formed in peripheral device region 200.To the device in device area 100 The conductive through hole contact of conductive electrode can be formed in contact area 300.
Substrate 8 can include substrate semiconductor layer 10.Substrate semiconductor layer 10 is semiconductor material layer, and can be included At least one elemental semiconductors, at least one III-V compound semiconductor material, at least one II-VI group compound Semi-conducting material, at least one organic semiconducting materials or other semi-conducting materials known in the art.Substrate 8 has main surface 9, can be the upper space of such as substrate semiconductor layer 10.Main surface 9 can be semiconductor surface.In one embodiment In, main surface 9 can be single crystalline semiconductor surface.In one embodiment, substrate 8 is comprising dopant well (for example, p traps) substrate The silicon wafer of semiconductor layer 10.
As used herein, " semi-conducting material " refers to have 1.0 × 10-6S/cm to 1.0 × 105In the range of S/cm The material of conductivity, and can be generated in 1.0S/cm to 1.0 × 10 when suitably being adulterated with electrical dopant5S/cm In the range of conductivity dopant material.As it is used herein, " electrical dopant " is directed to the balance in band structure (balance) n-type dopant of the p-type dopant with addition hole or the conduction band addition electronics into band structure.Such as this paper institutes , " conductive material ", which refers to have, is more than 1.0 × 105The material of the conductivity of S/cm.As used herein, " insulator material Material " or " dielectric substance ", which refer to have, is less than 1.0 × 10-6The material of the conductivity of S/cm.All surveys for conductivity Amount carries out at the standard conditions.It is alternatively possible at least one dopant well substrate semiconductor layer 10 is formed in substrate 8.
It is alternatively possible to using any appropriate method for the array for being used to implement vertical nand string in substrate semiconductor layer 10 Selection gate electrode (not shown) is formed on interior or 10 top of substrate semiconductor layer.For example, it is such as submitted on December 19th, 2013 , application No. is 14/133,979 United States Patent (USP), on March 25th, 2014 it is submitting, application No. is 14/225,116 U.S. State's patent and/or on March 25th, 2014 is submitting, (its whole passes through reference application No. is 14/225,176 United States Patent (USP) It is incorporated herein) described in, relatively low selection gate device level can be manufactured.Source level region 12 can be formed on from storage In the region of the substrate semiconductor layer 10 of 55 lateral shift of device stacked structure.Alternatively, source level region can be formed directly into Below the memory heap stack structure 55 of memory cell, such as submitted on June 27th, 2014 application No. is 14/317,274 United States Patent (USP) (it is incorporated herein by reference) it is described.Selection transistor can be formed on substrate semiconductor layer 10 Between the control grid of top and the most bottom surface of storage component part.
At least one optional fleet plough groove isolation structure 16 and/or at least one deep trench isolation structure may be used (not Show) electric isolution in the various semiconductor devices on substrate 8 is provided.It is formed at least in peripheral device region 200 One peripheral components 20 can include operation known in the art and needing the semiconductor devices in supports region 100 Any device.At least one peripheral components 20 can include associated with the array of the memory device in device area 100 Drive circuit.At least one peripheral components can include the transistor device in drive circuit.In one embodiment, At least one peripheral components can include one or more field-effect transistors, and each can include source region 201st, drain region 202, body region 203 (such as channel region), gate stack 205 and grid spacer 206.Gate stack 205 can include any kind of gate stack known in the art.For example, each gate stack 205 can be from side to another Side includes gate-dielectric, gate electrode and optional gate cap dielectric.Optionally, the planarization including dielectric substance Dielectric layer 170 can be employed in peripheral device region 200 to promote stack the material then formed on the substrate 8 Partial planarization.
The alternate layer of the first material and the second material different from the first material is formed above the top surface of substrate 8 It stacks.In one embodiment, the first material can be the insulating material to form insulating layer 32, and the second material can be The conductive material of conductive line structure is formed, conductive line structure can include conductive layer 46, source side selection gate electrode (not individually Show) and drain side selection gate electrode (not separately shown).Alternatively, the first material can be to form insulating layer 32 exhausted Edge body material, and the second material can be the expendable material deposited as sacrificial layer, and at least partially with conductive material Instead of to form various conductive line structures after the formation of memory heap stack structure 55.In one embodiment, it is alternately stacked It can include insulating layer 32 and material layer, which can include then being replaced with the conductive material for forming control gate electrode Expendable material or can include patterning (pattern) into storage component part control gate electrode conductive material.
Memory heap stack structure 55 can pass through insulating layer by using the various methods for the disclosure that will be described below 32 and conductive layer 46 be alternately stacked (32,46) to be formed.Drain region can be formed on the top of each semiconductor channel 60 Domain 63.It can be by removing insulating layer 32 and sacrificial from the peripheral device region 200 including peripheral components (such as drive circuit) The peripheral part being alternately stacked of domestic animal material layer 42 and deposit dielectric material is outer to be formed in planarized dielectric layer 170 Enclose region dielectric layer 64.Another part for being alternately stacked (32,42 or 46) in contact area 300 can be removed to form The lateral extent (such as sacrificial material layer 42 or conductive layer 46) of stepped surfaces, wherein material layer with it is vertical with substrate 8 away from From and reduce.It can be above stepped surfaces optionally with Reverse Step (retro-stepped) formula dielectric filler part 65.As it is used herein, Reverse Step structure refers to wherein horizontal vertical cross-sectional area hanging down with the top surface with substrate Straight distance and be altered in steps so that be included in relatively low level in the vertical cross-section area of the structure of the horizontal plane of overlying The structure in the vertical cross-section area of the structure at plane.Another part 38 of dielectric filler can be formed in area in part 65 It is formed in while in domain 300 in region 200.
Contact through hole groove is formed on the rear contact through-hole structure being then formed by being alternately stacked (32,42) At 76 position.If vertically adjacent to 32 pairs of insulating layer between material layer be sacrificial material layer 42, can be by passing through Contact through hole groove introduces etchant to remove sacrificial material layer 42.Etchant removes the material selectivity of insulating layer 32 sacrificial The material of domestic animal material layer 42 is to form interlayer cavity.Conductive layer 46 can be by depositing at least one conduction material in interlayer cavity Expect to be formed.Conductive layer 46 includes the control gate electrode for memory heap stack structure 55.Conductive layer 46 can be in contact zone Trapezoidal (ladder) structure is formed in domain 300, to facilitate the formation of contact through hole structure 66.
It can be by forming the via cavities for the stepped surfaces for extending to conductive layer 46 and by using optional dielectric liner In (liner) 64 and contact through hole structure 66 fill each via cavities to form contact through hole structure 66.Dielectric liner (if In the presence of if) electric isolution of contact through hole structure 66 can be enhanced.Contact can be promoted logical optionally with hard mask layer 36 The formation of pore structure 66.Peripheral contacts through-hole structure 86 can be formed in peripheral device region 200.It can be by being alternately stacked (32,46) rear contact through-hole structure 76 (for example, source electrode/source electrode local interlinkage) is formed to provide and source region 12 Electrical contact.Dielectric spacers 74 may be used to provide for the electric isolution of rear contact through-hole structure 76.It then, can be with shape Into the contact (not shown) to drain region 63, and covering can be formed and electric short circuit to drain region 63 bit line (not It shows).
With reference to figure 2A and 2B, in accordance with an embodiment of the present disclosure, the processing of the example arrangement of Fig. 1 is being used to form using it During step, the opening (cut- of the memory area 100 (for example, memory array area) of exemplary device structures is shown Out) part.Being alternately stacked (32,42) for insulating layer 32 and sacrificial material layer 42 is formed on the substrate 8.
Electrically insulating material available for insulating layer 32 includes but not limited to the undoped silicate glass (oxygen of no dopant SiClx) or doping silicate glass, such as borosilicate glass, phosphosilicate glass, boron phosphorus silicate glass, fluosilicate Glass, organic silicate glass and combinations thereof.Sacrificial material layer 42 includes sacrificial layer, such as silicon nitride or polysilicon sacrificial layer. In illustrated examples, insulating layer 32 can include silica (such as undoped silicate glass or the glassy silicate of doping Glass), and sacrificial material layer 42 can be the silicon nitride layer that then can be for example removed by using the wet etching of phosphoric acid.
The dielectric substance of insulating layer 32 is known as the first dielectric substance herein.First dielectric substance can be with second Dielectric substance is etched away to then be adopted for forming the separator dielectric medium structure as dielectric material structure simultaneously. In one embodiment, the first dielectric substance and the second dielectric substance can be selected so that the first dielectric substance be There is the first silica material of the first etch-rate, and the second dielectric substance in etching media (such as buffered hydrofluoric acid) It is the second silica material with the second etch-rate, Yi Ji in identical etching media (such as, buffered hydrofluoric acid) The ratio of one etch-rate and the second etch-rate is in the range of 1.5 to 1000.Buffered hydrofluoric acid is hydrofluoric acid and ammonium fluoride With 1：7 volume ratio is the NH4F of 12.5% HF and 87.5% by volume.
In illustrated examples, the first dielectric substance can be from borosilicate glass, phosphosilicate glass, boron phosphorus silicic acid It is selected in salt glass, fluorosilicate glass, organic silicate glass and combinations thereof, and the second dielectric substance can not mixed Miscellaneous silicate glass.The silicate material of doping can be by using the precursor and at least of such as tetraethyl orthosilicate (TEOS) A kind of chemical vapor deposition of dopant source (such as diborane, phosphotungstic acid, and/or fluorine-containing dopant gas) deposits, and Undoped silicate material can be deposited by using the chemical vapor deposition of the precursor of such as TEOS, without the use of any Dopant source.Alternatively, it is possible to undoped silicate glass is deposited instead of chemical vapor deposition using spin coating Or the silicate glass of doping.
In another illustrative example, the etch-rate difference between the first dielectric substance and the second dielectric substance can Difference is formed to provide in the different types of undoped silicate glass caused by the difference in different deposition process.Example Such as, the first dielectric substance for being adopted for insulating layer 32 can be formed sediment by low-pressure chemical vapor phase deposition (" LPCVD ") Long-pending undoped silicate glass (for example, silica), and the second dielectric substance then used can be passed through The undoped silicate glass (for example, silica) that gas ions enhance chemical vapor deposition (" PECVD ") to deposit.Pass through The undoped silicate glass of LPCVD deposits can be substantially free of hydrogen and carbon, and passes through the undoped of PECVD deposits Silicate glass can be including at least 0.1% hydrogen of atomic concentration and/or the carbon of at least every 100/1000000ths atomic concentration As impurity, so as to improve the etch-rate of buffered hydrofluoric acid.Figure 13 is shown by PECVD (for example, about 490nm/min) The undoped silicate glass of formation and by LPCVD (such as 120nm/min) formed undoped silicate glass between The comparison of etch-rate in buffered hydrofluoric acid.
With reference to 3A and 3B, separator can be formed by be alternately stacked (32,42) of insulating layer 32 and sacrificial material layer 42 Groove 47.Separator groove 47 can be for example by being alternately stacked application above (32,42) and patterning photoresist (photoresist) layer transmits the pattern in patterned photoresist layer to be formed and by being alternately stacked (32,42) To the top surface of the substrate 8 positioned at the bottom for being alternately stacked (32,42).Separator groove 47 is laterally extended in the horizontal direction. In one embodiment, separator groove 47 can have substantially homogeneous width, and can be parallel to each other.Separator groove 47 It can will be alternately stacked (32,42) and laterally be divided into multiple portions.The pattern of separator groove 47 can divide with what be will be subsequently formed Pattern from device dielectric medium structure is identical.
With reference to figure 4A and 4B, each separator groove 47 can be filled with the second dielectric substance discussed above.Second Dielectric substance is also referred to as separator insulating materials.Compare in buffered hydrofluoric acid as described above, the second dielectric substance has The low etch-rate of first dielectric substance of insulating layer 32.For example, isolator insulating materials can be undoped silicate Glass (for example, LPCVD silica).For example, pass through chemical-mechanical planarization (chemical mechanical Planarization, CMP), groove etching or combination, separator insulation material can be removed from the top surface being alternately stacked The redundance of material.The remainder of the separator insulating materials of deposit forms separator dielectric medium structure 45.In an implementation In example, separator dielectric medium structure 45 can be alternately stacked the various pieces of (32,42) with lateral separation.
Each separator dielectric medium structure 45 can be extended by being alternately stacked (32,42), i.e., prolong from the top surface of substrate 8 Reach the top surface for being alternately stacked (32,42).Therefore, what is formed at the processing step of Fig. 2A and 2B is alternately stacked (32,42) It is divided into the part of multiple lateral separations by separator dielectric medium structure 45, it is therein each including being alternately stacked (32,42) Discrete parts.
With reference to 5A and Fig. 5 B, can for example by applying mask layer on (32,42) are alternately stacked, patterned mask layer with And pattern is transmitted to lead to by being alternately stacked (32,42) in mask layer by the anisotropic etching of such as reactive ion etching It crosses and is alternately stacked (32,42) formation memory opening 49.Mask layer can include photoresist layer and optionally include additional Layer of hard mask material, such as carbon-coating.Then can mask layer for example be removed by ashing.Each memory opening 49 can be from friendship The top surface positioned at the substrate for being alternately stacked (32,42) bottom is extended perpendicularly into for the top surface for stacking (32,42).Each deposit Reservoir opening 49 can be between a pair of separated device dielectric medium structure 45, which is in Fig. 3 A and 3B The step of at the remainder of separator dielectric medium structure that is formed.
In one embodiment, separator dielectric medium structure 45 can be divided into two physics point by each memory opening 49 From part.In this case, each memory opening 49 being alternately stacked in (32,42) can be extended through positioned at corresponding Separator dielectric medium structure 45 in separator insulating materials, and separator dielectric medium structure 45 can be divided into two horizontal strokes To the part of separation.
Each separator dielectric medium structure 45 can prolong in forward position the first horizontal direction ld1 for forming memory opening 49 It stretches, and can be multiple to be divided by the formation of the memory of the part by separator dielectric medium structure 45 opening 49 Separator dielectric medium structure 45.It is exported from the identical separator dielectric medium structure 45 provided such as at the processing step of Fig. 4 A and 4B Each multiple separator dielectric medium structures 45 can be arranged along the first horizontal direction ld1, and can be by being alternately stacked It is spaced that (32,42) are stored by opening 49.From the identical separator provided such as at the processing step of Fig. 4 A and 4B Each multiple separator dielectric medium structures 45 derived from dielectric medium structure 45 can have vertical sidewall, which is located at one To in vertical plane, vertical plane is included in extending along the first horizontal direction ld1 at the processing step of Fig. 4 A and 4B The vertical plane of the side wall of corresponding separator dielectric medium structure 45.In multiple separator dielectric medium structures 45 and memory opening 49 Each the top for being alternately stacked (32,42) can be extended perpendicularly into from the bottom for being alternately stacked (32,42).Substrate The top surface of semiconductor layer 10 can be physically exposed to the bottom of each memory opening 49.
With reference to 6A-6C, the side wall of insulating layer 32 is by isotropic etching process and lateral recesses.It is lost by isotropism Quarter process can etch separates device dielectric medium structure 45 parallel physics expose portion.Isotropic etching process can be used Hydrofluoric acid, dilute hydrofluoric acid, buffered hydrofluoric acid or including at least another acid or its variant of diluent (such as deionized water) Wet etch process.Alternatively, isotropic etching process can be the gas phase etching process using HF steam.Alternatively Different etch chemistries can be used in ground, with second than the separator dielectric medium structure 45 around memory opening 49 First dielectric substance of the higher etch-rate etching isolation layer 32 of dielectric substance.
In one embodiment, the first dielectric substance of insulating layer 32 can be during isotropic etching process with First silica material of the first etch-rate removal, and the second dielectric substance of separator dielectric medium structure 45 can be The second silica material removed during isotropic etching process with the second etch-rate.First etch-rate and the second erosion The ratio of etching speed can be in the range of 1.5 to 1000, such as from 2 to 5.In one embodiment, the side of insulating layer 32 The lateral recesses distance of wall can be in the range of from 4nm to 30nm, such as from 5nm to 20nm, although smaller can also be used With the lateral recesses distance of bigger.
In one embodiment, the side wall of the physics exposure of separator dielectric medium structure 45 can be developed into isotropism Vertically constant convex during etching process.In other words, the side of the physics exposure of separator dielectric surface 45 Wall can have the convex horizontal cross-sectional shapes that will not change with the transformation along vertical direction.
With reference to shown in figure 7A-7C, etching the etchant of sacrificial material layer 42 can be introduced into go by memory opening 49 Except sacrificial material layer 42.Etchant is chosen to sacrificial material layer 42 and insulating layer 32 and substrate 8 is selectively removed. For example, if insulating layer 32 includes silica and sacrificial material layer 42 includes silicon nitride, using the wet etching of hot phosphoric acid It can be used with the removal sacrificial material layer 42 to 32 selectivity of insulating layer.Therefore, sacrificial material layer 42 is relative to insulating layer 32 are selectively etched out of each memory opening 49.In one embodiment, sacrificial material layer 42 can be from device region Domain 100 is completely removed.Therefore, laterally expanded at each grade that memory opening 49 is selectively located at before layer 42 Exhibition.
Interlayer cavity (that is, recess) 43 is formed at each layer of sacrificial material layer 42, and is connected to multiple deposit Reservoir opening 49.Separator dielectric medium structure 45 can provide the structure branch to insulating layer 32 after the formation of interlayer cavity 43 Support.Each interlayer cavity 43 can be positioned at insulating layer 32 vertically adjacent to between.The flat bottom surface of upper insulating layer coating 32 and The flat top surface of following insulating layer 32 can be exposed to each interlayer cavity 43 with physics.
With reference to figure 8A-8C, at least one conductive material (such as at least one metal material) can be deposited on multiple interlayers On the side wall of insulating layer 32 in cavity 43, around each memory opening 49 and above the top surface being alternately stacked. As it is used herein, metal material refers to the conductive material for including at least one metallic element.At least one conductive material can Be deposited on insulating layer 32 vertically adjacent to (that is, in cavity 43) in the space between.
Conductive material can be deposited by conformal deposition method, and this method can be such as chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), without electricity Plating, plating or combination.Conductive material can be metal element, the intermetallic alloy of at least two metal elements, at least one Conductive nitride, conductive metal oxide, conductiving doping semi-conducting material, the conductive metal-semiconducting alloy of metal element are (all Such as metal silicide), its alloy and combinations thereof or stack.The non-restrictive illustrative that can be deposited in multiple interlayer cavitys 43 Metal material includes tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt and ruthenium.In one embodiment, metal material can be with Metal and/or metal nitride including such as tungsten.In one embodiment, for filling the metal material of multiple interlayer cavitys 43 Material can be the combination of titanium nitride layer and tungsten packing material.
In one embodiment, can metal material be deposited by chemical vapor deposition or atomic layer deposition.At one In embodiment, metal material can use at least one fluorine-containing precursor gas as precursor gas during deposition process.One In a embodiment, the molecule of at least one fluorine-containing precursor gas cam includes at least one tungsten atom and at least one fluorine atom Compound.For example, if metal material includes tungsten, WF can be used during deposition process6And H2。
Continuous conduction material part 46L can in multiple interlayer cavitys 43, on the side wall of insulating layer 32 and alternately heap Be formed as single continuous structure above folded top surface.Therefore, each sacrificial material layer may alternatively be continuous conduction material Expect the corresponding portion of part 46L, form corresponding conductive layer.After the deposit of conductive material, each memory opening 49 It is middle to there is the cavity 49' surrounded by the conductive material deposited.
With reference to figure 9A-9C, the part of the conductive material of continuous conduction material part 46L can be by etching process from storage Device opening 49 removes, which can be isotropic etching process or anisotropic etch process.Using each to same In the case of property etching process, the removal of conductive material can be multiple so that pass through isotropic etching process, insulating layer 32 Side wall be physically exposed in each memory opening 49.In addition, isotropic etching process can be in the side of insulating layer 32 Wall physics terminates when being exposed to the periphery of each memory opening 49 so that conductive layer 46 can reside in each of insulating layer 32 Vertically adjacent to between.In the case of using anisotropic etch process, insulation material layer 32 may be used as etching mask, and And the entirety of the conductive material of the deposit in anisotropic etching removal memory opening 49 can be passed through.Anisotropic etching can It is selective with the semi-conducting material for substrate 8.
Conductive layer 46 (its be deposit conductive material remainder) side wall can with it is overlying and/or bottom It or can (it be insulating layer 32 relative to the side wall that memory is open in the identical vertical plane of the side wall of insulating layer 32 Side wall) it is laterally away from respective memory opening 49.Extend through be alternately stacked (32,42) and at least have in Fig. 6 A- At the processing step of 6C respective memory opening 49 volume memory opening 49 can by the removal of conductive material come It provides.
With reference to figure 10A-10C, memory heap stack structure 55 (that is, structure with layer (52,54,56,60)) is including storage Device film 50 (that is, film with layer (52,54,56)) and vertical semiconductor raceway groove 60 can be formed in each memory opening 49 In.Each memory film (52,54,56) can include barrier dielectric layer 52, charge storage region 54 and tunnel from outside to inside Dielectric 46.
Barrier dielectric layer 52 includes at least one dielectric substance, such as dielectric metal oxide and/or dielectric Conductor oxidate.As used herein, dielectric metal oxide refers to include at least one metallic element and at least oxygen Dielectric substance.Dielectric metal oxide can substantially be made of at least one of metallic element and oxygen or can be with base It is made of on this at least one metallic element, oxygen and at least one nonmetalloid (such as nitrogen).In one embodiment, stop Dielectric layer 52 can be included with electric medium constant (electricity Jie i.e. with the electric medium constant more than silicon nitride more than 7.9 Matter constant) dielectric metal oxide.In one embodiment, barrier dielectric layer 52 can include aluminium oxide, silica Or its stacking.The thickness of barrier dielectric layer 52 can be in the range of 2nm to 10nm, although smaller and bigger can also be used Thickness.
Charge storage region 54 can include the continuous of charge trapping material to extend vertically layer.Charge trapping material can be with It is dielectric charge trapping material, can is such as silicon nitride.Alternatively, charge storage region 54 may include such as adulterating The conductive material of polysilicon or metal material, the conductive material are for example recessed by the transverse direction being formed in sacrificial material layer 42 Multiple be electrically isolated partly (such as floating boom) is patterned into falling into.In one embodiment, charge storage region 54 can be with body Now be extended to from the bottom for being alternately stacked (32,46) top being alternately stacked single layer of charge storage material (32, 46) (such as silicon nitride layer).
Tunneling dielectric 56 includes dielectric substance, can be held under the conditions of suitable electrical bias by the dielectric substance Row charge tunnelling.Depending on the operation mode of monolithic three dimensional NAND string storage component part to be formed, can be noted by hot current-carrying Enter or transmit to perform charge tunnelling by Fowler-Nordheim tunnelling charge inducing.Tunnel dielectric 56 can include oxidation Silicon, silicon nitride, silicon oxynitride, dielectric metal oxide (such as aluminium oxide and hafnium oxide), dielectric metal oxynitrides, electricity Metal clad silicate, their alloy, and/or combination thereof.In one embodiment, tunnel dielectric 56 can include The stacking of first silicon oxide layer, silicon oxynitride layer and the second silicon oxide layer, the stacking are commonly referred to as that ONO is stacked.In an implementation In example, Tunneling dielectric 56 can include the silicon oxide layer for being substantially free of carbon or the silicon oxynitride layer substantially free of carbon.Tunnel The thickness of dielectric 56 can be in the range of 2nm to 20nm, but can also use the thickness of smaller and bigger.In same storage Device opening 49 in one group of Tunneling dielectric 56, charge storage region 54 and barrier dielectric 52 collectively form memory film (52, 54,56).
Vertical semiconductor raceway groove 60 includes such as at least one elemental semiconductors, at least one III-V compound Semi-conducting material, at least one II-VI group compound semiconductor materials, at least one organic semiconducting materials or known in the art Other semi-conducting materials semi-conducting material.In one embodiment, vertical semiconductor raceway groove 60 includes non-crystalline silicon or polycrystalline Silicon.Vertical semiconductor raceway groove 60 can pass through such as low-pressure chemical vapor phase deposition (low pressure chemical vapor Deposition, LPCVD) general character) deposition process formed.The thickness of vertical semiconductor raceway groove 60 can be 2nm to 10nm's In the range of, although the thickness of smaller and bigger can also be used.In one embodiment, vertical semiconductor raceway groove 60 can pass through External semiconductor channel layer, the deposit of anisotropic etching and the deposit of internal semiconductor channel layer are formed, anisotropy Etching removes the horizontal component of external semiconductor channel layer and memory film (56,54,52) and is physically exposed to each deposit The top surface of the substrate semiconductor layer 10 of 49 lower section of reservoir opening, the internal semiconductor channel layer is in the every of substrate semiconductor layer 10 On the madial wall of a top surface physically exposed and external semiconductor channel layer.External semiconductor channel layer and memory opening Each adjacent sets of internal semiconductor channel layer inside 49 form vertical semiconductor raceway groove 60.In each memory opening 49 Be not deposited material layer (52,54,56,60) filling volume in there may be cavity.
In the case where each memory opening 49 is not filled up completely by vertical semiconductor raceway groove 60, electric Jie can be deposited Material is to fill any residual cavity in each memory opening 49.Dielectric substance can include silica or organosilicon Silicate glass, and can be by the general character deposition process of such as low-pressure chemical vapor phase deposition (LPCVD) or by such as rotating The self-planarization deposition process of coating deposits.The redundance of dielectric substance can be from the top table for being alternately stacked (32,46) It is removed above face.Each remainder of dielectric substance forms dielectric core 62.
With reference to figure 11A-11C, dielectric core 62 can (it can be isotropic etching process or each by etching process Anisotropy etching process) vertically it is recessed.It can be filled with the doped semiconductor materials of the doping with the first conduction type Recess.The doped semiconductor materials of deposit can include such as DOPOS doped polycrystalline silicon, can pass through doping in situ and ion implanting At least one of doping or combination is adulterated.Such as pass through chemical-mechanical planarization (chemical mechanical Planarization, CMP) or groove etching to form drain region 63, can be from being alternately stacked on the top surface of (32,46) Side removes the redundance of the semi-conducting material of deposit.
Memory heap stack structure (52,54,56,60), laterally dielectric core 62 and contact memory are shown in Figure 12 The geometric properties of the separator dielectric medium structure 45 of stacked structure (52,54,56,60).
A pair of separated device dielectric medium structure 45 shown in Figure 12, which extends through, is alternately stacked (32,46), i.e., from alternately heap The bottom of folded (32,46) extends vertically up to the top for being alternately stacked (32,46).In addition, this is to separator dielectric medium structure 45 are laterally extended along the first horizontal direction ld1.Memory heap stack structure (52,54,56,60) including memory film (52,54, 56) it and vertical semiconductor raceway groove 60, and extends through and is alternately stacked (32,46).Memory heap stack structure (52,54,56,60) With a pair of of the first side wall 491, the side wall of a pair of the first side wall 491 contact a pair of separated device dielectric medium structure 45, and have Have along outwardly projecting a pair of of the second sidewalls 492 of the second horizontal direction ld2.The first side wall 491 is from a pair of of second sidewall 492 Substantially vertical edge 493 is laterally inward recess.In one embodiment, the first side wall 491 can have vertically extending recessed Surface, and second sidewall 492 can have vertically extending convex surface.
Dielectric core 62 can reside in vertical semiconductor raceway groove 60, and can have towards corresponding separator electricity A pair of recessed side wall of dielectric structure 45 side wall convex with the adjacent a pair to recessed side wall.The recessed side wall of dielectric core 62 With the internal side wall of convex side wall contact vertical semiconductor raceway groove 60.In one embodiment, memory heap stack structure (52,54, 56,60) vertical edge 493 of second sidewall with the angle [alpha] in the range of 45 degree to 135 degree with this to detaching dielectric medium structure 45 respective side walls are adjacent.In one embodiment, the angle between the first horizontal direction ld1 and the second horizontal direction ld2 can With in the range of from 60 degree to 120 degree.For example, angle between the first horizontal direction ld1 and the second horizontal direction ld2 can be with It is about 90 degree.
In one embodiment, vertical semiconductor raceway groove 60 can include a pair of convex exterior side wall and a pair of recessed outside The corresponding second sidewall 492 of side wall, a pair of convex exterior side wall and memory heap stack structure (52,54,56,60) is with memory The thickness tm of film (52,54,56) is spaced apart, a pair of recessed exterior side wall and the phase of memory heap stack structure (52,54,56,60) The first side wall 491 is answered to be spaced apart with the thickness tm of memory film (52,54,56).
In one embodiment, the lateral separation distance between the convex exterior side wall of a pair of vertical semiconductor raceway groove 60 Lsd2 is more than the lateral separation distance lsd1 between a pair of recessed exterior side wall of vertical semiconductor raceway groove 60.Memory film (52, 54,56) it can include contacting and laterally surrounding with vertical semiconductor raceway groove 60 Tunneling dielectric of vertical semiconductor raceway groove 60 56 and the charge storage region of the part of electric charge capture layer 54 that is presented as at the grade of conductive layer 46.Electric charge capture layer Extend through the pantostrat for being alternately stacked (32,46) and laterally surrounding tunnel dielectric 60.Memory film (52,54,56) can Further comprise laterally surrounding electric charge capture layer and 491 He of a pair of of the first side wall with memory heap stack structure (52,54,56) The barrier dielectric 52 of a pair of of second sidewall 492.
The storage component part of the disclosure can include the vertical nand device for being located at 8 top of substrate.Conductive layer 46 can wrap Include or may be electrically connected to the respective word of NAND device.Substrate 8 can include silicon substrate.Vertical nand device can include The array of monolithic three dimensional NAND string on silicon substrate.In first device level of the array of monolithic three dimensional NAND string at least The top of another memory cell in the second device level of array that one memory cell is located at monolithic three dimensional NAND string.Silicon Substrate can include integrated circuit, which includes the drive circuit for storage component part disposed thereon.
The array of monolithic three dimensional NAND string can include multiple semiconductor channels so that each in multiple semiconductor channels A at least one end (that is, vertical semiconductor raceway groove 60) extends substantially perpendicular to the top surface of substrate 8.Monolithic three dimensional The array of NAND string can include multiple charge storage cells.Each charge storage cell can be located in multiple semiconductor channels Near corresponding one.The array of monolithic three dimensional NAND string can be included with the top surface extension for being arranged essentially parallel to substrate 8 Bar shape multiple control gate electrodes (being such as presented as conductive layer 46).Multiple control gate electrodes can at least include position The first control gate electrode in the first device level and the second control gate electrode in the second device level.
Vertical semiconductor raceway groove 60 includes adjacent with the second sidewall 492 of memory heap stack structure (52,54,56,60) A pair of of active channel section ACS and with 491 adjacent pair of the first side wall of memory heap stack structure (52,54,56,60) without Source channel section ICS.
Figure 14 is the circuit diagram of the array region of any exemplary device structures of the disclosure.Circuit diagram represents Multiple NAND strings.Each NAND string includes multiple memory cells.
Collective reference Fig. 1, Figure 11 A-11C, Figure 12 and Figure 14, NAND memory device can be included with main surface 9 Substrate 8.A memory cell is disposed in the first NAND string more than first, and first NAND string is multiple to be substantially perpendicular to The first party of the main surface 9 of substrate 8 in device level upwardly extends.Each more than first in a memory cell is located at lining In corresponding one in multiple device levels of 8 top of bottom.
Each memory cell in NAND string includes the first control gate electrode 461, and (it is first of conductive layer 46 Point) a part and second control gate electrode 462 a part, this first control gate electrode 461 be located at memory film The adjacent of the first part 50A (it is located on the side of corresponding a pair of separated device dielectric medium structure 45) of (52,54,56), Second control gate electrode 462 is located at the second part 50B of memory film (52,54,56), and (it is located at corresponding a pair of separated On the opposite side of device dielectric medium structure 45) adjacent.Second control gate electrode 462 and first controls 461 electricity of gate electrode Insulation.
First control gate electrode 461 upwardly extends, and the second control gate in the second party for being basically parallel to main surface 9 Pole electrode 462 extends and is being arranged essentially parallel to main surface 9 and transverse to the third direction of second direction in a second direction It is upper to be spaced apart with the corresponding first control gate electrode 461.Each memory cell can include memory film (52,54,56) First part 50A and memory film (52,54,56) second part 50B, the first part of memory film (52,54,56) 50A is located between the first control gate electrode 461 and the first part of semiconductor channel 60, and the of memory film (52,54,56) Two part 50B are located between the first control gate electrode 462 and the second part of semiconductor channel 60.
Therefore, each memory cell of the present embodiment includes the single part of vertical semiconductor raceway groove 60 (that is, being electrically connected Continuous, single part), first memory membrane part 50A, second memory membrane part 50B, positioned at first memory membrane part 50A Adjacent first control gate electrode 461 at least part and the adjacent positioned at second memory membrane part 50B First control gate electrode 462 at least part.First control gate electrode 462 and first control gate electrode 461 with And first memory film is electrically isolated.In other words, the memory cell of the present embodiment is included in the public affairs in same level device level Raceway groove and memory film and the control gate electrode of separation altogether.
It can include the first wordline and the second wordline per level-one control gate pole electrode.First wordline can include pectination wordline WLL/410 has the contact with platform part (as shown in Figure 1) that is located in the first stepped contact region (300) and from platform Contact portion extends to multiple tips (461,463,465,467) in device area.Second wordline can include pectination wordline WLR/420 has the contact with platform part (not shown) that is located in the second stepped contact area (not shown) and from flat Platform contact portion extends to multiple tips (462,464,466,468) in device area.
At least a pair of of lower part selection gate electrode { (SGSL/430), (SGSR, 450) } (for example, be embodied as such as Figure 15 and The drain selection gate electrode of at least one bottommost conductive layer 44 shown in 17) main surface 9 of substrate 8 and multiple can be located at Between memory cell.This lower part selection gate electrode { (SGSL/430), (SGSR, 450) } can include the first lower part and select Select gate electrode (SGSL/430) and the second lower part selection gate electrode (SGSR, 450) }.First lower part selection gate electrode (SGSL/430) it may be coupled to the drain selection grid on the side of each memory heap stack structure (52,54,56,60) First subset of electrode (441,443,445,447), and the second lower part selection gate electrode (SGSR/450) may be coupled to On the opposite side of each memory heap stack structure (52,54,56,60) drain selection gate electrode (442,444,446, 448) second subset.
At least a pair of of top selection gate electrode (SGDL, SGDR) is (for example, be such as embodied as leading at least one top The drain electrode selection gate electrode 48 as shown in Figure 15 and 17 of electric layer 46) can be located at be alternately stacked in the top of (32,46) On multiple storage units.Such top selection gate electrode (SGDL, SGDR) can include the first top selection gate electricity Pole SGDL and the second top selection gate electrode SGDR.First top selection gate electrode SGDL may be coupled to be located at and each deposit First subset of the drain electrode selection gate electrode of the side of reservoir stacked structure (52,54,56,60), and the second top selects Gate electrode SGDR may be coupled to the drain selection on the opposite side of each memory heap stack structure (52,54,56,60) The second subset of gate electrode.
Each lower end of semiconductor channel may be electrically connected to source electrode line SL, and source electrode line SL can be presented as rear contact Through-hole structure 76.As shown in Figure 15 and 17, each upper end of semiconductor channel can pass through corresponding drain region 63 and part Interconnection (that is, electrode) 92 is connected to corresponding bit line 96 (for example, BL1, BL2, BL3, BL4).
It, can be by the way that the voltage of about 5-7V to be applied to the top selection grid of selection in non-limitative illustration example The voltage of about 0V is applied to non-selected top selection gate electrode (for example, SGDR/ by pole electrode (for example, SGDL/481) 482) selection line of about 3-5V reading voltage, is applied to the control gate electrode for being connected to selection (for example, the first control gate Pole electrode 461) selection wordline (for example, WLL/410) and the non-selected line of about 7-8V read into voltage be applied to connection It is applied to the non-selected wordline of non-selected control gate electrode and by negative 3-5V electric in the control grid with selection The second of extremely identical grade/unit controls gate electrode 462 to perform 49 (for example, MH1, MH2, MH3, MH4) of memory opening In memory cell read operation.The voltage of about 5-7V can be applied to the lower part selection gate electrode (example of selection Such as, SGSL/430), and the voltage of about 0V can be applied to be connected to identical memory heap stack structure (52,54,56, 60) the non-selected lower part selection gate electrode (for example, SGSR/450) (see Fig. 1).The voltage of about 1-2V can be applied To selected bit line (such as BL1), and about 0V voltages can be applied to non-selected bit line (such as BL2, BL3, BL4). The source electrode line SL/76 that can be presented as rear contact through-hole structure 76 can be biased in about 0-1V.It can contract as needed Put and/or adjust various voltages.
It, can be by the way that the voltage of about 2-3V be applied to selected top selection grid in non-limitative illustration example The voltage of about 0V is applied to selected top selection gate electrode (for example, SGDR/ by pole electrode (for example, SGDL/481) 482), the selection line program voltage of about 18-20V is applied to and is connected to selected control gate electrode (for example, the first control Gate electrode 461 processed) selection wordline (for example, WLL/410) and the non-selected program voltage of about 7-9V is applied It is performed on memory cell to the non-selected wordline (for example, WLR/420) for being connected to non-selected control gate electrode Programming operation.The voltage of about 0V can be applied to selected lower part selection gate electrode (for example, SGSL/430), and The voltage of about 0V can be applied to non-selected lower part selection gate electrode SGSR/450.The voltage of about 0V can be applied Be added to selected bit line (for example, BL1), and the voltage of about 2-3V can be applied to non-selected bit line (for example, BL2, BL3, BL4).Source electrode line SL can be biased in about 1-3V.During erasing operation, selected top selection gate electrode 10-12V can be biased to lower part selection gate electrode, selected bit line and source electrode line can be biased to 18-20V simultaneously And remaining line and electrode are no biasing (for example, about 0V).
With reference to figure 15-17, example arrangement can include memory device and memory heap stack structure (52,54,56,60), The memory device includes the stacking of alternating layer, which includes the insulating layer 32 being located on substrate 8 and conductive layer 46, the storage In device stacked structure (52,54,56,60) is open positioned at the memory for extending through stacking, and including having vertical component Semiconductor channel 60, direction extension of the vertical component along the top surface perpendicular to substrate 8.Memory heap stack structure (52,54, 56,60) multigroup at least two charge storage cell including being located at around the semiconductor channel 60 at each grade of conductive layer 46 (for example, layer 46A in the first order and layer 46B in the second level under the second level).Every group of at least two charge storages Element includes charge storage cell, is located at the grade identical with corresponding conductive layer 46, and pass through at least one corresponding tunnel Wear dielectric 56 with each other, be electrically isolated, and pass through at least one corresponding barrier dielectric 52 and phase with semiconductor channel 60 The control gate electrode (it is the adjacent part of conductive layer 46) answered is electrically isolated.
Separator dielectric medium structure 45 extend through stacking, memory heap stack structure 55 lateral wall contact portion and It is laterally separated the control gate electrode 46 of multiple charge storage cells (it is the part of charge storage region 54).It is patterned Conductive layer 46 includes the control gate electrode in multigroup at least two charge storage cell 54.Every group of at least two charge storages member Part includes being located at two regions in the continuous part of the electric charge capture layer of level-one.
Separator dielectric medium structure 45 can extend through the contact of stacking, memory heap stack structure (52,54,56,60) Side wall and the control gate electrode for being laterally separated multiple charge storage cells.In one embodiment, at least one blocking Dielectric can be the single continuous barrier dielectric layer for contacting each conductive layer 46 and every group of at least two charge storage cells 52.At least one corresponding Tunneling dielectric is to extend vertically through stacking and transversely about the single of semiconductor channel 60 Continuous Tunneling dielectric 56.
Example arrangement can include storage component part, include being located at insulating layer 32 above substrate 8 and patterned Conductive layer 46 is alternately stacked.Each memory heap stack structure (52,54,56,60) includes multiple memory cells, is arranged Into the string that upwardly extends of first party in the main surface 9 in a direction substantially perpendicular to the substrate 8 in multiple device levels.Multiple memories Each in unit is located in corresponding one in multiple device levels of 8 top of substrate.Semiconductor channel 60 extends through All grades in multiple device levels in each memory heap stack structure (52,54,56,60).
Embodiment of the disclosure is retained by reducing reading interference and improving data come for including vertical semiconductor raceway groove 60 Vertical field-effect transistor the distribution of better threshold voltage is provided.It is non-by providing spill for inactive channel portion ICS The channel portion ICS of activity is influenced by weaker fringe field, because inactive channel portion ICS is located at than reference configuration Further from the place of wordline (control grid electrode), in the reference configuration, inactive channel portion is not recessed.Therefore, it is applying During adding Vpass voltages, inactive channel portion ICS is received in leakage current modulation and is interfered less with.Therefore, the disclosure is matched Excellent transistor performance can be provided for every grade of multiple-unit memory heap stack structure by putting.
Although aforementioned be related to specific embodiment, it should be appreciated that the present disclosure is not limited thereto.Those of ordinary skill in the art will It will recognize that, the disclosed embodiments can be carry out various modifications, and such modification is intended within the scope of this disclosure. In the case of being shown in the disclosure using specific structure and/or the embodiment of configuration, it is to be understood that the disclosure can be used and be provided Any other functionally equivalent compatible structure and/or configuration put into practice, as long as these replacements are not forbidden clearly or separately It is known to be impossible for those of ordinary skills outside.Herein cited all publications, patent application and specially Profit is incorporated herein by reference in their entirety.

Claims (26)

1. a kind of storage component part, including：
Insulating layer and conductive layer on substrate are alternately stacked；
A pair of separated device dielectric medium structure extends through and described be alternately stacked and laterally prolong along the first horizontal direction It stretches；And
Memory heap stack structure, memory heap stack structure include memory film and extend through it is described be alternately stacked vertical partly lead Bulk channel, memory heap stack structure have a pair of of the first side wall of the side wall of contact a pair of separated device dielectric medium structure, and have Along outwardly projecting a pair of of the second sidewall of the second horizontal direction, wherein base of the first side wall from the pair of second sidewall Vertical edge is laterally inwardly recessed in sheet.
2. storage component part according to claim 1, wherein：
The first side wall has the recessed surface vertically extended；And
Second sidewall has the convex surface vertically extended.
3. storage component part according to claim 1, further includes dielectric core, the dielectric core has towards corresponding A pair of recessed side wall of separator dielectric medium structure and a pair of convex side wall of adjacent the pair of recessed side wall.
4. storage component part according to claim 1, wherein the pair of separator dielectric medium structure replaces heap from described The folded bottom extends perpendicularly into the top being alternately stacked.
5. storage component part according to claim 1, wherein the vertical edges of the second sidewall of the memory stacking structure Edge abuts the respective side walls of the pair of separator dielectric medium structure with the angle in the range of 45 degree to 135 degree.
6. storage component part according to claim 1, wherein first horizontal direction and second horizontal direction it Between angle in the range of from 60 degree to 120 degree.
7. storage component part according to claim 1, wherein vertical semiconductor raceway groove includes：
A pair of convex exterior side wall, with the thickness of memory film second sidewall interval corresponding with memory heap stack structure It opens；With
A pair of recessed exterior side wall, with the thickness of memory film the first side wall interval corresponding with memory heap stack structure It opens.
8. storage component part according to claim 8, wherein lateral separation between the pair of convex exterior side wall away from With a distance from more than the lateral separation between the pair of recessed exterior side wall.
9. storage component part according to claim 1, wherein
The insulating layer is included in first silica material in buffered hydrofluoric acid with the first etch-rate；
The pair of separator dielectric medium structure is included in the second silica material in buffered hydrofluoric acid with the second etch-rate Material；And
The ratio of first etch-rate and the second etch-rate is in the range of 2 to 5.
10. storage component part according to claim 1, wherein：
The insulating layer includes selection from borosilicate glass, phosphosilicate glass, boron phosphorus silicate glass, fluosilicate glass The material of glass, organic silicate glass and combinations thereof；And
The pair of separator dielectric medium structure includes undoped silicate glass.
11. storage component part according to claim 1, wherein the memory film includes：
It is contacted with vertical semiconductor raceway groove and transversely about the Tunneling dielectric of vertical semiconductor raceway groove；And
Transversely about the electric charge capture layer of Tunneling dielectric.
12. storage component part according to claim 11, wherein the memory film is also included transversely about the electricity Lotus capture layer and the pair of the first side wall with the memory heap stack structure and the blocking of the pair of second sidewall Dielectric.
13. storage component part according to claim 1, wherein：
The storage component part includes the vertical nand device being located on substrate；
The conductive layer includes or is electrically connected to the corresponding wordline of NAND device；
The substrate includes silicon substrate；
The vertical nand device includes the array of the monolithic three dimensional NAND string on silicon substrate；
At least one of first device level of the array of monolithic three dimensional NAND string memory cell is located at monolithic three dimensional NAND string Array the second device level in another memory cell on；
Silicon substrate includes integrated circuit, and the integrated circuit includes the drive circuit for storage component part disposed thereon； And
The array of monolithic three dimensional NAND string includes：
Multiple semiconductor channels, at least one end of each in plurality of semiconductor channel are substantially perpendicular to substrate Top surface extension；
Multiple charge storage cells, each charge storage cell are adjacent positioned at one corresponding with multiple semiconductor channels Place；And
Multiple control gate electrodes have the bar shape for the top surface extension for being arranged essentially parallel to substrate, the multiple control Gate electrode processed includes at least the first control gate electrode being located in the first device level and second in the second device level Control gate electrode.
14. a kind of method for manufacturing storage component part, including：
Being alternately stacked for insulating layer and sacrificial material layer is formed on substrate；
Multiple separator dielectric medium structures are formed, the multiple separator dielectric medium structure is arranged simultaneously along the first horizontal direction And it is laterally spaced by the memory opening by being alternately stacked；
Laterally it is recessed absolutely with the higher etch-rate of side wall of multiple separator dielectric medium structures than surrounding memory opening The side wall of edge layer；
Sacrificial material layer is replaced with conductive layer；And
The memory heap stack structure for including memory film and vertical semiconductor raceway groove is formed in each memory opening.
15. according to the method for claim 14, include wherein forming multiple separator dielectric medium structures：
Separator groove is formed by being alternately stacked；
Separator dielectric medium structure is formed in each separator groove；And
It is alternately stacked and multiple parts being laterally separated is divided by separator dielectric medium structure；And
Memory is configured to by each separator dielectric junction in part to be open, and separator dielectric medium structure is divided into multiple Separator dielectric medium structure.
16. it according to the method for claim 14, further includes：
It is open by memory and introduces etchant, the etchant is to the removal sacrificial material layer of insulating materials layer-selective；With And
Pass through memory opening depositing conductive material in insulating layer is vertically adjacent to the space between.
17. it according to the method for claim 16, wherein, after the deposit of conductive material, is enclosed by the conductive material deposited Around cavity be present in each storage opening, and the method is further included and is open removal conductive material from the memory Part is with the side wall for the recess for exposing insulating layer that is physically open from memory.
18. according to the method for claim 14, wherein each memory heap stack structure is formed in a pair of separated device dielectric On the side wall of structure and on the side wall of insulating layer.
19. according to the method for claim 14, wherein each memory heap stack structure, which has, contacts corresponding a pair of separated A pair of of the first side wall of the side wall of device dielectric medium structure, and with along outwardly projecting a pair of of the second side of the second horizontal direction Wall, wherein the first side wall is laterally inwardly recessed from the substantially vertical edge of the pair of second sidewall.
20. the method according to claim 11, wherein：
The first side wall has the recessed surface vertically extended；And
Second sidewall has the convex surface vertically extended.
Dielectric core is formed 21. according to the method for claim 14, being additionally included in each memory heap stack structure, it is described Dielectric core has towards the recessed side wall of a pair of corresponding separator dielectric medium structure and adjacent the pair of recessed side wall A pair of convex side wall.
22. according to the method for claim 14, wherein the multiple separator dielectric medium structure and memory opening The top being alternately stacked is extended perpendicularly into from the bottom being alternately stacked.
23. according to the method for claim 14, have wherein the vertical semiconductor raceway groove is formed：
A pair of convex exterior side wall, with the thickness of memory film second sidewall interval corresponding with memory heap stack structure It opens；With
A pair of recessed exterior side wall, with the thickness of memory film the first side wall interval corresponding with memory heap stack structure It opens.
24. according to the method for claim 23, wherein the lateral separation distance between the pair of convex exterior side wall is big Lateral separation distance between the pair of recessed exterior side wall.
25. the method according to claim 11, wherein：
The insulating layer is included in the first silica material formed by PECVD in buffered hydrofluoric acid with the first etch-rate Material；
The multiple separator dielectric medium structure is included in being formed by LPCVD with the second etch-rate in buffered hydrofluoric acid Second silica material；
The ratio of first etch-rate and the second etch-rate is in the range of 1.5 to 1000；And
Laterally it is recessed absolutely with the higher etch-rate of side wall of multiple separator dielectric medium structures than surrounding memory opening The step of side wall of edge layer, includes the use of buffered hydrofluoric acid and is etched selectively to insulating layer.
26. the method according to claim 11, wherein：
The storage component part includes the vertical nand device being located on substrate；
The conductive layer includes or is electrically connected to the corresponding wordline of NAND device；
The substrate includes silicon substrate；
Vertical nand device includes the array of the monolithic three dimensional NAND string on silicon substrate；
At least one of first device level of the array of monolithic three dimensional NAND string memory cell is located at monolithic three dimensional NAND string Array the second device level in another memory cell on；
Silicon substrate includes integrated circuit, and the integrated circuit includes the drive circuit for storage component part disposed thereon； And
The array of monolithic three dimensional NAND string includes：
Multiple semiconductor channels, at least one end of each in plurality of semiconductor channel are substantially perpendicular to substrate Top surface extension；
Multiple charge storage cells, each charge storage cell are adjacent positioned at one corresponding with multiple semiconductor channels Place；And
Multiple control gate electrodes have the bar shape for the top surface extension for being arranged essentially parallel to substrate, multiple control gates Pole electrode includes at least the first control gate electrode being located in the first device level and the second control in the second device level Gate electrode.
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