CN109524417A - 3D nand memory and forming method thereof - Google Patents
3D nand memory and forming method thereof Download PDFInfo
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- CN109524417A CN109524417A CN201811423518.0A CN201811423518A CN109524417A CN 109524417 A CN109524417 A CN 109524417A CN 201811423518 A CN201811423518 A CN 201811423518A CN 109524417 A CN109524417 A CN 109524417A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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Abstract
A kind of 3D nand memory and forming method thereof, the wherein forming method of the 3D nand memory, after forming stacked structure, it is not necessary that the peripheral region of stacked structure is first formed stepped region by multiple exposure mask and etching technics, several contact through holes can be formed in stacked structure directly on external zones, greatly simplify manufacture craft, it reduces the production cost, and, control gate and electrically conducting contact can be formed simultaneously, compared to the technique that existing control gate and electrically conducting contact are formed in different step, processing step is greatly simplified.And the generation for the problems such as forming method of 3D nand memory can also prevent mis-alignment, over etching and owe etching.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of 3D nand memory and forming method thereof.
Background technique
Nand flash memory is a kind of storage equipment more better than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.Currently, the 3D NAND of planar structure dodges
The limit of nearly true extension is deposited, in order to further improve memory capacity, reduces the carrying cost of every bit, proposes 3D knot
The 3D nand memory of structure.
In 3D nand memory structure, by the way of vertical stacking multi-layer data storage unit, stack is realized
3D nand memory structure.The forming process of existing 3D nand memory generally comprises: providing substrate, the substrate includes outer
Enclose area and core array area；Silicon nitride layer and the alternately stacked stack layer of silicon oxide layer is formed on the substrate, it is described to lamination cross
Across external zones and core array area；The stack layer of peripheral region is etched, stepped region is formed, the stepped region has several steps,
Each step is made of a lamination of the silicon nitride layer of adjacent layer and the composition of silicon oxide layer；Etch the heap in core array area
Lamination forms channel hole in stack layer；Memory block is formed in the channel hole；Silicon nitride layer is removed, silicon nitride is being removed
The position of layer forms metal control gate；After forming metal control gate, the dielectric layer of covering stacked structure is formed；Etch the medium
Layer, forms several contact through holes, several contact through holes expose the metal control gate surface of corresponding step in the dielectric layer；?
Several contact through holes fill metal, form several Metal contacts.
But the manufacture craft of existing 3D nand memory is complex.
Summary of the invention
The technical problem to be solved by the present invention is to how reduce the cost of manufacture of 3D nand memory.
To solve foregoing problems, the present invention provides a kind of forming methods of 3D nand memory, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes external zones and core array area；In the semiconductor substrate
External zones and core array area on form stacked structure, the stacked structure includes alternately stacked insulating layer and sacrificial layer；
The stacked structure on the external zones is etched, forms the different several contact through holes of depth in the stacked structure on external zones,
The bottom of several contact through holes exposes the sacrificial layer surface of different layers respectively；Several contact through holes side wall and
Layer of support material is formed on the surface of bottom surface and stacked structure；The sacrificial layer is removed, several cavitys are formed；Removal institute
The layer of support material of several contact through hole bottoms is stated, so that the cavity connection corresponding with bottom of each contact through hole；To institute
It states in several contact through holes and its cavity of corresponding connection and fills conductive material, the conduction for forming control gate and being connect with control gate
Contact portion.
Optionally, further includes: after forming layer of support material, etch the layer of support material and stacked structure, outside
It encloses and forms several pseudo- channel through-holes for exposing semiconductor substrate surface in the stacked structure in area and core array area, in core
Several channel through-holes for exposing semiconductor substrate surface are formed in stacked structure on array area；The shape in the channel through-hole
At storage organization；Pseudo- channel structure is formed in the pseudo- channel through-hole；After forming the storage organization and pseudo- channel structure, go
Except the sacrificial layer, several cavitys are formed.
Optionally, the forming process of the contact through hole includes: that the first figure is formed on the surface of the stacked structure
The mask layer of change there are the several of stacked structure surface exposed on external zones to open in the first patterned mask layer
Mouthful, several openings are arranged successively from the direction that external zones is directed toward core array area；On the described first patterned mask layer
Form photoresist layer；Carry out photoetching offset plate figure chemical industry skill, make the photoresist layer expose in the first patterned mask layer from
A farthest opening of core array area；Technique is performed etching, is to cover with the photoresist layer and the first patterned mask layer
Film etches the insulating layer of top in the stacked structure along the farthest opening, forms the first contact through hole, and described the
One contact through hole exposes the surface of the sacrificial layer of top insulating layer bottom；Photoetching offset plate figure chemical industry skill is carried out, the light is made
Photoresist layer exposes a remote opening of freestone heart array area second in the first patterned mask layer；Technique is performed etching, with
The photoresist layer and the first patterned mask layer are exposure mask, and the opening remote along described second etches in the stacked structure
The insulating layer of top, forms the second contact through hole, and second contact through hole exposes the sacrifice of top insulating layer bottom
The surface of layer, while continuing etching bottom sacrificial layer and insulating layer along the first contact through hole, so that the bottom of the first contact through hole
Expose the surface of the sacrificial layer of layer second from the bottom；Circulation carries out photoetching offset plate figure chemical industry skill and etching technics, successively exposes
Several openings from the direction that external zones is directed toward core array area, and it is sequentially etched the insulating layer and sacrificial layer of equivalent layer, directly
To several contact through holes of formation.
Optionally, the layer of support material is located at the first patterned exposure mask layer surface
Optionally, when removing sacrificial layer, the sacrificial layer has high etching selection ratio relative to layer of support material.
Optionally, the layer of support material is single-layer or multi-layer stacked structure.
Optionally, the layer of support material is the silica of single layer or the double stacked structure of silica and polysilicon.
Optionally, it before forming the pseudo- channel through-hole and channel through-hole, is formed in the backing material layer surface
The mask layer of second graphical, the mask layer of the second graphical fill full contact through hole.
Optionally, after forming the pseudo- channel through-hole and channel through-hole, the mask layer of the second graphical is removed.
Optionally, it is formed before storage organization in the channel through-hole, is formed in the bottom of the channel through-hole and partly led
Body epitaxial layer.
Optionally, the storage organization and pseudo- channel structure formed in same step or different step in formed.
Optionally, the storage organization includes at least electric charge capture layer and channel layer.
Optionally, after forming the storage organization and pseudo- channel structure, it is etched back to storage organization, in the insulating layer of top layer
Middle formation groove, filling semiconductor material forms plug in a groove.
Optionally, in the groove when filling semiconductor material, the also filling semiconductor material in the contact through hole.
Optionally, further includes: after forming the storage organization and pseudo- channel structure, etch the stacking in core array area
Structure, forms the grid separate slot for running through stacked structure, and the bottom-exposed of the grid separate slot goes out semiconductor substrate.
Optionally, after forming grid separate slot, the sacrificial layer is removed；Remove semiconductor material in contact through hole.
Optionally, when filling conductive material in Xiang Suoshu contact through hole and cavity, also filling is led in Xiang Suoshu grid separate slot
Electric material, the conductive material of the filling only cover the side wall and bottom surface of grid separate slot.
Optionally, further includes: be etched back to remove the conductive material of the grid separate slot side wall and bottom surface；It is being etched back to
After removing the grid separate slot side wall and the conductive material of bottom surface, isolation side walls are formed in the sidewall surfaces of grid separate slot；
It is formed on isolation side walls surface and fills full remaining grid separate slot conductive layer, form array common source.
Optionally, backing material layer surface and several cavitys after removing the sacrificial layer, in several contact through holes
Sidewall surfaces form high K film.
Optionally, the layer of support material of several contact through hole bottoms is removed, so that each contact through hole and bottom pair
High K film before the cavity connection answered, in the corresponding layer of support material for removing contact through hole bottom.
The present invention also provides a kind of 3D nand memories, comprising:
Semiconductor substrate, the semiconductor substrate include external zones and core array area；Positioned at the semiconductor substrate
Stacked structure on external zones and core array area, the stacked structure include alternately stacked insulating layer and control grid structure,
The control grid structure includes high K film and control gate；Several depth in the stacked structure on the external zones are different
Contact through hole, the bottom of several contact through holes exposes the control gate surface of different layers respectively；If logical positioned at the dry contact
The layer of support material of the sidewall surfaces in hole；Positioned at the layer of support material and corresponding control gate surface, and fill full contact through hole
Electrically conducting contact.
Optionally, further includes: several in the stacked structure on external zones and core array area expose semiconductor
The pseudo- channel through-hole of substrate surface, several ditches for exposing semiconductor substrate surface in stacked structure in core array area
Road through-hole；Storage organization in the channel through-hole；Pseudo- channel structure in the pseudo- channel through-hole.
Optionally, the material of the layer of support material is silica.
Optionally, the bottom of the channel through-hole also has semiconductor epitaxial layers, and the storage organization is located at outside semiconductor
Prolong on layer.
Optionally, the storage organization includes at least electric charge capture layer and channel layer.
Optionally, the storage organization top surface also has semiconductor material plug.
Optionally, further includes: in the stacked structure in core array area, through the grid separate slot of stacked structure；Position
Array common source in grid separate slot.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of the 3D nand memory, after forming stacked structure on external zones and core array area, etching
Stacked structure on the external zones forms the different contact through hole of several depth in the stacked structure on external zones, several
The bottom of contact through hole exposes the sacrificial layer surface of different layers respectively；In the side wall and bottom surface of several contact through holes
And layer of support material is formed on the surface of stacked structure；The sacrificial layer is removed, several cavitys are formed；If it is logical to remove dry contact
The layer of support material of hole bottom, so that the cavity connection corresponding with bottom of each contact through hole；If logical to the dry contact
Conductive material is filled in the cavity of hole and its corresponding connection, the electrically conducting contact for forming control gate and connecting with control gate.I.e. originally
Application is when forming electrically conducting contact and control gate, it is not necessary that the peripheral region of stacked structure is first passed through multiple exposure mask and etching work
Skill forms stepped region, and without being respectively formed electrically conducting contact and control gate by different steps, can be directly in external zones
On stacked structure in electrically conducting contact and control gate be formed simultaneously by integration making technology, greatly simplify production work
Skill.Also, stepped region is formed due to not needing, when forming electrically conducting contact, there is no the alignments of contact through hole and step to ask
Topic, and it is not necessarily to the stepped region of larger area, be conducive to the integrated level for improving device.Also, in several contact through holes
Layer of support material is formed on the surface of side wall and bottom surface and stacked structure, if layer of support material is in removal sacrificial layer formation
For maintaining the location and shape of the contact through hole formed, and the relative position of definition contact through hole and cavity when dry cavity,
By removing the high K film and layer of support material of each contact hole bottom, when being subsequently filled metal, thus may further
Guarantee the connection of electrically conducting contact and corresponding control gate, thus the integrated production of easy realization electrically conducting contact and control gate
Technique.
Further, the production of the channel through-hole of the pseudo- channel through-hole and core array area on external zones can carry out simultaneously,
Pseudo- channel structure is formed in pseudo- channel through-hole, when removing sacrificial layer, the puppet channel structure is used to support stacked structure, with
It prevents stacked structure from collapsing, storage organization is formed in the channel through-hole, with storing data.
Further, the forming process of the contact through hole includes: that the first figure is formed on the surface of the stacked structure
The mask layer of change there are the several of stacked structure surface exposed on external zones to open in the first patterned mask layer
Mouthful, several openings are arranged successively from the direction that external zones is directed toward core array area；On the described first patterned mask layer
Form photoresist layer；Carry out photoetching offset plate figure chemical industry skill, make the photoresist layer expose in the first patterned mask layer from
A farthest opening of core array area；Technique is performed etching, is to cover with the photoresist layer and the first patterned mask layer
Film etches the insulating layer of top in the stacked structure along the farthest opening, forms the first contact through hole, and described the
One contact through hole exposes the surface of the sacrificial layer of top insulating layer bottom；Photoetching offset plate figure chemical industry skill is carried out, the light is made
Photoresist layer exposes a remote opening of freestone heart array area second in the first patterned mask layer；Technique is performed etching, with
The photoresist layer and the first patterned mask layer are exposure mask, and the opening remote along described second etches in the stacked structure
The insulating layer of top, forms the second contact through hole, and second contact through hole exposes the sacrifice of top insulating layer bottom
The surface of layer, while continuing etching bottom sacrificial layer and insulating layer along the first contact through hole, so that the bottom of the first contact through hole
Expose the surface of the sacrificial layer of layer second from the bottom；Circulation carries out photoetching offset plate figure chemical industry skill and etching technics, successively exposes
Several openings from the direction that external zones is directed toward core array area, and it is sequentially etched the insulating layer and sacrificial layer of equivalent layer, directly
To several contact through holes of formation.When forming several contact through holes of step-like distribution using foregoing manner, compared to existing shape
At technique, the application is multiple without first passing through the peripheral region of stacked structure when forming several step-like contact through holes
Exposure mask and etching technics form stepped region, greatly simplify manufacture craft, reduce the production cost；And if forming dry contact
When through-hole, present stacked structure surface forms the first patterned mask layer, forms photoetching on the first patterned mask layer
Glue-line forms several contact through holes by multiple photoetching offset plate figure chemical industry skill and corresponding etching technics, if thus dry contact
The position of through-hole only depends on the position of several openings in the first patterned mask layer without regard to the position where stepped region
It sets, thus the generation of contact through hole Yu stepped region mis-alignment problem can be prevented, and over etching and deficient etching problem can be prevented
It generates；And by above-mentioned technique enable several contact through holes bottom expose equivalent layer sacrificial layer surface, thus
Without the size for considering stepped region, cost of manufacture is further decreased.
Further, after forming the storage organization and pseudo- channel structure, before removing the sacrificial layer, core battle array is etched
The stacked structure in area is arranged, the grid separate slot for running through stacked structure is formed, the bottom-exposed of the grid separate slot goes out semiconductor lining
Bottom can form array common source in grid separate slot.
Mis-alignment is not present in 3D nand memory of the invention, low manufacture cost, and 3D nand memory, and conduction connects
Contact portion and control gate poor contact, and the problem of to control gate over etching.
Detailed description of the invention
Fig. 1-19 is the structural schematic diagram of 3D of embodiment of the present invention nand memory forming process.
Specific embodiment
As described in the background art, the process is more complicated for existing 3D nand memory.
The study found that after forming stacked structure, being needed in stacked structure when existing 3D nand memory makes
Peripheral region forms stepped region, and multiple exposure mask and etching technics are needed when forming stepped region, then removes silicon nitride layer,
The position for removing silicon nitride layer forms metal control gate；Then after forming metal control gate, Jie of covering stacked structure is formed
Matter layer；Then, the dielectric layer is etched, forms several contact through holes in the dielectric layer, several contact through holes expose accordingly
The metal control gate surface of step；Finally, filling metal in several contact through holes, several Metal contacts are formed.I.e. existing system
When making metal control gate and Metal contacts, metal control gate and Metal contacts are formed by different processing steps, so that
The formation process of metal control gate and Metal contacts is complex.
In addition, existing technique is since contact through hole needs to expose corresponding ledge surface, when forming contact through hole
It is easy the presence of mis-alignment, also, in order to enable contact through hole can be aligned with corresponding ledge surface or to be formed
Metal contacts can with corresponding ledge surface keep well contact, this just needs the stepped region of larger area, reduces
The integrated level of device, and when forming contact through hole using masking process, is easy that there are contact through holes and respective step area
Mis-alignment problem and over etching (over etching is caused to step) and owe etching (contact through hole bottom does not expose corresponding
Step) the problems such as.
For this purpose, a kind of 3D nand memory and forming method thereof is provided in the embodiment of the present invention, wherein the 3D
The forming method of nand memory, when forming electrically conducting contact and control gate, without first leading to the peripheral region of stacked structure
It crosses multiple exposure mask and etching technics forms stepped region, and without being respectively formed electrically conducting contact and control by different steps
Grid can be formed simultaneously electrically conducting contact and control gate by integration making technology in the stacked structure directly on external zones,
Greatly simplify manufacture craft.Also, stepped region is formed due to not needing, when forming electrically conducting contact, there is no contacts
The alignment issues of through-hole and step, and it is not necessarily to the stepped region of larger area, be conducive to the integrated level for improving device.Also,
Layer of support material, layer of support material are formed on the side wall and bottom surface of several contact through holes and the surface of stacked structure
When removing sacrificial layer and forming several cavitys for maintaining the location and shape of the contact through hole formed, and definition contact through hole
Metal is subsequently filled by removing the high K film and layer of support material of each contact hole bottom with the relative position of cavity
When, to may further guarantee the connection of electrically conducting contact and corresponding control gate, thus easy realization electrically conducting contact
With the integration making technology of control gate.
It is right with reference to the accompanying drawing to keep the above objects, features, and advantages of the embodiment of the present invention more obvious and easy to understand
A specific embodiment of the invention is described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey
General proportion makees partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.This
It outside, should include the three-dimensional space of length, width and depth in actual fabrication.
Fig. 1-19 is the structural schematic diagram of 3D of embodiment of the present invention nand memory forming process.
With reference to Fig. 1, semiconductor substrate 201 is provided, the semiconductor substrate 201 includes external zones 21 and core array area
22；Stacked structure is formed in the external zones 21 of the semiconductor substrate 201 and core array area 22, the stacked structure includes handing over
For the insulating layer 204 and sacrificial layer 205 of stacking.
In one embodiment, the external zones 21 and core array area 22 are adjacent, and the external zones 21 is located at core battle array
It arranges 22 side of area or the external zones 21 surrounds the core array area 22, the stacked structure is across external zones 21 and core
Heart array area 22.
The material of the semiconductor substrate 201 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carbonization
Silicon (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be other materials, such as arsenic
Change III-V compounds of group such as gallium.In the present embodiment, the material of the substrate 200 is monocrystalline silicon (Si).
The stacked structure includes alternately stacked insulating layer 204 and sacrificial layer 205, the subsequent removal of the sacrificial layer 205
To form cavity, portion cavity is connected to corresponding contact through hole, then fills metal wherein, forms electrically conducting contact, separately
Metal is filled in a part of cavity, forms control gate.The insulating layer 204 is as between the control gate of different layers, and control
Electric isolation between grid and other devices (electrically conducting contact, channel hole etc.).
The insulating layer 204 and sacrificial layer 205 is alternately laminated refers to: after forming a layer insulating 204, in the insulating layer
204 surface forms one layer of sacrificial layer 205, then circuits sequentially and to be formed insulating layer 204 and sacrificial on insulating layer 204
The step of domestic animal layer 205.In the present embodiment, the top of the stacked structure is a layer insulating (top insulating layer) 204, most
The double stacked structure stacked below top insulating layer 204 for several layers, each layer of double stacked structure include a layer insulating
204 and the sacrificial layer 205 positioned at the layer insulating surface.
The stacked structure the number of plies (number of plies refers to the number of plies of insulating layer or sacrificial layer below top insulating layer, or
Person refers to the number of plies of the double stacked structure of insulating layer 204 and sacrificial layer 205 below top insulating layer), according to vertical direction
The number of the storage unit of required formation determines that the number of plies of the stacked structure can be 8 layers, 32 layers, 64 layers etc., stack layer
The number of plies it is more, can more improve integrated level.In the present embodiment, only it is 3 layers as example using the number of plies of stacked structure and is illustrated.
The sacrificial layer 205 is not identical as the material of insulating layer 204, and sacrificial layer 205 has high relative to insulating layer 204
Etching selection ratio, it is smaller to the etch amount of insulating layer 204 or ignore so that subsequent when removing sacrificial layer 205, guarantee
The integrality of insulating layer 204.
The material of the insulating layer 204 can be one of silica, silicon nitride, silicon oxynitride, fire sand, it is described
The material of sacrificial layer 205 can be silica, silicon nitride, silicon oxynitride, fire sand, unformed silicon, amorphous carbon, polysilicon
One of.In the present embodiment, the material of the insulating layer 204 is silica, and the material of sacrificial layer 205 is silicon nitride, described
Insulating layer 204 and sacrificial layer 205 are formed using chemical vapor deposition process.
In one embodiment, according to technique or the needs of device, N-type can also be formed in the semiconductor substrate 201
Deep trap 202, and the P type trap zone 203 in the deep trap 202 of N-type.
With reference to Fig. 2-6, the stacked structure on external zones 21 is etched, forms several depths in the stacked structure on external zones 21
It spends different contact through holes (209,210,211), the bottom of several contact through holes (209,210,211) exposes different layers respectively
205 surface of sacrificial layer.
The specific forming process of contact through hole (209,210,211) is described in detail with reference to the accompanying drawing.
Referring to FIG. 2, forming the first patterned mask layer 206, first figure on the surface of the stacked structure
There are several openings 207 for exposing the stacked structure surface on external zones 21, several openings 207 in the mask layer 206 of shape
It is arranged successively from the direction that external zones 21 is directed toward core array area 22.
The first patterned mask layer 206 forms exposure mask when contact through hole, institute as subsequent etching stacked structure
State the contact through hole formed in the quantity and subsequent stacked structure of the opening 207 formed in the first patterned mask layer 206
Quantity is consistent.
The first patterned mask layer 206 has high etching selection relative to insulating layer 204 and sacrificial layer 205
Than the material of the first patterned mask layer 206 can be polysilicon, unformed silicon, amorphous carbon, titanium nitride, nitridation
One or more of tantalum, the first patterned mask layer 206 can be (such as double-deck for single-layer or multi-layer stacked structure
Stacked structure).In the present embodiment, the material of the first patterned mask layer 206 is polysilicon.
In one embodiment, the described first specific forming process of patterned mask layer 206 are as follows: in the stacked structure
Surface forms the first mask layer；Patterned photoresist layer is formed on the first mask layer；Then with patterned
Photoresist layer is the first mask layer described in mask etching, forms several openings 207 in the first mask layer, forms figure
The mask layer 206 of shape.
It should be noted that referring to from the direction that external zones 21 is directed toward core array area 22: choosing one in external zones 21
Point, chooses a point in core array area 22, does the line extended to 22 midpoint of core array area from the point of external zones 21,
The direction that the line extends is the direction that core array area 22 is directed toward from external zones 21.Specific in structure described in Fig. 2, from
External zones 21 is directed toward the direction in core array area 22 as the direction in Fig. 2 from left to right.
With reference to Fig. 3, photoresist layer 208 is formed on the described first patterned mask layer 206；Carry out photoetching offset plate figure
Technique makes the photoresist layer 208 expose one that freestone heart array area 22 is farthest in the first patterned mask layer 206 and opens
Mouth 207.
The formation process of the photoresist layer 208 is spin coating proceeding, passes through exposure and imaging technique (photoetching offset plate figure chemical industry
Skill) make photoresist layer 208 expose a farthest opening of freestone heart array area 22 in the first patterned mask layer 206
207。
The distance of the first patterned several opening freestone heart array areas 22 of mask layer 206 refers to several openings half
The linear distance for projecting to a certain reference position in core array area 22 on conductor substrate 201, specific in Fig. 2, the first figure
A farthest opening 207 of freestone heart array area 22 is leftmost one opening in the mask layer 206 of change.
With reference to 4, technique is performed etching, is exposure mask, edge with the photoresist layer 208 and the first patterned mask layer 206
The farthest opening 207 etches the insulating layer 204 of top in the stacked structure, forms the first contact through hole 209, institute
State the surface that the first contact through hole 209 exposes the sacrificial layer 205 of 204 bottom of top insulating layer.
The insulating layer 204 of the etching top uses anisotropic dry etch process, such as reactive ion etching
Technique or plasma etch process.
When etching the insulating layer 204 of top, using the sacrificial layer 205 of bottom as etching stop layer.
205 surface of sacrificial layer of bottom can directly be stopped at by forming the first contact through hole 209, can also be removed with over etching
The sacrificial layer 205 of segment thickness.
With reference to Fig. 5, photoetching offset plate figure chemical industry skill is carried out, the photoresist layer 208 is made to expose the first patterned exposure mask
A remote opening 207 of freestone heart array area 22 second in layer 206；Technique is performed etching, with the photoresist layer 208 and first
Patterned mask layer 206 is exposure mask, and the opening 207 remote along described second etches the insulation of top in the stacked structure
Layer 204, forms the second contact through hole 210, and second contact through hole 210 exposes the sacrifice of 204 bottom of top insulating layer
The surface of 205 (layer sacrificial layer last) of layer, while continuing one layer of sacrificial layer 205 of etching bottom along the first contact through hole 209
(layer sacrificial layer last) and layer insulating 204 (layer insulating last), so that the bottom of the first contact through hole 209
Expose the surface of the sacrificial layer 205 of layer second from the bottom.
For aspect description, by stacked structure, (top is insulating layer in stacked structure, if being below top insulating layer
The double stacked structure that dried layer stacks, each layer of double stacked structure include a layer insulating and positioned at the layer insulating surface
Sacrificial layer) in several insulating layers be successively defined as top insulating layer from top to bottom, layer insulating last is second from the bottom
Layer insulating ... ..., inverse N (N is greater than 2) layer insulating (bottom insulating layer), by several sacrificial layers in stacked structure
Successively it is defined as layer sacrificial layer last, layer sacrificial layer ... ... second from the bottom, inverse N (N is greater than 2) layer sacrificial layer (most bottom
Layer sacrificial layer).
In the present embodiment, the photoresist layer 208 is made to expose freestone heart array area in the first patterned mask layer 206
The photoetching offset plate figure chemical industry skill of a 22 second remote openings 207 is cineration technics.
The etching technics that the insulating layer 204 of the etching top forms the second contact through hole 210 is anisotropic dry
Method etching technics, such as reactive ion etching process or plasma etch process.
In one embodiment, when performing etching technique, different etching gas can be used, such as first using to sacrificial layer
205 first gas with larger etch rate, then using the second gas to insulating layer 204 with larger etch rate.
With reference to Fig. 6, circulation carries out photoetching offset plate figure chemical industry skill and etching technics, successively exposes from external zones 21 and is directed toward core
Several openings 207 on the direction of heart array area 22, and it is sequentially etched the insulating layer 204 and sacrificial layer 205 of equivalent layer, until shape
At several contact through holes.
The quantity of the contact through hole of the formation and the number of plies of stacked structure are consistent, are directed toward core array area from external zones 21
On 22 direction, the bottom of several contact through holes of the formation is in step-like distribution, and the bottom of different contact through holes is corresponding
Expose the surface of the sacrificial layer 205 of different layers.
In the present embodiment, the number of plies of stacked structure is three layers, and the quantity for being correspondingly formed contact through hole is also three, thus is followed
Ring carries out the step of photoetching offset plate figure chemical industry skill and etching technics are as follows: carries out photoetching offset plate figure chemical industry skill, makes the photoresist layer
208 (referring to Fig. 5) expose a remote opening 207 of 22 third of freestone heart array area in the first patterned mask layer 206；Into
Row etching technics is exposure mask with the photoresist layer 208 and the first patterned mask layer 206, the opening remote along the third
207, the insulating layer 204 of top in the stacked structure is etched, third contact through hole 211, the third contact through hole are formed
211 expose the surface of the sacrificial layer 205 (layer sacrificial layer last) of 204 bottom of top insulating layer, while connecing along second
It touches the continuation of through-hole 210 one layer of sacrificial layer 205 of etching bottom (layer sacrificial layer last) and a layer insulating 204 is (last
Layer insulating) so that the bottom-exposed of the second contact through hole 210 goes out the surface of the sacrificial layer 205 of layer second from the bottom, while along
One contact through hole 209 continues one layer of sacrificial layer 205 of etching bottom (layer sacrificial layer second from the bottom) and a layer insulating 204 is (reciprocal
Second layer insulating) so that the bottom-exposed of the first contact through hole 209 goes out (the layer sacrifice third from the bottom of sacrificial layer 205 of the bottom
Layer) surface.
In the present embodiment, the number of plies of stacked structure is three layers, and the quantity of the contact through hole formed accordingly is three, including
First contact through hole 209, the second contact through hole 210, third contact through hole 211, different contact through holes expose different layers
The surface of sacrificial layer 205, such as the first contact through hole 209 expose the sacrificial layer 205 (layer sacrificial layer third from the bottom) of the bottom
Surface, the second contact through hole 210 exposes the surface of layer sacrificial layer 205 second from the bottom, and third contact through hole 211 exposes down
The surface of number first layer sacrificial layer 205.
In the present embodiment, when carrying out last etching technics, the photoresist layer is depleted, or is carried out last
When photoetching offset plate figure chemical industry skill, the photoresist layer is depleted.
In the present embodiment, several contact through holes (209-211) of step-like distribution are formed using foregoing manner, compared to existing
Some formation process, the application is when forming several step-like contact through holes, without first leading to the peripheral region of stacked structure
It crosses multiple exposure mask and etching technics forms stepped region, greatly simplify manufacture craft, reduce the production cost；And if being formed
When dry contact through-hole, present stacked structure surface forms the first patterned mask layer 206, in the first patterned mask layer
Photoresist layer 208 is formed on 206, if it is logical to form dry contact by multiple photoetching offset plate figure chemical industry skill and corresponding etching technics
Hole (209-211), thus several contact through holes (209-211) if position only depend in the first patterned mask layer 206
The position of dry opening 207 can prevent contact through hole from asking with stepped region mis-alignment without regard to the position where stepped region
The generation of topic, and the generation of over etching and deficient etching problem can be prevented；And several contact through holes are made by above-mentioned technique
Bottom can expose equivalent layer sacrificial layer surface, thus without consider stepped region size, further decrease production
Cost.
With reference to Fig. 7, on the side wall of several contact through holes (209-211) and the surface of bottom surface and stacked structure
Upper formation layer of support material 212.
Contact of the layer of support material 212 when subsequent removal sacrificial layer 205 forms several cavitys for maintaining to be formed
The location and shape of through-hole (209-211).
In one embodiment, the sacrificial layer 205 has high etching selection ratio relative to layer of support material 212, so that
Must be subsequent when removing sacrificial layer 205, so that layer of support material 212 is able to maintain completely, so that contact through hole (209-211)
Location and shape keep accurate.
The layer of support material 212 can be single-layer or multi-layer stacked structure, the thickness of layer of support material 212 be much smaller than or
Less than the width of contact through hole.In one embodiment, the layer of support material 212 can be the silica of single layer, or oxidation
The double stacked structure of silicon and polysilicon.It should be noted that in other embodiments, the supporting layer can be using other conjunctions
Suitable material.
In the present embodiment, since the described first patterned mask layer 206 does not remove also, 212 shape of layer of support material
At on the first patterned 206 surface of mask layer.In other embodiments, the layer of support material can be formed directly into stacking
The surface of structure.
Incorporated by reference to reference Fig. 8 and Fig. 9, the layer of support material 212 and stacked structure are etched, in external zones 21 and core battle array
Several pseudo- channel through-holes 214 for exposing 201 surface of semiconductor substrate are formed in stacked structure in column area 22, in core array
Several channel through-holes 215 for exposing 201 surface of semiconductor substrate are formed in stacked structure in area 22.
It is subsequently formed pseudo- channel structure in the puppet channel through-hole 214, subsequent when removing sacrificial layer, the puppet channel junction
Structure is used to support stacked structure, to prevent stacked structure from collapsing.
The storage organization of 3D nand memory is subsequently formed in the channel through-hole 215.
In one embodiment, specific referring to FIG. 8, before forming the pseudo- channel through-hole 214 and channel through-hole 215,
The mask layer 213 of second graphical, the mask layer 213 of the second graphical are formed on 212 surface of layer of support material
Fill full contact through hole (209-211).
The exposure mask when mask layer 213 of the second graphical is as etching layer of support material 212 and stacked structure, it is described
There are several openings for exposing 212 surface of layer of support material on stacked structure in the mask layer 213 of second graphical, it is several
The position of opening is corresponding with the position and quantity of pseudo- channel through-hole to be formed in stacked structure and channel through-hole.
The mask layer 213 of the second graphical can be single-layer or multi-layer stacked structure,
In one embodiment, the mask layer 213 of the second graphical includes filled layer, the antireflection on filled layer
Figure layer, the photoresist layer in antireflection figure layer.The filled layer has flat surface, and the filled layer fills full institute
It states contact through hole (209-211), the material of the filled layer can be agraphitic carbon or other suitable packing materials.
Referring to FIG. 9, etch the layer of support material 212 and stacked structure using anisotropic dry etch process,
Including reactive ion etching process or plasma etch process.
Several puppet channel through-holes 214 and channel through-hole 215 are independent through-hole one by one, pseudo- 214 He of channel through-hole
The width of channel through-hole 215 is less than the width of contact through hole (209-211).
In the present embodiment, it is patterned when forming pseudo- channel through-hole 214 and channel through-hole 215 to need to etch described first
Mask layer 206, and when forming pseudo- channel through-hole 214 and channel through-hole 215, the semiconductor of segment thickness can be removed with over etching
Substrate.
In one embodiment, the pseudo- channel through-hole 214 of the formation is arranged in array, so that the pseudo- channel junction being subsequently formed
Structure is also arranged in array, so that the enabling capabilities of several puppet channel structures are stronger, and the stress generated can be smaller.The channel
Through-hole 215 is also arranged in array, so as to form the storage organization of array arrangement.It should be noted that in other embodiments
In, the puppet channel through-hole 214 and channel through-hole 215 can be other arrangement modes.
In one embodiment, it is at least formed in the stacked structure between two adjacent contact through holes or around contact through hole
One pseudo- channel through-hole, it is subsequent after forming pseudo- channel structure, when removing sacrificial layer, it can make hanging contact through hole will not
Deformation or deflection are smaller.
After forming the pseudo- channel through-hole 214 and channel through-hole 215, need to remove the exposure mask of the second graphical
Layer 213 (refers to Fig. 8).The mask layer 213 for removing the second graphical can be using ashing and wet-etching technology.
In conjunction with reference Fig. 9 and Figure 10, storage organization 217 is formed in the channel through-hole in core array area 22；?
Pseudo- channel structure 218 is formed in the pseudo- channel through-hole on external zones 21 and core array area 22.
The storage organization includes at least electric charge capture layer and channel layer, in the present embodiment, electric charge capture layer ONO
Layer, i.e., the lamination of oxide-nitride-oxide, channel layer are polysilicon layer.It in a specific embodiment, can be in ditch
ONO layer, polysilicon layer and silicon oxide layer are deposited in road through-hole, successively to form storage organization.
The formation of the storage organization 217 and pseudo- channel structure 218 can in same step, can also different step into
Row.
In one embodiment, the storage organization 217 and when being formed in the progress of same step of pseudo- channel structure 218, shape
When including: formation deposit ONO layer, polysilicon layer and silicon oxide layer in channel through-hole at step, while in pseudo- channel through-hole
In can also deposit ONO layer, polysilicon layer and silicon oxide layer, after deposition, carry out flatening process (chemical mechanical milling tech),
Using the patterned mask layer 206 of layer of support material 212 or the first as stop-layer, this method save processing steps.
In another embodiment, the storage organization 217 and when being formed in different step progress of pseudo- channel structure 218,
Forming step includes: to first pass through exposure mask to cover pseudo- channel through-hole 214, and ONO layer, polycrystalline are then deposited in channel through-hole 215
Silicon layer then removes the exposure mask, and full silicon oxide layer is filled in pseudo- channel through-hole 214 and on 215 polysilicon layer of channel through-hole,
It finally carries out chemical mechanical grinding and exposes the first patterned mask layer 206 or 212 surface of layer of support material.
In another embodiment, the storage organization 217 and when being formed in different step progress of pseudo- channel structure 218,
Forming step includes: while depositing ONO layer in pseudo- channel through-hole 214 and channel through-hole 215, then passes through exposure mask for pseudo- channel
Through-hole 214 is covered, and then the deposit polycrystalline silicon layer on ONO layer in channel through-hole 215, then removes the exposure mask, in pseudo- channel
Full silicon oxide layer is filled on polysilicon layer on the ONO layer of through-hole 214 and in channel through-hole 215, is finally carried out chemical machinery and is ground
Mill exposes the first patterned mask layer 206 or 212 surface of layer of support material.
When forming storage organization 217 and pseudo- channel structure 218, the contact through hole (209-211) can pass through exposure mask
It covers, the exposure mask can be using the aforementioned same exposure mask for covering pseudo- channel through-hole.In one embodiment, in channel through-hole
In formation ONO layer, before polysilicon layer, the contact through hole (209-211) is covered by exposure mask, then in channel through-hole
After middle formation ONO layer, polysilicon layer, the exposure mask is then removed, in the more of contact through hole (209-211) side wall and channel through-hole
Crystal silicon layer surface is formed simultaneously silicon oxide layer.
In 3D nand memory manufacturing process, in order to guarantee effectively being electrically connected for source electrode and drain electrode (Source-Drain)
It connects, channel via etch must assure that the over etching amount certain to semiconductor substrate, but there are certain unevenness for over etching technique
Even property, it is different so as to cause channel hole length, that is, the passage length between source electrode and drain electrode is inconsistent, so as to cause storage
The threshold voltage (Vt) of array is unevenly distributed/does not restrain, and influences the performance of the various aspects such as reading and writing, erasing, storage.Thus exist
In one embodiment, referring to FIG. 10, being formed before storage organization 217 in the channel through-hole 215, in the channel through-hole
Semiconductor epitaxial layers 216 are formed on 215 bottom, by the channel via pad of over etching to equal height, so that it is equal to improve Vt distribution
Even property, prevents the influence of the performance to various aspects such as reading and writing, erasing, storages.The material of semiconductor epitaxial layers 216 be silicon, germanium or
Other suitable semiconductor materials.216 formation process of semiconductor epitaxial layers is selective epitaxial process.
In one embodiment, Figure 11 is please referred to, after forming the storage organization 217 and pseudo- channel structure 218, is etched back to
Storage organization 217 forms groove in the insulating layer 204 of top layer, and filling semiconductor material forms plug 220 in a groove.
The material of the plug 220 is that silicon, germanium or other semiconductor materials, the plug 220 are used for connection ditch channel layer
And form the bit line formed on stacked structure after control gate.The specific formation process of the plug 220 are as follows: be etched back to store
Structure 217 forms groove in the insulating layer 204 of top layer；It is formed in the groove and on the first patterned mask layer
Semiconductor material layer, the semiconductor material layer fill full groove；Semiconductor material on the insulating layer of planarization removal top
The bed of material and the first patterned mask layer form the plug 220 of semiconductor material in a groove；It, can be with after forming plug 220
One dielectric layer (such as silicon oxide layer) is formed on the stacked structure surface.
In one embodiment, when filling semiconductor material forms plug in the groove, in the contact through hole
Filling semiconductor material forms filling sacrificial layer 219.
In other embodiments, when filling semiconductor material forms plug in the groove, the contact through hole can
It is after forming the plug 220 or subsequent after removing the sacrificial layer 205 to be covered by exposure mask, remove the exposure mask.
With reference to Figure 12, after forming the storage organization 217 and pseudo- channel structure 218, the 205 (reference of sacrificial layer is removed
Figure 11), several cavitys 222 are formed.
Remove sacrificial layer 205 and use wet-etching technology, in the present embodiment, etching solution that the wet etching uses for
Concentrated phosphoric acid.When removing sacrificial layer 205, the sacrificial layer 205 has high relative to insulating layer 204 and layer of support material 212
Etching selection ratio.
In one embodiment, after forming the storage organization 217 and pseudo- channel structure 218, the sacrificial layer 205 is removed
Before, the stacked structure in core array area 22 is etched, the grid separate slot 221 for running through stacked structure, the grid separate slot are formed
221 bottom-exposed goes out semiconductor substrate 201.The width of the grid separate slot 221 is greater than contact through hole width and sacrificial layer
205 thickness, so that subsequent when filling metal layer, metal layer will not fill grid separate slot 221 full.
It is subsequently used for forming array common source in the grid separate slot 221.
In one embodiment, incorporated by reference to reference Figure 12 and 13, sacrificial layer 219 is filled when being formed in the contact through hole
When, the filling sacrificial layer 219 is removed by wet processing, retains layer of support material 212.
In other embodiments, when the double stacked structure that the layer of support material 212 is silicon oxide layer and polysilicon layer
When, the polysilicon layer can also be removed, silicon oxide layer is only retained.
It should be noted that in other embodiments, when not forming storage organization and pseudo- channel structure, being supported being formed
After material layer step, the step of being removed the sacrificial layer, form several cavitys.
In one embodiment, with reference to Figure 14, after removing sacrificial layer, the fid in several contact through holes (209-211)
The sidewall surfaces of 212 surface of the bed of material and several cavitys 22 form high K film 223.
The material HfO of the high K film 2232、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、
SrTiO3Or BaSrTiO, the formation process of the high K film 223 includes atom layer deposition process.
In one embodiment, when being formed with grid separate slot 221, the high K film 223 also covers grid separate slot 221
Side wall and bottom surface.
With reference to Figure 15, the layer of support material 212 of several contact through hole (209-211) bottoms is removed, so that each connecing
Touch through-hole (209-211) cavity connection corresponding with bottom.
In one embodiment, when in several contact through holes (209-211) 212 surface of layer of support material and several skies
When the sidewall surfaces of chamber 22 form high K film 223, in the backing material for removing several contact through hole (209-211) bottoms
Before layer 212, also need to remove the high K film 223 in the layer of support material 212 of the bottom contact through hole (209-211) accordingly.
The high K film 223 in the bottom several contact through holes (209-211) and layer of support material 212 are removed using anisotropy
Dry etch process, including reactive ion etching process and plasma etching industrial.
After each contact through hole (209-211) cavity connection corresponding with bottom, it is subsequently formed electrically conducting contact
It can be formed with control gate with same step, and each electrically conducting contact can be connected with the control gate of respective layer.
In one embodiment, when being formed with grid separate slot 221, while the high K film of 221 bottom of grid separate slot is removed
223。
With reference to Figure 16, conductive material is filled into several contact through holes and its cavity of corresponding connection, forms control
Grid 228 and the electrically conducting contact being connect with control gate 228 (224-226).
The conductive material of the filling can be metal or other conductive materials (such as polysilicon etc.).The present embodiment
In, the conductive material is metal, and the metal is W, Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several, the filling
The technique of conductive material includes atomic layer deposition or plating.
When filling conductive material, the grid separate slot 221 be not filled by it is full, the conductive material of the filling only cover grid every
The side wall and bottom surface of slot.
In the present embodiment, by previous process steps, without first by the peripheral region of stacked structure by multiple exposure mask and
Etching technics forms stepped region, and without being respectively formed electrically conducting contact and control gate by different steps, can directly exist
Electrically conducting contact (224-226) and control gate 228 are formed simultaneously by integration making technology in stacked structure on external zones 21,
Greatly simplify manufacture craft；Also, stepped region is formed due to not needing, when forming electrically conducting contact (224-226), no
There are the alignment issues of contact through hole and step, and are not necessarily to the stepped region of larger area, are conducive to the integrated level for improving device.
Also, layer of support material 212 is formed on the surface of the side wall of several contact through holes and bottom surface and stacked structure,
Contact through hole (209-211) of the layer of support material 212 when removing sacrificial layer 205 and forming several cavitys 222 for maintaining to be formed
Location and shape, and define contact through hole (209-211) and cavity 222 relative position, by removing each contact
223 and 212 layer of support material of high K film of hole bottom, when being subsequently filled metal, to may further guarantee conductive contact
The connection in portion and corresponding control gate, thus the integrated production of easy realization electrically conducting contact (224-226) and control gate 228
Technique；And since control gate 228 and electrically conducting contact (224-226) can form electrically conducting contact because may be not present simultaneously
When to the over etching problem of control gate.
With reference to Figure 17, it is etched back to the conductive material of removal grid separate slot 221 side wall and bottom surface.
The conductive material for being etched back to removal 221 side wall of grid separate slot and bottom surface can use wet-etching technology.
With reference to Figure 18, after being etched back to the metal step of removal 221 side wall of grid separate slot and bottom surface, in grid separate slot
221 sidewall surfaces form isolation side walls 229.
The isolation side walls 229 can be single-layer or multi-layer stacked structure, and the material of isolation side walls 229 is silica, nitrogen
One or more of SiClx, silicon oxynitride.
After forming isolation side walls 229, the semiconductor substrate of 221 bottom of grid separate slot can also be doped, be formed
Doped region 230.
With reference to Figure 19, the conductive layer 230 for filling full remaining grid separate slot is formed on 229 surface of isolation side walls, forms battle array
Column common source.
The material of the conductive layer 230 is polysilicon or metal.
Another embodiment of the present invention additionally provides a kind of 3D nand memory, please refers to Figure 19, comprising:
Semiconductor substrate 201, the semiconductor substrate 201 include adjacent external zones 21 and core array area 22；
Stacked structure on 201 external zones 21 of semiconductor substrate and core array area 22, the stacked structure
Including alternately stacked insulating layer 204 and control grid structure, the control grid structure includes high K film 223 and control gate 228；
The different contact through hole of several depth in the stacked structure on the external zones 21, several contact through holes
Bottom exposes the control gate surface of different layers respectively；
Positioned at the layer of support material 212 of the sidewall surfaces of several contact through holes；
Positioned at 228 surface of layer of support material 212 and corresponding control gate, and fill the electrically conducting contact of full contact through hole
(224-226)。
The stacked structure is across external zones 21 and core array area 22.
In one embodiment, further includes: several sudden and violent in the stacked structure on external zones 21 and core array area 22
Expose the pseudo- channel through-hole of semiconductor substrate surface, several expose in the stacked structure in core array area 22 is partly led
The channel through-hole on body substrate surface；Storage organization 217 in the channel through-hole；Puppet in the pseudo- channel through-hole
Channel structure 218.
In one embodiment, the material of the layer of support material 212 is silica.
In one embodiment, the bottom of the channel through-hole also has semiconductor epitaxial layers 216, the storage organization 217
On semiconductor epitaxial layers 216.
The storage organization 217 includes at least electric charge capture layer and channel layer.
217 top surface of storage organization also has semiconductor material plug 220.
In one embodiment, further includes: the stacked structure in core array area 22, through stacked structure grid every
Slot；Array common source 230 in grid separate slot.
It should be noted that in the present embodiment and in previous embodiment (3D nand memory forming process), identical structure
Restriction or description, repeat no more in the present embodiment, specifically please refer to the restriction or description of corresponding portion in previous embodiment.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (27)
1. a kind of forming method of 3D nand memory characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes external zones and core array area；
Stacked structure is formed on the external zones of the semiconductor substrate and core array area, the stacked structure includes alternating layer
Folded insulating layer and sacrificial layer；
The stacked structure on the external zones is etched, if it is logical to form the different dry contacts of depth in the stacked structure on external zones
The bottom in hole, several contact through holes exposes the sacrificial layer surface of different layers respectively；In the side of several contact through holes
Layer of support material is formed on the surface of wall and bottom surface and stacked structure；
The sacrificial layer is removed, several cavitys are formed；
The layer of support material of several contact through hole bottoms is removed, so that each contact through hole cavity corresponding with bottom
Connection；
Conductive material is filled into several contact through holes and its cavity of corresponding connection, form control gate and is connected with control gate
The electrically conducting contact connect.
2. the forming method of 3D nand memory as described in claim 1, which is characterized in that
Further include:
After forming layer of support material, the layer of support material and stacked structure are etched, on external zones and core array area
Stacked structure in form several pseudo- channel through-holes for exposing semiconductor substrate surface, the stacked structure in core array area
It is middle to form several channel through-holes for exposing semiconductor substrate surface；
Storage organization is formed in the channel through-hole；
Pseudo- channel structure is formed in the pseudo- channel through-hole；
After forming the storage organization and pseudo- channel structure, the sacrificial layer is removed, several cavitys are formed.
3. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that the formation of the contact through hole
Process includes: the first patterned mask layer of formation, the first patterned mask layer on the surface of the stacked structure
In there are several openings for exposing stacked structure surface on external zones, several openings are directed toward core array area from external zones
It is arranged successively on direction；Photoresist layer is formed on the described first patterned mask layer；Photoetching offset plate figure chemical industry skill is carried out, is made
The photoresist layer exposes a farthest opening of freestone heart array area in the first patterned mask layer；Perform etching work
Skill, along the farthest opening, etches the stacked structure using the photoresist layer and the first patterned mask layer as exposure mask
The insulating layer of middle top, forms the first contact through hole, and first contact through hole exposes the sacrificial of top insulating layer bottom
The surface of domestic animal layer；Photoetching offset plate figure chemical industry skill is carried out, the photoresist layer is made to expose freestone in the first patterned mask layer
A remote opening of heart array area second；Technique is performed etching, is to cover with the photoresist layer and the first patterned mask layer
Film, the opening remote along described second etch the insulating layer of top in the stacked structure, form the second contact through hole, described
Second contact through hole exposes the surface of the sacrificial layer of top insulating layer bottom, while continuing to etch bottom along the first contact through hole
Portion's sacrificial layer and insulating layer, so that the bottom-exposed of the first contact through hole goes out the surface of the sacrificial layer of layer second from the bottom；Recycle into
Row photoetching offset plate figure chemical industry skill and etching technics are successively exposed from several opening on the direction that external zones is directed toward core array area
Mouthful, and it is sequentially etched the insulating layer and sacrificial layer of equivalent layer, until forming several contact through holes.
4. the forming method of 3D nand memory as claimed in claim 3, which is characterized in that the layer of support material is located at
First patterned exposure mask layer surface.
5. the forming method of 3D nand memory as claimed in claim 1 or 3, which is characterized in that when removing sacrificial layer,
The sacrificial layer has high etching selection ratio relative to layer of support material.
6. the forming method of 3D nand memory as claimed in claim 5, which is characterized in that the layer of support material is single
Layer or multilayer lamination structure.
7. the forming method of 3D nand memory as claimed in claim 5, which is characterized in that the layer of support material is single
The silica of layer or the double stacked structure of silica and polysilicon.
8. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that being formed, the pseudo- channel is logical
Before hole and channel through-hole, the mask layer of second graphical, the second graphical are formed in the backing material layer surface
Mask layer fill full contact through hole.
9. the forming method of 3D nand memory as claimed in claim 8, which is characterized in that being formed, the pseudo- channel is logical
After hole and channel through-hole, the mask layer of the second graphical is removed.
10. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that the shape in the channel through-hole
Before storage organization, semiconductor epitaxial layers are formed in the bottom of the channel through-hole.
11. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that the storage organization and pseudo- ditch
Road structure formed in same step or different step in formed.
12. the forming method of 3D nand memory as claimed in claim 11, which is characterized in that the storage organization is at least
Including electric charge capture layer and channel layer.
13. the forming method of 3D nand memory as claimed in claim 11, which is characterized in that forming the storage knot
After structure and pseudo- channel structure, it is etched back to storage organization, forms groove in the insulating layer of top layer, in a groove filling semiconductor material
Material forms plug.
14. the forming method of 3D nand memory as claimed in claim 13, which is characterized in that filled in the groove
When semiconductor material, the also filling semiconductor material in the contact through hole.
15. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that further include: described in formation
After storage organization and pseudo- channel structure, the stacked structure in core array area is etched, the grid separate slot for running through stacked structure is formed,
The bottom-exposed of the grid separate slot goes out semiconductor substrate.
16. the forming method of 3D nand memory as claimed in claim 15, which is characterized in that after forming grid separate slot, go
Except the sacrificial layer；Remove semiconductor material in contact through hole.
17. the forming method of 3D nand memory as claimed in claim 15, which is characterized in that Xiang Suoshu contact through hole and
When filling conductive material in cavity, conductive material is also filled in Xiang Suoshu grid separate slot, the conductive material of the filling only covers
The side wall and bottom surface of grid separate slot.
18. the forming method of 3D nand memory as claimed in claim 17, which is characterized in that further include: it is etched back to remove
The conductive material of the grid separate slot side wall and bottom surface；It is being etched back to remove the grid separate slot side wall and bottom surface
After conductive material, isolation side walls are formed in the sidewall surfaces of grid separate slot；It is formed on isolation side walls surface and fills full remaining grid
Pole separate slot conductive layer forms array common source.
19. the forming method of 3D nand memory as described in claim 1, which is characterized in that after removing the sacrificial layer,
The sidewall surfaces of backing material layer surface and several cavitys in several contact through holes form high K film.
20. the forming method of 3D nand memory as claimed in claim 19, which is characterized in that if removing the dry contact
The layer of support material of via bottoms, so that before the cavity connection corresponding with bottom of each contact through hole, it is corresponding to remove
High K film in the layer of support material of contact through hole bottom.
21. a kind of 3D nand memory characterized by comprising
Semiconductor substrate, the semiconductor substrate include external zones and core array area；
Stacked structure on the external zones and core array area of the semiconductor substrate, the stacked structure include alternating layer
Folded insulating layer and control grid structure, the control grid structure includes high K film and control gate；
The different contact through hole of several depth in the stacked structure on the external zones, the bottom point of several contact through holes
The control gate surface of different layers is not exposed；
Positioned at the layer of support material of the sidewall surfaces of several contact through holes；
Positioned at the layer of support material and corresponding control gate surface, and fill the electrically conducting contact of full contact through hole.
22. 3D nand memory as claimed in claim 21, which is characterized in that further include: it is located at external zones and core array
Several pseudo- channel through-holes for exposing semiconductor substrate surface in stacked structure in area are located in core array area and stack knot
Several channel through-holes for exposing semiconductor substrate surface in structure；
Storage organization in the channel through-hole；
Pseudo- channel structure in the pseudo- channel through-hole.
23. 3D nand memory as claimed in claim 21, which is characterized in that the material of the layer of support material is oxidation
Silicon.
24. 3D nand memory as claimed in claim 22, which is characterized in that the bottom of the channel through-hole also has half
Conductor epitaxial layer, the storage organization are located on semiconductor epitaxial layers.
25. 3D nand memory as claimed in claim 22, which is characterized in that the storage organization is caught including at least charge
Obtain layer and channel layer.
26. 3D nand memory as claimed in claim 22, which is characterized in that the storage organization top surface also has
Semiconductor material plug.
27. 3D nand memory as claimed in claim 22, which is characterized in that further include: the heap in core array area
In stack structure, through the grid separate slot of stacked structure；Array common source in grid separate slot.
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| CN110112134A (en) * | 2019-06-17 | 2019-08-09 | 长江存储科技有限责任公司 | 3D nand memory and forming method thereof |
| CN110211947A (en) * | 2019-06-10 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of semi-conductor test structure |
| CN111170266A (en) * | 2019-12-31 | 2020-05-19 | 杭州士兰集成电路有限公司 | Semiconductor device and method for manufacturing the same |
| CN111415943A (en) * | 2020-05-21 | 2020-07-14 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory |
| CN111430361A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111430362A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
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