CN113725225A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN113725225A CN113725225A CN202110959778.5A CN202110959778A CN113725225A CN 113725225 A CN113725225 A CN 113725225A CN 202110959778 A CN202110959778 A CN 202110959778A CN 113725225 A CN113725225 A CN 113725225A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 230000002093 peripheral effect Effects 0.000 claims abstract description 66
- 239000011229 interlayer Substances 0.000 claims abstract description 64
- 238000003860 storage Methods 0.000 claims abstract description 28
- 238000000926 separation method Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 26
- 230000000149 penetrating effect Effects 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000005192 partition Methods 0.000 claims description 18
- 238000007789 sealing Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 description 16
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention discloses a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate and a stack structure positioned on the substrate, wherein the substrate comprises a device area, the device area comprises a storage array area and a peripheral area adjacent to the storage array area, the stack structure comprises a first stack structure positioned in the storage array area and a second stack structure positioned in the peripheral area, the first stack structure comprises interlayer insulating layers and interlayer gate layers which are alternately stacked, and the second stack structure comprises interlayer insulating layers and interlayer dielectric layers which are alternately stacked. According to the invention, the dielectric layers filling the edge step area and the peripheral area of the storage array area in the prior art are replaced by the stacked structure, so that the stress caused by the dielectric layers can be reduced, and further the stress in the chip is reduced.
Description
Technical Field
The present invention relates generally to electronic devices and, more particularly, to a semiconductor device and a method of manufacturing the same.
Background
The existing 3D NAND chip includes a plurality of memory array regions (planes) for forming a memory channel structure and a peripheral region around the memory array regions for forming contact contacts for electrical signal connection. The edges of the planes have a step structure and a dielectric layer (e.g., Tetraethylorthosilicate (TEOS)) covering the step structure, and each plane forms an independent memory array. Before the wafer is cut into a plurality of chips, the wafer comprises a plurality of chip integrated circuits and criss-cross cutting channels (the chip integrated circuits refer to the name of the chips before cutting), and an alignment mark can be formed on the substrate below the cutting channels to provide an alignment signal in the subsequent process of forming the step structure and the channel structure.
In the existing product structure, TEOS fills the step area and the peripheral area at the edge of the memory array, but TEOS causes a large stress and causes problems in the subsequent manufacturing process.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, aiming at reducing the stress inside a chip.
In one aspect, the present invention provides a semiconductor device comprising:
a substrate including a device region including a memory array region and a peripheral region adjacent to the memory array region;
a stack structure on the substrate, the stack structure including a first stack structure in the memory array region and a second stack structure in the peripheral region, the first stack structure including alternately stacked interlayer insulating layers and interlayer gate layers, and the second stack structure including alternately stacked interlayer insulating layers and interlayer dielectric layers.
Further preferably, the substrate further includes a scribe line region, the scribe line region includes a plurality of first scribe line regions and a plurality of second scribe line regions, and the plurality of first scribe line regions and the plurality of second scribe line regions intersect to define a plurality of device regions; the stacked structure further comprises a third stacked structure located in the first scribe line region and the second scribe line region, and the third stacked structure comprises the interlayer insulating layers and the interlayer dielectric layers which are alternately stacked.
Further preferably, an alignment mark is formed on the substrate corresponding to the first scribe line region and/or the second scribe line region.
Further preferably, an alignment mark is formed on the substrate corresponding to the peripheral region.
Further preferably, the semiconductor device further includes a separation structure vertically penetrating the stack structure, the separation structure surrounding the memory array region and separating the memory array region and the peripheral region.
Preferably, the semiconductor device further includes a plurality of hole structures vertically penetrating through the second stacked structure, the plurality of hole structures are located on one side of the partition structure away from the storage array region and are arranged at intervals around the partition structure, and each hole structure includes a first dielectric layer and a peripheral conductive pillar from outside to inside in a radial direction.
Further preferably, the separation structure includes a separation trench and a second dielectric layer filled in the separation trench.
Further preferably, the semiconductor device further comprises a ring structure vertically penetrating through the second stacked structure, the ring structure is located at the edge of the device region, and an inner ring of the ring structure surrounds the device region; and pointing the outer ring of the annular structure to the direction of the inner ring of the annular structure, wherein the annular structure comprises a third medium layer and a sealing ring.
Further preferably, the storage array region includes a step region, and the step region divides the storage array region into two sub-storage array regions.
Further preferably, the semiconductor device further includes a plurality of storage channel structures vertically penetrating the first stacked structure.
In another aspect, the present invention provides a method for manufacturing a semiconductor device, including:
forming a substrate, wherein the substrate comprises a device area, and the device area comprises a storage array area and a peripheral area adjacent to the storage array area;
forming a stack structure on the substrate, wherein the stack structure comprises a first stack structure in the memory array region and a second stack structure in the peripheral region, the first stack structure comprises interlayer insulating layers and interlayer gate layers which are alternately stacked, and the stack structure comprises interlayer insulating layers and interlayer dielectric layers which are alternately stacked;
and replacing the interlayer dielectric layer of the first stacked structure with an interlayer gate layer.
Further preferably, the substrate further includes a scribe line region, the scribe line region includes a plurality of first scribe line regions and a plurality of second scribe line regions, the plurality of first scribe line regions and the plurality of second scribe line regions intersect to define a plurality of device regions, the stacked structure further includes a third stacked structure located in the scribe line region, and the third stacked structure includes the interlayer insulating layers and the interlayer dielectric layers which are stacked alternately.
Further preferably, before the step of forming the stacked structure, an alignment mark is formed on the substrate corresponding to the first scribe line region and/or the second scribe line region.
It is further preferable that, before the step of forming the stacked structure, an alignment mark be formed on the substrate corresponding to the peripheral region.
Further preferably, the method for manufacturing the semiconductor device further includes forming a separation structure vertically penetrating through the stack structure, the separation structure surrounding the memory array region and separating the memory array region and the peripheral region.
Further preferably, the method for manufacturing the semiconductor device further includes forming a ring structure and a plurality of hole structures vertically penetrating through the second stacked structure, the ring structure is located at an edge of the device region, an inner ring of the ring structure surrounds the device region, and the plurality of hole structures are located on a side of the separation structure away from the memory array region and are spaced around the separation structure.
Further preferably, the step of forming the ring-shaped structure and the plurality of hole-shaped structures includes:
forming a separation trench vertically penetrating the stacked structure, and a plurality of dummy holes and dummy trenches vertically penetrating the second stacked structure;
forming a second dielectric layer in the separation groove, forming a first dielectric layer in the virtual hole, and forming a third dielectric layer in the virtual groove to form the separation structure, the virtual hole structure and the virtual ring structure;
and forming a peripheral conductive column in the first dielectric layer in the virtual hole structure, forming a sealing ring in the third dielectric layer in the virtual ring structure, and sequentially arranging the third dielectric layer and the sealing ring from the outer ring of the annular structure to the inner ring of the annular structure.
The invention has the beneficial effects that: the invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate and a stack structure positioned on the substrate, wherein the substrate comprises a device area, the device area comprises a storage array area and a peripheral area adjacent to the storage array area, the stack structure comprises a first stack structure positioned in the storage array area and a second stack structure positioned in the peripheral area, the first stack structure comprises interlayer insulating layers and interlayer gate layers which are alternately stacked, and the second stack structure comprises the interlayer insulating layers and the interlayer dielectric layers which are alternately stacked. According to the invention, the dielectric layers filling the edge step area and the peripheral area of the storage array area in the prior art are replaced by the stacked structure, so that the stress caused by filling a large number of dielectric layers can be reduced, and further the stress in the chip is reduced.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic top view of a semiconductor device;
fig. 2 is a schematic cross-sectional view of the semiconductor device of fig. 1 at a-a 1;
fig. 3 is a schematic top view of a semiconductor device according to a first embodiment of the present invention;
fig. 4 is a schematic top view of a semiconductor device according to a second embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a semiconductor device provided in accordance with a second embodiment of the present invention at a-a1 in fig. 4;
fig. 6 is a schematic cross-sectional view of a semiconductor device at a-a1 in fig. 4, according to a further embodiment of the second embodiment of the present invention;
fig. 7 is a schematic diagram of a top view of the semiconductor device of fig. 6;
fig. 8 is a schematic top view of a semiconductor device according to a third embodiment of the present invention;
fig. 9 is a schematic cross-sectional view of a semiconductor device provided in accordance with a third embodiment of the present invention at a-a1 in fig. 8;
fig. 10 is a schematic flow chart of a manufacturing method of a semiconductor device according to a fourth embodiment of the present invention;
fig. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention during a manufacturing process.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).
As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate. Directions are expressed herein in cartesian coordinates, directions parallel to the substrate are expressed by "X" with reference to the substrate; the direction perpendicular to the substrate is denoted by "Z"; "Y" denotes a direction parallel to the substrate and perpendicular to X; "vertical" refers to the direction (Z) perpendicular to the substrate.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, fig. 1 is a schematic top view of a semiconductor device, the semiconductor device 10 includes a substrate (not shown in the figure), the substrate includes a plurality of device regions 11 and a scribe line region 12, the scribe line region 12 includes a plurality of first scribe line regions 121 (along an X direction) and a plurality of second scribe line regions 122 (along a Y direction), the plurality of first scribe line regions 121 and the plurality of second scribe line regions 122 intersect to define a plurality of device regions 11, that is, the device region 11 is located in a region surrounded by the plurality of first scribe line regions 121 and the plurality of second scribe line regions 122 in a criss-cross manner, and each device region 11 is a chip integrated circuit. Each device region 11 includes a plurality of memory array regions 110 (e.g., 4) spaced apart from each other and a peripheral region 111 adjacent to the memory array regions 110. The alignment mark 13 may be formed on the substrate in a region corresponding to the first scribe line region 121 and/or the second scribe line region 122 to provide an alignment signal in a process of forming a step and channel structure.
It should be noted that the device region 11 may include one memory array region 110 and a peripheral region 111 corresponding to the one memory array region 110; the device region 11 may also include a plurality of memory array regions 110 and peripheral regions 111 (shown in fig. 1) corresponding one-to-one to the plurality of memory array regions 110; wherein each memory array region 110 is disposed adjacent to a corresponding peripheral region 111.
The semiconductor device 10 further includes a stack structure 1100 on the substrate and in the memory array region 110, and a memory channel structure (not shown) penetrating the stack structure 1100 in a direction perpendicular to the substrate, the stack structure 1100 including interlayer insulating layers and interlayer gate layers alternately stacked on the substrate, the interlayer insulating layers preferably being silicon oxide, and the interlayer gate layers preferably being tungsten. An edge step structure is formed at the edge of the stacked structure 1100, an effective step structure 1101 is formed in the middle of the stacked structure 1100, and the effective step structure 1101 is used for forming a word line contact. The semiconductor device 10 further includes a dielectric layer 112, such as Tetraethylorthosilicate (TEOS), formed on the substrate and in the peripheral region 111, and peripheral conductive pillars (not shown) formed therein for signal transmission. The memory array region 110 further includes a dielectric layer (e.g., TEOS) covering the edge step structure, so that the edge and peripheral regions 111 of the memory array region 110 are filled with the dielectric layer 112, which causes a very large stress, and the scribe line region 12 is filled with the dielectric layer 112, which further increases the stress. In addition, as the number of layers of stacked structure 1100 increases, the volume of dielectric layer 112 becomes larger and the stress becomes more severe.
As shown in fig. 1, the semiconductor device 10 is symmetrical in the X direction, i.e., the second scribe line region 122 (longitudinal scribe line region) extending in the longitudinal direction (Y direction) in fig. 1 is equidistant from the memory array regions 110 adjacent to both sides thereof; the semiconductor device 10 is asymmetric in the Y direction, that is, the first scribe line region 121 (lateral scribe line region) extending along the lateral direction (X direction) in fig. 1 has unequal distances to the memory array regions 110 adjacent to both sides thereof, for example, the memory array region 110 above the first scribe line region 121 in fig. 1 is farther from the first scribe line region 121, and the memory array region 110 below the first scribe line region 121 in fig. 1 is closer to the first scribe line region 121, because a certain space needs to be reserved in the peripheral region 111 on one side of the memory array region 110 to form other devices.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view of the semiconductor device of fig. 1 at a-a 1. It should be noted that fig. 2 is a structure after the photoresist 14 is spin-coated in the photolithography process for forming the step structure, and therefore the dielectric layer 112 is not formed yet, that is, the final product structure is filled with the dielectric layer 112 at the position of the photoresist 14. As shown in fig. 2, as the above analysis shows, the left and right sides of the first scribe line region 121 in fig. 2 are asymmetric, and it is found that, as the number of layers of the stacked structure 1100 increases, the thickness of the required photoresist 14 increases, which causes the photoresist 14 to be no longer flat on the surface of the first scribe line region 121, thereby causing the optical path difference of the alignment signal of the alignment mark 13 to be inconsistent, and the alignment to be deviated, when the alignment mark 13 is used for alignment to perform photolithography and a subsequent etching process to form a corresponding structure, the position of the formed structure may be deviated, for example, if the signal of the alignment mark is used for photolithography alignment, when a step structure is subsequently formed in the effective step region 1101, the position of the step structure formed in the effective step region 1101 may be deviated.
Referring to fig. 3, fig. 3 is a schematic top view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device 20 includes a substrate and a stacked structure 21 on the substrate, the substrate includes a device region 210, the device region 210 includes a memory array region 211 distributed at intervals and a peripheral region 212 adjacent to the memory array region 211, for example, the peripheral region 212 is located around the memory array region 211. The stack structure 21 includes a first stack structure 2110 in the memory array region 211 and a second stack structure 2111 in the peripheral region 212. The first stacked structure 2110 in the memory array region 211 includes alternately stacked interlayer insulating layers and interlayer gate layers, and the second stacked structure 2111 in the periphery region 212 includes alternately stacked interlayer insulating layers and interlayer dielectric layers. It is understood that the first stacked structure 2110 and the second stacked structure 2111 are both interlayer insulating layers and interlayer dielectric layers stacked alternately at the beginning of formation, and the interlayer dielectric layer of the first stacked structure 2110 is replaced by an interlayer gate layer in a subsequent process to realize a memory function of a memory cell in the memory array region 211. In the present embodiment, the semiconductor device 20 is a memory chip.
In this embodiment, the storage array region 211 includes a step region 213 in the middle, and the step region 213 partitions the storage array region 211 into two sub-storage array regions. The step regions 213 are also referred to as Word Line Central Driver (WLCD), and Word Line contacts located on the respective steps may be formed at the step regions 213.
Different from the prior art, the semiconductor device 20 provided in the first embodiment of the present invention has no step structure at the edge of the memory array region 211, and the stacked structure 21 continuously extends from the memory array region 211 to the peripheral region 212, so that the stacked structure 21 is used to replace a dielectric layer (TEOS) in the prior art, thereby reducing the stress inside the chip and further improving the product yield.
Referring to fig. 4, fig. 4 is a schematic top view of a semiconductor device according to a second embodiment of the present invention. For ease of understanding, the same reference numerals are used in the second embodiment for the same structures as in the first embodiment. The semiconductor device 200 includes a substrate and a stacked structure 21 on the substrate, the substrate includes a plurality of device regions 210 and a scribe lane region 220 distributed at intervals, the scribe lane region 220 includes a plurality of first scribe lane regions 221 (transverse scribe lane regions) and second scribe lane regions 222 (longitudinal scribe lane regions), and the plurality of first scribe lane regions 121 and the plurality of second scribe lane regions 122 intersect to define a plurality of the device regions 210. The device region 210 includes memory array regions 211 arranged at intervals and a peripheral region 212 located around the memory array regions 211. The stack structure 21 includes a first stack structure 2110 in the memory array region 211, a second stack structure 2111 in the periphery region 212, and a third stack structure 2112 in the scribe line region 220. The first stack structure 2110 includes interlayer insulating layers and interlayer gate layers that are alternately stacked, and the second stack structure 2111 and the third stack structure 2112 include the interlayer insulating layers and the interlayer dielectric layers that are alternately stacked. Note that the stacked structure 21 is represented by the same pattern in the drawing.
Unlike the prior art, the semiconductor device 200 according to the second embodiment of the present invention has no step structure at the edge of the memory array region 211, and the stacked structure 21 replaces the original dielectric layer (TEOS) in the memory array region 211, the peripheral region 212, and the scribe line region 220, so that the stress of the semiconductor device 200 can be greatly reduced. In addition, since the scribe line region 220 and the device region 210 are both stacked structures 21, the processes for forming other structures in the two regions are closer.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a semiconductor device at a-a1 in fig. 4 according to a second embodiment of the present invention. Fig. 5 is a structure after spin coating a photoresist in a photolithography process, as in fig. 2. Although the semiconductor device 200 in fig. 4 has asymmetry in the Y direction, which results in asymmetry on the left and right sides of the alignment mark 23 in fig. 5, this does not affect the flatness of the surface of the photoresist 24. Because the memory array region 211, the peripheral region 212 and the scribe line region 220 all have the same thickness of the stacked structure, and the stacked structure 21 is flat, the surface of the photoresist 24 above the stacked structure is always flat, and the alignment signal of the alignment mark 23 is not affected by symmetry, so the optical path difference of the alignment signal of the alignment mark 23 is consistent, and when the alignment is performed by using the alignment mark 23, the occurrence of deviation can be prevented, and thus the alignment can be performed accurately.
Referring to fig. 6 and 7, fig. 6 is a schematic cross-sectional view of a semiconductor device at a-a1 in fig. 4 according to a further embodiment of the second embodiment of the present invention, and fig. 7 is a schematic top view of the semiconductor device in fig. 6. The semiconductor device 200 includes a substrate 201 and a stack structure 21 located on the substrate 201, and further includes a plurality of storage channel structures 25 vertically penetrating through the first stack structure 2110, where the storage channel structures 25 include a blocking layer, a charge storage layer, a tunneling layer, a channel layer, and an insulating layer from outside to inside in a radial direction.
With continuing reference to fig. 6 and 7 in conjunction with fig. 4, the semiconductor device 200 further includes a separation structure 26 vertically penetrating the stacked structure 21 in the device region 210, and including a separation trench and a second dielectric layer filled in the separation trench, the separation structure 26 being disposed around the memory array region 211, which can also be understood as a fence-like wall around the memory array region 211 for separating the memory array region 211 from the peripheral region 212, i.e., separating the memory array region 211 from the peripheral region 212. In particular, the separation structure 26 may penetrate the second stack structure 2111 at an edge of the second stack structure 2111, such that the separation structure 26 separates the storage channel structure 25 from other devices. Compared with the prior art in which the memory array region 110 and the peripheral region 111 are separated by the edge step structure of the memory array region 110, the edge step structure is filled with a dielectric layer, and the contact area between the stacked structure 1100 and the dielectric layer is larger due to the larger exposed surface area of the step structure. In the embodiment, the memory array region 211 and the peripheral region 212 are separated by the separation structure 26, and since the material of the separation structure 26 is also a dielectric layer, and the exposed surface area of the separation structure 26 is smaller than that of the step structure, the contact area between the stack structure 21 and the dielectric layer is reduced compared with the prior art, and the volume of the dielectric layer is also reduced, thereby achieving the effect of reducing stress. With continuing reference to fig. 6 and 7 in conjunction with fig. 4, the semiconductor device 200 further includes a Ring structure 28 vertically penetrating through the second stacked structure 2111, the Ring structure 28 is located at an edge of the device region 210 and an inner Ring of the Ring structure 28 surrounds the device region 210, each Ring structure 28 includes a third dielectric layer 281 and a Seal Ring (Seal Ring)282 in a direction from an outer Ring of the Ring structure 28 to the inner Ring, wherein the Seal Ring 282 can provide a hermetic Seal, and plays a role in sealing water vapor and oxygen from entering a central region of the device region 210; in addition, the ring-shaped structure 28 is located at the edge of the device region 210, and thus it can be understood that the ring-shaped structure 28 is located between the device region 210 and the first scribe line region 221 to separate the device region 210 from the first scribe line region 221, and thus the structure within the device region 210 can be protected from mechanical damage when dicing along the first scribe line region 221 to separate the device regions 210.
With continuing reference to fig. 6 and fig. 7, in combination with fig. 4, the semiconductor device 200 further includes a plurality of hole structures 27 vertically penetrating through the second stacked structure 2111, each hole structure 27 includes, from outside to inside in a radial direction, a first dielectric layer 271 and a Peripheral conductive pillar (Peripheral Contact)272, the plurality of hole structures 27 are located on a side of the partition structure 26 away from the memory array region 211, and further, the plurality of hole structures 27 are located between the partition structure 26 and the ring structure 28 and are spaced around the partition structure 26.
In a further embodiment of the second embodiment of the present invention, a dielectric layer is surrounded on the outer surfaces of the peripheral conductive pillars 272 and the sealing ring 282, so that the forming process of the peripheral conductive pillars 272 and the sealing ring 282 can continue to use the original etching process. Because the original etching process is to etch TEOS (also silicon dioxide in nature) to form a virtual hole and a virtual trench, and then fill the virtual hole and the virtual trench with a conductive material and a metal layer to form the peripheral conductive pillar 272 and the sealing ring 282, respectively. In this embodiment, a step of adding an etching step of the second stacked structure 2111 and filling a dielectric layer (e.g., silicon dioxide) is performed, and then the etching step is performed to form the dummy holes and the dummy trenches, so that the etching material can be the same as that of the original process, and thus, the etching process does not need to be changed.
In this embodiment, the partition structure 26, the hole structure 27, and the ring structure 28 each include a dielectric layer, which may be an insulator such as silicon dioxide.
Referring to fig. 8, fig. 8 is a schematic top view of a semiconductor device according to a third embodiment of the present invention. The semiconductor device 300 comprises a substrate and a stacked structure 31 located on the substrate, wherein the substrate comprises a device region 310 and a dicing lane region 320, the device region 310 comprises memory array regions 311 distributed at intervals, and a peripheral region 312 located around the memory array regions 311. The stack structure 31 includes a first stack structure 3110 in the memory array region 311 and a second stack structure 3111 in the memory array region 312, the first stack structure 3110 includes alternately stacked interlayer insulating layers and interlayer gate layers, and the second stack structure 3111 includes alternately stacked interlayer insulating layers and interlayer dielectric layers. The scribe line region 320 is filled with a dielectric layer 32. The memory array region 311 includes a step region 313 in the middle, and the step region 313 divides the memory array region 311 into two sub memory array regions. The alignment mark 33 disposed in the X direction is formed on the substrate in the region corresponding to the peripheral region 312, and the alignment mark disposed in the Y direction may be disposed as needed, that is, may be disposed on the substrate corresponding to the peripheral region 312, or may be disposed on the substrate corresponding to the longitudinal scribe line. The third embodiment is different from the above embodiments in that a dielectric layer 32 is formed in the scribe line region 320 instead of the stacked structure 31.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view of a semiconductor device at a-a1 in fig. 8 according to a third embodiment of the present invention. It should be noted that fig. 9 is a schematic cross-sectional structure of the semiconductor device after the photoresist 34 is spin-coated during the photolithography process, fig. 9 is not a schematic cross-sectional structure of the semiconductor device after the semiconductor device is completely fabricated, and the final structure is a structure in which the dielectric layer 32 (as shown in fig. 8) is formed in the scribe line region 320. In fig. 9, although the scribe line region 320 is not filled with the dielectric layer 32, since the height of the stacked structure 31 is substantially uniform and the surface thereof is flat in the device region 310 except the scribe line region 320, the photoresist 34 formed by spin coating is flat on the surface of the device region 310. Therefore, unlike the prior art, the semiconductor device 300 according to the third embodiment of the present invention has the alignment mark 33 formed in the peripheral region 312, so that the photoresist 34 above the alignment mark 33 is flat, which can prevent the optical path difference of the alignment signal of the alignment mark 33 from being different, thereby reducing the deviation of the photolithography alignment and achieving more accurate alignment.
Referring to fig. 10, fig. 10 is a schematic flow chart illustrating a manufacturing method of a semiconductor device according to a fourth embodiment of the invention. For convenience of description, the present embodiment explains the manufacturing method by taking the manufacturing of the semiconductor device 200 in the second embodiment as an example, and therefore the reference numerals of the second embodiment are used in the fourth embodiment. The method of manufacturing the semiconductor device 200 includes the following steps S1-S6.
Step S1: forming a substrate 201, wherein the substrate 201 comprises a device region 210 and a scribe line region 220, the device region 210 comprises a memory array region 211 distributed at intervals and a peripheral region 212 adjacent to the memory array region 211, and the scribe line region 220 comprises a plurality of first scribe line regions 221 (along an X direction) and a plurality of second scribe line regions.
In the present embodiment, the substrate 201 is a semiconductor substrate, and may be, for example, a Silicon (Si), Germanium (Ge), SiGe substrate, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe or the like. Wherein the first scribe line regions 221 and the second scribe line regions 222 intersect to define the device regions 210.
Step S2: an alignment mark 23 is formed on the substrate 201 corresponding to the first scribe line region 221 and/or the second scribe line region 222.
In the present embodiment, the alignment mark 23 may be a grating structure formed by an etching process on the corresponding substrate 201.
Step S3: forming a stacked structure 21 on the substrate 201, wherein the stacked structure 21 includes a first stacked structure 2110 in the memory array region 211, a second stacked structure 2111 in the peripheral region 212, and a third stacked structure 2112 in the scribe lane region 220, and the stacked structure 21 includes alternately stacked interlayer insulating layers and interlayer dielectric layers.
In this embodiment, the interlayer insulating layer may be silicon oxide, and the interlayer dielectric layer may be silicon nitride. The interlayer insulating layer and the interlayer dielectric layer have different etching selectivity. The Deposition method of the interlayer insulating Layer and the interlayer dielectric Layer may adopt, but is not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), such as evaporation, sputtering, and other methods. Referring to fig. 11, fig. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the invention during a manufacturing process.
Step S4: forming a partition structure 26 vertically penetrating through the stacked structure 21 of the device region 210, and a virtual ring structure 280 and a plurality of virtual hole structures 270 vertically penetrating through the second stacked structure 2111, wherein the partition structure 26 surrounds the storage array region 211 and partitions the storage array region 211 and the peripheral region 212, the plurality of virtual hole structures 270 are located on a side of the partition structure 26 away from the storage array region and are spaced around the partition structure 26, the virtual ring structure 280 is located at an edge of the device region 210, and an inner ring of the virtual ring structure 280 surrounds the device region 210.
In this embodiment, the steps of forming the partition structure 26, the dummy hole structure 270, and the dummy ring structure 280 specifically include: 1) forming a separation trench vertically penetrating the device region 210 stack structure 21, a dummy hole and a dummy trench vertically penetrating the second stack structure 2111; 2) the second dielectric layer 261 is filled in the partition trench, the first dielectric layer 271 is filled in the dummy hole, and the third dielectric layer 281 is filled in the dummy trench to form the partition structure 26, the dummy hole structure 270, and the dummy ring structure 280. The first dielectric layer 271, the second dielectric layer 261 and the third dielectric layer 281 may be formed separately or simultaneously, and the materials of the first dielectric layer 271, the second dielectric layer 261 and the third dielectric layer 281 may be silicon oxide. The structure after completion of step S4 is shown in fig. 11.
Step S5: peripheral conductive pillars 272 are formed in the dummy via structure 270, and seal rings 282 are formed in the dummy ring structure 280.
In this embodiment, step S5 specifically includes: etching the dielectric layers of the dummy hole structure 270 and the dummy ring structure 280, filling a conductive material in the dummy hole structure 270 to form a peripheral conductive pillar 272, and forming a metal layer in the dummy ring structure 280 to form a seal ring 282.
Step S6: the interlevel dielectric layer of the first stacked structure 2110 is replaced with an interlevel gate layer.
In the present embodiment, the interlayer dielectric layer of the first stacked structure 2110 may be removed through the gate line slit and then the interlayer gate layer may be filled, so that the replacement process only occurs in the first stacked structure 2110 in the memory array region 211 since the separation structure 26 separates the memory array region 211 and the peripheral region 212. Before step S6, the preparation method further includes: forming a memory channel structure 25 vertically penetrating through the first stacked structure 2110 in the memory array region 211 by using the alignment mark 23; a step region 213 is formed in the middle of the memory array region 211 using the alignment mark 23.
In another embodiment, when the stacked structure formed in step S3 does not include the third stacked structure 2112 in the scribe lane region 220, and step S2 may include forming an alignment mark in the substrate under the peripheral region 212, the semiconductor device 300 provided in the third embodiment may be formed.
In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the continuous stack structure 21 is formed in the memory array region 211, the peripheral region 212, and the scribe line region 220, which not only eliminates the stress caused by TEOS, but also makes the photoresist 24 above the alignment mark 23 flat, thereby reducing the alignment deviation and making the alignment mark 23 not affected by symmetry. In addition, since the dummy hole structure 270 and the dummy ring structure 280 are formed at the positions of the peripheral conductive pillars 272 and the seal ring 282 first, the above improvement does not affect the etching process for forming the peripheral conductive pillars 272 and the seal ring 282 later.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (17)
1. A semiconductor device, comprising:
a substrate including a device region including a memory array region and a peripheral region adjacent to the memory array region;
a stack structure on the substrate, the stack structure including a first stack structure in the memory array region and a second stack structure in the peripheral region, the first stack structure including alternately stacked interlayer insulating layers and interlayer gate layers, and the second stack structure including alternately stacked interlayer insulating layers and interlayer dielectric layers.
2. The semiconductor device of claim 1, wherein the substrate further comprises a scribe lane region comprising a plurality of first scribe lane regions and a plurality of second scribe lane regions, the plurality of first scribe lane regions and the plurality of second scribe lane regions intersecting to define a plurality of the device regions; the stacked structure further comprises a third stacked structure located in the first scribe line region and the second scribe line region, and the third stacked structure comprises the interlayer insulating layers and the interlayer dielectric layers which are alternately stacked.
3. The semiconductor device according to claim 2, wherein an alignment mark is formed on the substrate corresponding to the first scribe line region and/or the second scribe line region.
4. The semiconductor device according to claim 1, wherein an alignment mark is formed on the substrate corresponding to the peripheral region.
5. The semiconductor device according to claim 1, further comprising a separation structure vertically penetrating the stack structure, the separation structure surrounding the memory array region and separating the memory array region and the peripheral region.
6. The semiconductor device according to claim 5, further comprising a plurality of hole structures vertically penetrating through the second stacked structure, the plurality of hole structures being located on a side of the partition structure away from the memory array region and spaced around the partition structure, each of the hole structures including the first dielectric layer and the peripheral conductive pillar from outside to inside in a radial direction.
7. The semiconductor device according to claim 5, wherein the separation structure comprises a separation trench and a second dielectric layer filled in the separation trench.
8. The semiconductor device of claim 1, further comprising a ring structure vertically penetrating the second stacked structure, the ring structure being located at an edge of the device region, and an inner ring of the ring structure surrounding the device region; and pointing the outer ring of the annular structure to the direction of the inner ring of the annular structure, wherein the annular structure comprises a third medium layer and a sealing ring.
9. The semiconductor device according to claim 1, wherein the memory array region includes a step region that partitions the memory array region into two sub-memory array regions.
10. The semiconductor device of claim 1, further comprising a plurality of storage channel structures extending vertically through the first stacked structure.
11. A method of manufacturing a semiconductor device, comprising:
forming a substrate, wherein the substrate comprises a device area, and the device area comprises a storage array area and a peripheral area adjacent to the storage array area;
forming a stacked structure on the substrate, wherein the stacked structure comprises a first stacked structure located in the memory array area and a second stacked structure located in the peripheral area, and the stacked structure comprises interlayer insulating layers and interlayer dielectric layers which are alternately stacked;
and replacing the interlayer dielectric layer of the first stacked structure with an interlayer gate layer.
12. The method of manufacturing a semiconductor device according to claim 11, wherein the substrate further comprises a scribe line region including a plurality of first scribe line regions and a plurality of second scribe line regions, the plurality of first scribe line regions and the plurality of second scribe line regions intersecting to define a plurality of device regions, the stacked structure further comprising a third stacked structure located in the scribe line regions, the third stacked structure including the interlayer insulating layers and the interlayer dielectric layers which are alternately stacked.
13. The method for manufacturing a semiconductor device according to claim 12, further comprising forming an alignment mark on the substrate corresponding to the first scribe line region and/or the second scribe line region before the step of forming the stack structure.
14. The method for manufacturing a semiconductor device according to claim 11, further comprising forming an alignment mark on the substrate corresponding to the peripheral region, before the step of forming the stack structure.
15. The method for manufacturing a semiconductor device according to claim 11, further comprising forming a separation structure vertically penetrating the stack structure, the separation structure surrounding the memory array region and separating the memory array region and the peripheral region.
16. The method for manufacturing a semiconductor device according to claim 15, further comprising forming a ring structure and a plurality of hole structures vertically penetrating through the second stacked structure, wherein the ring structure is located at an edge of the device region and an inner ring of the ring structure surrounds the device region, and the plurality of hole structures are located at a side of the separation structure away from the memory array region and are spaced around the separation structure.
17. The method according to claim 16, wherein the step of forming the ring-shaped structure and the plurality of hole-shaped structures comprises:
forming a separation trench vertically penetrating the stacked structure, and a plurality of dummy holes and dummy trenches vertically penetrating the second stacked structure;
forming a second dielectric layer in the separation groove, forming a first dielectric layer in the virtual hole, and forming a third dielectric layer in the virtual groove to form the separation structure, the virtual hole structure and the virtual ring structure;
and forming a peripheral conductive column in the first dielectric layer in the virtual hole structure, forming a sealing ring in the third dielectric layer in the virtual ring structure, and sequentially arranging the third dielectric layer and the sealing ring from the outer ring of the annular structure to the inner ring of the annular structure.
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