CN112466878A - Semiconductor device manufacturing method, semiconductor device and three-dimensional memory device - Google Patents
Semiconductor device manufacturing method, semiconductor device and three-dimensional memory device Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention provides a semiconductor device manufacturing method, a semiconductor device and a three-dimensional memory device, and particularly relates to the field of semiconductor integrated circuit manufacturing. The manufacturing method of the semiconductor device comprises the following steps: providing a semi-finished substrate, wherein the semi-finished substrate comprises a substrate body, a stacked layer arranged on the substrate body and an insulating covering layer covering the stacked layer; forming a dummy channel hole on the stacked layer and the insulating cover layer thereon; forming a support member in the dummy channel hole, wherein a support strength of the support member is greater than a support strength of an oxide insulating material. The manufacturing method of the semiconductor device, the semiconductor device and the three-dimensional memory device can increase the supporting strength of the pseudo channel structure and avoid the inclination and collapse of the step area.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular, to a semiconductor device manufacturing method, a semiconductor device, and a three-dimensional memory device.
Background
The NAND flash memory is a nonvolatile memory product with low power consumption, light weight and good performance, can still maintain stored data information under the condition of power failure, and is widely applied to electronic products. The three-dimensional memory device (3D NAND) is a novel flash memory type, and can further improve the storage capacity and reduce the storage cost on the basis of a two-dimensional NAND flash memory.
A step region and a storage string are arranged on an existing three-dimensional memory device, and for the step region in the three-dimensional memory device, a support member in a pseudo channel (Dummy channel DCH) plays an important structural support role. The dummy trenches are typically filled with an oxide insulating material to form supports for supporting functions. However, as the number of layers of the three-dimensional memory device increases, the supporting capability of the structure is not enough to support the step region, and the phenomenon that the step is inclined or even collapsed often occurs. In addition, in the metal connection process, a Peripheral Contact (PC) is often manufactured together with a metal connection part (CT) of the step area, and a peripheral Contact hole and a Contact hole of the step area are etched synchronously in the manufacturing process, so that not only is an etching window smaller, but also the process margin of the peripheral Contact is influenced, and DVC (distortion factor, which is an index of the distortion factor in English: Dark Contact) is easy to appear. In view of the above problems, it is desirable to provide a semiconductor device manufacturing method, a semiconductor device, and a three-dimensional memory device.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a semiconductor device manufacturing method, a semiconductor device and a three-dimensional memory device, which are used for improving the problem of poor pseudo-channel supporting capability in the existing semiconductor device manufacturing process.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a semi-finished substrate, wherein the semi-finished substrate comprises a substrate body, a stacked layer arranged on the substrate body and an insulating covering layer covering the stacked layer;
forming a dummy channel hole on the stacked layer and the insulating cover layer thereon;
forming a support member in the dummy channel hole, wherein a support strength of the support member is greater than a support strength of an oxide insulating material.
In an example of the present invention, a peripheral contact hole is simultaneously formed on the insulating cover layer at the periphery while the dummy channel hole is formed.
In an example of the present invention, the support is formed of a conductive material, and the fabrication method further includes a process of forming a dummy channel hole insulating sidewall in the dummy channel hole.
In an example of the present invention, the manufacturing method further includes a step of forming a contact hole insulating sidewall in the peripheral contact hole simultaneously when the dummy trench hole insulating sidewall is formed.
In an example of the present invention, the forming of the dummy trench hole insulating sidewalls and/or the contact hole insulating sidewalls includes: and forming an in-hole insulating layer in the pseudo channel hole and the peripheral contact hole, and correspondingly removing the bottom insulating layers of the pseudo channel hole and the peripheral contact hole.
In an example of the present invention, the process of forming the insulating layer includes a deposition process.
In an example of the present invention, the process of removing the bottom insulating layer of the dummy channel hole and the peripheral contact hole includes an etching process.
In an example of the present invention, the manufacturing method further includes a process of simultaneously forming the peripheral contact in the peripheral contact hole while forming the supporter.
In an example of the present invention, the method of forming the support and the peripheral contact includes a deposition process.
In one example of the present invention, the oxide insulating material is silicon oxide.
In an example of the present invention, the process of simultaneously forming the dummy channel hole and the peripheral contact hole includes a dry etching process.
In an example of the present invention, the manufacturing method further includes a process of forming a gate line slit after the support member is formed.
In an example of the present invention, the forming process of the gate line slit includes an etching process.
In an example of the present invention, the manufacturing method further includes a process of replacing the first dielectric layer in the stacked layer with a conductive layer.
In an example of the present invention, replacing the first dielectric layer in the stacked layer with a conductive layer includes: and etching and removing the first dielectric layer to form a plurality of cavities, and depositing a conductive layer in the cavities.
In an example of the present invention, the removing process of the first dielectric layer includes a wet etching process.
In an example of the present invention, the manufacturing method further includes a process of forming a surface insulating layer on the semiconductor device after replacing the first dielectric layer in the stacked layer with a conductive layer.
In an example of the present invention, the first dielectric layer is silicon nitride.
The invention also provides a semiconductor device which is prepared by adopting the manufacturing method of the semiconductor device.
The invention also provides a three-dimensional memory device, which comprises a substrate and a stacked layer arranged on the substrate, wherein a pseudo channel structure and a storage string are arranged on the stacked layer, the pseudo channel structure comprises a pseudo channel hole and a support arranged in the pseudo channel hole, and the support is formed by a material with the support strength higher than that of an oxide insulating material.
In an example of the present invention, the support is formed of a conductive material, an insulating sidewall is disposed in the dummy trench hole, and the support is formed in an inner hole of the insulating sidewall.
In an example of the present invention, the conductive material includes one or more of tungsten, copper, aluminum, gold, and silver.
As described above, the present invention provides a method for manufacturing a semiconductor device, and a three-dimensional memory device, which can increase the supporting strength of a dummy channel structure and prevent a step region from being inclined and collapsed. Meanwhile, the cost can be saved, the manufacturing of the contact element in the step area is not needed, and an etching window in the manufacturing process of the contact hole in the step area can be increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts;
FIG. 1 is a flow chart of one embodiment of a method for fabricating a semiconductor device according to the present invention;
FIG. 2 is a flowchart illustrating the detailed process of step S03 according to an embodiment of the method for fabricating a semiconductor device of the present invention;
FIG. 3 is a schematic diagram of a structure of a semi-finished substrate of the present invention;
FIG. 4 is a schematic diagram of a structure after forming a dummy channel hole and a peripheral contact hole simultaneously;
FIG. 5 is a schematic view of the structure after forming an insulating layer in the dummy channel hole and the peripheral contact hole;
FIG. 6 is a schematic diagram of the structure after removing the bottom insulating layer of the dummy channel hole and the peripheral contact hole;
FIG. 7 is a schematic structural view after forming a support member and a peripheral contact member in the dummy channel hole and the peripheral contact hole;
FIG. 8 is a schematic diagram of the structure after gate replacement is completed;
fig. 9 is a schematic view of a structure after a surface insulating layer is formed on a semiconductor device.
Description of the element reference numerals
1 semi-finished substrate
100 substrate body
200 layers stacked
201 dummy channel hole
2011 pseudo channel hole recess
202a dummy channel hole in-hole insulating layer
202 dummy trench hole insulating sidewalls
203 pseudo-channel hole insulating sidewall inner hole
204 support member
210 first dielectric layer
220 first dielectric layer
300 insulating cover layer
301 peripheral contact hole
3011 peripheral contact hole groove
302a contact hole internal insulation layer
302 contact hole insulating sidewall
303 contact hole insulation side wall inner hole
304 peripheral contact
400 surface insulating layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings in the embodiments of the present invention are partially schematic views, and only a part of the thickness and a part of the area in the stacked layers are taken as illustrations. The drawings provided in the embodiments are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the form, quantity and proportion of the components in the actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1 to 9, the present invention provides a method for manufacturing a semiconductor device, a semiconductor device and a three-dimensional memory device, which are used to solve the problems of weak pseudo channel supporting capability, simultaneous etching of a step region contact hole and a peripheral contact hole, and small etching window in the conventional three-dimensional memory device manufacturing process.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method including:
s01, providing a semi-finished substrate 1, wherein the semi-finished substrate 1 includes a substrate body 100, a stack layer 200 disposed on the substrate body 100, and an insulating cover layer 300 covering the stack layer 200 and the periphery thereof, and the stack layer 200 includes a first dielectric layer 210 and a second dielectric layer 220 alternately stacked. The second dielectric layer 220 may be a dielectric layer with an insulating function, such as an interlayer insulating layer, and the first dielectric layer 210 may be a conductive layer or a sacrificial layer, referring to fig. 3, fig. 3 is a schematic structural diagram of the semi-finished substrate 1 of the present invention. In this step, the semi-finished substrate 1 is a semi-finished product after certain process steps have been performed, wherein the substrate body 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the substrate body 100 may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, or SiC, or may also be a stacked structure, such as Si/SiGe, or may also be other substrate epitaxial layers, as an example of the present invention, in this embodiment, the substrate body 100 is a silicon substrate. The stacked layer 200 is formed by alternately stacking the second dielectric layers 220 and the first dielectric layers 210 and stacked in a direction perpendicular to the substrate body 100, and the number of the stacked layers 200 may be determined according to specific needs. In the present embodiment, the first dielectric layer 210 may be, for example, silicon nitride (Si)3N4) The second dielectric layer 220 may be, for example, silicon oxide (SiO)2). The insulating cap layer 300 may be, for example, silicon oxide (SiO)2). The second dielectric layer 220, the first dielectric layer 210, and the insulating cap layer 300 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. It should be noted that, in this step, the semi-finished substrate 1 may have other structures, such as a step region, a central storage region, a memory string, etc., or may not have these structures and be further fabricated after the fabrication of the method of the present invention is completed.
S02, a dummy channel hole 201 is formed on the stacked layer 200 and the insulating capping layer 300 thereon. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a dummy trench hole 201 formed in the stack 200 and the overlying insulating layer 300. In this step, a dummy channel hole 201 is formed in the stacked layer 200, wherein an upper portion of the dummy channel hole 201 penetrates through the insulating cover layer 300, and a bottom portion of the dummy channel hole 201 penetrates through the stacked layer 200 and sinks into the substrate body 100, thereby forming a dummy channel hole recess 2011. The process of forming the dummy channel holes 201 in this step includes, but is not limited to, a dry etching process, and may be, for example, an existing conventional channel hole etching process, such as a combination of a dry etching process, a wet etching process, and a subsequent cleaning process, in this embodiment, an anisotropic dry etching process is used, through the same anisotropic dry etching process, the dummy channel holes 201 are respectively formed on the stack layer 200, and the bottoms of the dummy channel holes 201 are etched into the substrate body 100, so as to form corresponding dummy channel hole recesses 2011.
S03, forming a support member 204 in the dummy channel hole 201, wherein the support member 204 has a support strength greater than that of the oxide insulating material. Referring to fig. 8, fig. 8 is a schematic structural view after forming a support 204 in the dummy trench hole 201. In this step, the support 204 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The oxide insulating material is an oxide insulating material commonly used in the conventional dummy trench filling process, such as silicon oxide. The material forming the support member 204 in the present invention may be any other material having a support strength greater than that of the conventional oxide insulating material for filling the dummy channel, including a metal conductive material and other insulating materials, as long as the material can enhance the support effect as long as the material has a support strength greater than that of the oxide insulating material for filling the dummy channel. Preferably, a support member 204 is formed in the dummy channel hole 201, and the support strength of the support member 204 is greater than that of the silicon oxide support member.
In an example of the present invention, a peripheral contact hole 301 is simultaneously formed on the insulating cover layer 300 at the periphery while the dummy channel hole 201 is formed. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a dummy channel hole 201 and a peripheral contact hole 301 formed on the substrate simultaneously. In this step, a dummy channel hole 201 is formed in the stacked layer 200 of the substrate, and a peripheral contact hole 301 is simultaneously formed in the insulating cover layer 300 at the periphery of the stacked layer 200, wherein the bottom portions of the dummy channel hole 201 and the peripheral contact hole 301 penetrate through the stacked layer 200 and the insulating cover layer 300 respectively and sink into the substrate body 100, and a dummy channel hole recess 2011 and a peripheral contact hole recess 3011 are formed respectively. In this step, the process of synchronously forming the dummy trench 201 and the peripheral contact hole 301 on the substrate includes, but is not limited to, a dry etching process, for example, a conventional trench etching process, such as a combination of a dry etching process, a wet etching process and a subsequent cleaning process, in this embodiment, an anisotropic dry etching process is used, after the same anisotropic dry etching process, a penetrating dummy trench 201 and a peripheral contact hole 301 are respectively formed on the stack layer 200 and the insulating cover layer 300, and bottoms of the dummy trench 201 and the peripheral contact hole 301 are respectively etched into the substrate body 100 to form a corresponding dummy trench 2011 and a corresponding peripheral contact hole 3011. In the step, the peripheral contact hole 301 and the pseudo channel hole 201 are etched synchronously, so that the cost can be reduced, and the step area contact hole etching window can be increased.
In an example of the present invention, in step S03, the supporting element 204 is formed of a conductive material, referring to fig. 2, fig. 2 is a flowchart illustrating a step S03 of an embodiment of a method for fabricating a semiconductor device according to the present invention. The step S03 further includes a step S031: a process of forming dummy channel hole insulating sidewalls 202 within the dummy channel holes 201. Referring to fig. 6, the process of forming the dummy trench insulating sidewall 202 in the dummy trench hole 201 includes: a dummy channel hole insulating layer 202a is formed in the dummy channel hole 201 as shown in fig. 5, and the bottom insulating layer of the dummy channel hole 201 is removed, thereby forming a dummy channel hole insulating sidewall 202 as shown in fig. 6. The dummy trench hole internal insulating layer 202a may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The process of removing the bottom insulating layer of the dummy channel hole 201 includes, but is not limited to, a dry etching process, such as a combination of dry etching, wet etching and a subsequent cleaning process. It should be noted that, in the process of etching and removing the bottom insulating layer of the dummy trench hole 201, a part of the sidewall insulating layer is also consumed.
In order to save the process and reduce the cost, in an example of the present invention, the step S03 further includes the step S032: the process of forming the contact hole insulating sidewalls 302 within the peripheral contact holes 301 is synchronized when forming the dummy channel hole insulating sidewalls 202. As shown in fig. 5 to 6, the process of simultaneously forming the dummy trench hole insulating sidewalls 202 and the contact hole insulating sidewalls 302 includes: and synchronously forming a pseudo channel hole internal insulating layer 202a and a contact hole internal insulating layer 302a on the pseudo channel hole 201 and the peripheral contact hole 301, and synchronously etching to correspondingly remove the bottom insulating layers of the pseudo channel hole 201 and the peripheral contact hole 301. The dummy channel intra-hole insulating layer 202a and the contact intra-hole insulating layer 302a are formed simultaneously by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The process of removing the bottom insulating layer of the dummy channel hole 201 and the bottom insulating layer of the peripheral contact hole 301 is performed by the same removing step, which includes, but is not limited to, a dry etching process, such as a combination of dry etching, wet etching, and a subsequent cleaning process.
In another example of the present invention, the above-mentioned contact hole insulating sidewalls 302 are separately formed before or after the formation of the dummy channel hole insulating sidewalls 202. The process of forming the contact hole insulating sidewalls 302 includes: a contact hole inner insulating layer 302a is formed in the peripheral contact hole 301, and a bottom insulating layer of the peripheral contact hole 301 is removed accordingly. The contact hole internal insulating layer 302a may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The process of removing the bottom insulating layer of the peripheral contact hole 301 includes, but is not limited to, a dry etching process, such as a combination of dry etching, wet etching and a subsequent cleaning process.
In the present invention, the time for forming the peripheral contact 304 in the peripheral contact hole 301 may not be limited, or may be performed separately before or after the support 204 is formed, and in order to save the process, the step is omitted, referring to fig. 2, in an example of the present invention, the step S03 further includes the step S033: the process of forming peripheral contacts 304 within the contact hole insulating sidewalls 302 is synchronized as supports 204 are formed within the dummy channel hole insulating sidewalls 202. While forming the support 204 in the dummy channel hole insulating sidewall 202, after simultaneously forming the peripheral contact 304 in the contact hole insulating sidewall 302, the semiconductor device structure as shown in fig. 7 is formed. It should be noted that when the peripheral contact 304 and the support 204 are formed simultaneously, the support 204 should be made of a conductive material, and in an example of the present invention, the support 204 and the peripheral contact 304 may be formed by depositing a conductive material (e.g., W) in the contact hole insulating sidewall inner hole 303 and the dummy trench hole insulating sidewall inner hole 203 through one or more thin film deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.
In an example of the present invention, the oxide insulating material is silicon oxide, and the conductive material forming the support 204 and the peripheral contact 304 includes one or more of tungsten, copper, aluminum, gold, and silver. Conductive materials are formed inside the insulating sidewalls in the dummy channel hole 201 and inside the insulating sidewalls in the peripheral contact hole 301, respectively, and are effectively insulated from the first dielectric layer 210 in the stack layer 200.
In an example of the present invention, the first dielectric layer is a sacrificial layer, and the manufacturing method further includes a process of forming a gate line gap (not shown) after the support member 204 is formed. The gate line slit is disposed in the stacked layer 200, penetrates through the substrate body 100 along a direction perpendicular to the substrate body 100, and divides the stacked layer 200 into a plurality of storage regions, and is used for removing the first dielectric layer 210 in the stacked layer 200 and replacing the first dielectric layer with a gate layer. The gate line gap can be formed by the conventional gate line gap forming method, such as various etching processes, for example: all means for forming the gate line gap, such as a combination of dry etching, wet etching and a subsequent cleaning process, are used, and in this embodiment, an anisotropic dry etching process is used to form the gate line gap.
In view of the manufacturing process of the three-dimensional memory device, please refer to fig. 7 to 8, and fig. 7 to 8 are the structural diagrams of the semiconductor device before and after the gate replacement, respectively. The manufacturing method of the present invention may further include a process of replacing the first dielectric layer 210 (silicon nitride layer) with a metal layer. In some embodiments, this replacement is also referred to as a "gate replacement" process, replacing the first dielectric layer 210 silicon nitride layer in the stack 200 with a metal layer (e.g., W). The process of replacing the silicon nitride layer with the metal layer includes: the first dielectric layer 210 is removed by etching to form a plurality of cavities, a metal layer is deposited in the cavities, and the cavities after the silicon nitride layer is removed can be filled with the metal layer (e.g., W) by wet etching the silicon nitride layer relative to the silicon oxide layer. In an example of the present invention, the removing of the first dielectric layer 210 is performed by a wet etching process, and an acid method may be used to etch and remove the first dielectric layer 210 in the stacked layer 200, in an implementation of the present embodiment, an acid solution with a high selectivity ratio between the first dielectric layer 210 (silicon nitride) and the second dielectric layer 220 (silicon oxide) is selected, so as to avoid the removal of the second dielectric layer 220 while removing the first dielectric layer 210, for example, phosphoric acid (H3PO4) may be used to remove the silicon nitride layer. The metal layer in the present invention may be filled by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In this embodiment, the metal layer is formed by a physical vapor deposition method.
Referring to fig. 9, in an example of the present invention, the method further includes a step of forming a surface insulating layer 400 on the semiconductor device after replacing the first dielectric layer 210 in the stack layer 200 with a conductive layer. The formation of the surface insulating layer 400 may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Before and after the surface insulating layer 400 is formed, a planarization process may be performed to achieve a better deposition effect, and the planarization process may be a chemical mechanical polishing process or a wafer planarization process commonly used in other semiconductor fields.
In an example of the present invention, there is also provided a semiconductor device manufactured by the semiconductor device manufacturing method described in any one of the above.
Referring to fig. 9, in an example of the present invention, there is further provided a three-dimensional memory device, including a substrate body 100 and a stacked layer 200 disposed on the substrate body 100, the stacked layer 200 and a periphery thereof are covered with an insulating cover layer 300, a dummy channel structure is disposed on the stacked layer 200, a peripheral contact structure is disposed on the insulating cover layer 300 at the periphery of the stacked layer 200, wherein the dummy channel structure includes a dummy channel hole 201 and a support 204 disposed in the dummy channel hole 201, and the support 204 is formed of a material having a supporting strength greater than that of an oxide insulating material. In an example of the present invention, the support member 204 is formed of a conductive material, an insulating sidewall is disposed in the dummy channel hole 201, and the support member 204 is formed in an inner hole of the insulating sidewall. In an example of the present invention, the conductive material includes one or more of tungsten, copper, aluminum, gold, and silver. In an example of the present invention, the peripheral contact structure includes a peripheral contact hole 301 and an insulating sidewall disposed within the peripheral contact hole 301, and a peripheral contact 304 formed within the insulating sidewall. The peripheral contact 304 is made of the same material as the support 204. By adopting the structure, the peripheral contact hole 301 and the dummy channel hole 201 can be synchronously etched, the insulating side walls in the peripheral contact hole 301 and the dummy channel hole 201 can also be synchronously formed, the supporting piece 204 and the peripheral contact piece 304 can also be synchronously formed, the working procedure and the cost can be saved, the etching window of a step area can be increased, the supporting strength of the dummy channel structure can be improved by adopting a metal material with higher hardness strength, and the three-dimensional memory device has more stable performance.
It should be noted that the three-dimensional memory device of the present invention also includes other common structures, such as memory strings, step regions, step region peripheral contacts, etc., and will not be described in detail herein.
As described above, the present invention provides a method for manufacturing a semiconductor device, and a three-dimensional memory device, which can increase the supporting strength of a dummy channel structure and prevent a step region from being inclined and collapsed. Meanwhile, the cost can be saved, the manufacturing of the contact element in the step area is not needed, and an etching window in the manufacturing process of the contact hole in the step area can be increased. Therefore, the invention effectively overcomes some practical problems in the prior art, thereby having high utilization value and use significance.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (22)
1. A method for manufacturing a semiconductor device, comprising:
providing a semi-finished substrate, wherein the semi-finished substrate comprises a substrate body, a stacked layer arranged on the substrate body and an insulating covering layer covering the stacked layer;
forming a dummy channel hole on the stacked layer and the insulating cover layer thereon;
forming a support member in the dummy channel hole, wherein a support strength of the support member is greater than a support strength of an oxide insulating material.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a peripheral contact hole is simultaneously formed in the insulating cover layer on the periphery at the same time as the formation of the dummy channel hole.
3. A method of fabricating a semiconductor device according to claim 2, wherein the support member is formed of a conductive material, the method further comprising a process of forming dummy channel hole insulating sidewalls in the dummy channel holes.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of forming a contact hole insulating sidewall in the peripheral contact hole simultaneously with the step of forming the dummy channel hole insulating sidewall.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the dummy trench hole insulating sidewall and/or the contact hole insulating sidewall comprises: and forming an in-hole insulating layer in the pseudo channel hole and the peripheral contact hole, and correspondingly removing the bottom insulating layers of the pseudo channel hole and the peripheral contact hole.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the insulating layer comprises a deposition process.
7. The manufacturing method of a semiconductor device according to claim 5, wherein the process of removing the bottom insulating layer of the dummy channel hole and the peripheral contact hole includes an etching process.
8. The semiconductor device manufacturing method according to any one of claims 3 to 7, further comprising a process of simultaneously forming a peripheral contact in the peripheral contact hole while forming the support.
9. The method of fabricating a semiconductor device according to claim 8, wherein the method of forming the support and the peripheral contact comprises a deposition process.
10. The method according to claim 1, wherein the oxide insulating material is silicon oxide.
11. The method of manufacturing a semiconductor device according to claim 2, wherein the process of simultaneously forming the dummy channel hole and the peripheral contact hole includes a dry etching process.
12. The method of manufacturing a semiconductor device according to claim 1, further comprising a process of forming a gate line slit after the support member is formed.
13. The method of manufacturing a semiconductor device according to claim 12, wherein the forming of the gate line slit includes an etching process.
14. The method of manufacturing a semiconductor device according to claim 13, further comprising replacing the first dielectric layer in the stacked layers with a conductive layer.
15. The method of claim 14, wherein replacing the first dielectric layer in the stack with a conductive layer comprises: and etching and removing the first dielectric layer to form a plurality of cavities, and depositing a conductive layer in the cavities.
16. The method for manufacturing a semiconductor device according to claim 14, wherein the process for removing the first dielectric layer comprises a wet etching process.
17. The method of manufacturing a semiconductor device according to claim 14, further comprising a process of forming a surface insulating layer on the semiconductor device after replacing the first dielectric layer in the stacked layers with a conductive layer.
18. The method of manufacturing a semiconductor device according to claim 1, wherein the first dielectric layer is silicon nitride.
19. A semiconductor device characterized by being produced by the semiconductor device production method according to any one of claims 1 to 18.
20. A three-dimensional memory device includes a substrate body and a stacked layer disposed on the substrate body, the stacked layer having a dummy channel structure and a memory string disposed thereon, wherein the dummy channel structure includes a dummy channel hole and a support disposed in the dummy channel hole, the support being formed of a material having a support strength greater than that of an oxide insulating material.
21. The three-dimensional memory device of claim 20, wherein the support is formed of a conductive material, an insulating sidewall is disposed within the dummy channel hole, and the support is formed within an inner hole of the insulating sidewall.
22. The three-dimensional memory device of claim 21, wherein the conductive material comprises one or more of tungsten, copper, aluminum, gold, silver.
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| CN113725225A (en) * | 2021-08-20 | 2021-11-30 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN113629059B (en) * | 2021-05-21 | 2024-05-10 | 长江存储科技有限责任公司 | Manufacturing method of 3D memory device and 3D memory device |
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