CN110896046A - Shallow trench isolation structure, semiconductor device and preparation method thereof - Google Patents
Shallow trench isolation structure, semiconductor device and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The invention provides a shallow trench isolation structure, a semiconductor device and a preparation method thereof, which can form an insulating side wall on the side wall of a dielectric material layer above a semiconductor substrate, thereby eliminating the side ditch phenomenon of the shallow trench isolation structure, avoiding the problems of element electric leakage and the like, improving the reliability of the device and being suitable for manufacturing semiconductor device products such as an integrated circuit memory and the like.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a shallow trench isolation structure, a semiconductor device and a preparation method thereof.
Background
As the feature size of semiconductor devices is reduced, the isolation area between devices is also reduced accordingly and becomes important to prevent the adjacent devices from short-circuiting. Referring to fig. 1, the STI technology specifically uses silicon nitride (not shown) as a protection layer, and etches a Shallow trench in a semiconductor substrate 100 by photolithography and etching, and then fills silicon oxide (e.g., high-concentration plasma silicon dioxide HDP oxide)102 as a dielectric substance to form an STI structure 11 for electrically isolating adjacent devices in an integrated circuit. However, due to the existence of wet etching processes for silicon oxide in the subsequent processes, such as wet etching of the pad oxide layer 101 on the surface of the semiconductor substrate 100, due to the isotropic characteristic of the wet etching, the corners of the STI structures 11 near the Active Area (AA) are etched by the wet etching processes, so as to generate the side trenches (divot)103, and the side trenches 103 may cause leakage of the formed devices, and even cause failure of the integrated circuit.
Therefore, a new semiconductor device having a shallow trench isolation structure and a method for manufacturing the same are needed, which can eliminate divot phenomenon of the STI structure, avoid the problems of element leakage and the like, and improve the reliability of the device.
Disclosure of Invention
The invention aims to provide a shallow trench isolation structure, a semiconductor device and a preparation method thereof, which can eliminate side trenches of the shallow trench isolation structure, avoid the problems of element electric leakage and the like and improve the reliability of the device.
In order to achieve the above object, the present invention provides a method for preparing a shallow trench isolation structure, comprising the following steps:
providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate, wherein a first groove is formed in the hard mask layer;
etching the semiconductor substrate by taking the hard mask layer as a mask to form a second groove corresponding to the first groove in the semiconductor substrate;
filling a dielectric material layer in the second trench and the first trench, wherein the dielectric material layer fills the first trench and the second trench;
removing the hard mask layer, wherein the part, corresponding to the first groove, in the dielectric material layer protrudes relative to the surface of the semiconductor substrate to form a protruding side wall; and the number of the first and second groups,
and forming an insulating side wall on the protruding side wall of the dielectric material layer.
Optionally, the depth of the second trench in the semiconductor substrate is 300nm to 600 nm.
Optionally, the step of filling the dielectric material layer in the second trench includes:
depositing the dielectric material layer on the hard mask layer, wherein the second groove is filled with the dielectric material layer;
densifying the dielectric material layer; and the number of the first and second groups,
planarizing a top surface of the dielectric material layer to a top surface of the hard mask layer.
Optionally, a dry etching process is used to remove the hard mask layer, and the dry etching process also etches the dielectric material layer at the same time to reduce the height of the protruding sidewall of the dielectric material layer.
Optionally, the step of forming the insulating sidewall spacer includes:
forming an insulating dielectric layer on the semiconductor substrate and the dielectric material layer by adopting an atomic layer deposition method, a chemical vapor deposition method or a thermal oxidation method, wherein the insulating dielectric layer covers the top surface of the dielectric material layer and the protruding side wall; and the number of the first and second groups,
and etching to remove the part of the insulating medium layer covering the top surface of the dielectric material layer and the semiconductor substrate, and reserving the part of the insulating medium layer covering the protruding side wall of the dielectric material layer to form the insulating side wall.
Optionally, the thickness of the insulating side wall is 5nm to 35 nm.
Optionally, the step of forming the hard mask layer having the first trench includes:
forming a first patterning layer on the hard mask layer;
etching the hard mask layer to the surface of the semiconductor substrate by taking the first patterning layer as a mask so as to transfer the first patterning layer into the hard mask layer;
removing the first patterning layer, and sequentially forming a covering layer and a second patterning layer on the hard mask layer and the semiconductor substrate, wherein the covering layer fills pattern gaps in the hard mask layer, and the second patterning layer has a different pattern from the first patterning layer;
etching the covering layer by taking the second patterning layer as a mask, and stopping etching on the surface of the hard mask layer so as to transfer the pattern in the second patterning layer into the covering layer;
and removing the second patterning layer, and etching a hard mask layer to the surface of the semiconductor substrate by taking the covering layer as a mask so as to transfer the pattern in the covering layer into the hard mask layer, thereby forming the first groove in the hard mask layer.
Optionally, the first patterned layer has a plurality of lines extending along the first direction, and after the pattern of the first patterned layer is transferred to the hard mask layer, the hard mask layer has a plurality of initial lines extending along the first direction, and a first channel is defined between two adjacent initial lines.
Optionally, the second patterning layer has a pattern which is aligned with the initial line of the hard mask layer and exposes a partial region of the initial line, after the pattern in the covering layer is transferred into the hard mask layer, a second channel is formed in the hard mask layer, the initial line is cut into short lines by the second channel, the second channel is communicated with the first channels on two sides of the initial line, and the first channel and the second channel form the first channel.
The present invention also provides a shallow trench isolation structure, comprising:
the dielectric material layer is filled in the groove of the semiconductor substrate, and the top surface of the dielectric material layer is higher than the top surface of the semiconductor substrate to form a convex side wall; and the number of the first and second groups,
and the insulating side wall is formed on the protruding side wall of the dielectric material layer.
Optionally, the thickness of the insulating side wall is 5nm to 35 nm.
Optionally, the depth of the trench in the semiconductor substrate is 300nm to 600 nm.
Optionally, the groove extends along an inclined first direction, and an included angle between the first direction and a horizontal direction from left to right is 5 ° to 85 °.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps: the shallow trench isolation structure is prepared by adopting the preparation method of the shallow trench isolation structure.
Optionally, a core region and a peripheral region are defined on the semiconductor substrate, the core region and the peripheral region are isolated from each other by the shallow trench isolation structure, and a plurality of shallow trench isolation structures are further formed in the core region of the semiconductor substrate to define a plurality of active regions arranged in an array in the core region;
the preparation method of the semiconductor device further comprises the following steps: manufacturing memory cells on each active region to form a memory array in the core region; and manufacturing a peripheral circuit in the peripheral area, wherein the peripheral circuit is electrically connected with the corresponding memory unit in the memory array.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate having a trench; and the number of the first and second groups,
according to the shallow trench isolation structure, the shallow trench isolation structure is formed in the trench, and the top surface of the shallow trench isolation structure is higher than the top surface of the semiconductor substrate.
Optionally, the semiconductor device is a memory, a core region and a peripheral region are defined on the semiconductor substrate, the core region and the peripheral region are isolated from each other by using the shallow trench isolation structure, the core region of the semiconductor substrate further includes a plurality of shallow trench isolation structures, the peripheral region of the semiconductor substrate further includes the shallow trench isolation structure, a top width of the shallow trench isolation structure of the core region is smaller than a top width of the shallow trench isolation structure of the peripheral region, and a trench depth corresponding to the shallow trench isolation structure of the core region is smaller than a trench depth corresponding to the shallow trench isolation structure of the peripheral region.
Optionally, all the shallow trench isolation structures in the core region define a plurality of active regions arranged in an array in the semiconductor substrate of the core region, and the semiconductor device further includes: memory cells formed on each of the active regions, all of the memory cells forming a memory array in the core region; and peripheral circuitry formed in the peripheral region, the peripheral circuitry being electrically connected to respective ones of the memory cells in the memory array.
Compared with the prior art, the shallow trench isolation structure, the semiconductor device and the preparation method thereof have the following beneficial effects:
1. the side-ditch phenomenon of the shallow trench isolation structure is eliminated by forming the insulating side wall on the convex side wall of the dielectric material layer above the semiconductor substrate, so that the problems of element electric leakage and the like are avoided, and the reliability of the device is improved.
2. The semiconductor substrate can be divided into a core area and a peripheral area through the formed shallow trench isolation structure, the key sizes of the shallow trench isolation structures in the core area and the peripheral area can be different, and the shallow trench isolation structure is suitable for manufacturing semiconductor device products such as an integrated circuit memory and the like.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional shallow trench isolation structure with a side-trench problem.
Fig. 2 is a flowchart of a method for fabricating a shallow trench isolation structure according to an embodiment of the invention.
Fig. 3A and 4A are schematic top-view structural diagrams of the method for fabricating a shallow trench isolation structure according to the embodiment of the invention in the process of fabricating a hard mask layer having a first trench when step S1 is performed.
Fig. 3B is a schematic cross-sectional view taken along line XX' in fig. 3A.
Fig. 4B is a schematic cross-sectional view taken along line XX' in fig. 4A.
Fig. 5A, 6A and 7A are schematic top-view structural diagrams of the method for fabricating a shallow trench isolation structure according to the embodiment of the invention in the process of fabricating the second trench of the hard mask layer when step S1 is performed.
Fig. 5B and 5C are schematic cross-sectional views along the line XX 'and the line YY' in fig. 5A, respectively.
Fig. 6B and 6C are schematic cross-sectional views along the line XX 'and the line YY' in fig. 6A, respectively.
Fig. 7B and 7C are schematic sectional views along the line XX 'and the line YY' in fig. 7A, respectively.
Fig. 8A is a schematic top view (with the hard mask layer omitted) of the method for fabricating a shallow trench isolation structure according to the embodiment of the invention, in which step S2 is performed.
Fig. 8B and 8C are schematic cross-sectional views along line XX 'and line YY' in fig. 8A, respectively (showing a hard mask layer).
Fig. 9A is a schematic top view illustrating the step S3 in the method for fabricating the sti structure according to the embodiment of the invention.
Fig. 9B and 9C are schematic cross-sectional views along the line XX 'and the line YY' in fig. 9A, respectively.
Fig. 10A is a schematic top view illustrating the step S4 in the method for fabricating the sti structure according to the embodiment of the invention.
Fig. 10B and 10C are schematic sectional views along the line XX 'and the line YY' in fig. 10A, respectively.
Fig. 11A and 12A are schematic top-view structural diagrams during the step S4 in the method for fabricating a shallow trench isolation structure according to the embodiment of the invention.
Fig. 11B and 11C are schematic sectional views along the line XX 'and the line YY' in fig. 11A, respectively.
Fig. 12B and 12C are schematic sectional views along the line XX 'and the line YY' in fig. 12A, respectively.
Fig. 13 is a schematic cross-sectional view of a shallow trench isolation structure in a semiconductor device in accordance with an embodiment of the present invention.
Wherein the reference numerals are as follows:
100. 300-a semiconductor substrate;
101-pad oxide layer;
102-silicon oxide;
11. 307-shallow trench isolation structures (i.e., STI structures);
103-side ditch;
300 a-a second trench in the semiconductor substrate extending along line XX';
300 b-a second trench in the semiconductor substrate along the YY' line;
300 c-a wide trench formed by combining a second trench 300a and second trenches 300b communicated with the two sides of the second trench in the semiconductor substrate;
300 d-active area;
301-a hard mask layer;
3011-initial lines in the hard mask layer;
301 a-a first channel in the hard mask layer;
301 b-short lines in the hard mask layer;
301c — a second channel in the hard mask layer;
301 d-a wide channel formed by combining a second channel in the hard mask layer and first channels communicated with the two sides of the second channel;
302-a first patterned layer;
302 a-lines in a first patterned layer;
302 b-openings in a first patterned layer;
303-a cover layer;
303 a-openings in the cover layer;
304-a second patterned layer;
304 a-openings in a second patterned layer;
305-a layer of dielectric material;
305 a-the raised sidewalls of the dielectric material layer;
306-an insulating dielectric layer;
306 a-insulating side walls;
307-shallow trench isolation structures;
3071-shallow trench isolation structure in the peripheral region;
3072 shallow trench isolation structures in the core region;
i-a peripheral region;
II-core region;
h1 — buried depth of the shallow trench isolation structure in the peripheral region in the semiconductor substrate 300;
h2 — buried depth of shallow trench isolation structures in the core region in the semiconductor substrate 300;
w1 — top width of shallow trench isolation structure in peripheral region;
w2 — top width of shallow trench isolation structures in core area;
d-the linewidth of insulating sidewall spacers 306 a.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings in order to make the objects and features of the present invention more comprehensible, however, the present invention may be realized in various forms and should not be limited to the embodiments described above. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 2, the present invention provides a method for fabricating a shallow trench isolation structure, which includes the following steps:
s1, providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate, wherein a first groove is formed in the hard mask layer;
s2, etching the semiconductor substrate by taking the hard mask layer as a mask to form a second groove corresponding to the first groove in the semiconductor substrate;
s3, filling a dielectric material layer in the second trench and the first trench, the dielectric material layer filling the first trench and the second trench;
s4, removing the hard mask layer, wherein the part of the dielectric material layer corresponding to the first groove protrudes relative to the surface of the semiconductor substrate to form a protruding side wall;
and S5, forming an insulating side wall on the protruding side wall of the dielectric material layer.
Fig. 3A, fig. 4A, fig. 5A, fig. 6A, and fig. 7A are schematic top-view structural diagrams of the method for fabricating a shallow trench isolation structure according to the present embodiment during the step S1, fig. 3B is a schematic cross-sectional diagram along line XX 'in fig. 3A, and fig. 4B is a schematic cross-sectional diagram along line XX' in fig. 4A; FIG. 5B is a schematic cross-sectional view taken along line XX' in FIG. 5A; FIG. 6B is a schematic cross-sectional view taken along line XX' in FIG. 6A; FIG. 7B is a schematic cross-sectional view taken along line XX' in FIG. 7A; FIG. 6C is a schematic cross-sectional view taken along line YY' in FIG. 6A; fig. 7C is a schematic cross-sectional view taken along the line YY' in fig. 7A.
Referring to fig. 3A to 3B, fig. 4A to 4B, fig. 5A to 5C, fig. 6A to 6C and fig. 7A to 7C, in step S1, a semiconductor substrate 300 is provided, and a hard mask layer 301 having a first trench for forming a second trench required in the semiconductor substrate 300 is formed on the semiconductor substrate 300, so that the size, shape and extending direction of the first trench formed in the hard mask layer 301 can be adjusted according to the semiconductor device to be actually fabricated. The scheme of forming the hard mask layer 301 having the first trench according to the present invention is described in detail below with an example of an objective of manufacturing an isolation trench between memory cells in a memory array of a memory, and specifically includes the following steps:
referring to fig. 3A and 3B, a semiconductor substrate 300 is provided, and the semiconductor substrate 300 provides an operation platform for subsequent processes, which may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a die, or a wafer processed by an epitaxial growth process. The semiconductor substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, a germanium-on-insulator (ge) substrate, or the like. Then, a pad oxide layer (not shown) may be formed on the surface of the semiconductor substrate 300 by a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, or the like. Next, a dielectric material with a high selectivity ratio, such as silicon nitride or silicon oxynitride, is deposited on the surface of the pad oxide layer by a thermal oxidation process, an atomic layer deposition process, or a chemical vapor deposition process, so as to form a dielectric material film (not shown). The dielectric material film and the pad oxide layer constitute the hard mask layer 301 of this embodiment. In addition, a lateral direction (i.e., XX ' extending direction in fig. 3A) and a longitudinal direction (not shown, i.e., horizontal direction from left to right in fig. 3A) perpendicular to each other may be predefined in a plane of the surface of the semiconductor substrate 300, for example, when the sti structure is used to define an active region corresponding to a memory cell in a memory array, the lateral direction may be defined to form an angle with an extending direction of a word line (e.g., LL ' line extending direction in fig. 8A) or an extending direction of a bit line (e.g., YY ' line extending direction in fig. 8A), and the longitudinal direction may be perpendicular to the lateral direction. Of course, in other embodiments of the present invention, it is also possible to define the lateral direction as the same direction as the extending direction of the word line or the extending direction of the bit line, and the longitudinal direction and the lateral direction intersect perpendicularly.
Referring to fig. 3A and 3B, a photoresist (not shown) may be used to coat the surface of the hard mask layer 301, and an exposure process and a developing process may be performed to form the first patterned layer 302, where the first patterned layer 302 may have a plurality of parallel lines 302a arranged at equal intervals, and a linear opening 302B exposing the surface of the hard mask layer 301 is formed between adjacent lines 302 a. Wherein the line 302a extends along a first direction (as shown by the direction of the YY ' line in fig. 5A, i.e., the bit line direction of the memory), and a first included angle of 5 ° to 85 ° is formed between the lines 302a and XX ', i.e., the sum of the first included angle and the included angle of the line 302a with the horizontal direction from left to right in fig. 3A (i.e., the predefined longitudinal direction perpendicular to the XX line ') is equal to 90 °, i.e., the included angle of the line 302a with the horizontal direction from left to right in fig. 3A (i.e., the direction from left to right in the fig.) is also in the range of 5 ° to 85 °.
Referring to fig. 4A and 4B, with the first patterned layer 302 as a mask, the hard mask layer 301 is etched on the surface of the semiconductor substrate 300 by using a plasma dry etching process, so as to transfer the pattern of the first patterned layer 302 into the hard mask layer 301. At this time, initial lines 3011 (i.e., the pattern of the hard mask layer 301) extending along the first direction are formed in the hard mask layer 301, and a first channel 301a is defined between two adjacent initial lines 3011, that is, the first channel 301a is located between two adjacent initial lines 3011 and is a pattern gap of the hard mask layer 301, and the bottom of the first channel 301a exposes the surface of the semiconductor substrate 300.
Step four, referring to fig. 5A to 5C, the first patterned layer 302 may be removed by an ashing process, and the capping layer 303 may be formed on the hard mask layer 301 by spin coating, vapor deposition, and the like, where the thickness of the capping layer 303 is sufficient to fill the first trench 301a (i.e., the pattern gap of the hard mask layer 301) and provide a flat upper surface, and the material of the capping layer 303 is, for example, amorphous carbon, porous carbon, organic dielectric material (ODL), and the material of the capping layer can spontaneously form a flat upper surface after deposition, or silicon oxide, silicon oxynitride, titanium nitride, and the like that require top surface planarization, and the material of the capping layer 303 needs to be further combined with a chemical mechanical polishing process to provide a flat upper surface, and the material of the capping layer 303 has a higher etching selectivity ratio to the hard mask layer 301 so as to facilitate subsequent removal; then, the surface of the capping layer 303 is coated with photoresist (not shown), and an exposure process, a development process, and the like may be performed to form a second patterned layer 304, the second patterned layer 304 having a pattern (i.e., an opening 304a in fig. 5A) aligned with the initial line 3011 of the hard mask layer 301 and exposing a partial region of the initial line 3011, which is different from the pattern of the first patterned layer 302. In addition, the openings 304a above each of the initial lines 3011 are arranged at equal intervals along the first direction, and the intervals ultimately define the size and the position of active regions to be formed in the semiconductor substrate 300.
Step five, referring to fig. 6A to 6C, the second patterned layer 304 is used as a mask, the capping layer 303 is etched by using a plasma dry etching process, and the etch stops on the surface of the initial line 3011 of the hard mask layer 301, to transfer the pattern in the second patterned layer 304 into the cap layer 303, which, at this point, the covering layer 303 has an opening 303a formed therein above the initial line 3011 of the hard mask layer 301, a width of the opening 303a along the XX ' line extending direction may be equal to or greater than a width of the initial line 3011 along the XX ' line extending direction, a length of the opening 303a along the first direction (i.e., the YY line extending) is less than a length of the initial line 3011 along the YY ' line extending direction, and the covering layer 303 above each initial line 3011 may have a plurality of spaced openings 303a along the initial line 3011 for performing etching segmentation on a plurality of places of the initial line 3011.
Step six, referring to fig. 7A to 7C, removing the second patterned layer 304, and etching the initial line 3011 of the hard mask layer 301 to the surface of the semiconductor substrate 300 by using the capping layer 303 as a mask and using a plasma dry etching process to transfer the pattern in the capping layer 303 into the hard mask layer 301, where the pattern of the hard mask layer 301 is actually a combination of the patterns of the first patterned layer 302 and the second patterned layer 304, so as to combine the pattern of the semiconductor substrate 300 to be obtained in the present invention in the semiconductor substrate 300, for example, in this embodiment, the hard mask layer 301 is divided into an array by combining the patterns of the first patterned layer 302 and the second patterned layer 304, the array has a parallelogram-shaped line 301b extending along a first direction (i.e. a YY' line extending direction), and a second channel 301C is provided between two adjacent lines 301b distributed along the first direction, two adjacent lines 301b distributed along the extending direction of the XX 'line are staggered and have a first trench 301a therebetween, and two first trenches 301a between two opposite lines 301b distributed along the extending direction of the XX' line are communicated with a second trench 301c at the side wall to form a wider wide trench 301d, or the second trench 301c is communicated with the side wall of the first trench 301a on both sides of the corresponding line 301b, thereby forming the wide trench 301 d. That is, the first channel 301a and the second channel 301c in the hard mask layer 301 form a first trench (301a +301c +301d) of the hard mask layer 301. Thereafter, the remaining capping layer 303 may be removed to expose the surface of the hard mask layer 301.
Fig. 8A is a schematic top view of the method for fabricating a shallow trench isolation structure in the present embodiment during the step S2, and fig. 8A is a schematic top view of the semiconductor substrate 300 with the trench after the hard mask layer is omitted; FIG. 8B is a schematic cross-sectional view taken along line XX' in FIG. 8A; fig. 8C is a schematic cross-sectional view taken along the line YY' in fig. 8A.
Referring to fig. 8A to 8C, in step S2, the semiconductor substrate 300 is etched by using the hard mask layer 301 having the first trench (i.e., the combination of the first trench 301a and the second trench 301C) as a mask, and a plasma dry etching process is performed to form a second trench 300a corresponding to the second trench 301C and a second trench 300b corresponding to the first trench 301a in the semiconductor substrate 300. At this time, the semiconductor substrate 300 is divided into an array of active regions 300d by the second trenches 300b and 300a, which can be used to fabricate a memory array, and the sidewalls of the second trenches 300a extending along the first direction are connected to the second trenches 300b at two sides to form wide trenches 300c (i.e., corresponding to the wide trenches 301d in the hard mask layer 301). The outer contour of each active region 300d is a parallelogram and is arranged at equal intervals in the first direction (i.e., the direction in which the YY 'line extends) and is arranged in parallel in a direction perpendicular to the first direction (i.e., the direction in which the LL' line extends). The cross-sectional shapes of the second trench 300b and the second trench 300a may be any shapes, and the inverted trapezoid is selected in this example, so that the aspect ratio of subsequent material filling can be reduced, and the problem of filling voids can be improved. The second trenches 300b and 300a have a depth ranging from 300nm to 600 nm. Since the opening of the area corresponding to the wide trench 300c is larger and the opening of the area corresponding to the second trench 300a is smaller, the etching process for forming the wide trench 300c and the second trench 300a has different etching rates in the areas corresponding to the wide trench 300c and the second trench 300a, so that the depth (as shown in the figure) of the wide trench 300c is slightly larger than the depth of the second trench 300a, and the depth difference is in the range of 10nm to 200 nm.
It should be noted that, in the embodiment of the present invention, according to actual requirements, the patterns in the first patterned layer 302 and the second patterned layer 304 may be adjusted to change the combined effect of the patterns in the first patterned layer 302 and the second patterned layer 304, so that the array arrangement effect of the semiconductor substrate 300 divided by all trenches is different, and thus the outer contour of each active region 300d divided by the semiconductor substrate 300 is not limited to a parallelogram, and may also be a rectangle or other suitable shape.
Fig. 9A is a schematic top view illustrating the method for fabricating a shallow trench isolation structure in step S3; FIG. 9B is a schematic cross-sectional view taken along line XX' in FIG. 9A; fig. 9C is a schematic cross-sectional view taken along the line YY' in fig. 9A. Referring to fig. 9A to 9C, in step S3, a liner oxide layer (not shown) with a thickness of 5nm to 35nm is formed on the sidewalls and the bottom surfaces of the second trenches 300a and 300b and the wide trench 300C by a thermal oxidation process or an atomic layer deposition process, so as to improve the adhesion and isolation performance of the dielectric material layer 305 to be filled subsequently; then, a dielectric material layer 305 may be filled into the second trenches 300a, 300b and the wide trench 300c through a high density plasma deposition (HDP CVD) process, preferably, the dielectric material layer 305 has a dielectric constant K value smaller than 3, such as silicon oxide, silicon oxynitride, etc., in order to achieve an isolation structure with higher isolation performance, prevent leakage and alleviate an electrical coupling effect, the dielectric material layer 305 is deposited to a thickness sufficient to fill the second trenches 300a, 300b and the wide trench 300c and to be higher than the hard mask layer 301 by a certain thickness; then, the dielectric material layer 305 is subjected to densification processing, for example, nitrogen ion and carbon ion plasma implantation is performed, and rapid annealing with an annealing time of less than 60s or high-temperature annealing with an annealing temperature of more than 500 ℃ (e.g., 900 ℃, 1050 ℃, etc.) is performed, so as to eliminate the filling defects in the dielectric material layer 305, make the dielectric material layer more dense, and inhibit ions in the active region from diffusing and migrating into the finally formed shallow trench isolation structure, thereby reducing the leakage current generated between the active region and the shallow trench isolation structure, and realizing the isolation structure with higher isolation performance. A Chemical Mechanical Polishing (CMP) process is then used to planarize the top surface of the dielectric material layer 305 to the surface of the hard mask layer 301 to provide a planar platform for subsequent processing. In other embodiments of the present invention, the dielectric material layer 305 may be densified only by a high temperature annealing process.
Fig. 10A is a schematic top view illustrating the method for fabricating a shallow trench isolation structure in step S4; FIG. 10B is a schematic cross-sectional view taken along line XX' of FIG. 10A; fig. 10C is a schematic sectional view along the YY' line of fig. 10A. Referring to fig. 10A to 10C, in step S4, the hard mask layer 301 may be removed by etching using a wet etching process or a dry etching process, in which an etchant with a relatively smaller etching selectivity for the hard mask layer 301 and the dielectric material layer 305 may be selected to etch and remove the hard mask layer 301, so that during the etching and removing the hard mask layer 301, the dielectric material layer 305 may also be thinned to reduce the thickness (or height) of the dielectric material layer 305 above the top surface of the semiconductor substrate 300, and thus, after the hard mask layer 301 is removed, the portions of the dielectric material layer 305 corresponding to the first trench (i.e., the first trench 301a, the second trench 301C, and the wide trench 301d) of the hard mask layer 301 protrude from the surface of the semiconductor substrate 300, and a protruding sidewall 305a is formed. The height of the protruding sidewalls 305a (i.e., the height of the remaining dielectric material layer 305 above the top surface of the semiconductor substrate 300 on both sides) may be 10nm to 100nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, or 80 nm. In this step, when the hard mask layer is removed, the dielectric material layer is etched to a certain degree, so that the height of the step of the dielectric material layer protruding out of the surface of the substrate can be reduced, the surface of the step is relatively smooth, and the step coverage performance of the subsequent insulating dielectric layer 306 is improved.
Fig. 11A and 12A are schematic top-view structural diagrams of the method for fabricating a shallow trench isolation structure in the present embodiment during the step S4; FIG. 11B is a schematic cross-sectional view taken along line XX' in FIG. 11A; FIG. 12B is a schematic cross-sectional view taken along line XX' in FIG. 12A; FIG. 11C is a schematic cross-sectional view taken along line YY' in FIG. 11A; fig. 12C is a schematic cross-sectional view taken along the line YY' in fig. 12A. Referring to fig. 11A to 11C and fig. 12A to 12C, in step S5, an insulating sidewall spacer 306a is formed on the protruding sidewall 305a of the dielectric material layer 305 above the semiconductor substrate 300, which includes the following steps:
first, referring to fig. 11A to 11C, an insulating dielectric layer 306 may be formed on the semiconductor substrate 300 and the dielectric material layer 305 by using a thermal oxidation process, an atomic layer deposition process or a chemical vapor deposition process, preferably, the atomic layer deposition process is used, the atomic layer deposition process may precisely control the thickness of the deposited insulating dielectric layer 306, and further may control the line width (e.g., D in fig. 6) of the subsequently formed insulating sidewall spacer 306a to be maintained in a specific range, for example, 5nm to 35nm, and under the condition of avoiding the edge trench problem, the effective area of the active region that can be used for manufacturing the memory cell may be ensured as much as possible, so as to avoid affecting the formation of the electrical elements such as the memory cell, and to maximize the storage density. The material of the insulating dielectric layer 306 may be at least one of aluminum oxide, titanium nitride, silicon oxynitride, or silicon oxide.
Referring to fig. 12A to 12C, a plasma dry etching process may be used to etch and remove the top surface of the dielectric material layer 305 and the excess insulating dielectric layer 306 on the semiconductor substrate 300, to leave a certain thickness of the insulating dielectric layer 306 on the protruding sidewalls 305a of the dielectric material layer 305 to form insulating sidewalls 306a, each shallow trench isolation structure 307 of the present embodiment is thus formed, the shallow trench isolation structure 307 includes a liner oxide layer covering the sidewalls and bottom surface of the second trench (300A, 300b in fig. 8A and 10A), a dielectric material layer 305 filled in the second trench (300A, 300b in fig. 8A and 10A) and having a top higher than the upper surface of the semiconductor substrate 300, and insulating sidewalls 306a covering the protruding sidewalls 305a of the dielectric material layer 305 on the upper portion of the semiconductor substrate 300. In addition, since the bottom of the insulating sidewall 306a is actually located on the surface of the active region 300D, the line width thereof needs to be controlled as much as possible to avoid occupying too much active region area, so as to increase the device density and the integration level as much as possible while ensuring the elimination of the side trench, and preferably, the line width (or thickness, as shown by D in fig. 13) of the insulating sidewall 306a is 5nm to 35nm, for example, 10nm, 15nm, 20nm, 25nm, and the like.
In view of the above, the method for manufacturing the shallow trench isolation structure according to the present invention forms the insulating sidewall 306a on the protruding sidewall of the portion of the dielectric material layer 305 filled in the corresponding trench of the semiconductor substrate above the semiconductor substrate 300, and eliminates the problem of the side trench at the top boundary of the trench by using the insulating sidewall 306a, thereby improving the isolation performance of the shallow trench isolation structure 307 and avoiding electrical leakage.
Referring to fig. 12A to 12C and fig. 13, the present invention further provides a shallow trench isolation structure, which is preferably prepared by the method for preparing a shallow trench isolation structure provided by the present invention, but is not limited thereto, and the shallow trench isolation structure 307 includes: a dielectric material layer 306 filled in the trench of the semiconductor substrate 300, and a top surface of the dielectric material layer 305 is higher than a top surface of the semiconductor substrate 300 to form a convex sidewall 305 a; and insulating side walls 306a covering the protruding side walls 305a of the dielectric material layer 306. That is, the shallow trench isolation structure 307 provided by the present invention has two parts: the portion buried in the semiconductor substrate 300 (or the portion below the top surface of the semiconductor substrate 300, referred to as a first portion) and the portion exposed above the top surface of the semiconductor substrate 300 (or the portion above the top surface of the semiconductor substrate 300, referred to as a second portion) comprise a layer 305 of dielectric material and insulating side walls 306a covering the protruding sidewalls of the layer 305 of dielectric material. It should be noted that the bottom of the insulating sidewall 306a is actually located above the active region 300d, and occupies a certain width of the active region 300 d. The height of the shallow trench isolation structure 307 from top to bottom is 300nm to 600nm, so as to control the isolation between the electronic devices such as transistors formed in the active region 300d around the shallow trench isolation structure 307. In addition, the K value of the dielectric material layer 305 of the shallow trench isolation structure 307 is less than 3, so as to isolate the electronic devices such as transistors formed in the active region 300d around the shallow trench isolation structure 307, prevent the leakage of electricity, and reduce the electrical coupling effect.
In this embodiment, a core region II and a peripheral region I are defined on the semiconductor substrate 300), the core region II and the peripheral region I are isolated from each other by a shallow trench isolation structure 307, a plurality of shallow trench isolation structures 307 are further formed in the core region II of the semiconductor substrate 300 to define a plurality of active regions 300d arranged in an array in the core region II, so as to be suitable for manufacturing a memory, and each active region 300d may extend along a first direction (i.e., a YY 'line extending direction in fig. 12A), that is, the shallow trench isolation structure 307 between two active regions 300d arranged in parallel perpendicular to the first direction extends along the first direction (i.e., a YY' line extending direction in fig. 12A). The angle between the first direction (i.e., the direction in which the YY' line extends in fig. 12A) and the horizontal direction from left to right in fig. 12A is 5 ° to 85 °.
In addition, the material of the semiconductor substrate 300 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The material of the dielectric material layer 305 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like, for example. The material of the insulating sidewall spacers 306a includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and the like. The cross-sectional shape of the trench for the dielectric material layer 305 in the semiconductor substrate 300 may be a rectangle, a U-shape or an inverted trapezoid, and the obtuse angle range formed by the sidewall of the inverted trapezoid trench and the horizontal direction includes 160 ° to 179.9 °, and preferably 165 ° to 175 °, so as to reduce the filling difficulty of the dielectric material layer 305.
As described above, in the shallow trench isolation structure of the present invention, since the insulating sidewall 306a is formed on the protruding sidewall 305a of the dielectric material layer 305 located above the semiconductor substrate, the edge-trenching phenomenon at the boundary of the top of the trench can be eliminated by the insulating sidewall 306a, thereby improving the isolation performance of the shallow trench isolation junction structure and avoiding electrical leakage.
Referring to fig. 2, fig. 3A to fig. 12C and fig. 13, the present invention further provides a method for manufacturing a semiconductor device, which includes: the shallow trench isolation structure 307 is prepared by the preparation method of the shallow trench isolation structure. When the semiconductor device to be manufactured is a memory, a plurality of shallow trench isolation structures 307 are manufactured on the semiconductor substrate 300, wherein a certain shallow trench isolation structure 307 may divide the semiconductor substrate 300 into a core region II and a peripheral region I, and all the shallow trench isolation structures 3071 in the core region II may divide the semiconductor substrate 300 in the core region II into a plurality of active regions 300d arranged in an array. The shallow trench isolation structure 3071 in the peripheral area I and the shallow trench isolation structure 3072 in the core area II can be simultaneously prepared by the preparation method of the shallow trench isolation structure of the invention, and the density of elements in the peripheral area I is relatively small, the line width W1 of the shallow trench isolation structure 3071 is relatively large, the density of elements in the core area II is relatively large, and the line width W2 of the shallow trench isolation structure 3072 is relatively small, so that when the semiconductor substrate 300 in the peripheral area I and the semiconductor substrate 300 in the core area II are simultaneously etched to form the second trenches required by the shallow trench isolation structures 3071 and 3072, the second trench in the peripheral area I is relatively deep, namely the depth H1 of the shallow trench isolation structure 3071 in the peripheral area I buried in the semiconductor substrate 300 is greater than the depth H2 of the shallow trench isolation structure 3072 in the core area II buried in the semiconductor substrate 300. Wherein H1 and H2 are respectively between 300nm and 600nm to control the isolation between the electronic elements such as transistors formed in the surrounding active region 300 d.
In addition, it should be noted that the size, the pitch and the extending direction of the sti structures 3071 in the peripheral region I and 3072 in the core region II determine the extending direction, the size, the shape and the pitch of each active region 300d in the active region array. In this embodiment, the active regions 300d in the array are parallelograms, and the length direction extends along a first direction (i.e., a bit line direction, a direction along which the YY' line in fig. 12A extends), the first direction and the horizontal direction are 5 ° to 85 °, and the active regions 300d are arranged in an inclined manner, so that the channel length and the array density in the active regions can be increased as much as possible in the same area.
When used for manufacturing a memory, the method for manufacturing a semiconductor device of the present invention further comprises: fabricating memory cells on each of the active regions 300d to form a memory array in the core region II; and, forming peripheral circuits (not shown, and may include transistors, capacitors, resistors, and the like) in the peripheral region I, wherein the peripheral circuits are electrically connected to the corresponding memory cells in the memory array.
Referring to fig. 12A to 12C and fig. 13, the present invention further provides a semiconductor device, including: a semiconductor substrate 300 having a trench (300A, 300b), and a shallow trench isolation structure 307 formed in the trench (300A, 300b in fig. 8A and 10A), and a top surface of the shallow trench isolation structure 307 is higher than a top surface of the semiconductor substrate 300.
The semiconductor device of the present invention may be a memory, and accordingly, the semiconductor substrate 300 defines a core region II and a peripheral region I, the core region II and the peripheral region I are isolated from each other by a shallow trench isolation structure 307, that is, the semiconductor substrate 300 defines the core region II and the peripheral region I by a shallow trench isolation structure 307, trenches (for example, one of 300A, 300b, and 300c in fig. 8A and 10A) are respectively formed in the semiconductor substrates 300 of the core region II and the peripheral region I, the shallow trench isolation structures 307 are respectively formed in each trench, the shallow trench isolation structures 3072 arranged in an array may be provided in the core region II, all the shallow trench isolation structures 3072 in the core region II may define a plurality of active regions 300d arranged in an array in the semiconductor substrate 300 of the core region II, for use in the manufacture of memory arrays. The sti structures 3071 in the peripheral region I, which may be used to space adjacent devices, are relatively low in density, the line width W1 of the sti structures 3071 is relatively high, the density of the devices in the core region II is relatively high, and the line width W2 of the sti structure 3072 is relatively low, so that when the semiconductor substrate 300 in the peripheral region I and the semiconductor substrate 300 in the core region II are etched simultaneously to form corresponding trenches 3071, 3072, the opening width W2 of the trench (shown as 300b in fig. 8A and 10A) in the core region II (i.e. the top width of the sti structure 3072) is smaller than the opening width W1 of the trench (shown as 300A in fig. 8A and 10A) in the peripheral region I (i.e. the top width of the sti structure 3071), the trench depth W1 of the core region II (i.e. the depth of the sti structure 72 buried in the semiconductor substrate 300, or the height of the portion of the shallow trench isolation structure 3072 below the top surface of the semiconductor substrate 300) H2 is less than the trench depth (i.e., the depth of the shallow trench isolation structure 3071 buried in the semiconductor substrate 300, or the height of the portion of the shallow trench isolation structure 3071 below the top surface of the semiconductor substrate 300) H1 of the peripheral region I. Wherein H1 and H2 are respectively between 300nm and 600nm to control the isolation between the electronic elements such as transistors formed in the surrounding active region 300 d. Therefore, the critical dimensions of the shallow trench isolation 307 in the core region II and the peripheral region I may be different, so as to be suitable for manufacturing semiconductor device products such as integrated circuit memories.
In addition, all the shallow trench isolation structures 3072 in the core region II define a plurality of active regions 300d arranged in an array in the semiconductor substrate 300 of the core region II, and the memory further includes: memory cells formed in each of the active regions 300d and peripheral circuitry formed in the peripheral region I, all of the memory cells forming a memory array in the core region II, the peripheral circuitry being electrically connected to corresponding ones of the memory cells in the memory array.
It should be noted that the sti structures 3071 in the peripheral region I and the sti structures 3072 in the core region II are fabricated at the same time, and the dimensions, the pitch, and the extending direction of the sti structures 3071 in the peripheral region I and the sti structures 3072 in the core region II determine the extending direction, the dimensions, the shape, and the pitch of each active region 300d in the active region array, and further determine the size, the word line direction, and the bit line direction of the memory cell in the memory array. In this embodiment, the active region 300d in the memory array is a parallelogram, and the length direction extends along an inclined first direction (i.e., a bit line direction, an extending direction of the YY' line in fig. 12A), an included angle between the first direction and a horizontal direction from left to right in fig. 12A is 5 ° to 85 °, and the active region 300d is disposed in an inclined manner, so that the channel length and the memory array density in the active region can be increased as much as possible in the same area. In other embodiments of the present invention, the first direction may be a direction perpendicular to the extending direction of the XX 'line in fig. 12A, and the active region 300d is defined by the shallow trench isolation structure 307 along the extending direction of the XX' line and the shallow trench isolation structure extending along the first direction to have a rectangular shape.
In view of the above, the semiconductor device of the present invention, due to the shallow trench isolation structure of the present invention, can reduce the side-ditch phenomenon of the shallow trench isolation structure, avoid the problems of element leakage and the like, and improve the reliability of the device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (18)
1. A preparation method of a shallow trench isolation structure is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate, wherein a first groove is formed in the hard mask layer;
etching the semiconductor substrate by taking the hard mask layer as a mask to form a second groove corresponding to the first groove in the semiconductor substrate;
filling a dielectric material layer in the second trench and the first trench, wherein the dielectric material layer fills the first trench and the second trench;
removing the hard mask layer, wherein the part, corresponding to the first groove, in the dielectric material layer protrudes relative to the surface of the semiconductor substrate to form a protruding side wall; and the number of the first and second groups,
and forming an insulating side wall on the protruding side wall of the dielectric material layer.
2. The method of claim 1, wherein the second trench has a depth of 300nm to 600nm in the semiconductor substrate.
3. The method of claim 1, wherein the step of filling the dielectric material layer in the second trench comprises:
depositing the dielectric material layer on the hard mask layer, wherein the second groove is filled with the dielectric material layer;
densifying the dielectric material layer; and the number of the first and second groups,
planarizing a top surface of the dielectric material layer to a top surface of the hard mask layer.
4. The method of claim 1, wherein the hard mask layer is removed by a dry etching process, and the dielectric material layer is etched by the dry etching process to reduce the height of the protruding sidewall of the dielectric material layer.
5. The method for preparing the shallow trench isolation structure of claim 1, wherein the step of forming the insulating spacers comprises:
forming an insulating dielectric layer on the semiconductor substrate and the dielectric material layer by adopting an atomic layer deposition method, a chemical vapor deposition method or a thermal oxidation method, wherein the insulating dielectric layer covers the top surface of the dielectric material layer and the protruding side wall; and the number of the first and second groups,
and etching to remove the part of the insulating medium layer covering the top surface of the dielectric material layer and the semiconductor substrate, and reserving the part of the insulating medium layer covering the protruding side wall of the dielectric material layer to form the insulating side wall.
6. The method of claim 1, wherein the insulating spacer has a thickness of 5nm to 35 nm.
7. The method of fabricating the shallow trench isolation structure of any of claims 1 to 6, wherein the step of forming the hard mask layer having the first trench comprises:
forming a first patterning layer on the hard mask layer;
etching the hard mask layer to the surface of the semiconductor substrate by taking the first patterning layer as a mask so as to transfer the first patterning layer into the hard mask layer;
removing the first patterning layer, and sequentially forming a covering layer and a second patterning layer on the hard mask layer and the semiconductor substrate, wherein the covering layer fills pattern gaps in the hard mask layer, and the second patterning layer has a different pattern from the first patterning layer;
etching the covering layer by taking the second patterning layer as a mask, and stopping etching on the surface of the hard mask layer so as to transfer the pattern in the second patterning layer into the covering layer;
removing the second patterning layer, and etching a hard mask layer to the surface of the semiconductor substrate by taking the covering layer as a mask so as to transfer the pattern in the covering layer to the hard mask layer, thereby forming the first groove in the hard mask layer; and the number of the first and second groups,
and removing the covering layer.
8. The method of claim 7, wherein the first patterned layer has a plurality of lines extending along the first direction, and after the pattern of the first patterned layer is transferred to the hard mask layer, the hard mask layer has a plurality of initial lines extending along the first direction, and a first trench is defined between two adjacent initial lines to serve as the pattern gap.
9. The method of claim 8, wherein the second patterned layer has a pattern aligned with the initial line of the hard mask layer and exposing a portion of the initial line, and the hard mask layer forms a second trench after transferring the pattern in the capping layer into the hard mask layer, the second trench severing the initial line into a stub, the second trench communicating with the first trench on either side of the initial line, the first trench and the second trench forming the first trench.
10. A shallow trench isolation structure, comprising:
the dielectric material layer is filled in the groove of the semiconductor substrate, and the top surface of the dielectric material layer is higher than the top surface of the semiconductor substrate to form a convex side wall; and the number of the first and second groups,
and the insulating side wall is formed on the protruding side wall of the dielectric material layer.
11. The shallow trench isolation structure of claim 10 wherein the thickness of the insulating sidewall spacers is between 5nm and 35 nm.
12. The shallow trench isolation structure of claim 10 wherein the depth of the trench in the semiconductor substrate is in the range of 300nm to 600 nm.
13. The shallow trench isolation structure of claim 10 wherein the trench extends in a sloped first direction having an angle of 5 ° to 85 ° with respect to a horizontal direction from left to right.
14. A method of manufacturing a semiconductor device, comprising: the shallow trench isolation structure is prepared by the method for preparing the shallow trench isolation structure as claimed in any one of claims 1 to 9.
15. The method of claim 14, wherein a core region and a peripheral region are defined on the semiconductor substrate, the core region and the peripheral region are isolated from each other by the shallow trench isolation structures, and a plurality of shallow trench isolation structures are further formed in the core region of the semiconductor substrate to define a plurality of active regions arranged in an array in the core region;
the preparation method of the semiconductor device further comprises the following steps: manufacturing memory cells on each active region to form a memory array in the core region; and manufacturing a peripheral circuit in the peripheral area, wherein the peripheral circuit is electrically connected with the corresponding memory unit in the memory array.
16. A semiconductor device, comprising:
a semiconductor substrate having a trench; and the number of the first and second groups,
the shallow trench isolation structure of any of claims 10 through 13 formed in the trench with a top surface higher than a top surface of the semiconductor substrate.
17. The semiconductor device as claimed in claim 16, wherein the semiconductor device is a memory, the semiconductor substrate defines a core region and a peripheral region, the core region and the peripheral region are isolated from each other by a shallow trench isolation structure, the core region of the semiconductor substrate further has a plurality of shallow trench isolation structures therein, the peripheral region of the semiconductor substrate further has the shallow trench isolation structures therein, a top width of the shallow trench isolation structures in the core region is smaller than a top width of the shallow trench isolation structures in the peripheral region, and a trench depth corresponding to the shallow trench isolation structures in the core region is smaller than a trench depth corresponding to the shallow trench isolation structures in the peripheral region.
18. The semiconductor device of claim 17, wherein all of the shallow trench isolation structures in the core region define a plurality of active regions in the semiconductor substrate of the core region arranged in an array, the semiconductor device further comprising: memory cells formed on each of the active regions, all of the memory cells forming a memory array in the core region; and peripheral circuitry formed in the peripheral region, the peripheral circuitry being electrically connected to respective ones of the memory cells in the memory array.
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Cited By (5)
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| WO2022028028A1 (en) * | 2020-08-05 | 2022-02-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN114121776A (en) * | 2022-01-26 | 2022-03-01 | 晶芯成(北京)科技有限公司 | Manufacturing method of semiconductor isolation structure |
| CN115497869A (en) * | 2022-11-17 | 2022-12-20 | 合肥新晶集成电路有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| WO2023284010A1 (en) * | 2021-07-13 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method, semiconductor structure, and memory |
| CN117438372A (en) * | 2023-12-21 | 2024-01-23 | 粤芯半导体技术股份有限公司 | Pressure-resistant deep trench isolation method and device, electronic equipment and storage medium |
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