CN105633000A - Shallow trench isolation structure, method of forming same, semiconductor device and method of forming same - Google Patents
Shallow trench isolation structure, method of forming same, semiconductor device and method of forming same Download PDFInfo
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- CN105633000A CN105633000A CN201410617677.XA CN201410617677A CN105633000A CN 105633000 A CN105633000 A CN 105633000A CN 201410617677 A CN201410617677 A CN 201410617677A CN 105633000 A CN105633000 A CN 105633000A
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Abstract
Disclosed are a shallow trench isolation structure, a method of forming the same, a semiconductor device and a method of forming the same. The method of forming the semiconductor comprises the steps of providing a semiconductor substrate; forming, in the semiconductor substrate, trenches and shallow trench isolation structures located in the trenches, each shallow trench isolation structure including a filling portion filled in the corresponding trench and a covering portion being located on the filling portion and covering the partial semiconductor substrate outside the corresponding trench; forming a gate structure on the semiconductor substrate outside the shallow trench isolation structures; etching the semiconductor substrate at two sides of the gate structure to form grooves; and forming a germanium-silicon layer epitaxially in each groove. The semiconductor device formed in the invention has no problem of low or a lack of germanium-silicon material growth capacity, and is excellent in performance.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of fleet plough groove isolation structure and forming method thereof and a kind of semiconductor device and forming method thereof.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, generally includes the reduction of MOSFET element channel length, gate oxide thickness thinning etc., to obtain device speed faster. But it is as very large scale integration technology when being developed to sub-micro level, particularly 90 nanometers and during techniques below node, channel length reduction can bring series of problems, in order to control short-channel effect, can be adulterated the impurity of higher concentration in channels, this can reduce the mobility of carrier, thus causing that device performance declines, simple device size reduction is difficult to meet the development of large scale integrated circuit technology. Therefore, stress engineering is widely studied the mobility for improving carrier, thus obtaining device speed faster, and meets the rule of Moore's Law.
Embedded germanium silicon source and drain technology (EmbeddingSiGe) technology is important in 45 nanometers and techniques below node and core Technology. Fig. 1 illustrates that prior art forms the schematic diagram of the intermediate structure of embedded germanium silicon source and drain, with reference to Fig. 1, there is in Semiconductor substrate 10 fleet plough groove isolation structure 20, Semiconductor substrate 10 is sequentially formed with gate dielectric layer 31, gate electrode layer 32 and hard mask layer 33, the sidewall of gate dielectric layer 31, gate electrode layer 32 and hard mask layer 33 is also formed with side wall 34. In the embedded germanium silicon source and drain technology of prior art, Semiconductor substrate 10 outside etching side wall 34 forms groove 40, optionally epitaxial growth Ge silicon layer (not shown) in groove 40 again, because germanium silicon crystal lattice constant is not mated with silicon, on the direction of vertical-channel, silicon crystal lattice is stretched generation tensile stress, it is subject to compression along channel direction silicon crystal lattice and produces compressive stress, it is possible to improve the current driving ability of PMOS transistor.
But, the performance of the transistor with embedded germanium silicon source and drain that prior art is formed is not good.
Summary of the invention
The problem that this invention address that is, the performance with embedded germanium silicon source and drain device that prior art is formed is not good.
For solving the problems referred to above, the present invention proposes the method for the formation of a kind of fleet plough groove isolation structure, the forming method of described fleet plough groove isolation structure includes: providing Semiconductor substrate, form patterned mask layer at described semiconductor substrate surface, described mask layer has the first opening; Etch described Semiconductor substrate along described first opening, in described Semiconductor substrate, form groove; Being etched back to described mask layer, increase described first opening, form the second opening, described second opening is more than the opening of described groove; Full oxide is filled in the second opening of described groove and described mask layer; Described oxide is carried out planarization process.
Alternatively, described second opening is more than described first opening
Alternatively, the material of described mask layer is silicon nitride, is etched back to described mask layer and adopts phosphoric acid solution, and wherein, the percent by volume of phosphoric acid is 85%��88%, and solution temperature is 155 DEG C��165 DEG C.
Alternatively, it is also formed with pad oxide between described semiconductor substrate surface and described mask layer.
Alternatively, the forming method of described fleet plough groove isolation structure also includes, and after described oxide is carried out planarization process, removes described mask layer.
Accordingly, present invention also offers a kind of fleet plough groove isolation structure, described fleet plough groove isolation structure is formed in Semiconductor substrate, in described Semiconductor substrate, there is groove, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove.
Alternatively, the covering part of described fleet plough groove isolation structure covers the width of the Semiconductor substrate outside described groove and is
Alternatively, described fleet plough groove isolation structure also includes the pad oxide that is positioned at described semiconductor substrate surface.
The embodiment of the present invention additionally provides the forming method of a kind of semiconductor device, and the forming method of described semiconductor device includes: provide Semiconductor substrate; In described Semiconductor substrate, form groove and be positioned at the fleet plough groove isolation structure of described groove, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills full described groove, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove; Semiconductor substrate outside described fleet plough groove isolation structure is formed grid structure; Etch the Semiconductor substrate of described grid structure both sides, form groove; Germanium silicon layer it is epitaxially formed in described groove.
Alternatively, in described Semiconductor substrate, form groove and the fleet plough groove isolation structure being positioned at described groove includes: forming patterned mask layer at described semiconductor substrate surface, described mask layer has the first opening; Etch described Semiconductor substrate along described first opening, in described Semiconductor substrate, form groove; Being etched back to described mask layer, increase described first opening, form the second opening, described second opening is more than the opening of described groove; In the second opening of described groove and described mask layer, fill full oxide, and described oxide is carried out planarization process, form fleet plough groove isolation structure; Remove described mask layer.
Alternatively, described second opening is more than described first opening
Alternatively, the material of described mask layer is silicon nitride, is etched back to described mask layer and adopts phosphoric acid solution, and wherein, the percent by volume of phosphoric acid is 85%��88%, and solution temperature is 155 DEG C��165 DEG C.
Alternatively, it is also formed with pad oxide between described semiconductor substrate surface and described mask layer.
Alternatively, before the Semiconductor substrate etching described grid structure both sides forms groove, also include: form the protective layer covering described semiconductor substrate surface and described grid structure; Form the side wall covering described gate structure sidewall.
Accordingly, present invention also offers a kind of semiconductor device, described semiconductor device includes: Semiconductor substrate, has groove in described Semiconductor substrate; Fleet plough groove isolation structure, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove; It is positioned at the grid structure in the Semiconductor substrate outside described fleet plough groove isolation structure; It is positioned at the groove of the Semiconductor substrate of described grid structure both sides; It is positioned at the germanium silicon layer of described groove.
Alternatively, the covering part of described fleet plough groove isolation structure covers the width of the Semiconductor substrate outside described groove and is
Alternatively, described semiconductor device also includes: cover described semiconductor substrate surface and the protective layer of described grid structure; Cover the side wall of described gate structure sidewall.
Compared with prior art, technical scheme has the advantage that
The forming method of the fleet plough groove isolation structure of the embodiment of the present invention forms patterned mask layer at semiconductor substrate surface, and described mask layer has the first opening, etches described Semiconductor substrate along described first opening, forms groove in described Semiconductor substrate, then, it is etched back to described mask layer, increases described first opening, form the second opening so that described second opening is more than the opening of described groove, in the second opening of described groove and described mask layer, fill full oxide again, and described oxide is carried out planarization process. the fleet plough groove isolation structure that said method is formed is adopted to have filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove. it is used for above-mentioned fleet plough groove isolation structure forming the semiconductor device with embedded germanium silicon source and drain, when Semiconductor substrate in etching grid structure both sides forms groove, owing to the covering part of described fleet plough groove isolation structure covers part semiconductor substrate, the Semiconductor substrate of shallow trench interrupter sidewall had protective effect, decrease the loss in etching process of the backing material of fleet plough groove isolation structure sidewall, remaining backing material is more, " seed " needed for can providing for follow-up germanium and silicon epitaxial, enhance germanium and silicon epitaxial energy for growth, improve the performance of formed semiconductor device.
Accordingly, the fleet plough groove isolation structure of the embodiment of the present invention and semiconductor device structure also have above-mentioned advantage.
Accompanying drawing explanation
Fig. 1 is the intermediate structure schematic diagram that prior art forms embedded germanium silicon source and drain;
Fig. 2 to Fig. 9 is the intermediate structure schematic diagram in the forming process of the PMOS transistor of the embodiment of the present invention.
Detailed description of the invention
By background technology it can be seen that the performance with embedded germanium silicon source and drain device that formed of prior art is not good.
The present inventor have studied the forming method of the embedded germanium silicon source and drain of prior art and finds, with reference to Fig. 1, prior art is selective epitaxial growth germanium silicon layer in described groove 40, silicon in Semiconductor substrate 10 is " seed " in germanium and silicon epitaxial growth course, and germanium silicon grows along the lattice of silicon. but in prior art, electric isolation is realized by fleet plough groove isolation structure 20 between semiconductor device, fleet plough groove isolation structure 20 uses silicon dioxide to be filled with, in the process carrying out wall embeded silicon etching process (SiRecessEtch) and being formed groove 40, the silicon at fleet plough groove isolation structure 20 edge can be etched away, silicon " seed " required for germanium and silicon epitaxial can not be provided, therefore, at fleet plough groove isolation structure 20 and active-surface, germanium and silicon epitaxial can be subject to the impact of fleet plough groove isolation structure 20, low even can lack in the growth of fleet plough groove isolation structure 20 marginal existence germanium silicon material. result in the embedded germanium silicon source and drain existing defects that prior art is formed, it is impossible to the channel region at transistor introduces enough stress, and transistor performance is not good.
Based on above research, the present inventor proposes the forming method of a kind of fleet plough groove isolation structure, patterned mask layer is formed at semiconductor substrate surface, described mask layer has the first opening, etch described Semiconductor substrate along described first opening, in described Semiconductor substrate, form groove, then, it is etched back to described mask layer, increases described first opening, form the second opening so that described second opening is more than the opening of described groove, in the second opening of described groove and described mask layer, fill full oxide again, and described oxide is carried out planarization process. the fleet plough groove isolation structure that said method is formed is adopted to have filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove. it is used for above-mentioned fleet plough groove isolation structure forming the semiconductor device with embedded germanium silicon source and drain, when Semiconductor substrate in etching grid structure both sides forms groove, owing to the covering part of described fleet plough groove isolation structure covers part semiconductor substrate, the Semiconductor substrate of shallow trench interrupter sidewall had protective effect, decrease the loss of the backing material of fleet plough groove isolation structure sidewall, remaining backing material is more, " seed " needed for can providing for follow-up germanium and silicon epitaxial, enhance germanium and silicon epitaxial energy for growth, improve the performance of formed semiconductor device.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
It should be noted that provide the purpose of these accompanying drawings to contribute to understand embodiments of the invention, and should not be construed as the restriction improperly to the present invention. For the purpose of becoming apparent from, shown in figure, size is not necessarily to scale, it is possible to can make amplify, reduce or other change.
Below for the forming method of PMOS transistor, the forming method of the fleet plough groove isolation structure of the present invention and the forming method of semiconductor device are described.
First, with reference to Fig. 2, it is provided that Semiconductor substrate 100, forming patterned mask layer 120 on described Semiconductor substrate 100 surface, described mask layer has the first opening 121.
Described Semiconductor substrate 100 is the work platforms of subsequent technique. In the present embodiment, described Semiconductor substrate 100 is monocrystalline substrate. In other embodiments, described Semiconductor substrate 100 can also be silicon-on-insulator (SOI) or other semi-conducting materials.
In certain embodiments, before described Semiconductor substrate 100 surface forms patterned mask layer 120, it has been initially formed pad oxide (not shown). The material of described pad oxide is silicon oxide, it is possible to by the oxidation technology of described Semiconductor substrate 100 is obtained. Described pad oxide can protect Semiconductor substrate 100 surface from damage and to pollute, it is also possible to reduces the stress that between mask layer 120 and Semiconductor substrate 100, directly contact produces.
The material of described patterned mask layer 120 can be silicon nitride, silicon oxynitride or fire sand. In the present embodiment, the material of described mask layer 120 is silicon nitride. Specifically, first, chemical gaseous phase depositing process is adopted to form silicon nitride layer on described Semiconductor substrate 100 surface; Then, described silicon nitride layer is coated with photoresist, after exposed and developed, form the photoresist layer of image conversion; Again with described patterned photoresist layer for silicon nitride layer described in mask etching, until exposing Semiconductor substrate 100 surface, form patterned silicon nitride mask layer 120. Having the first opening 121 on described patterned mask layer 120, the first opening 121 has defined the region of fleet plough groove isolation structure to be formed in Semiconductor substrate 100, and the region covered by mask layer 120 is subsequently formed active area.
In other embodiments, described mask layer 120 can also be photoetching offset plate figure.
Then, with reference to Fig. 2 and Fig. 3, etch described Semiconductor substrate 100 along described first opening 121, in described Semiconductor substrate 100, form groove 130.
In certain embodiments, dry etch process is adopted to etch described Semiconductor substrate 100. Such as, in one embodiment, adopting reactive ion etching process to etch described Semiconductor substrate 100, etching gas is HBr, O2��Cl2And CH2F2Mixing gas.
The silicon nitride layer graphically changed is Semiconductor substrate 100 described in mask etching, compared to photoresist mask, it is possible to reduce the optical effect of Semiconductor substrate 100, optimizes etching effect, it is thus achieved that with design size closer groove 130 size. In the present embodiment, the opening size of the groove 130 obtained after etching described Semiconductor substrate 100 is equivalently-sized or close with described mask layer 120 first opening 121.
Then, with reference to Fig. 3 and Fig. 4, being etched back to described mask layer 120, increase described first opening 121, form the second opening 122, described second opening 122 is more than the opening of described groove 130.
In the present embodiment, the material of described mask layer 120 is silicon nitride, is etched back to silicon nitride (SiNpullback) and adopts phosphoric acid solution. Wherein, the percent by volume of phosphoric acid is 85%��88%, and solution temperature is 155 DEG C��165 DEG C, and etch period is 20 seconds��40 seconds. In other embodiments, the technique being etched back to described mask layer 120 is determined according to the material of described mask layer 120, as long as making the size of described first opening 121 increase.
In the present embodiment, after being etched back to technique, the first opening 121 of described mask layer 120 increases, and defines the second opening 122. Owing to described groove 130 is formed along described first opening 121 etching, the size of described second opening 122 is also greater than the size of described groove 130 opening so that described second opening 122 exposes the surface of the part semiconductor substrate 100 outside described groove 130. In the present embodiment, described second opening 122 is more than described first openingAs shown in Figure 4, the width Delta L on Semiconductor substrate 100 surface outside the groove 130 that the side of described second opening 122 exposes isFor example, it is possible to beOrDeng.
Then, with reference to Fig. 5, in the second opening 122 (with reference to Fig. 4) of described groove 130 and described mask layer 120, fill full oxide (not shown), and described oxide is carried out planarization process, form fleet plough groove isolation structure 140.
In certain embodiments, in described groove 130 before fill oxide, in described groove 130, also define laying (not shown). Such as, Semiconductor substrate 100 surface exposed by aoxidizing described groove 130 forms described laying, and described laying can repair the damage forming the Semiconductor substrate 100 in the process of groove 130, groove 130 exposed in etching.
In the present embodiment, the material of described oxide is silicon oxide. In described groove 130 and described second opening 122, the technique of fill oxide is chemical vapour deposition (CVD). Such as, in one embodiment, adopting sub-aumospheric pressure cvd (SACVD) technique to form described oxide, deposition source material is TEOS and O3. After depositing operation, the oxide formed fills the second opening 122 of full described groove 130 and described mask layer 120, and covers the surface of described mask layer 120. Then, use CMP process that described oxide is carried out planarization process. In CMP process, with described mask layer 120 for stop layer, remove the undesired oxide on described mask layer 120, form fleet plough groove isolation structure 140. In certain embodiments, after planarization processes, the top surface of described fleet plough groove isolation structure 140 flushes with the top surface of described mask layer 120; In other are implemented, owing to the material oxidation silicon of described fleet plough groove isolation structure 140 is softer than the material silicon nitride of mask layer 120, after planarization processes, the top surface of described fleet plough groove isolation structure 140 is lower than the top surface of described mask layer 120.
Compared with prior art, in the present embodiment, in described groove 130 before fill oxide, described mask layer 120 is etched back to, the first opening 121 making mask layer 120 increases and forms the second opening 122, and described second opening 122 is also greater than the opening of described groove 130; Then, in described groove 130 during fill oxide, oxide also fills completely described second opening 122; After having carried out planarization process, the fleet plough groove isolation structure formed has filling part 140a and covers part 140b, described filling part 140a fills the groove 130 in full described Semiconductor substrate 100, and described covering part 140b is positioned on described filling part 140a and covers the part semiconductor substrate 100 outside described groove 130. Therefore, follow-up to described fleet plough groove isolation structure 140 outside Semiconductor substrate 100 perform etching time, described covering part 140b can protect the Semiconductor substrate 100 of filling part 140a sidewall to be not etched removal.
Then, with reference to Fig. 6, remove described mask layer 120, the Semiconductor substrate 100 outside described fleet plough groove isolation structure 140 is formed grid structure 150.
The technique removing described mask layer 120 can be determined according to the material of mask layer 120. In the present embodiment, described mask layer 120 is silicon nitride, it is possible to adopt hot phosphoric acid solution to remove.
In the present embodiment, described grid structure 150 includes the gate dielectric layer 151 of surfaces of active regions, gate electrode layer 152 and the hard mask layer 153 that are sequentially formed in outside fleet plough groove isolation structure 140. In the present embodiment, described gate dielectric layer 151 is silicon oxide, and gate electrode layer 152 is polysilicon, and hard mask layer 153 is silicon nitride. The technique forming described grid structure 150 includes: form silicon oxide layer on described Semiconductor substrate 100 surface; Described silicon oxide layer is formed polysilicon layer; Patterned silicon nitride hard mask layer is formed again on described polysilicon layer; Grid structure 150 is formed for polysilicon layer described in mask etching and silicon oxide layer with silicon nitride hard mask layer.
In certain embodiments, described gate dielectric layer 151 is high-k (high K) material, and gate electrode layer 152 is metal material, constitute high-K metal gate (HKMG) structure, be conducive to improving the breakdown voltage of MOS transistor, reduce leakage current, improve transistor performance. In certain embodiments, described gate electrode layer 152 is pseudo-grid, after being subsequently formed source and drain areas, it is necessary to removes pseudo-grid, forms metal gates. The concrete structure of the grid structure 150 in described Semiconductor substrate 100 is not made restriction by the present invention, and forming method is referred to existing technique, does not repeat them here.
Then, with reference to Fig. 7, form the protective layer 160 covering described Semiconductor substrate 100 surface and described grid structure 150, and form the side wall 170 covering described gate structure sidewall.
In the present embodiment, adopting atomic layer deposition processes to form described protective layer 160, the material of described protective layer 160 is silicon oxide. Described atom layer deposition process forms silica material by the mode successively grown on described Semiconductor substrate 100 surface and described grid structure 150, for protecting the surface of semiconductor device to be formed, reduces the loss of surface silicon. In other embodiments, it is also possible to aoxidized described Semiconductor substrate 100 surface and described grid structure 150 sidewall by oxidation technology, form described protective layer 160.
In the present embodiment, the material of described side wall 170 is silicon nitride. First, form the silicon nitride material covering whole Semiconductor substrate 100 surface and described grid structure 150, then, dry etch process is adopted to carve described silicon nitride material, owing to dry etching has preferably directivity, the silicon nitride material of Semiconductor substrate 100 surface and grid structure 150 top surface is removed, and the silicon nitride material being positioned at described grid structure 150 sidewall is retained, and forms side wall 170. In certain embodiments, the material of described side wall 170 can also be silicon oxynitride or silicon oxide.
In certain embodiments, after forming described protective layer 160 and described side wall 170, also PMOS transistor to be formed has been carried out ion implantation technology, defined leakage light-dope structure.
Then, with reference to Fig. 8, etch the Semiconductor substrate 100 of described grid structure 150 both sides, form groove 180.
In certain embodiments, before forming described groove 180, also defining silicon nitride shielding layer on described Semiconductor substrate 100 surface and described grid structure 150 surface, described silicon nitride shielding layer is for protecting the region and grid structure 150 that not necessarily form embedded germanium silicon source and drain in described Semiconductor substrate 100; Described silicon nitride shielding layer is also used as extension and selects layer, it is to avoid in follow-up germanium and silicon epitaxial technique, germanium silicon material epitaxial growth grid structure 150 surface or other not necessarily form the region of germanium silicon material.
In the present embodiment; first; adopt the protective layer 160 on Semiconductor substrate 100 surface of described grid structure 150 both sides of dry etch process removal; then; with described grid structure 150 and described fleet plough groove isolation structure 140 for mask; continue to etch the Semiconductor substrate 100 of described grid structure 150 both sides, form groove 180.
In certain embodiments, adopting dry etching to form described groove 180, being shaped as of described groove 180 is U-shaped. Such as, adopting reactive ion etching to form described groove 180, etching gas includes SF6��CF4, or CHF3Deng.
In another embodiment, the groove 180 formed after etching is �� type, described �� type groove has the tip of the protrusion pointing to transistor channel region at the middle part of groove, follow-up in described �� type groove formed germanium silicon material time, germanium silicon material fills full whole groove, germanium silicon material at the most advanced and sophisticated place that described groove protrudes is closer to the channel region of PMOS transistor, it is possible to increase the stress introduced at PMOS transistor channel region. In one embodiment, the technique forming described �� type groove is: first carrying out plasma etching, the etching gas of described plasma etching includes HBr, O2��He��Cl2And NF3; Carrying out wet etching after plasma etching, described wet-etching technology adopts TMAH (Tetramethylammonium hydroxide) solution, and the temperature of TMAH solution is 15 DEG C��20 DEG C, and etch period is 50 seconds��500 seconds. The etching technics forming described �� type groove can also with reference to existing technique, for instance the wet etching after above-mentioned plasma etching can also adopt potassium hydroxide solution or ammonia spirit, does not repeat them here.
Compared with prior art, embodiments of the invention are etching the Semiconductor substrate 100 of described grid structure 150 both sides, formed in the process of groove 180, owing to the covering part 140b (with reference to Fig. 5) of described fleet plough groove isolation structure 140 covers part semiconductor substrate 100 surface of active area, the semiconductor substrate materials that the filling part 140a of 140 with described fleet plough groove isolation structure is adjacent had protective effect, there remains more silicon materials between the groove 180 and the described fleet plough groove isolation structure 140 that are formed after etching, " seed " needed for can providing for follow-up germanium and silicon epitaxial growth, enhance germanium and silicon epitaxial energy for growth.
Then, with reference to Fig. 9, in described groove 180 (with reference to Fig. 8), germanium silicon layer 190 is formed.
In certain embodiments, before forming germanium silicon layer in described groove 180, Semiconductor substrate 100 surface also described groove 180 exposed has carried out prerinse, to remove oxygen element and the silicon dangling bonds on substrate 100 surface, prepares clean substrate surface for being subsequently formed germanium silicon layer. It is for instance possible to use Semiconductor substrate 100 surface that described groove 180 is exposed by SC-1 solution, SC-2 solution is carried out, it is also possible to adopt hydrogen to toast substrate 100 surface that described groove 180 exposes.
In described groove 180, form germanium silicon layer 190 adopt selective epitaxial process. Described selective epitaxial process can be ultra-high vacuum CVD (UHVCVD) or molecular beam epitaxy (MEB). Described selective epitaxial process, by regulating extension parameter, utilizes epitaxial material to adsorb more than the absorption at oxide or nitride surface to realize epitaxially grown selectivity at silicon face, forms the germanium silicon material with similar lattice arrangement at silicon face.
Specifically, in the present embodiment, adopting ultra-high vacuum CVD technique to form germanium silicon layer 190 in described groove 180, reacting gas includes SiH2Cl2, HCl and GeH4. In the technical process being epitaxially formed germanium silicon material, owing to described fleet plough groove isolation structure 140 and described grid structure 150 surface are respectively provided with silicon nitride or silicon oxide, germanium silicon material is gone out thus without epitaxial growth, and only at the Semiconductor substrate 100 surface Epitaxial growth germanium silicon material that described groove 180 exposes.
In certain embodiments, described germanium silicon layer 190 fills full described groove 180, and its top surface flushes with the top surface of described fleet plough groove isolation structure 140. In other embodiment, the top surface of described germanium silicon layer 190 can also be higher than the top surface of described fleet plough groove isolation structure 140. Additionally, the shape of described germanium silicon layer 190 is mated with described groove 180, it is possible to for U-shaped or �� type. Owing to germanium silicon material lattice paprmeter is more than silicon, therefore, described germanium silicon layer 190 can introduce compressive stress at the channel region of PMOS transistor, improves the performance of PMOS transistor.
Compared with prior art, the embodiment of the present invention is owing to having enough substrate silicon materials between described groove 180 and described fleet plough groove isolation structure 140, enough silicon " seed " can be provided for germanium and silicon epitaxial, it is absent from prior art and occurs that germanium silicon material grows low or disappearance problem at fleet plough groove isolation structure edge, the embedded germanium silicon source and drain quality formed is high, and the performance boost of pair pmos transistor is notable.
In subsequent technique, also at the laminated construction of described grid structure 150 surface cvd silicon oxide and silicon nitride, side wall after etched, can be formed; Carry out ion implanting in grid structure 150 both sides and form the source-drain area of PMOS transistor; And forming dielectric layer, through hole and conductive plunger etc., concrete technology is referred to existing technique, does not repeat them here.
Accordingly, present invention also offers the fleet plough groove isolation structure adopting said method to be formed and semiconductor device.
With reference to Fig. 5, described fleet plough groove isolation structure 140 is formed in Semiconductor substrate 100, there is in described Semiconductor substrate groove (sign), described fleet plough groove isolation structure 140 includes filling part 140a and covers part 140b, wherein, described filling part 140a fills the groove in full described Semiconductor substrate 100, the part semiconductor substrate 100 that described covering part 140b is positioned on described filling part 140a and covers outside described groove. In certain embodiments, the width of the Semiconductor substrate 100 outside the covering part 140b described groove of covering of described fleet plough groove isolation structure 140 isIn certain embodiments, described Semiconductor substrate 100 surface also has pad oxide (not shown).
With reference to Fig. 9, the semiconductor device of the embodiment of the present invention includes: Semiconductor substrate 100, has groove (sign) in described Semiconductor substrate 100; Fleet plough groove isolation structure 140, described fleet plough groove isolation structure 140 includes filling part 140a and covers part 140b, wherein, described filling part 140a fills the groove in full described Semiconductor substrate 100, the part semiconductor substrate 100 that described covering part 140b is positioned on described filling part 140a and covers outside described groove; It is positioned at the grid structure 150 in the Semiconductor substrate 100 outside described fleet plough groove isolation structure 140; It is positioned at the groove (sign) of the Semiconductor substrate of described grid structure 150 both sides; It is positioned at the germanium silicon layer 190 of described groove. In certain embodiments, the width of the Semiconductor substrate 100 outside the covering part 140b described groove of covering of described fleet plough groove isolation structure 140 isIn certain embodiments, described semiconductor device also includes, and covers the protective layer 160 of described Semiconductor substrate 100 surface and described grid structure 150, and covers the side wall 170 of described grid structure 150 sidewall.
The advantage of fleet plough groove isolation structure of the present invention and semiconductor device is referred to the description of above-mentioned pair pmos transistor forming method, does not repeat them here.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. the forming method of a fleet plough groove isolation structure, it is characterised in that including:
Thering is provided Semiconductor substrate, form patterned mask layer at described semiconductor substrate surface, described mask layer has the first opening;
Etch described Semiconductor substrate along described first opening, in described Semiconductor substrate, form groove;
Being etched back to described mask layer, increase described first opening, form the second opening, described second opening is more than the opening of described groove;
Full oxide is filled in the second opening of described groove and described mask layer;
Described oxide is carried out planarization process.
2. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that described second opening is more than described first opening
3. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that the material of described mask layer is silicon nitride, it is etched back to described mask layer and adopts phosphoric acid solution, wherein, the percent by volume of phosphoric acid is 85%��88%, and solution temperature is 155 DEG C��165 DEG C.
4. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that be also formed with pad oxide between described semiconductor substrate surface and described mask layer.
5. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that also include, after described oxide is carried out planarization process, remove described mask layer.
6. a fleet plough groove isolation structure, described fleet plough groove isolation structure is formed in Semiconductor substrate, it is characterized in that, in described Semiconductor substrate, there is groove, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove.
7. fleet plough groove isolation structure as claimed in claim 6, it is characterised in that the covering part of described fleet plough groove isolation structure covers the width of the Semiconductor substrate outside described groove and is
8. fleet plough groove isolation structure as claimed in claim 6, it is characterised in that also include the pad oxide being positioned at described semiconductor substrate surface.
9. the forming method of a semiconductor device, it is characterised in that including:
Semiconductor substrate is provided;
In described Semiconductor substrate, form groove and be positioned at the fleet plough groove isolation structure of described groove, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills full described groove, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove;
Semiconductor substrate outside described fleet plough groove isolation structure is formed grid structure;
Etch the Semiconductor substrate of described grid structure both sides, form groove;
Germanium silicon layer it is epitaxially formed in described groove.
10. the forming method of semiconductor device as claimed in claim 9, it is characterised in that form groove in described Semiconductor substrate and the fleet plough groove isolation structure being positioned at described groove includes:
Forming patterned mask layer at described semiconductor substrate surface, described mask layer has the first opening;
Etch described Semiconductor substrate along described first opening, in described Semiconductor substrate, form groove;
Being etched back to described mask layer, increase described first opening, form the second opening, described second opening is more than the opening of described groove;
In the second opening of described groove and described mask layer, fill full oxide, and described oxide is carried out planarization process, form fleet plough groove isolation structure;
Remove described mask layer.
11. the forming method of semiconductor device as claimed in claim 10, it is characterised in that described second opening is more than described first opening
12. the forming method of semiconductor device as claimed in claim 10, it is characterised in that the material of described mask layer is silicon nitride, it is etched back to described mask layer and adopts phosphoric acid solution, wherein, the percent by volume of phosphoric acid is 85%��88%, and solution temperature is 155 DEG C��165 DEG C.
13. the forming method of semiconductor device as claimed in claim 10, it is characterised in that be also formed with pad oxide between described semiconductor substrate surface and described mask layer.
14. the forming method of semiconductor device as claimed in claim 9, it is characterised in that before the Semiconductor substrate etching described grid structure both sides forms groove, also include:
Form the protective layer covering described semiconductor substrate surface and described grid structure;
Form the side wall covering described gate structure sidewall.
15. a semiconductor device, it is characterised in that including:
Semiconductor substrate, has groove in described Semiconductor substrate;
Fleet plough groove isolation structure, described fleet plough groove isolation structure includes filling part and covering part, wherein, described filling part fills the groove in full described Semiconductor substrate, the part semiconductor substrate that described covering part is positioned on described filling part and covers outside described groove;
It is positioned at the grid structure in the Semiconductor substrate outside described fleet plough groove isolation structure;
It is positioned at the groove of the Semiconductor substrate of described grid structure both sides;
It is positioned at the germanium silicon layer of described groove.
16. semiconductor device as claimed in claim 15, it is characterised in that the covering part of described fleet plough groove isolation structure covers the width of the Semiconductor substrate outside described groove and is
17. semiconductor device as claimed in claim 15, it is characterised in that also include:
Cover described semiconductor substrate surface and the protective layer of described grid structure;
Cover the side wall of described gate structure sidewall.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994065A (en) * | 2016-10-27 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110896046A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure, semiconductor device and preparation method thereof |
| CN110896047A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method of semiconductor device |
| CN113178483A (en) * | 2021-04-27 | 2021-07-27 | 福建省晋华集成电路有限公司 | Semiconductor structure and semiconductor structure preparation method |
-
2014
- 2014-11-05 CN CN201410617677.XA patent/CN105633000A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994065A (en) * | 2016-10-27 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107994065B (en) * | 2016-10-27 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110896046A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure, semiconductor device and preparation method thereof |
| CN110896047A (en) * | 2018-09-12 | 2020-03-20 | 长鑫存储技术有限公司 | Shallow trench isolation structure and preparation method of semiconductor device |
| CN113178483A (en) * | 2021-04-27 | 2021-07-27 | 福建省晋华集成电路有限公司 | Semiconductor structure and semiconductor structure preparation method |
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