CN114284290A - Three-dimensional memory and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 239000010410 layer Substances 0.000 claims description 495
- 238000005530 etching Methods 0.000 claims description 78
- 230000006870 function Effects 0.000 claims description 53
- 238000003860 storage Methods 0.000 claims description 53
- 230000000149 penetrating effect Effects 0.000 claims description 46
- 230000000903 blocking effect Effects 0.000 claims description 38
- 239000011810 insulating material Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 31
- 230000005641 tunneling Effects 0.000 claims description 25
- 230000006386 memory function Effects 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 abstract description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 230000002093 peripheral effect Effects 0.000 description 14
- 238000000151 deposition Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005429 filling process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
The invention relates to a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises the following steps: forming a stacked structure on the substrate, the stacked structure forming a step structure at one end in a transverse direction parallel to the substrate; forming an insulating covering layer covering the step structure; forming a redundant channel hole on the step structure, wherein the redundant channel hole extends in a longitudinal direction perpendicular to the substrate, the top end portion of the redundant channel hole is positioned in the insulating cover layer, and the redundant channel hole does not penetrate through the step structure; forming a redundant channel structure in the redundant channel hole; and forming a virtual channel structure which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure, wherein the orthographic projection of the virtual channel structure on the substrate is positioned in the orthographic projection of the redundant channel structure on the substrate, so that in the forming process of the three-dimensional memory, the difference between the top size and the bottom size of the virtual channel structure can be reduced, the process window in the process of forming the contact plug can be increased, the difficulty of the manufacturing process is reduced, and the production cost is reduced.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
[ background of the invention ]
As technology evolves, the semiconductor industry is continually looking for new ways of manufacturing such that each memory die in a memory device has a greater number of memory cells. Among them, the 3DNAND (three-dimensional) memory has become a leading-edge memory technology with great development potential due to its advantages of high storage density and low cost.
In the three-dimensional memory, a way of vertically stacking multiple layers of memory cells is generally adopted to achieve the purpose of accommodating higher storage capacity in a smaller space so as to improve the storage density and capacity of the three-dimensional memory. The stacked structure in a three-dimensional memory generally includes a core array region and a step region in which a plurality of dummy channel structures are distributed.
However, in the formation process of the three-dimensional memory, the above-mentioned dummy trench structure has a problem of large difference between the bottom dimension and the top dimension, which further increases the difficulty of the formation process of the three-dimensional memory and is not favorable for reducing the production cost.
[ summary of the invention ]
The invention aims to provide a three-dimensional memory and a manufacturing method thereof, so as to reduce the process difficulty and the production cost.
In order to solve the above problems, the present invention provides a method for manufacturing a three-dimensional memory, the method comprising: forming a stacked structure on the substrate, the stacked structure forming a step structure at one end in a transverse direction parallel to the substrate; forming an insulating covering layer covering the step structure; forming a redundant channel hole on the step structure, wherein the redundant channel hole extends in a longitudinal direction perpendicular to the substrate, the top end portion of the redundant channel hole is positioned in the insulating cover layer, and the redundant channel hole does not penetrate through the step structure; forming a redundant channel structure in the redundant channel hole; and forming a virtual channel structure which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure, wherein the orthographic projection of the virtual channel structure on the substrate is positioned in the orthographic projection of the redundant channel structure on the substrate.
Wherein, form redundant channel structure in redundant channel hole, specifically include: and filling an insulating material in the redundant channel hole to form a redundant channel structure.
Wherein, form redundant channel structure in redundant channel hole, specifically include: forming an etching stop layer on the side wall of the redundant channel hole; and forming a first insulating layer which is positioned on the surface of the etching stop layer and fills the residual space in the redundant channel hole so as to form a redundant channel structure comprising the etching stop layer and the first insulating layer, wherein the orthographic projection boundary of the virtual channel structure on the substrate is positioned in the orthographic projection boundary of the etching stop layer on the substrate.
Wherein, stacked structure includes the first stacked structure and the second stacked structure that stack the setting in vertical, forms stacked structure on the substrate, specifically includes: forming a first stack structure on a substrate, the first stack structure including a step region and a core region connected to the step region in a lateral direction parallel to the substrate; forming a first channel hole through the first stack structure in the core region; forming a sacrificial material layer in the first channel hole; forming a second stack structure on the first stack structure and the sacrificial material layer; and removing part of the second stack structure on the step area and part of the first stack structure in the step area to form the step structure.
The manufacturing method of the three-dimensional memory further comprises the following steps: and a second channel hole formed on the core region and penetrating through the second stack structure, the second channel hole being communicated with the first channel hole, and the second channel hole and the redundant channel hole being formed through the same process step.
The manufacturing method of the three-dimensional memory further comprises the following steps: removing the sacrificial material layer through the second trench hole; and forming a channel structure in the first channel hole and the second channel hole, wherein the channel structure and the redundant channel structure are formed through the same process step, and the redundant channel structure comprises a storage function layer positioned on the side wall of the redundant channel hole, a channel layer positioned on the surface of the storage function layer and a second insulating layer positioned on the surface of the channel layer and filling the residual space in the redundant channel hole.
Wherein, form and extend and run through the dummy channel structure of redundant channel structure and step structure in vertical, specifically include: forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer and the step structure in the redundant channel structure; and forming a virtual channel structure in the virtual channel hole.
Wherein, form and extend and run through the dummy channel structure of redundant channel structure and step structure in vertical, specifically include: forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer and the step structure in the redundant channel structure; forming a dummy channel structure in the dummy channel hole
Wherein, the storage function layer includes setting gradually charge-trapping layer and the tunnel layer on the lateral wall in redundant channel hole, forms and extends and runs through redundant channel structure and step structure's virtual channel structure on vertical, specifically includes: forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer, the tunneling layer and the step structure in the redundant channel structure; and forming a virtual channel structure in the virtual channel hole.
Wherein, the storage function layer includes setting gradually charge-trapping layer and the tunnel layer on the lateral wall in redundant channel hole, forms and extends and runs through redundant channel structure and step structure's virtual channel structure on vertical, specifically includes: forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer, the tunneling layer, the charge capturing layer and the step structure in the redundant channel structure; and forming a virtual channel structure in the virtual channel hole.
Wherein, the storage function layer includes setting gradually charge-trapping layer and the tunnel layer on the lateral wall in redundant channel hole, forms and extends and runs through redundant channel structure and step structure's virtual channel structure on vertical, specifically includes: forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer, the tunneling layer, the charge capturing layer, the charge blocking layer and the step structure in the redundant channel structure; and forming a virtual channel structure in the virtual channel hole.
Wherein, the substrate includes base and sacrificial layer of longitudinal stack setting, after forming the dummy channel structure that extends and runs through redundant channel structure and step structure in longitudinal extension, still includes: removing the substrate and the sacrificial layer; forming a common source layer on a lower surface of the stack structure; forming an interlayer dielectric layer on one side of the common source layer, which is far away from the stacked structure; forming a plurality of conductive contacts penetrating through the interlayer dielectric layer; an interconnect layer is formed on a side of the interlevel dielectric layer facing away from the common source layer, and the plurality of conductive contacts include source contacts extending in a longitudinal direction and electrically connected at one end to the common source layer and at the other end to the interconnect layer.
In order to solve the above problems, the present invention also provides a three-dimensional memory, including: a base structure; a stacked structure on the base structure, the stacked structure forming a step structure at one end in a lateral direction parallel to the base structure; an insulating cover layer covering the step structure; a redundant channel structure located on the step structure, the redundant channel structure extending in a longitudinal direction perpendicular to the base structure, a top end portion of the redundant channel structure being located in the insulating cover layer, and the redundant channel structure not penetrating through the step structure; and the virtual channel structure extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure, and the orthographic projection of the virtual channel structure on the base structure is positioned in the orthographic projection of the redundant channel structure on the base structure.
The redundant channel structure is made of an insulating material.
The redundant channel structure comprises an etching stop layer arranged around the side surface of the virtual channel structure, and the orthographic projection boundary of the virtual channel structure on the substrate structure is positioned in the orthographic projection boundary of the etching stop layer on the substrate structure.
Wherein the stack structure includes a first stack structure and a second stack structure stacked in a longitudinal direction, the first stack structure including a core region connected to the step region in a lateral direction parallel to the base structure and in a step region, the step structure being formed by removing a portion of the second stack structure on the step region and a portion of the first stack structure in the step region, the three-dimensional memory further including a channel structure penetrating the first stack structure in the core region and penetrating the second stack structure on the core region, the channel structure including a third insulating layer, a first channel layer disposed around a side surface of the third insulating layer, and a first memory function layer disposed around a side surface of the first channel layer.
The redundant channel structure comprises a second channel layer and a second storage function layer, wherein the second channel layer is arranged around the side surface of the virtual channel structure, the second storage function layer is arranged around the side surface of the second channel layer, the orthographic projection boundary of the virtual channel structure on the substrate structure is located in the orthographic projection boundary of the second channel layer on the substrate structure, the second channel layer and the first channel layer are formed through the same process step, and the second storage function layer and the first storage function layer are formed through the same process step.
The redundant channel structure comprises a second storage function layer arranged around the side surface of the virtual channel structure, wherein the orthographic projection boundary of the virtual channel structure on the substrate structure is positioned in the orthographic projection boundary of the second storage function layer on the substrate structure, and the second storage function layer and the first storage function layer are formed through the same process step.
The first storage function layer comprises a first tunneling layer arranged around the side surface of the first channel layer, a first charge trapping layer arranged around the side surface of the first tunneling layer and a first charge blocking layer arranged around the side surface of the first charge trapping layer.
The redundant channel structure comprises a second charge trapping layer and a second charge blocking layer, wherein the second charge trapping layer is arranged around the side surface of the virtual channel structure, the second charge blocking layer is arranged around the side surface of the second charge trapping layer, the orthographic projection boundary of the virtual channel structure on the base structure is located in the orthographic projection boundary of the second charge trapping layer on the base structure, the second charge trapping layer and the first charge trapping layer are formed through the same process step, and the second charge blocking layer and the first charge blocking layer are formed through the same process step.
The redundant channel structure comprises a second charge blocking layer arranged around the side surface of the virtual channel structure, wherein the orthographic projection boundary of the virtual channel structure on the substrate structure is positioned in the orthographic projection boundary of the second charge blocking layer on the substrate structure, and the second charge blocking layer and the first charge blocking layer are formed through the same process step.
Wherein, the base structure includes: a common source layer on a lower surface of the stack structure; the interlayer dielectric layer is positioned on one side, away from the stacked structure, of the common source layer; a plurality of conductive contacts extending through the interlevel dielectric layer; and an interconnect layer on a side of the interlevel dielectric layer facing away from the common source layer, wherein the plurality of conductive contacts include a source contact extending in a longitudinal direction and having one end electrically connected to the common source layer and another end electrically connected to the interconnect layer.
The invention has the beneficial effects that: the invention provides a three-dimensional memory and a manufacturing method thereof, a stacked structure is formed on a substrate, one end of the stacked structure in the transverse direction parallel to the substrate forms a step structure and forms an insulating covering layer covering the step structure, then a redundant channel hole is formed on the step structure, the redundant channel hole extends in the longitudinal direction vertical to the substrate, the top end part of the redundant channel hole is positioned in the insulating covering layer, the redundant channel hole does not penetrate through the step structure, then the redundant channel structure is formed in the redundant channel hole and forms a virtual channel structure which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure, the orthographic projection of the virtual channel structure on the substrate is positioned in the orthographic projection of the redundant channel structure on the substrate, thereby reducing the difference between the top size and the bottom size of the virtual channel structure in the forming process of the three-dimensional memory, and is favorable for enlarging the process window when the contact plug is formed, thereby reducing the difficulty of the manufacturing process and reducing the production cost.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention;
fig. 2a to 2r are schematic cross-sectional structures corresponding to a process flow of manufacturing a three-dimensional memory according to an embodiment of the invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the various figures, elements of similar structure are identified by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain pertinent portions may not be shown in the figures.
The present invention may be embodied in various forms, some examples of which are described below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention, where a specific flow of the method for manufacturing the three-dimensional memory may be as follows:
step S11: a stacked structure is formed on a substrate, and the stacked structure forms a step structure at one end in a lateral direction parallel to the substrate.
Fig. 2a shows a schematic cross-sectional structure of the completed step S11.
The substrate 21 is used to support device structures thereon and may comprise a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). The stacked structure 22 may include several gate sacrificial layers 221 and gate insulating layers 222 alternately stacked in a longitudinal direction Z perpendicular to the substrate 21. Specifically, the above-mentioned several gate sacrificial layers 221 and gate insulating layers 222 may extend in a first lateral direction X parallel to the substrate 21, and form a step structure 22A at least one end of the first lateral direction X, the step structure 22A being stepped in the longitudinal direction Z. In a specific implementation, a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, a laser assisted deposition method, or the like may be adopted to form the gate insulating layer 222 and the gate sacrificial layer 221 of the stacked structure 22 on the substrate 21, and then the stacked structure 22 may be etched to make at least one end of the stacked structure 22 in the first lateral direction X have a step shape.
The gate sacrificial layer 221 may be, but not limited to, silicon nitride, and the gate insulating layer 222 may be, but not limited to, silicon oxide, so as to form a stacked structure of silicon nitride layer/silicon oxide layer, and in the subsequent steps, the gate sacrificial layer 221 is replaced by a replacement process and a conductive material (e.g., tungsten) is filled at the same position to form a gate layer.
In the three-dimensional memory, the number of layers of the stacked structure 22 determines the number of memory cells included in the vertical direction (perpendicular to the longitudinal direction Z of the substrate 21), for example, the number of layers of the stacked structure 22 may be 32, 64, 96, 128, etc., and the greater the number of layers of the stacked structure 22, the higher the integration of the three-dimensional memory.
Step S12: and forming an insulating covering layer covering the step structure.
Fig. 2b shows a schematic cross-sectional structure of the completed step S12.
The insulating cover layer 23 may be made of an insulating material such as silicon oxide. Specifically, the insulating cover layer 23 covering the step structure 22A may be formed by filling a dielectric material on the step structure 22A. In some embodiments, the insulating cover layer 23 may also cover a peripheral region of the substrate 21 not covered by the stacked structure 22, that is, the insulating cover layer 23 may be formed by filling an insulating material on the substrate 21 and covering the step structure 22A. In other embodiments, after forming the insulating capping layer 23, a side surface (i.e., an upper surface) of the insulating capping layer 23 facing away from the substrate 21 may be planarized by a chemical mechanical polishing method to improve stability of a device structure formed on the insulating capping layer 23.
Step S13: and forming a redundant channel hole on the step structure, wherein the redundant channel hole extends in the longitudinal direction vertical to the substrate, the top end part of the redundant channel hole is positioned in the dielectric layer, and the redundant channel hole does not penetrate through the step structure.
Fig. 2c shows a schematic cross-sectional structure after step S13 is completed.
In the present embodiment, the depth of the redundant channel hole 24 is smaller than the height of the stacked structure 22, and the end surface of the top end of the redundant channel hole 24 is located in the upper surface of the insulating cover layer 23. Specifically, the step structure 22A covered with the insulating cover layer 23 may be etched from top to bottom by an anisotropic etching process (e.g., a dry etching process) to form the redundant channel hole 24 extending in the longitudinal direction Z perpendicular to the substrate 21 and not penetrating through the step structure 22A.
In some embodiments, the depth of the redundant channel hole 24 may be between 1/3 and 2/3 (e.g., 1/3, 1/2, 2/3, etc.) of the height of the stacked structure 22.
Step S14: a redundant channel structure is formed in the redundant channel hole.
In an embodiment, the material of the redundant channel structure may be an insulating material such as silicon oxide, and accordingly, the step S14 may specifically include:
step S141: and filling an insulating material in the redundant channel hole to form a redundant channel structure.
Fig. 2d shows a schematic cross-sectional structure diagram after step S141 is completed.
Specifically, the redundant channel structure 25 having the air cavity gap 25A may be obtained by depositing an insulating material in the redundant channel hole 24 described above, and the air cavity gap 25A may be formed during the deposition of the insulating material. In addition, in practical implementation, one or more air cavity gaps 25A may be formed during the filling process by controlling the filling process of the insulating material used to fabricate the redundant trench structure 25.
In an alternative embodiment, the redundant channel structure may include an etching stop layer on a sidewall of the redundant channel hole and a first insulating layer on a surface of the etching stop layer, and accordingly, the step S14 may specifically include:
step S142: an etch stop layer is formed on sidewalls of the redundant channel hole.
Step S143: and forming a first insulating layer which is positioned on the surface of the etching stop layer and fills the residual space in the redundant channel hole so as to form a redundant channel structure comprising the etching stop layer and the first insulating layer.
Fig. 2e shows a schematic cross-sectional structure diagram after step S143 is completed.
The etch stop layer 251 covers at least the sidewalls of the redundant channel hole 24, for example, the etch stop layer 251 may cover both the sidewalls and the bottom surface of the redundant channel hole 24. In addition, in a specific implementation, a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, a laser assisted deposition method, or the like may be adopted to form an etching stop layer 251 covering the sidewall and the bottom surface of the redundant channel hole 24 on the inner wall of the redundant channel hole 24, and then a first insulating layer 252 may be deposited on the inner side of the etching stop layer 251 to fill the remaining space in the redundant channel hole 24, so as to obtain the redundant channel structure 25. Also, in some embodiments, one or more air cavity gaps 252A may be formed during the filling process by controlling the filling process of the insulating material used to make the first insulating layer 252.
Specifically, the material of the etch stop layer 251 may be an insulating material such as silicon nitride, or may be an insulating material such as polysilicon, and the material of the first insulating layer 252 may be an insulating material such as silicon oxide. Also, it is understood that the etch stop layer 251 and the first insulating layer 252 may have different etch selectivity ratios, so that the first insulating layer 252 can be selectively removed with respect to the etch stop layer 251 by using a selective etchant during a subsequent process.
In the above embodiments, the air cavity gaps 25A/252A formed during the deposition of the insulating material may be formed due to the different deposition rates of the insulating material on the surfaces of the different materials. For example, if the deposition rate of the insulating material on the side surfaces of the redundant channel hole 24 is greater than the deposition rate of the insulating material on the bottom surface of the redundant channel hole 24, the insulating material may grow in the redundant channel hole 24 from the four sides toward the lateral center of the redundant channel hole 24, so that an air cavity gap may exist in the lateral center of the finally grown insulating material film.
Step S15: and forming a virtual channel structure which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure, wherein the orthographic projection of the virtual channel structure on the substrate is positioned in the orthographic projection of the redundant channel structure on the substrate.
Fig. 2f shows a schematic cross-sectional structure after step S15 is completed.
A tip portion of the dummy channel structure 26 is located in the insulating cap layer 23, and the dummy channel structure 26 penetrates the step structure 22A and may extend to the substrate 21. Specifically, the dummy trench structure 26 may be formed by sequentially etching the redundant trench structure 25 and the step structure 22A from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a dummy trench hole sequentially penetrating through the redundant trench structure 25 and the step structure 22A from top to bottom, and then filling an insulating material such as silicon oxide in the dummy trench hole.
In the present embodiment, as shown in fig. 2d, when the redundant channel structure 25 is formed by depositing an insulating material in the redundant channel hole 24, one or more air cavity gaps 25A are formed corresponding to the interior of the redundant channel structure 25, thus, compared to the solution of some embodiments, in which the dummy channel structure is formed by directly etching the insulating capping layer, the solution of the present embodiment, in which the dummy channel structure 26 is formed by etching the redundant channel structure 25, because the air cavity gap 25A exists in the redundant channel structure 25, the time for etching and forming the virtual channel hole can be shortened, the production efficiency can be improved, and simultaneously, the problems of shape distortion and lateral size expansion of the top end part of the virtual channel hole or the virtual channel structure 26 in the redundant channel structure 25 can be improved to a certain extent.
In one embodiment, as shown in fig. 2e, when the redundant channel structure 25 includes the etching stop layer 251 located on the sidewall of the redundant channel hole 24 and the first insulating layer 252 located on the surface of the etching stop layer 251, an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process) may be used to sequentially etch the first insulating layer 252 and the step structure 22A in the redundant channel structure 25 from top to bottom on the substrate 21, so as to form a virtual channel hole sequentially penetrating through the redundant channel structure 25 and the step structure 22A from top to bottom, and then the virtual channel hole may be filled with an insulating material such as silicon oxide to form the virtual channel structure 26. Accordingly, the orthographic projection boundary of the dummy channel structure 26 on the substrate 21 may be located within the orthographic projection boundary of the etch stop layer 251 in the redundant channel structure 25 on the substrate 21.
Moreover, compared with the scheme in which the dummy channel structure is formed by directly etching the insulating cover layer in some embodiments, in the scheme in which the dummy channel structure 26 is formed by etching the first insulating layer 252 in the redundant channel structure 25 in this embodiment, since the air cavity gap 252A exists in the first insulating layer 252 in the redundant channel structure 25, the time required for forming the dummy channel hole by etching can be shortened, which is beneficial to improving the production efficiency.
Meanwhile, in the process of etching the first insulating layer 252 in the redundant channel structure 25 to form the virtual channel hole penetrating through the redundant channel structure 25, the etch stop layer 251 in the redundant channel structure 25 on the side surface of the first insulating layer 252 can stop the lateral etching on the etch stop layer 251 on the side surface of the first insulating layer 252, so as to avoid the problem of shape distortion and lateral size expansion of the virtual channel hole or the top end portion of the virtual channel structure 26 in the redundant channel structure 25.
Also, it is understood that when the etching stop layer 251 covers both the sidewall and the bottom surface of the redundant channel hole 24, the etching stop layer 251 on the bottom surface of the redundant channel hole 24 or the first insulating layer 251 may be at least partially removed during the etching of the first insulating layer 252 in the redundant channel structure 25 to form the virtual channel hole, so as to obtain the virtual channel hole or the virtual channel structure 26 penetrating through the first insulating layer 252 in the redundant channel structure 25 and the etching stop layer 251 on the bottom surface of the first insulating layer 251.
In the above embodiment, the three-dimensional memory may further include a channel structure extending in a direction perpendicular to the substrate 21 and penetrating the stacked structure 22. Moreover, in order to increase the number of layers of the stacked structure 22 to increase the storage density of the three-dimensional memory and at the same time not increase the difficulty of the etching process for forming the channel structure, the stacked structure 22 may include a plurality of stacked structures stacked in the longitudinal direction Z, and the channel structure penetrating through the stacked structure 22 may be formed by multiple times of etching correspondingly. Moreover, for convenience of understanding and explanation, the present embodiment is described by taking as an example that the stacking structure 22 includes a first stacking structure and a second stacking structure stacked in the longitudinal direction Z, and accordingly, the step S11 may specifically include:
step S111: a first stack structure is formed on a substrate, the first stack structure including a step region and a core region connected to the step region in a lateral direction parallel to the substrate.
Step S112: a first channel hole is formed through the first stack structure in the core region.
Step S113: a sacrificial material layer is formed in the first channel hole.
Step S114: a second stack structure is formed over the first stack structure and the sacrificial material layer.
Step S115: and removing part of the second stack structure on the step area and part of the first stack structure in the step area to form the step structure.
Fig. 2g shows a schematic cross-sectional structure diagram after step S115 is completed.
Each of the first stack structure Deck1 and the second stack structure Deck2 in the stack structure 22 may include a plurality of gate sacrificial layers 221 and gate insulating layers 222 alternately stacked in a vertical direction Z perpendicular to the substrate 21. The number of layers of the second stack structure Deck2 may be the same as or different from that of the first stack structure Deck 1.
The first channel hole 27 may be formed by etching the first stack structure Deck1 from top to bottom in the Core Area. The first channel hole 27 penetrates the first stack structure Deck1, and may extend to the substrate 21 in a direction perpendicular to the longitudinal direction Z of the substrate 21.
The above-mentioned sacrificial material layer 28 may be formed by depositing a filling sacrificial material in the first channel hole 27 using a chemical vapor deposition process, and removing the sacrificial material located outside the first channel hole 27 using chemical mechanical planarization. Wherein the sacrificial material may be any one of polysilicon, carbon and tungsten.
Specifically, the above-described step structure 22A may be formed by performing a plurality of "trim-etch" cycles of the portion of the second stack structure Deck2 on the step region SS and the portion of the first stack structure Deck1 in the step region SS.
In the above embodiment, after the step S125, the method may further include:
step S116: and a second channel hole formed on the core region and penetrating through the second stack structure, the second channel hole being communicated with the first channel hole, and the second channel hole and the redundant channel hole being formed through the same process step.
Fig. 2h shows a schematic cross-sectional structure after step S116 is completed.
Specifically, the second channel hole 29 penetrating the second stack structure Deck2 to the upper surface of the first stack structure Deck1 in the vertical direction Z of the substrate 21 may be formed by etching the above-described second stack structure Deck2 from top to bottom, and the bottom of the second channel hole 29 exposes the top surface of the sacrificial material layer 28 in the first channel hole 27.
In this embodiment, the depth of the redundant channel hole 24 may be the same as the height of the second stack structure Deck2, and the redundant channel hole 24 and the second channel hole 29 may be formed together by the same process step, for example, by the same etching process step, that is, the step S13 and the step S116 may be performed simultaneously, so that no additional process step is required.
Step S117: the sacrificial material layer is removed through the second trench hole.
Fig. 2i shows a schematic cross-sectional structure after step S117 is completed.
Specifically, a selective etchant may be used to remove the sacrificial material layer 28 selectively with respect to the first stack structure Deck1 and the second stack structure Deck 2.
Step S118: and forming a channel structure in the first channel hole and the second channel hole, wherein the channel structure and the redundant channel structure are formed through the same process step.
Fig. 2j shows a schematic cross-sectional structure after step S118 is completed.
Specifically, a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, a laser assisted deposition method, or the like may be adopted to sequentially deposit the first memory function layer 303 and the first channel layer 302 on the inner walls of the first channel hole 27 and the second channel hole 29 described above, and fill a dielectric material (e.g., silicon oxide) in the first channel hole 27 and the second channel hole 29 in which the first memory function layer 303 and the first channel layer 302 are formed, to form the third insulating layer 301, so as to obtain the channel structure 30 having the third insulating layer 301, the first channel layer 302, and the first memory function layer 303. The first memory function layer 303 may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially formed on inner walls of the first channel hole 27 and the second channel hole 29, and specifically, the charge blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 302 may be made of silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, and have a "SONO" structure corresponding to the channel structure. Further, it is to be understood that the memory function layer 303 described here is an ONO layer composed of a first oxide layer, a nitride layer, and a second oxide layer, but may have another structure, for example, NONO.
In the present embodiment, the redundant channel structure 25 and the channel structure 30 may be formed together by the same process step, i.e., the step S14 and the step S118 may be performed simultaneously, so that no additional process step is required. Specifically, the above-described redundant channel structure 25 may include a second storage function layer 255 on sidewalls and a bottom surface of the above-described redundant channel hole 24, a second channel layer 254 on a surface of the second storage function layer 255, and a second insulating layer 253 on a surface of the second channel layer 254 and filling a remaining space in the redundant channel hole 24. Here, the second memory functional layer 255 and the first memory functional layer 303 in the channel structure 30 may have the same structure and be formed together through the same process steps. The second channel layer 254 and the first channel layer 302 in the channel structure 30 described above may have the same structure and be formed together by the same process steps. The second insulating layer 253 and the third insulating layer 301 in the channel structure 30 described above may have the same structure and be formed together by the same process steps.
In a specific embodiment, the step S15 may specifically include:
step S151: and forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer and the step structure in the redundant channel structure.
Step S152: and forming a virtual channel structure in the virtual channel hole.
Fig. 2k shows a schematic cross-sectional structure after step S152 is completed.
Specifically, the second insulating layer 253 in the redundant channel structure 25, the second channel layer 254 and the second storage function layer 255 in the redundant channel structure 25, which are located on the bottom surface of the redundant channel hole 24, and the step structure 22A in the stacked structure 22 may be sequentially etched from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a virtual channel hole which sequentially penetrates through the redundant channel structure 25 and the step structure 22A from top to bottom, and then, an insulating material such as silicon oxide may be filled in the virtual channel hole to form the virtual channel structure 26.
As such, the orthographic projection boundary of the dummy channel structure 26 formed by the steps S151 and S152 on the substrate 21 is located within the orthographic projection boundary of the second channel layer 254 on the sidewall of the redundant channel hole 24 on the substrate 21 in the redundant channel structure 25. Also, it is understood that in the process of etching the second insulating layer 253 in the redundant channel structure 25 to form the above-mentioned virtual channel hole penetrating through the redundant channel structure 25, the second channel layer 254 on the sidewall of the redundant channel hole 24 in the redundant channel structure 25 may have the same function as the etch stop layer 251 in the above-mentioned embodiment, and the lateral etching can be stopped on the second channel layer 254 on the side surface of the above-mentioned second insulating layer 253, so as to avoid the problems of shape distortion and lateral size expansion of the top end portion of the above-mentioned virtual channel hole or virtual channel structure 26 in the redundant channel structure 25.
In an alternative embodiment, the step S151 may be replaced by:
step S153: and forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer and the second channel layer in the redundant channel structure and the step structure.
Accordingly, the cross-sectional structure of the step S152 is schematically shown in fig. 2 l.
Specifically, the second insulating layer 253 and the second channel layer 254 in the redundant channel structure 25, the second storage function layer 255 on the bottom surface of the redundant channel hole 24 in the redundant channel structure 25, and the step structure 22A in the stacked structure 22 may be sequentially etched from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a virtual channel hole sequentially penetrating through the redundant channel structure 25 and the step structure 22A from top to bottom, and then, an insulating material such as silicon oxide may be filled in the virtual channel hole to form the virtual channel structure 26.
In this way, the orthographic projection boundary of the dummy channel structure 26 formed in the above steps S153 and S152 on the substrate 21 is located within the orthographic projection boundary of the second memory function layer 255 located on the sidewall of the redundant channel hole 24 in the above redundant channel structure 25 on the substrate 21. Further, it is understood that, in the process of etching the second insulating layer 253 and the second channel layer 254 in the redundant channel structure 25 to form the above-mentioned virtual channel hole penetrating through the redundant channel structure 25, the second memory function layer 255 on the sidewall of the redundant channel hole 24 in the redundant channel structure 25 may have the same function as the etch stop layer 251 in the above-mentioned embodiment, and the lateral etching can be stopped on the second memory function layer 255 on the side surface of the above-mentioned second insulating layer 253, so as to avoid the problem of shape distortion and lateral size expansion of the above-mentioned virtual channel hole or the top end portion of the virtual channel structure 26 in the redundant channel structure 25.
In another alternative embodiment, the step S151 may be replaced by:
step S154: and forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the second channel layer, the tunneling layer and the step structure in the redundant channel structure.
Specifically, the second insulating layer 253, the tunneling layer of the second channel layer 254 and the second storage function layer 255 in the redundant channel structure 25, the charge trapping layer and the charge blocking layer of the second storage function layer 255 on the bottom surface of the redundant channel hole 24 in the redundant channel structure 25, and the step structure 22A in the stacked structure 22 may be etched sequentially from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a dummy channel hole sequentially penetrating through the redundant channel structure 25 and the step structure 22A from top to bottom, and then, an insulating material such as silicon oxide may be filled in the dummy channel hole to form the dummy channel structure 26.
In this way, the orthographic projection boundary of the dummy channel structure 26 formed in the above steps S154 and S152 on the substrate 21 is located within the orthographic projection boundary of the charge trapping layer located on the sidewall of the redundant channel hole 24 in the second storage function layer 255 of the above redundant channel structure 25 on the substrate 21. Further, it is understood that, in the process of etching the second insulating layer 253, the second channel layer 254 and the tunneling layer in the redundant channel structure 25 to form the virtual channel hole penetrating through the redundant channel structure 25, the charge trapping layer on the sidewall of the redundant channel hole 24 in the second storage function layer 255 of the redundant channel structure 25 may have the same function as the etch stop layer 251 in the above embodiment, and the lateral etching can be stopped on the second storage function layer 255 on the side surface of the second insulating layer 253, so as to avoid the problem of shape distortion and lateral size expansion of the virtual channel hole or the top end portion of the virtual channel structure 26 in the redundant channel structure 25.
In another alternative embodiment, the step S151 may be replaced by:
step S155: and forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the second channel layer, the tunneling layer, the charge trapping layer and the step structure in the redundant channel structure.
Specifically, the second insulating layer 253, the second channel layer 254, the tunneling layer of the second storage function layer 255, the charge trapping layer of the second storage function layer 255, the charge blocking layer of the second storage function layer 255 on the bottom surface of the redundant channel hole 24 in the redundant channel structure 25, and the step structure 22A in the stacked structure 22 may be etched sequentially from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a virtual channel hole sequentially penetrating through the redundant channel structure 25 and the step structure 22A from top to bottom, and then, an insulating material such as silicon oxide may be filled in the virtual channel hole to form the virtual channel structure 26.
In this way, the orthographic projection boundary of the dummy channel structure 26 formed in the above steps S155 and S152 on the substrate 21 is located within the orthographic projection boundary of the charge blocking layer located on the sidewall of the redundant channel hole 24 in the second memory function layer 255 of the above redundant channel structure 25 on the substrate 21. Further, it is understood that, in the process of etching the second insulating layer 253, the second channel layer 254 and the tunneling layer in the redundant channel structure 25 to form the virtual channel hole penetrating through the redundant channel structure 25, the charge blocking layer on the sidewall of the redundant channel hole 24 in the second storage function layer 255 of the redundant channel structure 25 may have the same function as the etch stop layer 251 in the above embodiment, and the lateral etching can be stopped on the second storage function layer 255 on the side surface of the second insulating layer 253, so as to avoid the problem of shape distortion and lateral size expansion of the virtual channel hole or the top end portion of the virtual channel structure 26 in the redundant channel structure 25.
In another alternative embodiment, the step S151 may be replaced by:
step S156: and forming a virtual channel hole which extends in the longitudinal direction and penetrates through the redundant channel structure and the step structure by etching the second insulating layer, the second channel layer, the tunneling layer, the charge capturing layer, the charge blocking layer and the step structure in the redundant channel structure.
Accordingly, the cross-sectional structure of the step S152 is schematically shown in fig. 2 m.
Specifically, the second insulating layer 253, the second channel layer 254, the tunneling layer of the second storage function layer 255, the charge trapping layer of the second storage function layer 255, the charge blocking layer of the second storage function layer 255, and the step structure 22A in the stacked structure 22 may be sequentially etched from top to bottom on the substrate 21 by using an anisotropic etching process (e.g., a dry etching process) or an isotropic etching process (e.g., a wet etching process), so as to form a virtual channel hole sequentially penetrating through the redundant channel structure 25 and the step structure 22A from top to bottom, and then, an insulating material such as silicon oxide may be filled in the virtual channel hole to form the virtual channel structure 26.
In this way, the orthographic projection of the dummy channel structure 26 formed in the above steps S156 and S152 on the substrate 21 can be completely overlapped with the orthographic projection of the redundant channel structure 25 on the substrate 21. Moreover, it can be understood that, since there may be air cavity gaps inside the second insulating layer 253 in the redundant channel structure 25, the scheme of forming the dummy channel structure 26 in this embodiment can shorten the time required for etching the dummy channel holes, which is beneficial to improving the production efficiency.
In the above embodiment, after the step S118, the method may further include:
step S16: a gate line slit is formed on the core region to penetrate the stacked structure.
Specifically, the gate line slit may be formed by etching the stacked structure 22 from top to bottom.
Step S17: and replacing the grid sacrificial layer of the stacked structure into a grid layer through the grid line gap.
Specifically, the gate layer may be formed by replacing the gate sacrificial layer 221 with a replacement process and filling a conductive material (e.g., tungsten) at the same position.
Step S18: and forming a common source structure in the gate line gap.
Specifically, the common source structure may be obtained by filling the gate line gap with an insulating material (e.g., an oxide) serving as a spacer and a conductive material (e.g., titanium or titanium nitride, polysilicon, and/or metal tungsten) serving as a common source. In addition, in a specific implementation, after the step S17 and before the step S18, the gate layer obtained by the replacement may be etched through the gate line gap to form a gap between the gate layer and the gate line gap, and in a subsequent process, when an insulating material and a semiconductor material and/or a metal material are filled in the gate line gap, the gap between the gate layer and the gate line gap may also be filled with the insulating material and the semiconductor material and/or the metal material.
Step S19: a plurality of word line contacts formed on the stepped structure through the insulating capping layer are electrically connected to the gate layer at positions of the stepped structure, respectively.
Fig. 2n shows a schematic cross-sectional structure after step S19 is completed.
Specifically, the plurality of word line contacts 31A described above are perpendicular to the substrate 21, and may extend to the multi-level steps of the step structure 22A in the longitudinal direction Z, respectively. In one embodiment, as shown in fig. 2n, at the same time of forming the plurality of word line contacts 31A, peripheral pad contacts 31B penetrating through the insulating cover layer 23 may be formed on the peripheral region of the substrate 21 not covered by the stacked structure 22, the peripheral pad contacts 31B are used for electrical connection with peripheral circuits, and the number and arrangement thereof may be prepared according to actual requirements. Among them, the material of the word line contact 31A and the peripheral pad contact 31B may be a conductive material, such as tungsten.
In the above embodiment, the three-dimensional memory may be embodied as a three-dimensional memory having a back source contact, and accordingly, after the step S19, the method may further include:
step S20: a first interlayer dielectric layer is formed on the stacked structure.
Step S21: a plurality of first conductive contacts are formed through the first interlayer dielectric layer.
Step S22: a first interconnect layer is formed on the first interlevel dielectric layer.
Fig. 2o shows a schematic cross-sectional structure of the completed step S22.
The material of the first interlayer dielectric layer 33 may be an insulating material such as silicon oxide. The first interconnect layer 35 may be made of a conductive material such as tungsten.
Specifically, in the previous step, a channel plug 32 may be formed at an end of the channel structure 30 far from the substrate 21. The material of the channel plug 32 may be selected from the same material as the first channel layer 302 of the channel structure 30, such as polysilicon, and the channel plug 32 may serve as the drain of the channel structure 30.
In this embodiment, the plurality of first conductive contacts 34 may include bit line contacts, and the bit line contacts may extend in a direction perpendicular to the substrate 21, and have one end electrically connected to the channel plugs 32 and the other end electrically connected to corresponding conductive traces in the first interconnect layer 35. The plurality of first conductive contacts 34 may further include word line contacts, which may extend in a direction perpendicular to the substrate 21 and have one end electrically connected to the word line contact 31A and the other end electrically connected to the corresponding conductive trace in the first interconnect layer 35. The plurality of first conductive contacts 34 may further include peripheral circuit contacts, which may extend in a direction perpendicular to the substrate 21 and have one end electrically connected to the peripheral circuit contact 31B and the other end electrically connected to corresponding conductive traces in the first interconnect layer 35.
Step S23: and providing a peripheral circuit chip, and bonding the peripheral circuit chip to the second interconnection layer through the bonding structure.
Fig. 2p shows a schematic cross-sectional structure of the completed step S23.
Specifically, the peripheral circuit chip 36 and the bonding structure may refer to specific embodiments of the peripheral circuit chip and the bonding structure in the prior art, and therefore, detailed descriptions thereof are omitted here.
In the above embodiment, as shown in fig. 2p, the substrate 21 may include a base 211 and a sacrificial layer 212 stacked in the longitudinal direction Z. The substrate 211 may include, among other things, at least one of single crystal silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, or other semiconductor materials known in the art. The material of the sacrificial layer 212 may be polysilicon. The channel structure 30, the dummy channel structure 26, and the common source structure may extend in the vertical direction Z to the inside of the sacrificial layer 212.
In a specific embodiment, after the step S23, the method further includes:
step S24: and removing the substrate and the sacrificial layer.
Specifically, the semiconductor structure obtained after the step S23 is completed may be turned over by 180 °, and then the substrate 211 and the sacrificial layer 212 may be removed by etching through a dry etching process or a wet etching process. Moreover, since the channel structure 30 extends in the longitudinal direction Z and extends into the sacrificial layer 212, the bottom of the channel structure 30 is exposed after the substrate 211 and the sacrificial layer 212 are removed.
Step S25: a common source layer is formed on a lower surface of the stack structure.
Fig. 2q shows a schematic cross-sectional structure of the completed step S25.
Specifically, before the above step S25, the first memory function layer 303 in the bottom portion of the channel structure 30 exposed after the above step S24 is completed may be removed to expose the first channel layer 302 in the bottom portion of the channel structure 30 by using an etching process, and then the first dopant of P-type or N-type may be implanted into the bottom portion and a portion near the bottom portion of the first channel layer 302 in the channel structure 30 by using an ion implantation process to dope the bottom portion and the portion near the bottom portion of the first channel layer 302. Next, a common source layer 37 covering and connecting the bottom of the first channel layer 302 may be formed on the lower surface of the stacked structure 22, wherein the common source layer 37 may be a polysilicon layer doped with the first dopant.
In some embodiments, after forming the common source layer 37, a chemical mechanical polishing process may be used to planarize a surface of the common source layer 37 facing away from the stacked structure 22, so as to obtain the common source layer 37 with a planarized surface.
Step S26: and forming a second interlayer dielectric layer on one side of the common source layer, which faces away from the stacked structure.
Step S27: a plurality of second conductive contacts are formed through the second interlevel dielectric layer.
Step S28: and forming a second interconnection layer on the side of the second interlayer dielectric layer, which faces away from the common source layer.
Fig. 2r shows a schematic cross-sectional structure of the completed step S28.
In this embodiment, the plurality of second conductive contacts 38 may include a source contact, and the source contact may extend in the longitudinal direction Z and have one end electrically connected to the common source layer 37 and the other end electrically connected to the second interconnection layer 39. In some embodiments, the plurality of second conductive contacts may further include a peripheral circuit contact, which may extend in the longitudinal direction Z and have one end electrically connected to the peripheral circuit contact 31B and the other end electrically connected to the second interconnect layer 39.
The method for fabricating a three-dimensional memory according to this embodiment includes forming a stacked structure on a substrate, forming a step structure at one end of the stacked structure parallel to a transverse direction of the substrate, forming an insulating cover layer covering the step structure, forming a redundant channel hole on the step structure, the redundant channel hole extending in a longitudinal direction perpendicular to the substrate, a top end of the redundant channel hole being located in the insulating cover layer, the redundant channel hole not penetrating through the step structure, forming a redundant channel structure in the redundant channel hole, and forming a dummy channel structure extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure, an orthographic projection of the dummy channel structure on the substrate being located in an orthographic projection of the redundant channel structure on the substrate, so that in a process for forming the three-dimensional memory, a difference between a top dimension and a bottom dimension of the dummy channel structure can be reduced, and is favorable for enlarging the process window when the contact plug is formed, thereby reducing the difficulty of the manufacturing process and reducing the production cost.
A three-dimensional memory fabricated according to the above method embodiment of the present invention is shown in fig. 2r, and includes: a base structure; a stacked structure 22 on the base structure, the stacked structure 22 forming a step structure at one end in a lateral direction parallel to the base structure; an insulating cover layer 23 covering the step structure; a redundant channel structure 25 located on the stepped structure, the redundant channel structure 25 extending in a longitudinal direction Z perpendicular to the base structure, a top end portion of the redundant channel structure 25 being located in the insulating cap layer 23, and the redundant channel structure 25 not penetrating through the stepped structure; a dummy channel structure 26 extending in the longitudinal direction Z and penetrating the redundant channel structure 25 and the step structure, an orthographic projection of the dummy channel structure 26 on the base structure being located within an orthographic projection of the redundant channel structure 25 on the base structure.
Specifically, the substrate structure may include a common source layer 37 on a lower surface of the stacked structure 22; an interlayer dielectric layer on a side of the common source layer 37 facing away from the stacked structure 22; a plurality of conductive contacts 38 extending through the interlevel dielectric layer; an interconnect layer 38 on a side of the interlevel dielectric layer facing away from the common source layer 37, wherein the plurality of conductive contacts 38 may include a source contact that may extend in the longitudinal direction and that is electrically connected to the common source layer 37 at one end and to the interconnect layer 38 at the other end.
In one embodiment, the material of the redundant channel structure 25 may be an insulating material.
In an alternative embodiment, the redundant channel structure 25 may include an etch stop layer disposed around a side surface of the dummy channel structure 26, and an orthographic boundary of the dummy channel structure 26 on the base structure is located within an orthographic boundary of the etch stop layer on the base structure.
In a specific embodiment, the above-mentioned stacked structure 22 may include a first stacked structure Deck1 and a second stacked structure Deck2 which are stacked in the longitudinal direction Z, the first stacked structure Deck1 may include a core region which is connected to a step region in a lateral direction parallel to the base structure and in a step region, and the above-mentioned step structure may be formed by removing a part of the second stacked structure on the step region and a part of the first stacked structure in the step region.
Specifically, the above three-dimensional memory may further include a channel structure 30 penetrating the first stack structure Deck1 in the core region and penetrating the second stack structure Deck2 on the core region, and the channel structure 30 may include a third insulating layer, a first channel layer disposed around a side surface of the third insulating layer, and a first memory function layer disposed around a side surface of the first channel layer.
In one embodiment, the redundant channel structure 25 may include a second channel layer disposed around a side surface of the dummy channel structure 26 and a second memory function layer disposed around a side surface of the second channel layer, wherein an orthographic projection boundary of the dummy channel structure 26 on the base structure is located within an orthographic projection boundary of the second channel layer on the base structure, and the second channel layer and the first channel layer are formed through the same process step, and the second memory function layer and the first memory function layer are formed through the same process step.
In a specific embodiment, the redundant channel structure 25 may include a second storage function layer disposed around a side surface of the dummy channel structure 26, wherein an orthographic boundary of the dummy channel structure 26 on the base structure is located within an orthographic boundary of the second storage function layer on the base structure, and the second storage function layer and the first storage function layer are formed through the same process step.
In one embodiment, the first storage function layer may include a first tunneling layer disposed around a side surface of the first channel layer, a first charge trapping layer disposed around a side surface of the first tunneling layer, and a first charge blocking layer disposed around a side surface of the first charge trapping layer.
In some embodiments, the redundant channel structure 25 may include a second charge trapping layer disposed around a side surface of the dummy channel structure 26 and a second charge blocking layer disposed around a side surface of the second charge trapping layer, wherein an orthographic projection boundary of the dummy channel structure 26 on the base structure is located within an orthographic projection boundary of the second charge trapping layer on the base structure, and the second charge trapping layer and the first charge trapping layer are formed by a same process step, and the second charge blocking layer and the first charge blocking layer are formed by a same process step.
In some embodiments, the redundant channel structure 25 may include a second charge blocking layer disposed around a side surface of the dummy channel structure 26, wherein an orthographic projection boundary of the dummy channel structure 26 on the base structure is located within an orthographic projection boundary of the second charge blocking layer on the base structure, and the second charge blocking layer is formed by the same process step as the first charge blocking layer.
It should be noted that, in the present embodiment, reference may be made to the specific implementation described in the above method embodiments for each structure of the three-dimensional memory, and therefore, details are not described here again.
The three-dimensional memory provided by the embodiment can reduce the difference between the top size and the bottom size of the virtual channel structure, and is further beneficial to increasing a process window when a contact plug is formed, so that the difficulty of a manufacturing process is reduced, and the production cost is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention. The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (22)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
forming a stacked structure on a substrate, the stacked structure forming a step structure at one end in a lateral direction parallel to the substrate;
forming an insulating covering layer covering the step structure;
forming a redundant channel hole on the stepped structure, the redundant channel hole extending in a longitudinal direction perpendicular to the substrate, a top end portion of the redundant channel hole being located in the insulating cover layer, and the redundant channel hole not penetrating through the stepped structure;
forming a redundant channel structure in the redundant channel hole;
forming a dummy channel structure extending in the longitudinal direction and penetrating the redundant channel structure and the step structure, an orthographic projection of the dummy channel structure on the substrate being within an orthographic projection of the redundant channel structure on the substrate.
2. The method according to claim 1, wherein the forming of the redundant channel structure in the redundant channel hole specifically comprises:
and filling an insulating material in the redundant channel hole to form a redundant channel structure.
3. The method according to claim 1, wherein the forming of the redundant channel structure in the redundant channel hole specifically comprises:
forming an etching stop layer on the side wall of the redundant channel hole;
and forming a first insulating layer which is positioned on the surface of the etching stop layer and fills the residual space in the redundant channel hole to form a redundant channel structure comprising the etching stop layer and the first insulating layer, wherein the orthographic projection boundary of the virtual channel structure on the substrate is positioned in the orthographic projection boundary of the etching stop layer on the substrate.
4. The method for manufacturing a three-dimensional memory according to claim 1, wherein the stack structure includes a first stack structure and a second stack structure stacked in the longitudinal direction, and the forming a stack structure on a substrate specifically includes:
forming a first stack structure on a substrate, the first stack structure comprising a step region and a core region connected to the step region in a lateral direction parallel to the substrate;
forming a first channel hole through the first stack structure in the core region;
forming a sacrificial material layer in the first channel hole;
forming a second stack structure on the first stack structure and the sacrificial material layer;
removing a portion of the second stack structure on the stepped region and a portion of the first stack structure in the stepped region to form the stepped structure.
5. The method of fabricating a three-dimensional memory according to claim 4, further comprising:
and a second channel hole formed in the core region and penetrating through the second stack structure, the second channel hole being communicated with the first channel hole, and the second channel hole and the redundant channel hole being formed through the same process step.
6. The method of fabricating a three-dimensional memory according to claim 5, further comprising:
removing the sacrificial material layer through the second trench hole;
and forming a channel structure in the first channel hole and the second channel hole, wherein the channel structure and the redundant channel structure are formed through the same process step, and the redundant channel structure comprises a storage function layer positioned on the side wall of the redundant channel hole, a channel layer positioned on the surface of the storage function layer, and a second insulating layer positioned on the surface of the channel layer and filling the residual space in the redundant channel hole.
7. The method according to claim 6, wherein the forming of the dummy trench structure extending in the longitudinal direction and penetrating the redundant trench structure and the step structure comprises:
forming a virtual channel hole extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure by etching the second insulating layer and the step structure in the redundant channel structure;
and forming a virtual channel structure in the virtual channel hole.
8. The method according to claim 6, wherein the forming of the dummy trench structure extending in the longitudinal direction and penetrating the redundant trench structure and the step structure comprises:
forming a virtual channel hole extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure by etching the second insulating layer and the channel layer in the redundant channel structure and the step structure;
and forming a virtual channel structure in the virtual channel hole.
9. The method according to claim 6, wherein the storage function layer includes a charge blocking layer, a charge trapping layer and a tunneling layer sequentially disposed on the sidewall of the redundant channel hole, and the forming of the dummy channel structure extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure includes:
forming a virtual channel hole extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer and the tunneling layer in the redundant channel structure and the step structure;
and forming a virtual channel structure in the virtual channel hole.
10. The method according to claim 6, wherein the storage function layer includes a charge blocking layer, a charge trapping layer and a tunneling layer sequentially disposed on the sidewall of the redundant channel hole, and the forming of the dummy channel structure extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure includes:
forming a virtual channel hole extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer, the tunneling layer, the charge trapping layer and the step structure in the redundant channel structure;
and forming a virtual channel structure in the virtual channel hole.
11. The method according to claim 6, wherein the storage function layer includes a charge blocking layer, a charge trapping layer and a tunneling layer sequentially disposed on the sidewall of the redundant channel hole, and the forming of the dummy channel structure extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure includes:
forming a virtual channel hole extending in the longitudinal direction and penetrating through the redundant channel structure and the step structure by etching the second insulating layer, the channel layer, the tunneling layer, the charge trapping layer, the charge blocking layer and the step structure in the redundant channel structure;
and forming a virtual channel structure in the virtual channel hole.
12. The method of claim 1, wherein the substrate comprises a base and a sacrificial layer stacked in the longitudinal direction, and further comprises, after the forming the dummy channel structure extending in the longitudinal direction and penetrating the redundant channel structure and the step structure:
removing the substrate and the sacrificial layer;
forming a common source layer on a lower surface of the stack structure;
forming an interlayer dielectric layer on one side of the common source layer, which is far away from the stacked structure;
forming a plurality of conductive contacts penetrating through the interlayer dielectric layer;
and forming an interconnection layer on one side of the interlayer dielectric layer, which is far away from the common source layer, wherein the plurality of conductive contacts comprise source contacts, the source contacts extend in the longitudinal direction, one end of each source contact is electrically connected with the common source layer, and the other end of each source contact is electrically connected with the interconnection layer.
13. A three-dimensional memory, comprising:
a base structure;
a stacked structure on the base structure, the stacked structure forming a step structure at one end in a lateral direction parallel to the base structure;
an insulating cover layer covering the step structure;
a redundant channel structure located on the step structure, the redundant channel structure extending in a longitudinal direction perpendicular to the base structure, a top end portion of the redundant channel structure being located in the insulating cap layer, and the redundant channel structure not penetrating through the step structure;
a dummy channel structure extending in the longitudinal direction and penetrating the redundant channel structure and the step structure, an orthographic projection of the dummy channel structure on the base structure being within an orthographic projection of the redundant channel structure on the base structure.
14. The three-dimensional memory according to claim 13, wherein the redundant channel structure is made of an insulating material.
15. The three-dimensional memory according to claim 13, wherein the redundant channel structure comprises an etch stop layer disposed around a side surface of the dummy channel structure, and an orthographic boundary of the dummy channel structure on the base structure is located within an orthographic boundary of the etch stop layer on the base structure.
16. The three-dimensional memory according to claim 13, wherein the stack structure includes a first stack structure and a second stack structure which are arranged in a stacked manner in the longitudinal direction, the first stack structure comprises a step region and a core region connected to the step region in a lateral direction parallel to the base structure, the step structure is formed by removing a portion of the second stack structure above the step region and a portion of the first stack structure in the step region, the three-dimensional memory further includes a channel structure in the core region through the first stack structure and on the core region through the second stack structure, the channel structure includes a third insulating layer, a first channel layer disposed around a side surface of the third insulating layer, and a first memory function layer disposed around a side surface of the first channel layer.
17. The three-dimensional memory according to claim 16, wherein the redundant channel structure comprises a second channel layer disposed around a side surface of the dummy channel structure and a second storage function layer disposed around a side surface of the second channel layer, wherein an orthographic boundary of the dummy channel structure on the base structure is located within an orthographic boundary of the second channel layer on the base structure, and the second channel layer is formed by a same process step as the first channel layer, and the second storage function layer is formed by a same process step as the first storage function layer.
18. The three-dimensional memory according to claim 16, wherein the redundant channel structure comprises a second storage function layer disposed around a side surface of the dummy channel structure, wherein an orthographic boundary of the dummy channel structure on the base structure is located within an orthographic boundary of the second storage function layer on the base structure, and the second storage function layer is formed by the same process step as the first storage function layer.
19. The three-dimensional memory according to claim 16, wherein the first storage function layer comprises a first tunneling layer disposed around a side surface of the first channel layer, a first charge trapping layer disposed around a side surface of the first tunneling layer, and a first charge blocking layer disposed around a side surface of the first charge trapping layer.
20. The three-dimensional memory according to claim 19, wherein the redundant channel structure comprises a second charge trapping layer disposed around a side surface of the dummy channel structure and a second charge blocking layer disposed around a side surface of the second charge trapping layer, wherein an orthographic projection boundary of the dummy channel structure on the base structure is located within an orthographic projection boundary of the second charge trapping layer on the base structure, and the second charge trapping layer is formed by the same process step as the first charge trapping layer, and the second charge blocking layer is formed by the same process step as the first charge blocking layer.
21. The three-dimensional memory according to claim 19, wherein the redundant channel structure comprises a second charge blocking layer disposed around a side surface of the dummy channel structure, wherein an orthographic projection boundary of the dummy channel structure on the base structure is within an orthographic projection boundary of the second charge blocking layer on the base structure, and the second charge blocking layer is formed by a same process step as the first charge blocking layer.
22. The three-dimensional memory according to claim 13, wherein the base structure comprises:
a common source layer on a lower surface of the stack structure;
the interlayer dielectric layer is positioned on one side, away from the stacked structure, of the common source layer;
a plurality of conductive contacts extending through the interlevel dielectric layer;
an interconnect layer on a side of the interlevel dielectric layer facing away from the common source layer, wherein the plurality of conductive contacts include source contacts extending in the longitudinal direction and having one end electrically connected to the common source layer and another end electrically connected to the interconnect layer.
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