CN113629059B

CN113629059B - Manufacturing method of 3D memory device and 3D memory device

Info

Publication number: CN113629059B
Application number: CN202110559965.4A
Authority: CN
Inventors: 李磊; 蒲浩; 李拓; 许宗珂
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2024-05-10
Anticipated expiration: 2041-05-21
Also published as: CN113629059A

Abstract

The application discloses a manufacturing method of a 3D memory device and the 3D memory device. The manufacturing method of the 3D memory device comprises the following steps: forming a laminated structure above the substrate; forming a plurality of channel pillars penetrating the stacked structure; and forming a plurality of dummy channel columns penetrating through the laminated structure, wherein the side wall of each dummy channel column is an oxide layer, and oxidizing the polysilicon layer by adopting a wet oxidation process to form the oxide layer. The manufacturing method is beneficial to reducing the production cost and improving the yield and the reliability of the 3D memory device.

Description

Manufacturing method of 3D memory device and 3D memory device

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a method for manufacturing a 3D memory device and a 3D memory device.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as nonvolatile flash memories. Two main non-volatile flash technologies employ NAND and NOR architectures, respectively. The read speed in the NAND memory device is slightly slower, but the write speed is fast, the erase operation is simple, and smaller memory cells can be realized, thereby achieving higher memory density, as compared to the NOR memory device. Therefore, 3D memory devices employing NAND structures have found wide application.

In a 3D memory device of a NAND structure, gate conductors of a selection transistor and a memory transistor are provided in a stacked structure, and a memory cell string having a memory function is formed in a single channel group (SINGLE CHANNEL formation) structure. With the increasing number of memory cell layers stacked in the vertical direction in 3D memory devices, a dummy channel pillar (Dummy Channel Hole) is required to mechanically support the stacked structure to prevent the stacked structure from being deformed, however, the process of manufacturing the dummy channel pillar in the prior art still has the problems of uncontrolled size and excessive cost.

Further improvements in 3D memory device manufacturing methods and 3D memory devices are desired to improve the yield and reliability of 3D memory devices.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a method for manufacturing a 3D memory device and a 3D memory device, so that the size of a dummy channel pillar is more easily controlled and the production cost is reduced.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a laminated structure above the substrate; forming a plurality of channel pillars through the stacked structure; and forming a plurality of dummy channel columns penetrating through the laminated structure, wherein at least one part of each dummy channel column is an oxide layer, and oxidizing the polysilicon layer by adopting a wet oxidation process to form the oxide layer.

Optionally, the method for forming the plurality of false channel pillars includes: forming a plurality of openings through the laminate structure; forming the polysilicon layer within the plurality of openings; and oxidizing the polysilicon layer to form the oxide layer, thereby forming at least a portion of each of the dummy channel columns.

Optionally, the polysilicon layer is uniformly formed on the exposed surface of the opening, so that the oxide layer forms sidewalls of the plurality of dummy channel columns.

Optionally, after oxidizing the polysilicon layer to form the oxide layer, the method further includes: and filling the open holes to form oxide covering the oxide layer.

Optionally, a corrosion inhibitor control enhancement method (Inhibitor Controlled Enhanced, abbreviated as ICE) growth method is adopted to form the oxide.

Optionally, the thickness of the side wall of the false channel column is not less than 10 nanometers.

According to another aspect of the present invention, there is provided a 3D memory device including: a substrate; a stacked structure over the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars extending through the stacked structure; and a plurality of dummy channel columns penetrating through the laminated structure, wherein at least a part of each dummy channel column is an oxide layer, and the oxide layer is formed by oxidizing the polysilicon layer by a wet oxidation process.

Optionally, the oxide layer forms sidewalls of the plurality of dummy channel pillars.

Optionally, the false channel column further includes: and an oxide covering the oxide layer.

According to the manufacturing method of the 3D memory device and the 3D memory device, the wet oxidation process is adopted to oxidize the polycrystalline silicon layer, the sacrificial layer and the interlayer insulating layer in the insulating laminated structure cannot be oxidized in the process of the wet oxidation process, the obtained oxide layer has the thickness consistent with or smaller than that of the polycrystalline silicon layer, the thickness cannot be expanded in the process of the polycrystalline silicon layer, therefore, the window from the false channel column to the grid line cannot be reduced, and the yield and reliability of the 3D memory device are improved. Furthermore, the polysilicon layer is oxidized by adopting a wet oxidation process to form an oxide layer in the false channel column, thereby being beneficial to reducing the production cost.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows an electron micrograph according to a conventional 3D memory device.

Fig. 2a and 2b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.

Fig. 3 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 4a to 4e show cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the invention.

Fig. 5a to 5c respectively show height variation diagrams of a conventional 3D memory device.

Fig. 6a to 6c respectively show height variation diagrams of a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.

In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

In a 3D memory device of a NAND structure, gate conductors of a selection transistor and a memory transistor are provided in a stacked structure, and a memory cell string having a memory function is formed in a single channel group (SINGLE CHANNEL formation) structure. With the increasing number of memory cell layers stacked in the vertical direction in 3D memory devices, a dummy channel pillar (Dummy Channel Hole) is required to mechanically support the stacked structure to prevent the stacked structure from being deformed, however, the conventional process for manufacturing the dummy channel pillar still has the problems of uncontrolled size and excessive cost. For example, conventional processes for fabricating dummy channel pillars typically employ a remote plasma oxidation (Remote Plasma Oxidation, RPO) process to oxidize silicon nitride to obtain a dense silicon oxide material, fig. 1 shows an electron micrograph of a 3D memory device according to conventional processes, which, as shown in fig. 1, increases the risk of Critical Dimensions (CD) of the dummy channel pillars, thereby shrinking the windows of the dummy channel pillars to Gate Lines (GL); further, the process is costly, and the dummy channel columns are only supporting structures and do not serve as storage, so that they do not correspond to the cost spent.

The inventors of the present application have noted the above-described problem affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 2a and 2b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 2a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory transistors M1 to M4 are connected to the corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in fig. 2b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a stacked structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillars 110 penetrate the stacked structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. A blocking dielectric layer 114 is interposed between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for controlling the select and memory transistors, and the doping type of the channel layer 111 is the same as the type of the select and memory transistors. For example, for an N-type select transistor and a memory transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2 and the memory transistors M1 to M4 use a common channel layer 111 and blocking dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the epitaxial layers and the blocking dielectric layers of the first and second selection transistors Q1 and Q2 and the epitaxial layers and the blocking dielectric layers of the memory transistors M1 to M4 may be formed separately from each other.

In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, the ground selection line GSL is biased to about zero volt while the source line SL is grounded, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 3 shows a perspective view of a 3D memory device. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 3.

The 3D memory device 200 shown in this embodiment includes 4*4 total 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4x 4 total 64 memory cells. It is to be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example 1024, and the number of memory cells in each memory cell string may be any number, for example 32 or 64.

In the 3D memory device 200, the memory cell strings include respective channel pillars 110, and common gate conductors 121, 122, and 123, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a stacked structure 120. The interlayer insulating layer is not shown in the drawing.

The internal structure of the channel pillar 110 is shown in fig. 2b and will not be described in detail herein. The channel pillars 110 penetrate the stacked structure 120 and are arranged in an array, wherein a first end of the plurality of channel pillars 110 in the same column is commonly connected to the same bit line (i.e., one of the bit lines BL1 to BL 4), a second end is commonly connected to the substrate 101, and a second end forms a common source connection through the substrate 100.

The gate conductor 122 of the first select transistor Q1 is divided into different gate lines by a gate line slit (GATE LINE SLIT) 161. The gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 to SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are connected to the corresponding word lines, respectively. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 171, the gate lines of the same level reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive paths 133.

The gate conductors of the second selection transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 171, the gate lines reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other and then are connected to the same ground selection line GSL via the conductive paths 133.

Fig. 4a to 4e show cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the invention. The cross-sectional view is taken along line AA in fig. 3.

The method starts with a semiconductor structure in which an insulating stack structure has been formed on a semiconductor substrate 101, as shown in fig. 4 a.

The semiconductor structure includes a semiconductor substrate 101 and an insulating stack structure thereon. The insulating stack structure includes a plurality of interlayer insulating layers 151 and a plurality of sacrificial layers 152 alternately stacked. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride.

To form a conductive path from the gate conductor to the word line, a plurality of sacrificial layers 152 are, for example, patterned in a step-like manner, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to the overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, a dielectric layer will be used to cover the insulating stack. The sacrificial layer 152 will be replaced with a gate conductor that is further connected to a word line, as described below.

In order to facilitate a programming operation for memory cells in the 3D memory device, a plurality of well regions and CMOS circuits (not shown) for driving the selection transistors and the memory transistors are formed in the semiconductor substrate 101. The plurality of well regions include, for example, a deep N-well 102, a high voltage P-well 103 located in the deep N-well 102, a high voltage N-well 105 adjacent to the high voltage P-well 103, a p+ doped region 104 located in the high voltage P-well 103, and an n+ doped region 106 located in the high voltage N-well 105. In this embodiment, the high voltage P-well 103 serves as a common source region of the channel pillar, the high voltage N-well 105 is used to precharge the common source region, and the p+ doped region 104 and the n+ doped region 106 serve as contact regions, respectively, to reduce contact resistance. The high voltage P-well 103 serves as a common source region for a plurality of channel pillars and is thus located below the insulating stack structure.

Further, a plurality of openings 141 are formed through the insulating stack structure as shown in fig. 4 b. The openings 141 are located, for example, in non-storage areas of the insulating stack. In this step, for example, using the substrate 101 as a stop layer, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation is employed, and etching is stopped near the surface of the substrate 101 by controlling etching time.

Further, a polysilicon layer is formed within the plurality of openings 141 and oxidized to form an oxide layer 142, the oxide layer 142 forming at least a portion of the dummy channel pillars 140, as shown in fig. 4 c.

In this step, a polysilicon layer is formed, for example, using atomic layer deposition (Atomic Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD), preferably using plasma chemical vapor deposition.

In this embodiment, the wet oxidation process is used to oxidize the polysilicon layer, and the wet oxidation process will not oxidize the sacrificial layer 152 and the interlayer insulating layer 151 in the insulating stack structure during the process, and the obtained oxide layer 142 has a thickness consistent with or smaller than that of the polysilicon layer, so that there is no risk of enlarging the window, and the window from the dummy channel pillar 140 to the gate line is not reduced, which is beneficial to improving the yield and reliability of the 3D memory device. Further, the polysilicon layer is oxidized by a wet oxidation process to form the oxide layer 142, thereby being beneficial to reducing the production cost.

Alternatively, the polysilicon layer is uniformly formed on the exposed surface of the opening 141, so that the oxide layer 142 forms sidewalls of the plurality of dummy channel pillars, and the thickness of the sidewalls of the dummy channel pillars 140 is, for example, not less than 10 nm, to provide sufficient supporting force. Optionally, each dummy channel column 140 further includes an oxide 143, such as silicon oxide, overlying the surface of oxide layer 142. Optionally, a corrosion inhibitor control enhancement method (Inhibitor Controlled Enhanced, abbreviated as ICE) growth method is adopted to form the oxide.

In the final 3D memory device, the dummy channel pillars 140 pass through at least a portion of the gate conductors in the stacked structure, and the dummy channel pillars 140 are not connected to the bit lines, thereby providing only mechanical support, and are not used to form select transistors and memory transistors. Thus, the dummy channel columns 140 do not form an effective memory cell.

Further, in the storage region of the insulating stack structure, channel pillars 110 penetrating the insulating stack structure are formed, and a plurality of conductive channels are formed in the dielectric layer, as shown in fig. 4 d.

The lower portion of the channel pillar 110 includes a semiconductor layer 116. Further, the channel pillar 110 (see fig. 2 b) includes a channel layer 111 extending from an upper portion thereof to the semiconductor layer 116. As shown, at the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 sequentially stacked on the channel layer 111, and at both ends of the channel pillar 110, the channel pillar 110 includes a blocking dielectric layer 114 stacked on the channel layer 111 or the semiconductor layer 116. The lower end of the channel pillar 110 is in contact with the high voltage P-well 103 in the semiconductor substrate 101. In the final 3D memory device, the upper ends of the channel pillars 110 are connected to bit lines, thereby forming an effective memory cell.

In this embodiment, an insulating layer and a metal layer are formed in the sidewalls and the core portion of the plurality of contact holes in the 3D memory device, respectively, and then a conductive path is formed. The conductive path includes a conductive post as a core and an insulating layer as an isolation layer for separating the conductive post from surrounding conductive material. The conductive pillars in the conductive channels are composed of, for example, ti/TiN or W, and the insulating layer is composed of, for example, silicon oxide. The plurality of conductive channels includes, for example, conductive channels SL1, HV1. Conductive vias SL1 and HV1 are in contact with p+ doped region 104 and n+ doped region 106, respectively, in the substrate, thereby providing electrical connection between the common source region and the high voltage N-well in the substrate and external circuitry.

Further, a gate line slit 171 (see fig. 3) is formed in the insulating stack structure, the sacrificial layer 152 in the stack structure is insulated via the gate line slit 171 to form a cavity, and the cavity is filled with a metal layer to form the gate conductor 120, as shown in fig. 4 e.

In forming the gate line slits 171, anisotropic etching, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation may be employed. For example, by controlling the etching time, etching is stopped near the surface of the semiconductor substrate 101.

In this embodiment, the gate line slit 171 divides the gate conductor into a plurality of gate lines. For this, the gate line slit 171 penetrates the insulating stack structure.

In forming the cavity, the sacrificial layer 152 in the insulating stack structure is removed by isotropic etching using the gate line slit 171 as an etchant passage to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. An etching gas is used as an etchant in a gas phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the interlayer insulating layer and the sacrificial layer in the insulating stack structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C ₄F₈、C₄F₆、CH₂F₂ and O ₂ may be used in vapor etching. In the etching step, the gate line slit 171 is filled with an etchant. The end of the sacrificial layer 152 in the insulating stack structure is exposed to the opening of the gate line slit 171, and thus, the sacrificial layer is contacted to the etchant. The etchant gradually etches the sacrificial layer from the opening of the gate line slit 171 toward the inside of the insulating stack structure. Due to the selectivity of the etchant, the etching removes the sacrificial layer 152 with respect to the interlayer insulating layer in the insulating stack structure.

In forming the gate conductor, atomic Layer Deposition (ALD) is used to fill the gate line slits 171 and the cavities with metal layers using the gate line slits 171 as a deposition path.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF ₆, and the reducing gas used is, for example, silane SiH ₄ or diborane B ₂H₆. In the atomic layer deposition step, a deposition process is performed by using chemisorption of a reaction product of tungsten hexafluoride WF ₆ and silane SiH ₄ to obtain a tungsten material.

Fig. 5a to 5c respectively show height variation diagrams of a conventional 3D memory device. Fig. 6a to 6c respectively show height variation diagrams of a 3D memory device according to an embodiment of the present invention. The abscissa of each height change graph represents the position coordinate of the 3D storage device in the horizontal direction, and the ordinate represents the position coordinate of the 3D storage device in the height direction.

As shown in fig. 5a, the height of the highest die (die) and the height of the lowest die are-2080 a and-2590 a, respectively; as shown in fig. 5b, the highest plateau region and the lowest plateau region of the 3D memory device are-1717 a and-1810 a, respectively; as shown in fig. 5c, the word line size of the formed 3D memory device ranges from-3200 a to-2130 a.

As an example, the sidewall thickness of the dummy channel pillar provided by the present application is 12nm, and as shown in fig. 6a, the height of the highest die (die) and the height of the lowest die are-1112 a and-1200 a, respectively; as shown in fig. 6b, the highest plateau region and the lowest plateau region of the 3D memory device are-1123 a and-1569 a, respectively; as shown in fig. 6c, the word line size of the 3D memory device is formed in the range-1371 a to-1600 a.

Therefore, the fake channel pillar in the 3D memory device provided by the embodiment of the application can provide mechanical support with enough strength to meet the actual demands.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A method of manufacturing a 3D memory device, comprising:

Forming a laminated structure above the substrate;

forming a plurality of channel pillars through the stacked structure; and

Forming a plurality of openings through the laminate structure;

forming a polysilicon layer within the plurality of openings; and

Oxidizing the polysilicon layer by adopting a wet oxidation process to form an oxide layer;

filling the plurality of openings to form a plurality of dummy channel pillars through the stacked structure, the oxide layer forming at least a portion of the dummy channel pillars,

Wherein the oxide layer has a thickness consistent with or less than the thickness of the polysilicon layer.

2. The method of manufacturing of claim 1, wherein the polysilicon layer is formed on an exposed surface of the opening.

3. The method of manufacturing of claim 1, wherein filling the opening comprises: an oxide is formed overlying the oxide layer.

4. A method of manufacturing according to claim 3, wherein the oxide is formed using a corrosion inhibitor control enhancement ICE growth process.

5. The method of manufacturing according to any one of claims 2 to 4, wherein the sidewall thickness of the dummy channel column is not less than 10 nm.

6. A 3D memory device, comprising:

A substrate;

A stacked structure over the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

a plurality of channel pillars extending through the stacked structure; and

A plurality of dummy channel pillars extending through the stacked structure, at least a portion of each of the dummy channel pillars being an oxide layer,

The oxide layer is formed by oxidizing the polysilicon layer by a wet oxidation process, wherein the oxide layer has a thickness consistent with or smaller than that of the polysilicon layer.

7. The 3D memory device of claim 6, wherein the oxide layer forms sidewalls of the plurality of dummy channel pillars.

8. The 3D memory device of claim 7, wherein the dummy channel pillar further comprises: and an oxide covering the oxide layer.

9. The 3D memory device of claim 7 or 8, wherein the sidewall thickness of the dummy channel pillar is not less than 10 nanometers.