CN109346471B

CN109346471B - Method for forming three-dimensional memory and three-dimensional memory

Info

Publication number: CN109346471B
Application number: CN201811344515.8A
Authority: CN
Inventors: 宋玉洁; 夏志良; 华文宇; 刘藩东
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-11-13
Filing date: 2018-11-13
Publication date: 2020-06-23
Anticipated expiration: 2038-11-13
Also published as: CN109346471A

Abstract

The invention relates to a method for forming a three-dimensional memory and the three-dimensional memory. The three-dimensional memory includes an array memory region having at least one block memory region. The block storage area includes: having a substrate and a stack layer on the substrate, the stack layer including gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate; the first grid line gap and the second grid line gap are arranged at intervals; one or more third gate line gaps between the first gate line gaps and the second gate line gaps; a through array barrier structure located between adjacent gate line gaps; and a dummy channel structure column located on at least one side of the through array barrier structure along the extension direction of the gate line gap; wherein at least one of the one or more third gate line gaps is disconnected at locations corresponding to the columns of dummy channel structures.

Description

Method for forming three-dimensional memory and three-dimensional memory

Technical Field

The present invention relates generally to semiconductor manufacturing methods, and more particularly to a method of forming a three-dimensional memory and a three-dimensional memory.

Background

To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional (3D) structure, which increases integration density by arranging memory cells three-dimensionally over a substrate.

In a three-dimensional memory device such as a 3D NAND flash memory, the array memory region may include one or more block memory regions (blocks). The block storage region further may include a plurality of finger storage regions (fingers) separated by Gate Line Slots (GLS). A Through Array Barrier (TAB) and a Through Array Contact (TAC) therein are disposed in the finger storage region. As the storage density in the array storage region increases, the pitch of the respective patterns therein needs to be further reduced. For example, the spacing reserved for the gate line gap and the through array barrier structure needs to be reduced, but this may result in bridging (bridge) and even contact of the material in the gate line gap with the through array barrier structure.

Disclosure of Invention

The invention provides a method for forming a three-dimensional memory and the three-dimensional memory, which can enlarge the space between a grid line gap and a through array barrier structure under the condition of not increasing the size of an array storage area.

According to one aspect of the present invention, a three-dimensional memory includes an array memory region having at least one block memory region. The block storage area includes: having a substrate and a stack layer on the substrate, the stack layer including gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate; the first grid line gap and the second grid line gap are arranged at intervals; one or more third gate line gaps between the first and second gate line gaps; a through array barrier structure located between adjacent gate line gaps; and a dummy channel structure column located on at least one side of the through array barrier structure along the extension direction of the gate line gap; wherein at least one of the one or more third gate line gaps is open at locations corresponding to the columns of dummy channel structures.

In an embodiment of the invention, the at least one notch of the third gate line gap break is aligned with the dummy channel structure row in the arrangement direction of the dummy channel structure row.

In an embodiment of the invention, the at least one third gate line gap is disconnected at a position corresponding to each dummy channel structure column.

In an embodiment of the invention, a cross-section of an end portion where the at least one third gate line gap is disconnected in a direction parallel to the substrate is circular or rectangular.

In an embodiment of the invention, the three-dimensional memory further includes a through-array contact located within the through-array barrier structure.

In an embodiment of the invention, the three-dimensional memory further includes a channel hole array located between the first gate line gap and the second gate line gap, and the channel hole array is divided into a plurality of finger storage regions by the one or more third gate line gaps.

In an embodiment of the invention, the through array barrier structure is provided with the channel hole array on at least one side of the extending direction of the gate line gap, and the dummy channel structure column located between the channel hole array and the through array barrier structure.

In an embodiment of the invention, the three-dimensional memory further includes an insulating layer and an array common source located in the first gate line gap and the second gate line gap.

Another aspect of the present invention provides a method of forming a three-dimensional memory, comprising the steps of: providing a semiconductor structure having a substrate and alternating stacked layers on the substrate; forming a column of dummy channel structures through the alternating stack of layers; forming a through array barrier structure on the semiconductor structure, wherein the dummy channel structure column is positioned on at least one side of the through array barrier structure; and forming first and second gate line gaps arranged at intervals on the semiconductor structure and one or more third gate line gaps between the first and second gate line gaps, wherein the through array barrier structures are positioned between adjacent gate line gaps, and at least one of the one or more third gate line gaps is disconnected at a position corresponding to the virtual channel structure column.

In an embodiment of the invention, the at least one third gate line gap is aligned with the dummy channel structure column in an arrangement direction of the dummy channel structure column.

In an embodiment of the invention, the method further includes forming a through-array contact located in the through-array barrier structure.

In an embodiment of the present invention, the method further includes forming a channel hole array on the semiconductor structure, where the channel hole array is located between the first gate line gap and the second gate line gap and is divided into a plurality of finger storage regions by the one or more third gate line gaps.

In an embodiment of the invention, the method further includes forming an insulating layer and an array common source in the first gate line gap and the second gate line gap.

In the three-dimensional memory and the forming method thereof, the grid line gap in the block memory is disconnected with the position adjacent to the virtual channel structure column, so that the end part of the disconnected position avoids the penetrating array barrier structure, and the bridging or contact problem caused by too close distance between the penetrating array barrier structure and the grid line gap is remarkably relieved. Since the dummy channel structure columns are spaced apart from each other at a large distance in a direction perpendicular to the extending direction of the gate line gap, the end of the gate line gap is sufficiently distant from the dummy channel structure columns. The invention makes the layout of the three-dimensional memory more reasonable, and is beneficial to reducing the size of the three-dimensional memory in the direction vertical to the extending direction of the grid line gap. In addition, the grid line gaps can be disconnected at a plurality of positions, so that the grids in the storage regions are interconnected through the conductors at the plurality of disconnected positions, and the parallel structure can reduce the interconnected resistance value, thereby improving the transmission delay of the three-dimensional memory.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a top view of a three-dimensional memory.

Fig. 2 is a top view of a three-dimensional memory device according to an embodiment of the present invention.

FIG. 3 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the invention.

Fig. 4A-4D are schematic diagrams of an exemplary process for forming a three-dimensional memory, in accordance with an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

FIG. 1 is a top view of a three-dimensional memory. Referring to FIG. 1, a three-dimensional memory 100 may have an array memory region, which may include one or more block memory regions 110 as shown in FIG. 1. The block storage region 110 has a substrate in a vertical direction and a stack layer (not shown) on the substrate, and the stack layer may include gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate. Each block storage area may in turn be divided into a plurality (3 shown) of finger storage areas 120. The block storage area 110 may be defined by the

gate slots

101 and 102 arranged at intervals, and the block storage area 110 is divided into 3 finger storage areas 120 by the gate slots 103. Unlike

gate gaps

101 and 102, gate gap 103 is open at gap G, thereby allowing the gate layers of each finger storage region 120 to be conductive to each other. Each finger storage area 120 has an array of channel holes 122 formed therein, a through array barrier structure (TAB)124, and a Through Array Contact (TAC) 126. Here, the spacing between the TAB 124 and the gate line gap 103 is limited by the size of the three-dimensional memory 100 itself. As can be seen in particular in fig. 1, the two end portions 103a of the gate gap 103 at the gap G are typically circular in cross-section. The end 103a is thus closer to the TAB 124. The closer spacing tends to cause the material in the gate gap 103 to bridge or even contact the TAB 124.

Embodiments of the present invention describe three-dimensional memories and methods of fabricating the same that allow for increased spacing between gate line gaps and through array barrier structures without increasing the size of the array storage area.

The three-dimensional memory may include an array region (array) that may include a core region (core) and word line connection regions. The core area is an area including memory cells. The word line connection region is a region including the word line connection circuit. The word line connection regions are typically a staircase (SS) structure. It will be understood that this is not a limitation of the invention. Other structures, such as a planar structure, may be used for the word line connection regions. The array region may have a substrate and stacked layers, as viewed in a vertical direction. Fig. 2 is a top view of a three-dimensional memory device according to an embodiment of the present invention. To avoid obscuring the focus of the present invention, only the core area of the three-dimensional memory 200 containing 1 array memory is shown in FIG. 2. The three-dimensional memory 200 may have an array memory region that may include one or more block memory regions 210 as shown in fig. 2. The block storage region 210 has a substrate in a vertical direction and a stack layer (not shown) on the substrate, and the stack layer may include gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate. Each block storage area 210 may in turn be divided into a plurality (3 shown) of finger storage areas 220. The block storage area 210 may be defined by the first gate line gap 201 and the second gate line gap 202 which are arranged at intervals, and the block storage area 210 is further divided into 3 finger storage areas 220 by 2 third gate line gaps 203. In the present embodiment, each finger storage area 220 has a TAB 224 located between adjacent gate gaps. For example, TAB 224 is respectively provided between the first gate line gap 201 and the upper third gate line gap 203, between 2 third gate line gaps 203, and between the lower third gate line gap 203 and the second gate line gap 202. On both sides of each TAB 224 along the gate gap extending direction (X direction in the drawing), dummy

channel structure columns

223a and 223b are provided, respectively. The dummy

channel structure columns

223a and 223b include a plurality of dummy channel structures arranged in a direction (Y direction in the drawing) of the extending direction of the gate slits. Here, the dummy channel structure plays a supporting role. It is understood that the dummy channel structure columns are not limited to the distribution shown in fig. 2, and may be distributed in other ways. For example, the dummy channel structure columns may be more or less in the X direction.

In this embodiment, the third gate line gap 203 is broken at positions corresponding to the dummy

channel structure columns

223a and 223b, and is distributed to form a pair of end portions 203a and another pair of end portions 203b with gaps G1 and G2 therebetween, respectively. In one example, the cut (HCut) of the third gate line gap 203 is aligned with the dummy channel structure column 203a in the arrangement direction (Y direction in the drawing) of the dummy channel structure column so as to avoid the TAB 224. In the embodiment of the present application, the gap of the third gate line gap 203 in the X direction may be varied, for example, the third gate line gap 203 is disconnected at a position corresponding to each of the dummy channel structure columns (203a, 203b, and others), and for example, the third gate line gap 203 is disconnected at a position corresponding to a part of the dummy channel structure column (203 a). The number of the gaps of each third gate line gap 203 and/or the positions of the breaks in the X direction may be the same or different. Further, some or all of the notch positions where there may be some of the third gate line gaps 203 are not located at the dummy

channel structure columns

223a and 223 b.

In the present embodiment, the third gate line gap 203 is disconnected from the position adjacent to the dummy

channel structure columns

223a and 223b, so that the

end portions

203a and 203b of the disconnected position avoid the TAB 224, thereby significantly alleviating the problem of bridging or contact between the TAB 224 and the third gate line gap 203 due to too close distance. The embodiment enables the layout of the three-dimensional memory to be more reasonable, and is beneficial to reducing the size in the Y direction. In addition, since the gate line gaps 203 of the present embodiment can be disconnected at a plurality of positions, so that the gates of the finger storage regions 220 are interconnected through a plurality of conductors at the disconnected positions, the parallel structure can reduce the resistance value of the interconnection, thereby improving the transmission delay of the three-dimensional memory.

Further details of the present embodiment are described below with continued reference to fig. 2. It is understood that the present application may be practiced without relying on the details described below. As shown in fig. 2, each finger storage region 220 has therein an array formed of a number of channel holes 222 perpendicular to the substrate. These channel holes 222 have structures such as a memory layer, a channel layer therein, and a gate layer on the side of the channel holes, a source on the bottom of the channel holes 222, and a drain on the top constitute a memory cell string. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer disposed radially outward and inward of the channel hole. Instead, the memory layer may be a floating gate structure disposed between the channel hole and the gate layer. The dummy channel structure may be similar to the structure within the channel hole, with the difference that the dummy channel structure is not drawn out of the contact. The dummy channel structure and the structure in the channel hole may be different, for example, the dummy channel structure is only filled with the insulating material.

In addition, TAC 226 is provided inside the TAB 224. The TAC 226 is a connection electrically connecting the memory array to peripheral circuitry. The number of contacts in the TAC 226 may be as desired.

With continued reference to fig. 2, the cross-section of both end portions 203a of the respective third gate line gaps 203 at the TAB 224 in the extending direction of the three-dimensional memory is typically circular, which is larger than the end dimension of a rectangle. Even so, the spacing D in the X direction provided in this embodiment ensures that the end 203a and the TAB 224 are not easily bridged or contacted. In other embodiments, the cross-section of the end 203a can be other shapes, such as rectangular.

In some embodiments, the spacing D1 of the dummy channel structure column in the Y direction is larger than the spacing D2 of the TAB 224 in the Y direction, so the end (e.g., 203a) of the third gate line gap 203 is far enough from the dummy channel structure column (e.g., 223a) to further reduce the risk of electrical leakage due to bridging or contact.

An Array Common Source (ACS) may be disposed in the gate slots 201-203 to provide a Common Source for the memory Array. An insulating layer can be arranged between the array common source and the side wall of the grid line gap.

In the present embodiment, the substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), SiGe, Si: C, or the like, although this is not a limitation. Some doped wells, such as N-wells or P-wells, may be provided on the substrate as desired. The material of the gate layer is, for example, a metal (e.g., tungsten). The material of the dielectric layer is, for example, silicon oxide. The material of the dielectric layer is not limited to this, and may be other insulating materials.

In an embodiment of the present invention, an exemplary material of the blocking layer and the tunneling layer is silicon oxide, silicon oxynitride, or a mixture thereof, and an exemplary material of the charge trapping layer is silicon nitride or a multilayer structure of silicon nitride and silicon oxynitride. The blocking layer, the charge trapping layer, and the tunneling layer may be formed, for example, in a multilayer structure having silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO); an exemplary material for the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si: C, SiGe: C, SiGe: H, and other semiconductor materials.

FIG. 3 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the invention. Fig. 4A-4C are schematic diagrams of an exemplary process for forming a three-dimensional memory according to an embodiment of the invention, wherein fig. 4A is a cross-sectional view and fig. 4B-4C are top views. The method of forming the three-dimensional memory of the present embodiment is described below with reference to fig. 3 to 4C.

In step 302, a semiconductor structure is provided.

The semiconductor structure is to be used in a subsequent process to ultimately form at least a portion of a three-dimensional memory device. The semiconductor structure may include a core region. The core region may have a substrate, gate layers and dielectric layers or dummy gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate on the substrate, as viewed in a vertical direction.

In the cross-sectional view of the semiconductor structure illustrated in fig. 4A, the semiconductor structure 400a may include a substrate 401 and a stack of layers 410 on the substrate. The stacked layer may be a stack in which the first material layers 411 and the second material layers 412 are alternately stacked. The first material layer may be a gate layer or a dummy gate layer. The second material layer is a dielectric layer.

In an embodiment of the invention, the material of the substrate is, for example, silicon. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods may be used to alternately deposit silicon nitride and silicon oxide on the substrate in sequence to form the stack.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired.

In step 304, columns of dummy channel structures are formed through the alternating stack of layers.

In this step, dummy

channel structure columns

223a, 223b composed of some dummy channel structures are formed on the semiconductor structure 400 b.

Typically, in this step, a channel hole array composed of a plurality of channel holes 222 is also formed on the semiconductor structure 400 b.

In some embodiments, the dummy channel structure and the structures in the channel hole may be fabricated in the same set of processes. In other embodiments, the dummy trench structure and the structure in the trench hole can be fabricated in different processes.

At step 306, a through array barrier structure is formed on the semiconductor structure.

In this step, a through-array barrier structure (TAB) penetrating the stacked layers in a direction perpendicular to the substrate may be formed in the semiconductor structure. Here, the dummy channel structure column is located on at least one side of the array blocking structure. Typically, the column of dummy channel structures is adjacent to the through array barrier structures in the X-direction.

The Trench (Trench) may be formed by photolithography and etching, and then filled with an insulating material as TAB.

In the top view of the semiconductor structure illustrated in fig. 4C, the TAB 224 is formed on the semiconductor structure 400C through the stack of layers 410 (shown with reference to fig. 4A) perpendicular to the substrate 401. TAB 224 has dummy

channel structure columns

223a and 223b on either side. In other words, each TAB 224 is located between two dummy

channel structure columns

223a and 223 b.

In step 308, a first gate line gap and a second gate line gap are formed on the semiconductor structure at intervals, and one or more third gate line gaps are formed between the first gate line gap and the second gate line gap.

In this step, various gate line gaps may be formed in the semiconductor structure through the stacked layers in a direction perpendicular to the substrate, thereby distinguishing the respective block storage regions and the finger storage region. At this time, TAB is located between the spaced gate gaps. At least one of the third gate line gaps is disconnected at a position corresponding to the dummy channel structure column, thereby avoiding the TAB.

In the top view of the semiconductor structure illustrated in fig. 4D, the first gate line gap 201 and the second gate line gap 202 are formed on the semiconductor structure 400D through the stacked layers 410 (shown with reference to fig. 4A) perpendicular to the substrate 401, and 2 third gate line gaps 203 are formed together between the first gate line gap 201 and the second gate line gap 202. The third gate line gap 203 is broken at positions corresponding to the dummy

channel structure columns

223a and 223b, where the broken positions form a pair of end portions 203a and another pair of end portions 203b, respectively. The

end portions

203a, 203b have a circular or rectangular cross section (plane shown in the figure) in a direction parallel to the substrate.

After the gate line gap is formed, a block storage region 210 is defined between the first gate line gap 201 and the second gate line gap 202. The array of channel holes between the first gate line gap 201 and the second gate line gap 202 is divided into a plurality of finger storage areas 220 by the respective third gate line gaps 203.

After the gate line gap is formed, the method further comprises the step of forming an insulating layer and an Array Common Source (ACS) in the gate line gap 201-203. The array common source is positioned in the insulating layer.

After step 308, a through array contact 226 within the TAB 224 may also be formed, resulting in the structure shown in FIG. 2.

Other details of the three-dimensional memory device, such as word line connection regions, peripheral interconnects, etc., are not material to the present invention and will not be described further herein.

In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D NAND flash memory.

This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A three-dimensional memory comprising an array storage area having at least one block storage area, the block storage area comprising:

having a substrate and a stack layer on the substrate, the stack layer including gate layers and dielectric layers alternately stacked in a direction perpendicular to the substrate;

the first grid line gap and the second grid line gap are arranged at intervals;

one or more third gate line gaps between the first and second gate line gaps;

a through array barrier structure located between adjacent gate line gaps; and

the dummy channel structure column is positioned on at least one outward side of the run-through array barrier structure along the extension direction of the grid line gap;

wherein at least one of the one or more third gate line gaps is open at locations corresponding to the columns of dummy channel structures.

2. The three-dimensional memory according to claim 1, wherein the at least one third gate line gap break notch is aligned with the dummy channel structure column in an arrangement direction of the dummy channel structure column.

3. The three-dimensional memory of claim 1, wherein the at least one third gate line gap is open at locations corresponding to each column of dummy channel structures.

4. The three-dimensional memory according to claim 1, wherein a cross-section of an end portion where the at least one third gate line gap is disconnected in a direction parallel to the substrate is circular or rectangular.

5. The three-dimensional memory of claim 1, further comprising a through array contact within the through array barrier structure.

6. The three-dimensional memory of claim 1, further comprising an array of channel holes between the first gate line gap and the second gate line gap, the array of channel holes divided into a plurality of finger storage regions by the one or more third gate line gaps.

7. The three-dimensional memory of claim 6, wherein the through array barrier structures are provided with the array of channel holes on at least one side of the direction of extension of the gate line apertures, and the column of dummy channel structures between the array of channel holes and through array barrier structures.

8. The three-dimensional memory of claim 1, further comprising an insulating layer and an array common source located within the first gate line gap and the second gate line gap.

9. A method of forming a three-dimensional memory, comprising the steps of:

providing a semiconductor structure having a substrate and alternating stacked layers on the substrate;

forming a column of dummy channel structures through the alternating stack of layers;

forming a through array barrier structure on the semiconductor structure, wherein the dummy channel structure column is positioned on at least one side of the through array barrier structure, which is outward along the extension direction of the grid line gap; and

and forming a first grid line gap and a second grid line gap which are arranged at intervals on the semiconductor structure, and one or more third grid line gaps which are arranged between the first grid line gap and the second grid line gap, wherein the penetrating array blocking structures are arranged between adjacent grid line gaps, and at least one third grid line gap in the one or more third grid line gaps is disconnected at the position corresponding to the virtual channel structure column.

10. The method of claim 9, wherein the at least one third gate line gap is aligned with the column of dummy channel structures in an alignment direction of the column of dummy channel structures.

11. The method of claim 9, wherein the at least one third gate line gap is open at locations corresponding to each column of dummy channel structures.

12. The method of claim 9, wherein a cross-section of an end of the at least one third grid gap discontinuity in a direction parallel to the substrate is circular or rectangular.

13. The method of claim 9, further comprising forming a through array contact within the through array barrier structure.

14. The method of claim 9, further comprising forming an array of channel holes on the semiconductor structure, the array of channel holes being located between the first and second gate line gaps and divided into a plurality of finger storage regions by the one or more third gate line gaps.

15. The method of claim 9, further comprising forming an insulating layer and an array common source within the first and second gate line gaps.