CN109346471A - Form the method and three-dimensional storage of three-dimensional storage - Google Patents
Form the method and three-dimensional storage of three-dimensional storage Download PDFInfo
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- CN109346471A CN109346471A CN201811344515.8A CN201811344515A CN109346471A CN 109346471 A CN109346471 A CN 109346471A CN 201811344515 A CN201811344515 A CN 201811344515A CN 109346471 A CN109346471 A CN 109346471A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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Abstract
The present invention relates to a kind of methods and three-dimensional storage for forming three-dimensional storage.Three-dimensional storage includes array memory block, and array memory block has at least one block memory block.Block memory block includes: the stack layer with substrate and on substrate, and stack layer includes along the alternately stacked grid layer in direction and dielectric layer with substrate transverse；Spaced first grid line gap and second gate line gap；One or more third grid line gaps between first grid line gap and second gate line gap；Run through array barrier structure between adjacent grid line gap；And it is arranged positioned at through array barrier structure along the virtual channel structure of at least side of grid line gap extending direction；Wherein, at least one third grid line gap in one or more third grid line gaps is corresponding to disconnection at virtual channel structure column.
Description
Technical field
The invention mainly relates to semiconductor making methods, are particularly to the formation of the method and three-dimensional storage of three-dimensional storage
Device.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional (3D) structure,
It improves integration density by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, array memory block may include one or more block memory blocks
(block).Block memory block further may include multiple finger memory blocks separated by grid line gap (Gate Line Slit, GLS)
(finger).It is equipped with through array barrier structure (Through Array Barrier, TAB) and is located in referring to memory block
Run through array contact portion (Through Array Contact, TAC) in it.With in array memory block, storage density is mentioned
Height, wherein the spacing needs of each pattern further reduce.Such as keep for grid line gap and between array barrier structure
Spacing needs to reduce, but this may cause the material in grid line gap and even connects with through array barrier structure bridge joint (bridge)
Touching.
Summary of the invention
The present invention provides a kind of method and three-dimensional storage for forming three-dimensional storage, can not increase array storage
Expand grid line gap and the spacing between array barrier structure in the case where area's size.
A kind of three-dimensional storage, including array memory block, the array memory block are provided according to an aspect of the present invention
With at least one block memory block.Described piece of memory block includes: the stack layer with substrate and on the substrate, the heap
Lamination includes along the alternately stacked grid layer in direction and dielectric layer with the substrate transverse；Spaced first grid line gap and
Second gate line gap；One or more third grid line gaps between the first grid line gap and second gate line gap；Positioned at adjacent
Grid line gap between run through array barrier structure；And it is located at the array barrier structure that runs through along grid line gap extending direction
At least side virtual channel structure column；Wherein, at least one third grid line in one or more of third grid line gaps
Gap is corresponding to disconnection at the virtual channel structure column.
In one embodiment of this invention, the notch and the virtual channel junction that at least one described third grid line gap disconnects
Structure is listed in the orientation of the virtual channel structure column and is aligned.
In one embodiment of this invention, at least one described third grid line gap is corresponding to each virtual channel structure column
Place disconnects.
In one embodiment of this invention, the end of at least one third grid line gap gap is flat with the substrate
The section in capable direction is round or rectangle.
In one embodiment of this invention, three-dimensional storage further includes positioned at the running through in array barrier structure
Array contact portion.
In one embodiment of this invention, three-dimensional storage further include positioned at the first grid line gap and second gate line gap it
Between channel hole array, the channel hole array is divided into multiple finger memory blocks by one or more of third grid line gaps.
In one embodiment of this invention, the array barrier structure that runs through is at least the one of the grid line gap extending direction
Side is provided with the channel hole array, and described virtual positioned at the channel hole array and between array barrier structure
Channel structure column.
In one embodiment of this invention, three-dimensional storage further includes being located at the first grid line gap and second grid line
Insulating layer and array common source in gap.
Another aspect of the present invention provides a kind of method for forming three-dimensional storage, comprising the following steps: provides semiconductor
Structure, the semiconductor structure have substrate and are alternately stacked layer on the substrate；It is formed through the alternately heap
The virtual channel structure of lamination arranges；It is formed on the semiconductor structure and runs through array barrier structure, the virtual channel structure
Column are located at at least side for running through array barrier structure；And spaced first is formed on the semiconductor structure
Grid line gap and second gate line gap and one or more third grid lines between the first grid line gap and second gate line gap
Gap, wherein it is described through array barrier structure between adjacent gate line gap, in one or more of third grid line gaps extremely
A few third grid line gap is corresponding to disconnection at the virtual channel structure column.
In one embodiment of this invention, at least one described third grid line gap and the virtual channel structure are listed in described
It is aligned in the orientation of virtual channel structure column.
In one embodiment of this invention, at least one described third grid line gap is corresponding to each virtual channel structure column
Place disconnects.
In one embodiment of this invention, the end of at least one third grid line gap gap is flat with the substrate
The section in capable direction is round or rectangle.
In one embodiment of this invention, the above method further includes being formed to be located at the passing through in array barrier structure
Wear array contact portion.
In one embodiment of this invention, the above method further includes forming channel hole array on the semiconductor structure,
The channel hole array is between the first grid line gap and second gate line gap and by one or more of third grid line gaps
It is divided into multiple finger memory blocks.
In one embodiment of this invention, the above method further includes in the first grid line gap and the second gate line gap
Form insulating layer and array common source.
In three-dimensional storage of the invention and forming method thereof, grid line gap in block storage in virtual channel structure
It arranges adjacent position to disconnect, so that the end of open position be made to avoid through array barrier structure, run through to significantly alleviate
Array barrier structure and grid line gap are because of bridge joint or contact problems caused by hypotelorism.Due to virtual channel structure be listed in it is vertical
It is directly larger in the spacing on the direction of grid line gap extending direction, therefore the end of grid line gap foot at a distance from virtual channel structure column
It is enough remote.The invention enables three-dimensional storage layout it is more reasonable, be conducive to reduce the direction perpendicular to grid line gap extending direction
On size.And since grid line gap of the invention can be disconnected in multiple positions, to make each grid for referring to storage section logical
The conductor interconnection of multiple gaps is crossed, this parallel-connection structure can reduce the resistance value of interconnection, so as to improve three-dimensional storage
Transmission delay.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is a kind of top view of three-dimensional storage.
Fig. 2 is the top view of three-dimensional storage part according to an embodiment of the invention.
Fig. 3 is the method flow diagram of the formation three-dimensional storage of one embodiment of the invention.
Fig. 4 A-4D is the schematic diagram in the example process of the formation three-dimensional storage of one embodiment of the invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
Fig. 1 is a kind of top view of three-dimensional storage.Refering to what is shown in Fig. 1, three-dimensional storage 100 can have array storage
Area may include one or more block memory blocks 110 as shown in Figure 1.Block memory block 110 in vertical direction have substrate and
Stack layer (not shown) on the substrate, stack layer may include along the alternately stacked grid layer in direction with substrate transverse
And dielectric layer.Each piece of memory block can be divided into multiple (showing 3 in figure) again and refer to memory block 120.Block memory block 110 can by
It is defined every the grid line gap 101 and 102 of setting, block memory block 110 is divided by grid line gap 103 for 3 finger memory blocks 120.Grid line gap 103
Different from grid line gap 101 and 102, it is disconnected at notch G, so that each grid layer mutual conduction for referring to memory block 120.
It is each to refer to the array formed in memory block 120 with channel hole 122, run through array barrier structure (TAB) 124 and run through array
Contact portion (TAC) 126.Here, the pitch-limited of TAB 124 and grid line gap 103 is in the size of three-dimensional storage 100 itself.Especially
It is that as shown in Figure 1, two end 103as of the grid line gap 103 at notch G are typically circle in cross section.Therefore end
Spacing between 103a and TAB 124 is closer.The material and TAB 124 that closer spacing is easy to cause in grid line gap 103 bridge
(bridge) it even contacts.
The embodiment of the present invention describes three-dimensional storage and preparation method thereof, can expand grid line gap and obstruct with through array
Spacing between structure, and without not increasing array memory block size.
Three-dimensional storage may include array area (array), and array area may include core space (core) and wordline bonding pad.Core
Heart district is the region for including storage unit.Wordline bonding pad is the region for including wordline connection circuit.Wordline bonding pad is typically
Ladder (stair step, SS) structure.It is to be understood that the limitation of this and non-present invention.Wordline bonding pad can use completely
Other structures, such as flat structures.In terms of vertical direction, array area can have substrate and stack layer.Fig. 2 is according to the present invention one
The top view of the three-dimensional storage part of embodiment.For emphasis of the invention of avoiding confusion, three-dimensional storage 200 is only shown in Fig. 2
In include 1 array memory core space.Three-dimensional storage 200 can have array memory block, may include as shown in Figure 2
One or more block memory blocks 210.Block memory block 210 has substrate and the stack layer on the substrate in vertical direction
(not shown), stack layer may include along the alternately stacked grid layer in direction and dielectric layer with substrate transverse.Each piece of memory block
210 can be divided into multiple (3 are shown in figure) again refers to memory block 220.It block memory block 210 can be by spaced first grid line gap
201 and second gate line gap 202 define, block memory block 210 is further divided by 2 third grid line gaps 203 for 3 finger memory blocks 220.
In the present embodiment, each to refer to that memory block 220 has the TAB 224 between adjacent gate line gap.For example, first grid line gap
Between 201 and the third grid line gap 203 of top, between 2 third grid line gaps 203, the third grid line gap 203 of lower section and second gate
TAB 224 is respectively provided between line gap 202.In each TAB 224 along the two sides of grid line gap extending direction (X-direction in figure),
It is respectively provided with virtual channel (dummy channel) structure column 223a and 223b.Virtual channel structure column 223a and 223b include
The virtual channel structure of multiple direction (Y-direction in figure) arrangements in grid line gap extending direction.Here, virtual channel structure plays
Supporting role.It is appreciated that virtual channel structure arranges the distribution being not limited in Fig. 2, it can also be other distribution modes.Such as
Virtual channel structure column in the X direction can be more or less.
In this embodiment, third grid line gap 203 is corresponding to disconnection at virtual channel structure column 223a and 223b, distribution
A pair of end portions 203a and another pair end 203b is formed, is respectively provided with notch G1 and G2 therebetween.In one example, third
Orientation (the Y in figure that the notch (HCut) and virtual channel structure column 203a that grid line gap 203 disconnects are arranged in virtual channel structure
Direction) on be aligned, to avoid TAB 224.In embodiments herein, the notch of third grid line gap 203 in the X direction
It can change, such as third grid line gap 203 is corresponding at each virtual channel structure column (203a, 203b and other)
It disconnects, for another example third grid line gap 203 is corresponding to disconnection at partial virtual channel structure column (such as 203a).Each third grid line
The quantity of 203 notch of gap and/or the position disconnected in the X direction can be identical, be also possible to different.Further, may be used
To there is some or all of gap position of part third grid line gap 203 not at virtual channel structure column 223a and 223b.
In the present embodiment, third grid line gap 203 is disconnected in the adjacent position virtual channel structure column 223a and 223b,
To make end 203a, 203b of open position avoid TAB 224, to significantly alleviate TAB 224 and third grid line gap 203
Because of bridge joint or contact problems caused by hypotelorism.The present embodiment makes three-dimensional storage layout more reasonable, is conducive to
Reduce the size in Y-direction.And since the grid line gap 203 of the present embodiment can be disconnected in multiple positions, so that each finger be allowed to deposit
Grid between storage area 220 is interconnected by the conductor of multiple gaps, and this parallel-connection structure can reduce the resistance value of interconnection, thus
Improve the transmission delay of three-dimensional storage.
Continue with the other details that the present embodiment is described with reference to Fig. 2.It is appreciated that the application can be independent of under
Implement in the case where stating details.As shown in Fig. 2, having in each finger memory block 220 by many channel holes 222 perpendicular to substrate
The array of formation.With the structure of such as memory layer, channel layer in these channel holes 222, with the grid layer of channel hole side,
The drain electrode of the source electrode and top of 222 bottom of channel hole constitutes memory cell string.Memory layer may include the radial direction along channel hole
Barrier layer, electric charge capture layer and the tunnel layer being arranged from outside to inside.As replacement, memory layer may be to be arranged in channel hole
FGS floating gate structure between grid layer.Virtually channel structure can be similar with the structure in channel hole, the difference is that virtually
Channel structure is not brought out contact portion.Virtually channel structure is also possible to different from the structure in channel hole, such as virtually
Insulating materials has been filled only in channel structure.
In addition, being provided with TAC 226 in TAB 224.TAC 226 is the line for being electrically connected storage array and peripheral circuit.
In TAC 226 quantity of contact portion can as needed depending on.
With continued reference to Fig. 2, two end 203as of each third grid line gap 203 at TAB 224 prolong in three-dimensional storage
The cross section stretched on direction is typically circle, this is bigger than the end size of rectangle.Nonetheless, it is provided in the present embodiment
It is not easy to bridge or contacts between the certifiable end 203a and TAB 224 of space D in X-direction.In other embodiments, end
The cross section of 203a can also be other shapes, such as rectangle.
In some embodiments, the space D 1 of virtual channel structure column in the Y direction than TAB 224 in the Y direction between
It is big away from D2, therefore the end (such as 203a) of third grid line gap 203 is enough at a distance from virtual channel structure column (such as 223a)
Far, bridge joint or contact bring leakage risk are more reduced.
Settable array common source (Array Common Source, ACS), mentions in grid line gap 201-203 for storage array
For common source electrode.Settable insulating layer between array common source and grid line gap side wall.
In the present embodiment, substrate is typically siliceous substrate, such as Si, SOI (silicon-on-insulator), SiGe, Si:C
Deng, although this and it is non-limiting.The trap of some doping, such as N trap or p-well can be set as needed on substrate.The material of grid layer
Material is e.g. metal (such as tungsten).The material of dielectric layer is, for example, silica.The material of dielectric layer is without being limited thereto, is also possible to other
Insulating materials.
In an embodiment of the present invention, the exemplary materials of barrier layer and tunnel layer are silica, silicon oxynitride or both
Mixture, the exemplary materials of electric charge capture layer are the multilayered structure of silicon nitride or silicon nitride and silicon oxynitride.Barrier layer,
Electric charge capture layer, tunnel layer can form the multilayer knot for example with silicon oxynitride-silicon-nitride and silicon oxide (SiON/SiN/SiO)
Structure；Channel layer exemplary materials are polysilicon.It is to be understood that these layers can choose other materials.For example, the material on barrier layer
Material may include high K oxide layer；The material of channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C, SiGe:H
Equal semiconductor materials.
Fig. 3 is the method flow diagram of the formation three-dimensional storage of one embodiment of the invention.Fig. 4 A-4C is that the present invention one is implemented
Schematic diagram in the example process of the formation three-dimensional storage of example, wherein Fig. 4 A is cross-sectional view, and Fig. 4 B-4C is top view.Under
The method of the formation three-dimensional storage of face description the present embodiment with reference to shown in Fig. 3-4C.
In step 302, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for follow-up process to ultimately form three-dimensional storage part.Partly lead
Body structure may include core space.In terms of vertical direction, core space can have substrate, edge and the side of substrate transverse on substrate
To alternately stacked grid layer and dielectric layer or dummy gate layer and dielectric layer.
In the cross-sectional view of the semiconductor structure exemplified by Fig. 4 A, semiconductor structure 400a may include substrate 401 and be located at
Stack layer 410 on substrate.Stack layer can be first material layer 411 and the alternately stacked lamination of second material layer 412.First material
The bed of material can be grid layer or dummy gate layer.Second material layer is dielectric layer.
In an embodiment of the present invention, the material of substrate is, for example, silicon.First material layer and second material layer are, for example, nitrogen
The combination of SiClx and silica.By taking the combination of silicon nitride and silica as an example, chemical vapor deposition (CVD), atom can be used
Layer deposition (ALD) or other suitable deposition methods, successively alternating deposit silicon nitride and silica, formation stack on substrate
Layer.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.For example, can basis in substrate
Need to form various well regions.
In step 304, formed through the virtual channel structure column for being alternately stacked layer.
In this step, the virtual channel junction being made of some virtual channel structures is formd on semiconductor structure 400b
Structure column 223a, 223b.
Typically, in this step, the channel being made of many channel holes 222 is yet formed on semiconductor structure 400b
Hole array.
In some embodiments, virtual channel structure can make with the structure in channel hole in same group of technique.?
In other embodiments, virtual channel structure can also make from the structure in channel hole in different groups of techniques.
In step 306, is formed on semiconductor structure and run through array barrier structure.
In this step, can in the semiconductor structure, the side being formed in perpendicular to substrate extends upward through passing through for stack layer
Wear array barrier structure (TAB).Here, virtual channel structure column are located at through at least side of array barrier structure.Typically,
Virtual channel structure column with to run through array barrier structure adjacent in the X direction.
Groove (Trench) can be formed by lithography and etching, then fill insulant in the trench, as TAB.
In the top view of the semiconductor structure exemplified by Fig. 4 C, form on semiconductor structure 400c perpendicular to substrate
401 TAB 224 through stack layer 410 (with reference to shown in Fig. 4 A).224 two sides TAB have virtual channel structure column 223a and
223b.In other words, each TAB 224 is located between two virtual channel structure column 223a and 223b.
In step 308, spaced first grid line gap and second gate line gap are formed on semiconductor structure and is located at
One or more third grid line gaps between first grid line gap and second gate line gap.
In this step, can in the semiconductor structure, the side being formed in perpendicular to substrate extends upward through each of stack layer
Kind grid line gap, to distinguish each piece of memory block and refer to memory block.At this point, TAB can be located between the grid line gap at interval.These
At least one third grid line gap in three grid line gaps is corresponding to disconnection at virtual channel structure column, to avoid TAB.
In the top view of the semiconductor structure exemplified by Fig. 4 D, form on semiconductor structure 400d perpendicular to lining
The first grid line gap 201 and second gate line gap 202 through stack layer 410 (with reference to shown in Fig. 4 A) at bottom 401, and landform together
At 2 third grid line gaps 203 between first grid line gap 201 and second gate line gap 202.Third grid line gap 203 is in correspondence
It is disconnected at virtual channel structure column 223a and 223b, gap is respectively formed a pair of end portions 203a and another pair end 203b.
End 203a, 203b are round or rectangle in the section (plane as shown in the figure) in the direction parallel with substrate.
After forming grid line gap, block memory block 210 is defined between first grid line gap 201 and second gate line gap 202.It is located at
Channel hole array between first grid line gap 201 and second gate line gap 202 is divided into multiple fingers by each third grid line gap 203 and deposits
Storage area 220.
It further include that insulating layer and array common source (ACS) are formed in grid line gap 201-203 after forming grid line gap.Battle array
Column common source is located in insulating layer.
After step 308, may also include to be formed in TAB 224 through array contact portion 226, thus obtain as
Structure shown in Fig. 2.
Other details of three-dimensional storage part, such as wordline bonding pad, periphery interconnection etc., and the emphasis of non-present invention,
This not reinflated description.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3D nand flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (15)
1. a kind of three-dimensional storage, including array memory block, the array memory block has an at least one block memory block, described piece
Memory block includes:
Stack layer with substrate and on the substrate, the stack layer include that edge replaces with the direction of the substrate transverse
The grid layer and dielectric layer of stacking；
Spaced first grid line gap and second gate line gap；
One or more third grid line gaps between the first grid line gap and second gate line gap；
Run through array barrier structure between adjacent grid line gap；And
It is arranged through array barrier structure along the virtual channel structure of at least side of grid line gap extending direction positioned at described；
Wherein, at least one third grid line gap in one or more of third grid line gaps is corresponding to the virtual channel junction
It is disconnected at structure column.
2. three-dimensional storage as described in claim 1, which is characterized in that the notch that at least one described third grid line gap disconnects
It is listed in the orientation of the virtual channel structure column and is aligned with the virtual channel structure.
3. three-dimensional storage as described in claim 1, which is characterized in that at least one described third grid line gap is corresponding to often
It is disconnected at a virtual channel structure column.
4. three-dimensional storage as described in claim 1, which is characterized in that the end of at least one third grid line gap gap
Portion is round or rectangle in the section in the direction parallel with the substrate.
5. three-dimensional storage as described in claim 1, which is characterized in that further include being located at described run through in array barrier structure
Run through array contact portion.
6. three-dimensional storage as described in claim 1, which is characterized in that further include being located at the first grid line gap and second gate
Channel hole array between line gap, the channel hole array are divided into multiple fingers by one or more of third grid line gaps and store
Area.
7. three-dimensional storage as claimed in claim 6, which is characterized in that the array barrier structure that runs through is in the grid line gap
At least side of extending direction is provided with the channel hole array, and is located at the channel hole array and ties with through array barrier
The virtual channel structure column between structure.
8. three-dimensional storage as described in claim 1, which is characterized in that further include positioned at the first grid line gap and described the
Insulating layer and array common source in two grid line gaps.
9. a kind of method for forming three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure has substrate and is alternately stacked layer on the substrate；
It is formed through the virtual channel structure column for being alternately stacked layer；
It is formed on the semiconductor structure and runs through array barrier structure, the virtual channel structure column run through array positioned at described
At least side of barrier structure；And
Spaced first grid line gap and second gate line gap are formed on the semiconductor structure and are located at the first grid
One or more third grid line gaps between line gap and second gate line gap, wherein described be located at adjacent gate through array barrier structure
Between line gap, at least one third grid line gap in one or more of third grid line gaps is corresponding to the virtual channel junction
It is disconnected at structure column.
10. according to the method described in claim 9, it is characterized in that, at least one described third grid line gap and the virtual ditch
Road structure is listed in the orientation of the virtual channel structure column and is aligned.
11. according to the method described in claim 9, it is characterized in that, at least one described third grid line gap is corresponding to each
It is disconnected at virtual channel structure column.
12. method as claimed in claim 9, which is characterized in that the end of at least one third grid line gap gap exists
The section in the direction parallel with the substrate is round or rectangle.
13. method as claimed in claim 9, which is characterized in that further include being formed to be located at described run through in array barrier structure
Run through array contact portion.
14. method as claimed in claim 9, which is characterized in that further include forming channel hole battle array on the semiconductor structure
Column, the channel hole array is between the first grid line gap and second gate line gap and by one or more of third grid lines
Gap is divided into multiple finger memory blocks.
15. method as claimed in claim 9, which is characterized in that further include in the first grid line gap and second grid line
Insulating layer and array common source are formed in gap.
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