CN111403406A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN111403406A CN111403406A CN202010175101.8A CN202010175101A CN111403406A CN 111403406 A CN111403406 A CN 111403406A CN 202010175101 A CN202010175101 A CN 202010175101A CN 111403406 A CN111403406 A CN 111403406A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides a three-dimensional memory and a preparation method thereof, belonging to the field of semiconductor memory design and manufacture.A first block memory area of the three-dimensional memory comprises a first core area and a first step area, a second memory area comprises a second core area and a second step area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area and the second step area are adjacently arranged along a second direction and are mutually isolated, the first step area is provided with a first step broadening part which extends to the inside of the second core area along the first direction, and the second step area is provided with a second step broadening part which extends to the inside of the first core area along the first direction in a reverse way.
Description
Technical Field
The invention belongs to the field of semiconductor memory design and manufacture, and particularly relates to a three-dimensional memory and a preparation method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to address the difficulties encountered with flat flash memories and to pursue lower production costs per unit cell, three-dimensional memory structures have arisen that can enable each memory die in a memory device to have a greater number of memory cells.
In non-volatile memories, such as NAND memories, one way to increase memory density is by using vertical memory arrays, i.e. 3D NAND memories, while CTF (Charge Trap Flash) type 3D NAND memories are currently the leading and very promising memory technology.
A 3D NAND memory will typically include one or more chip (plane) storage areas. Symmetrical connection regions for the extraction gates will generally be provided on both sides of the chip storage region. Generally, the connection region has a Step-Step shape. The slice and connection areas are typically divided into blocks, forming a plurality of Block storage areas (blocks).
In the existing 3D NAND memory, the area occupied by the step area of each block storage area is only the area of one block storage area, so that the step architectural design is limited.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a three-dimensional memory and a method for fabricating the same, which is used to solve the problem of step areas of block storage areas in the prior art.
In order to achieve the above and other related objects, the present invention provides a three-dimensional memory, which includes a first block and a second block, wherein the first block includes a first core region and a first step region located in the middle of the first core region, the second block includes a second core region and a second step region located in the middle of the second core region, the first core region and the second core region are adjacently arranged along a first direction and are isolated from each other, the first step region and the second step region are adjacently arranged along a second direction and are isolated from each other, wherein the first step region has a first step widening portion extending to the inside of the second core region along the first direction, and the first step widening portion is isolated from the second core region by a first gate line gap; the second step region has a second step widening extending in a first direction back to the interior of the first core region, the second step widening being isolated from the first core region by a second gate line gap.
Optionally, the first core region includes a first sub-core region and a second sub-core region located at two ends of the first terrace region and the second terrace region, the first sub-core region is connected to the first terrace region, the second core region includes a third sub-core region and a fourth sub-core region located at two ends of the first terrace region and the second terrace region, and the fourth core region is connected to the second terrace region; the first storage area further comprises a first bridging wall located on one side of the first stepped area and the second stepped area, the first bridging wall is connected with the first stepped area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall located on the other side of the first stepped area and the second stepped area, and the second bridging wall is connected with the second stepped area, the third sub-core area and the fourth sub-core area.
Optionally, the first sub-core region and the third sub-core region are separated by a first inter-block gate line gap, the first inter-block gate line gap is connected to the first gate line gap, the second sub-core region and the fourth sub-core region are separated by a second inter-block gate line gap, and the second inter-block gate line gap is connected to the second gate line gap.
Optionally, the first step widening portion extends to be adjacent to the second bridging wall and is separated from the second bridging wall by a third gate line gap, the first gate line gap is connected to the third gate line gap, the second step widening portion extends to be adjacent to the first bridging wall and is separated from the first bridging wall by a fourth gate line gap, and the fourth gate line gap is connected to the second gate line gap.
Optionally, the first core region and the second core region each include a plurality of finger storage regions, and the finger storage regions are isolated from each other by inter-finger grid gaps.
Optionally, the width of the first step expanse extending into the second core region is an integer multiple of the width of the finger storage region.
Optionally, the widths of the first bridge wall and the second bridge wall are between the width of 0.5 finger storage areas and the width of 2 finger storage areas.
Optionally, the steps of the first step area and the second step area sequentially decrease from the corresponding core areas to the isolation zone between the first step area and the second step area, and are cut off at the isolation zone.
Optionally, the first direction and the second direction are perpendicular to each other.
Optionally, the first core region and the second core region include a stacked structure and a channel storage structure array penetrating through the stacked structure, and the channel storage structure includes a channel hole penetrating through the stacked structure and a memory film and a channel layer located in the channel hole.
The invention also provides a preparation method of the three-dimensional memory, which comprises the following steps: providing a substrate, and forming a stacked structure on the substrate; forming a first storage area and a second storage area in the stacked structure, wherein the first storage area comprises a first core area and a first step area located in the middle of the first core area, the second storage area comprises a second core area and a second step area located in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are isolated from each other, the first step area and the second step area are adjacently arranged along a second direction and are isolated from each other, the first step area is provided with a first step widening portion extending to the inside of the second core area along the first direction, and the first step widening portion is isolated from the second core area through a first grid line gap; the second step region has a second step widening extending in a first direction back to the interior of the first core region, the second step widening being isolated from the first core region by a second gate line gap.
Optionally, the first core region includes a first sub-core region and a second sub-core region located at two ends of the first terrace region and the second terrace region, the first sub-core region is connected to the first terrace region, the second core region includes a third sub-core region and a fourth sub-core region located at two ends of the first terrace region and the second terrace region, and the fourth core region is connected to the second terrace region; the first storage area further comprises a first bridging wall located on one side of the first stepped area and the second stepped area, the first bridging wall is connected with the first stepped area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall located on the other side of the first stepped area and the second stepped area, and the second bridging wall is connected with the second stepped area, the third sub-core area and the fourth sub-core area.
Optionally, the first sub-core region and the third sub-core region are separated by a first inter-block gate line gap, the first inter-block gate line gap is connected to the first gate line gap, the second sub-core region and the fourth sub-core region are separated by a second inter-block gate line gap, and the second inter-block gate line gap is connected to the second gate line gap.
Optionally, the first step widening portion extends to be adjacent to the second bridging wall and is separated from the second bridging wall by a third gate line gap, the first gate line gap is connected to the third gate line gap, the second step widening portion extends to be adjacent to the first bridging wall and is separated from the first bridging wall by a fourth gate line gap, and the fourth gate line gap is connected to the second gate line gap.
Optionally, the first core region and the second core region each include a plurality of finger storage regions, the finger storage regions are separated by finger inter-finger gate gaps, a width of a first step widening portion extending to the inside of the second core region is an integral multiple of a width of the finger storage region, a width of the first bridging wall is between 0.5 and 2 widths of the finger storage regions, and a width of the second bridging wall is between 0.5 and 2 widths of the finger storage regions.
Optionally, the steps of the first step area and the second step area sequentially decrease from the corresponding core areas to the isolation zone between the first step area and the second step area, and are cut off at the isolation zone.
As described above, the three-dimensional memory and the manufacturing method thereof of the present invention have the following beneficial effects:
the present invention achieves an increase in the step area width in a first direction (e.g., Y direction) for a single block storage region by a novel gate line gap (G L S) design such that the step area of a block storage region has a step extension that extends into the core area of an adjacent block storage region.
The increase of the width of the step area of the single storage area in the Y direction is beneficial to the increase of the number of subareas, meanwhile, the bridge wall has larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design difficulty of the framework of the three-dimensional memory.
Drawings
FIG. 1 is a schematic diagram of a layout structure of a three-dimensional memory.
FIG. 2 is a schematic diagram of a three-dimensional memory according to the present invention.
FIG. 3 is a schematic diagram of a layout structure of a three-dimensional memory according to the present invention.
FIG. 4 is a schematic diagram of another layout structure of the three-dimensional memory according to the present invention.
Description of the element reference numerals
11. 12 blocks of memory area
111 core region
112 step area
113 bridging wall
21 first block of memory area
211 first sub-core region
212 second sub-core region
213 first step area
214 first step widening
215 first bridging wall
22 second block of memory
221 third sub-core region
222 fourth sub-core region
223 second step area
224 second step widening
225 second bridge wall
241 first grid line gap
242 first inter-block gate line gap
243 second inter-block grid line gap
244 third grid gap
245 second grid gap
246 fourth grid gap
247 isolation zone
248 finger gap between grid lines
23 denotes a storage area
31 third Block storage area
32 fourth block of memory
41. 42, 43, 44 block storage area
414 first step widening
424 second step widening
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Fig. 1 is a schematic structural diagram of a three-dimensional (3D) NAND memory, which includes a plurality of block memory areas 11 and 12, each block memory area includes a core area 111 and a step area 112, the step area 112 is disposed in the middle of the core area 111, and the step area 112 is matched with a bridging wall 113, so that the step area 112 connects the core areas 111 at two ends thereof. In this three-dimensional memory, the shared region in the step district of each block storage area is only the region of a block storage area, for example, this three-dimensional memory a block storage area contains 3 and indicates the storage area, and the width in step district can only be designed to be not more than 3 and indicates the width of storage area, and the bridge wall also need occupy the storage area that indicates of certain width moreover, like this, can make the step district width in the Y direction limited, has restricted the architectural design of step and the design of bridge wall.
The invention provides a three-dimensional memory, which realizes the increase of the step area width of a single block storage area in a first direction (for example, Y direction) through a novel gate line gap (G L S) design, so that a step area of a block storage area has a step widening part extending into a core area of an adjacent block storage area.
As shown in fig. 2 to fig. 3, the present embodiment provides a three-dimensional memory, which includes a plurality of Block memory areas (blocks), for example, as shown in fig. 3, the three-dimensional memory may include a first Block memory area 21, a second Block memory area 22, a third Block memory area and a fourth Block memory area, of course, in an actual device design, the three-dimensional memory may include more Block memory areas, such as 8 Block memory areas, 16 Block memory areas or more, and is not limited to the examples in the figures herein.
For a more convenient and detailed description, in this embodiment, taking two block memory regions as an example, as shown in fig. 2, the three-dimensional memory includes a first block memory region 21 and a second block memory region 22, the first block memory region 21 and the second block memory region 22 are isolated from each other, the first block memory region 21 includes a first core region and a first terrace region 213 located in the middle of the first core region, the second memory region includes a second core region and a second terrace region 223 located in the middle of the second core region, the first core region and the second core region are arranged adjacently in a first direction and isolated from each other, the first terrace region 213 and the second terrace region 223 are arranged adjacently in a second direction and isolated from each other, wherein the first terrace region 213 has a first terrace extension 214 extending into the second core region in the first direction, the first step widening 214 is isolated from the second core region by a first gate line gap 241; the second stepped region 223 has a second step-widening 224 extending in the first direction back to the inside of the first core region, the second step-widening 224 being separated from the first core region by a second gate line gap 245, in particular, as shown in fig. 2, the first step-widening 214 is arranged in a staggered manner with respect to the second step-widening 224. The first direction and the second direction are preferably perpendicular to each other, for example, as shown in fig. 2, the first direction may be a Y direction, and the second direction may be an X direction.
As shown in fig. 2, the first core region includes a first sub-core region 211 and a second sub-core region 212 located at two ends of the first terrace region 213 and the second terrace region 223, the first sub-core region 211 is connected to the first terrace region 213, the second core region includes a third sub-core region 221 and a fourth sub-core region 222 located at two ends of the first terrace region 213 and the second terrace region 223, and the fourth core region is connected to the second terrace region 223; the first block storage area 21 further includes a first bridging wall 215 located at one side of the first block area 213 and the second block area 223, the first bridging wall 215 connects the first block area 213, the first sub-core area 211, and the second sub-core area 212, the second block storage area 22 further includes a second bridging wall 225 located at the other side of the first block area 213 and the second block area 223, and the second bridging wall 225 connects the second block area 223, the third sub-core area 221, and the fourth sub-core area 222. Of course, the layout of the first sub-core region 211, the second sub-core region 212, the third sub-core region 221, the fourth sub-core region 222, the first step region 213 and the second step region 223 is not limited to the above-listed examples, for example, the first step region 213 may be connected to the second sub-core region 212 and connected to the first sub-core region 211 through a first bridging wall 215, and similarly, the second step region 223 may be connected to the third sub-core region 221 and connected to the third sub-core region through a second bridging wall 225, and the structure thereof may refer to the schematic structure of the third block storage region and the fourth block storage region in fig. 3.
As shown in fig. 2, the first sub-core region 211 and the third sub-core region 221 are separated by a first inter-block gate line gap 242, the first inter-block gate line gap 242 is connected to the first gate line gap 241, the second sub-core region 212 and the fourth sub-core region 222 are separated by a second inter-block gate line gap 243, and the second inter-block gate line gap 243 is connected to the second gate line gap 245.
As shown in fig. 2, the first step-widening 214 extends to adjacent to the second bridging wall 225 and is separated from the second bridging wall 225 by a third gate line gap 244, the first gate line gap 241 is connected to the third gate line gap 244, the second step-widening 224 extends to adjacent to the first bridging wall 215 and is separated from the first bridging wall 215 by a fourth gate line gap 246, and the fourth gate line gap 246 is connected to the second gate line gap 245.
As shown in fig. 2, the steps of the first step region 213 and the second step region 223 sequentially decrease from the corresponding core regions toward the isolation zone 247 between the first step region 213 and the second step region 223, and after the isolation zone 247 is cut off, for example, after the steps are sequentially decreased, the substrate surface under the step regions is exposed at the isolation zone 247, so as to realize the cut-off isolation of the first step region 213 and the second step region 223.
Specifically, as shown in fig. 2, for the first and second memory blocks 21 and 22, the primary isolation structure of the present embodiment includes a first inter-block gate line gap 242, a first gate line gap 241, a third gate line gap 244, an isolation strip 247, a fourth gate line gap 246, a second gate line gap 245 and a second inter-block gate line gap 243 connected in sequence, wherein the first inter-block gate line gap 242 extends along a second direction (X direction) to isolate the first sub-core region 211 from the third sub-core region 221, the first gate line gap 241 extends along a first direction (Y direction) to isolate the first step region 213 from the third sub-core region 221, the third gate line gap 244 extends along a second direction (X direction) to isolate the first step region 213 from the second bridge wall 225, the isolation strip 247 extends along the first direction (Y direction) to isolate the first step region 213 from the second sub-core region 213, the isolation strip 213 extends along the second direction (X direction) to isolate the first step region 213 from the second sub-core region, the second step region 213 from the second bridge wall 225, the isolation strip 247 extends along the first direction (Y direction) to provide a novel isolation barrier, the isolation strip 247, the isolation strip may be disposed along the second isolation strip gap, the isolation strip may be disposed along the second isolation strip isolation region, the isolation strip may be disposed along the second isolation region, the first isolation region, the isolation strip may be disposed along the second isolation strip, the second isolation strip isolation region, the first isolation strip isolation region 213, the second isolation region, the isolation strip isolation region may be disposed along the second isolation region, the second isolation line gap may be disposed along the second isolation line gap extension direction (Y direction, the second isolation line gap extension direction, the isolation region, the isolation strip isolation region may be disposed along the second isolation region, the isolation line gap extension direction, the isolation region, the second isolation region may be disposed along the isolation line gap extension direction, the isolation region, the second isolation region, the isolation region may be disposed along the isolation region, the isolation region.
The first core region and the second core region each include a plurality of finger storage regions 23, each finger storage region 23 being separated by an inter-finger gate line gap 248, and at this time, in order to more effectively utilize a device region, the width of the first step broadening 214 extending into the second core region is an integral multiple of the width of the finger storage region 23. In addition, since the step area is widened as a whole, the width of the first bridging wall 215 of the present embodiment may be designed to be between the width of 0.5 finger storage areas 23 and the width of 2 finger storage areas 23, and the width of the second bridging wall 225 may be designed to be between the width of 0.5 finger storage areas 23 and the width of 2 finger storage areas 23. The width of the step area of the single storage area in the Y direction is increased, so that the bridge wall has larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design difficulty of the architecture of the three-dimensional memory.
As shown in fig. 2, in a specific embodiment, the first core region and the second core region each include 3 finger storage regions 23 including a bridge wall, the first terrace region 213 and the second terrace region 223 extend into an adjacent core region in addition to occupying the width of the 3 finger storage regions 23 of the core region corresponding to the first terrace region and additionally occupy the width of 2 finger storage regions 23, that is, the first terrace widening 214 and the second terrace widening 224 have the width of 2 finger storage regions 23, and the area occupied by each of the first terrace region 213 and the second terrace region 223 is the width of 5 finger storage regions 23, wherein the first bridge wall 215 and the second bridge wall 225 each occupy the width of one finger storage region 23.
In another specific embodiment, as shown in fig. 4, the three-dimensional memory includes 4 block storage regions 41, 42, 43, 44, each core region includes 2 finger storage regions including a bridge wall, the first terrace region 213 and the second terrace region 223 extend into the adjacent core region besides the width of the 2 finger storage regions of the core region corresponding to the first terrace region, and additionally occupy 1 finger storage region, that is, the first terrace widening 414 and the second terrace widening 424 have the width of 1 finger storage region, and the area occupied by each of the first terrace region 213 and the second terrace region 223 is the width of 3 finger storage regions, wherein each of the first bridge wall 215 and the second bridge wall 225 occupies the width of one finger storage region.
According to the idea of the present invention, the three-dimensional memory can be applied to a scene in which 1 block storage area includes only 1 finger storage area, or a scene in which 1 block storage area includes 4 or more finger storage areas, without being limited to the above-listed examples.
In this embodiment, the three-dimensional memory may be a 3D NAND memory, wherein the first core region and the second core region include a stack structure on a substrate and a channel memory structure array penetrating through the stack structure, and the channel memory structure includes a channel hole penetrating through the stack structure and a memory film and a channel layer in the channel hole.
In the present embodiment, the substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), SiGe, SiC, or the like, but is not limited to the above-exemplified examples. Peripheral devices such as field effect transistors, capacitors, inductors and/or diodes may be provided on the substrate as desired, and serve as various functional devices of the memory, such as buffers, amplifiers, decoders, etc. The stacked structure comprises a stack of a sacrificial dielectric layer and a gate dielectric layer, for example, the stacked structure comprises silicon nitride layers and silicon oxide layers which are alternately stacked. The sacrificial dielectric layer is removed in a subsequent process, and replaced with a gate layer, which may be a material such as polysilicon, copper, aluminum, tungsten, titanium nitride, tantalum nitride, etc., in a corresponding position, but is not limited to the examples listed herein.
In this embodiment, the memory film includes a blocking layer, a charge trapping layer and a tunneling layer, wherein the blocking layer is located on a sidewall surface of the channel hole, the charge trapping layer is located on a surface of the blocking layer, and the tunneling layer is located on a surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include a semiconductor material such as single crystal silicon, single crystal germanium, SiGe, SiC, SiGeC, SiGeH, or the like.
As shown in fig. 2 and fig. 3, the present embodiment further provides a method for manufacturing a three-dimensional memory, including the steps of:
firstly, step 1) is carried out, a substrate is provided, and a stacked structure is formed on the substrate.
In the present embodiment, the substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), SiGe, SiC, or the like, but is not limited to the above-exemplified examples. Peripheral devices such as field effect transistors, capacitors, inductors and/or diodes may be provided on the substrate as desired, and serve as various functional devices of the memory, such as buffers, amplifiers, decoders, etc. The stacked structure comprises a stack of a sacrificial dielectric layer and a gate dielectric layer, for example, the stacked structure comprises silicon nitride layers and silicon oxide layers which are alternately stacked. The sacrificial dielectric layer is removed in a subsequent process, and replaced with a gate layer, which may be a material such as polysilicon, copper, aluminum, tungsten, titanium nitride, tantalum nitride, etc., in a corresponding position, but is not limited to the examples listed herein.
Then, step 2) is performed, a first block storage region 21 and a second block storage region 22 are formed in the stacked structure, the first block storage region 21 includes a first core region and a first step region 213 located in the middle of the first core region, the second storage region includes a second core region and a second step region 223 located in the middle of the second core region, the first core region and the second core region are adjacently arranged along a first direction and are isolated from each other, the first step region 213 and the second step region 223 are adjacently arranged along a second direction and are isolated from each other, wherein the first step region 213 has a first step extension 214 extending to the inside of the second core region along the first direction, and the first step extension 214 is isolated from the second core region by a first gate line gap 241; the second stepped region 223 has a second step widening 224 extending in the first direction back to the inside of the first core region, the second step widening 224 being isolated from the first core region by a second gate line gap 245.
The first core region includes a first sub-core region 211 and a second sub-core region 212 located at two ends of the first terrace region 213 and the second terrace region 223, the first sub-core region 211 is connected to the first terrace region 213, the second core region includes a third sub-core region 221 and a fourth sub-core region 222 located at two ends of the first terrace region 213 and the second terrace region 223, and the fourth core region is connected to the second terrace region 223; the first block storage area 21 further includes a first bridging wall 215 located at one side of the first block area 213 and the second block area 223, the first bridging wall 215 connects the first block area 213, the first sub-core area 211, and the second sub-core area 212, the second block storage area 22 further includes a second bridging wall 225 located at the other side of the first block area 213 and the second block area 223, and the second bridging wall 225 connects the second block area 223, the third sub-core area 221, and the fourth sub-core area 222. The first sub-core region 211 and the third sub-core region 221 are separated by a first inter-block gate line gap 242, the first inter-block gate line gap 242 is connected to the first gate line gap 241, the second sub-core region 212 and the fourth sub-core region 222 are separated by a second inter-block gate line gap 243, and the second inter-block gate line gap 243 is connected to the second gate line gap 245. The first step widenings 214 extend adjacent to the second bridge wall 225 and are separated from the second bridge wall 225 by third gate line gaps 244, the first gate line gaps 241 are connected to the third gate line gaps 244, the second step widenings 224 extend adjacent to the first bridge wall 215 and are separated from the first bridge wall 215 by fourth gate line gaps 246, the fourth gate line gaps 246 are connected to the second gate line gaps 245.
In this embodiment, the forming the first core region and the second core region includes: a stacked structure is formed on a substrate, and an array of trench storage structures is formed in the stacked structure through the stacked structure, the trench storage structures including a trench hole through the stacked structure and a memory film and a channel layer in the trench hole. The memory film comprises a blocking layer, a charge trapping layer and a tunneling layer, wherein the blocking layer is located on the surface of the side wall of the channel hole, the charge trapping layer is located on the surface of the blocking layer, and the tunneling layer is located on the surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include a semiconductor material such as single crystal silicon, single crystal germanium, SiGe, SiC, SiGeC, SiGeH, or the like.
In the process of forming the channel hole structure, the first inter-gate line gap 242, the first gate line gap 241, the third gate line gap 244, the fourth gate line gap 246, the second gate line gap 245 and the second inter-gate line gap 243 may also be simultaneously formed in the stacked structure, wherein the first inter-gate line gap 242 extends along the second direction (X direction) to isolate the first sub-core region 211 from the third sub-core region 221, the first gate line gap 241 extends along the first direction (Y direction) to isolate the first step region 213 from the third sub-core region 221, the third gate line gap 244 extends along the second direction (X direction) to isolate the first step region 213 from the second bridging wall 225, the fourth gate line gap 246 extends along the second direction (X direction) to isolate the second step region 223 from the first bridging wall 215, the second gate line gap 245 extends along a first direction (Y direction) for isolating the second step region 223 from the second sub-core region 212, and the two inter-block gate line gaps extends along a second direction (X direction) for isolating the second sub-core region 212 from the fourth sub-core region 222.
In the above process, a plurality of inter-finger gate line gaps 248 may be formed in the stacked structure at the same time to isolate a plurality of finger storage regions in both the first core region and the second core region. At this time, in order to more effectively use the device region, the width of the first step broadening 214 extending into the second core region is an integer multiple of the width of the finger storage region. In addition, since the step area is widened as a whole, the width of the first bridging wall 215 of this embodiment may be designed to be between the width of 0.5 finger storage areas 23 and the width of 2 finger storage areas 23, and the width of the second bridging wall 225 may be designed to be between the width of 0.5 finger storage areas and the width of 2 finger storage areas. The width of the step area of the single storage area in the Y direction is increased, so that the bridge wall has larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design difficulty of the architecture of the three-dimensional memory.
As shown in fig. 2, in a specific embodiment, each of the first core region and the second core region includes 3 finger storage regions including a bridge wall, the first terrace region 213 and the second terrace region 223 extend into an adjacent core region in addition to occupying the width of the 3 finger storage regions of the core region corresponding to the first terrace region and occupy the width of 2 finger storage regions, that is, the first terrace widening 214 and the second terrace widening 224 have the width of 2 finger storage regions, and the area occupied by each of the first terrace region 213 and the second terrace region 223 is the width of 5 finger storage regions, wherein each of the first bridge wall 215 and the second bridge wall 225 occupies the width of one finger storage region.
In another embodiment, as shown in fig. 4, the first core region and the second core region each include 2 finger storage regions including a bridge wall, the first terrace region 213 and the second terrace region 223 extend into the adjacent core region in addition to occupying the width of the 2 finger storage regions of the core region corresponding to the first terrace region and additionally occupy the width of 1 finger storage region, that is, the first terrace widening 214 and the second terrace widening 224 have the width of 1 finger storage region, and the area occupied by each of the first terrace region 213 and the second terrace region 223 is the width of 3 finger storage regions, wherein each of the first bridge wall 215 and the second bridge wall 225 occupies the width of one finger storage region.
According to the idea of the present invention, the three-dimensional memory can be applied to a scene in which 1 block storage area includes only 1 finger storage area, or a scene in which 1 block storage area includes 4 or more finger storage areas, without being limited to the above-listed examples.
Next, the first step region 213 and the second step region 223 are manufactured by a step etching process, and steps of the first step region 213 and the second step region 223 are sequentially lowered from the corresponding core regions toward the isolation zone 247 between the first step region 213 and the second step region 223, and are cut at the isolation zone 247. The isolation strip 247 extends in a first direction (Y direction) for isolating the first stepped region 213 from the second stepped region 223.
As described above, the three-dimensional memory and the manufacturing method thereof of the present invention have the following beneficial effects:
the present invention achieves an increase in the step area width in a first direction (e.g., Y direction) for a single block storage region by a novel gate line gap (G L S) design such that the step area of a block storage region has a step extension that extends into the core area of an adjacent block storage region.
The increase of the width of the step area of the single storage area in the Y direction is beneficial to the increase of the number of subareas, meanwhile, the bridge wall has larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design difficulty of the framework of the three-dimensional memory.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (16)
1. A three-dimensional memory is characterized by comprising a first memory block and a second memory block, wherein the first memory block comprises a first core area and a first step area located in the middle of the first core area, the second memory block comprises a second core area and a second step area located in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are isolated from each other, the first step area and the second step area are adjacently arranged along a second direction and are isolated from each other, the first step area is provided with a first step widening portion extending to the inside of the second core area along the first direction, and the first step widening portion is isolated from the second core area through a first grid line gap; the second step region has a second step widening extending in a first direction back to the interior of the first core region, the second step widening being isolated from the first core region by a second gate line gap.
2. The three-dimensional memory according to claim 1, wherein: the first core area comprises a first sub-core area and a second sub-core area which are positioned at two ends of the first step area and the second step area, the first sub-core area is connected with the first step area, the second core area comprises a third sub-core area and a fourth sub-core area which are positioned at two ends of the first step area and the second step area, and the fourth core area is connected with the second step area; the first storage area further comprises a first bridging wall located on one side of the first stepped area and the second stepped area, the first bridging wall is connected with the first stepped area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall located on the other side of the first stepped area and the second stepped area, and the second bridging wall is connected with the second stepped area, the third sub-core area and the fourth sub-core area.
3. The three-dimensional memory according to claim 2, wherein: the first sub-core region and the third sub-core region are separated by a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core region and the fourth sub-core region are separated by a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
4. The three-dimensional memory according to claim 3, wherein: the first step widening portion extends to be adjacent to the second bridging wall and is isolated from the second bridging wall through a third grid line gap, the first grid line gap is connected with the third grid line gap, the second step widening portion extends to be adjacent to the first bridging wall and is isolated from the first bridging wall through a fourth grid line gap, and the fourth grid line gap is connected with the second grid line gap.
5. The three-dimensional memory according to claim 2, wherein: the first core area and the second core area comprise a plurality of finger storage areas, and the finger storage areas are isolated through inter-finger grid gaps.
6. The three-dimensional memory according to claim 5, wherein: the width of the first step widening extending into the second core region is an integer multiple of the width of the finger storage region.
7. The three-dimensional memory according to claim 5, wherein: the width of the first bridging wall and the width of the second bridging wall are between the width of 0.5 finger storage areas and the width of 2 finger storage areas.
8. The three-dimensional memory according to claim 1, wherein: the steps of the first step area and the second step area are sequentially reduced from the corresponding core areas to the isolation zones between the first step area and the second step area, and are cut off in the isolation zones.
9. The three-dimensional memory according to claim 1, wherein: the first direction and the second direction are perpendicular to each other.
10. The three-dimensional memory according to claim 1, wherein: the first core region and the second core region comprise a stack structure and a channel storage structure array penetrating through the stack structure, and the channel storage structure comprises a channel hole penetrating through the stack structure, and a memory film and a channel layer located in the channel hole.
11. A preparation method of a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, and forming a stacked structure on the substrate;
forming a first storage area and a second storage area in the stacked structure, wherein the first storage area comprises a first core area and a first step area located in the middle of the first core area, the second storage area comprises a second core area and a second step area located in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are isolated from each other, the first step area and the second step area are adjacently arranged along a second direction and are isolated from each other, the first step area is provided with a first step widening portion extending to the inside of the second core area along the first direction, and the first step widening portion is isolated from the second core area through a first grid line gap; the second step region has a second step widening extending in a first direction back to the interior of the first core region, the second step widening being isolated from the first core region by a second gate line gap.
12. The method for manufacturing a three-dimensional memory according to claim 11, wherein: the first core area comprises a first sub-core area and a second sub-core area which are positioned at two ends of the first step area and the second step area, the first sub-core area is connected with the first step area, the second core area comprises a third sub-core area and a fourth sub-core area which are positioned at two ends of the first step area and the second step area, and the fourth core area is connected with the second step area; the first storage area further comprises a first bridging wall located on one side of the first stepped area and the second stepped area, the first bridging wall is connected with the first stepped area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall located on the other side of the first stepped area and the second stepped area, and the second bridging wall is connected with the second stepped area, the third sub-core area and the fourth sub-core area.
13. The method for manufacturing a three-dimensional memory according to claim 12, wherein: the first sub-core region and the third sub-core region are separated by a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core region and the fourth sub-core region are separated by a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
14. The method for manufacturing a three-dimensional memory according to claim 13, wherein: the first step widening portion extends to be adjacent to the second bridging wall and is isolated from the second bridging wall through a third grid line gap, the first grid line gap is connected with the third grid line gap, the second step widening portion extends to be adjacent to the first bridging wall and is isolated from the first bridging wall through a fourth grid line gap, and the fourth grid line gap is connected with the second grid line gap.
15. The method for manufacturing a three-dimensional memory according to claim 12, wherein: the first core area and the second core area respectively comprise a plurality of finger storage areas, the finger storage areas are isolated by finger grid gaps, the width of a first step widening part extending to the inside of the second core area is an integral multiple of the width of the finger storage areas, the width of a first bridging wall is between 0.5 and 2 of the finger storage areas, and the width of a second bridging wall is between 0.5 and 2 of the finger storage areas.
16. The method for manufacturing a three-dimensional memory according to claim 11, wherein: the steps of the first step area and the second step area are sequentially reduced from the corresponding core areas to the isolation zones between the first step area and the second step area, and are cut off in the isolation zones.
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