CN111415939A

CN111415939A - Three-dimensional NAND memory string and preparation method thereof

Info

Publication number: CN111415939A
Application number: CN201910016421.6A
Authority: CN
Inventors: 肖德元; 张汝京
Original assignee: SiEn Qingdao Integrated Circuits Co Ltd
Current assignee: SiEn Qingdao Integrated Circuits Co Ltd
Priority date: 2019-01-08
Filing date: 2019-01-08
Publication date: 2020-07-14

Abstract

The invention provides a three-dimensional NAND memory string and a preparation method thereof, wherein the method comprises the following steps: providing a semiconductor substrate; forming a stacked structure on a semiconductor substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of sacrificial layers containing first conductive type elements which are alternately stacked; the annealing process modifies the semiconductor layer part of the second conductivity type formed in the stacked structure into a semiconductor layer of the first conductivity type; forming a composite layer on the surfaces and the side walls of the plurality of first dielectric layers and the side wall of the semiconductor layer of the first conduction type; the sacrificial layer containing the first conductive type element is removed and a control gate is formed at this position. Partially inverting the conductivity type through an annealing process to form a junction type storage unit, and connecting a plurality of storage units in series to form a three-dimensional NAND junction type storage string; the runway-shaped conductive channel layer is arranged, so that the contact area between the control gate and the composite layer can be effectively increased, the charge retention time of the NAND memory string is prolonged, and the memory performance of the NAND memory string is improved.

Description

Three-dimensional NAND memory string and preparation method thereof

Technical Field

The invention relates to the field of semiconductor memory devices, in particular to a three-dimensional NAND memory string and a preparation method thereof.

Background

As the size of memory cells of two-dimensional (2D) memory devices continues to decrease, their fabrication processes encounter various challenges, physical limits, such as exposure technology limits, development technology limits, and storage electron density limits, causing significant increases in storage signal collision and disturb so that multi-level cell (M L C) operations are difficult to perform, and as the limitations of 2D memory devices are overcome, research into memory devices having three-dimensional (3D) structures has been increasing, increasing integration density by three-dimensionally arranging memory cells on substrates in recent years.

The 3D NAND memory is a flash memory device with three-dimensional stacked memory cells, and the existing 3D NAND memory cell architecture is usually designed for vertical channel, horizontal control gate layer, compared to planar NAND memory for higher storage density per unit area.

The conventional 3D NAND is usually a junction-less (P-N junction) memory string, and generally, a dielectric layer and a sacrificial layer are alternately deposited to form a stacked structure, a through groove is formed in the stacked structure, a vertical channel is formed in the groove, the doping types of the vertical channel are the same, and the doping types of a source, a drain and a channel in a memory cell on the entire memory string are the same, so that no junction is formed. The non-junction type NAND memory has different writing and reading modes from the junction type NAND memory, and has different performances, and can be selectively used according to different use conditions.

Based on the above, it is necessary to provide a junction type 3D NAND memory string and a method for manufacturing the same.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional NAND memory string and a method for fabricating the same, which are used to solve the problem of the prior art that the structure of the three-dimensional NAND memory string has only a junction-free structure.

To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional NAND memory string, comprising:

providing a semiconductor substrate;

forming a stacked structure on the semiconductor substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of sacrificial layers containing first conductive type elements which are alternately stacked;

forming a groove through the stacked structure:

forming a semiconductor layer of a second conductivity type in the groove;

enabling a first conduction type element in the sacrificial layer containing the first conduction type element to diffuse into the semiconductor layer of the second conduction type along the transverse direction by adopting an annealing process, enabling the semiconductor layer of the second conduction type in a region corresponding to the transverse direction of the sacrificial layer containing the first conduction type element to be inverted into the semiconductor layer of the first conduction type, and forming a conduction channel layer of the three-dimensional NAND storage string by the semiconductor layer of the first conduction type and the semiconductor layer of the second conduction type;

forming a trench through and extending the entire stack;

selectively removing the sacrificial layer containing the first conductive type element to form an opening between two adjacent first dielectric layers, wherein the opening exposes the peripheral side of the first conductive type semiconductor layer;

forming a composite layer on the surfaces and the side walls of the plurality of first dielectric layers and on the periphery of the semiconductor layer of the first conductivity type, wherein the composite layer sequentially comprises a tunneling dielectric layer, a charge trapping layer and a grid dielectric layer;

and forming a control gate in the opening.

Optionally, the preparation method further comprises:

forming word line plugs on the surfaces of the control gates, and forming word lines on the tops of the sub-line plugs;

forming a second dielectric layer on the stacked structure;

and forming a bit line plug which penetrates through the second dielectric layer and is connected with the conductive channel layer, and forming a bit line on the top of the bit line plug.

Further, the step of forming the word line plug includes:

gradually etching a plurality of layers of the first dielectric layer and a plurality of layers of the control gates to form a ladder-shaped structure so as to expose each layer of the control gate;

and forming the word line plug on the exposed surface of the control gate.

Optionally, the annealing temperature of the annealing process is between 700 ℃ and 900 ℃, and the annealing time of the annealing process is between 10min and 60 min.

Optionally, the shape of the groove in the transverse direction is racetrack shaped.

Optionally, the semiconductor substrate comprises a second conductive type semiconductor substrate, active regions of a first conductive type are formed at intervals in the semiconductor substrate, and the three-dimensional NAND memory string is formed on the active regions of the first conductive type.

Optionally, the material of the first dielectric layer includes one or a combination of two or more of the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, and the material of the sacrificial layer containing the first conductive type element includes silicon glass containing the first conductive type element.

Optionally, the groove is formed by an anisotropic dry etching process, and the semiconductor layer of the second conductivity type includes polysilicon of the second conductivity type.

Optionally, the tunneling dielectric layer, the charge trapping layer and the gate dielectric layer are formed by an atomic layer deposition process or a chemical vapor deposition process, the tunneling dielectric layer is made of silicon oxide, the charge trapping layer is made of silicon nitride, and the gate dielectric layer is made of silicon oxide, aluminum oxide or a high-K dielectric.

Optionally, the control gate is formed by an organic metal chemical vapor deposition process, and a material of the control gate includes tantalum nitride or tungsten.

The present invention also provides a three-dimensional NAND memory string, wherein the three-dimensional NAND memory string at least comprises:

a semiconductor substrate;

a NAND memory string disposed in a vertical direction on the semiconductor substrate, the NAND memory string comprising:

the stacked structure comprises a plurality of first dielectric layers and a plurality of control gates which are stacked alternately;

a conductive channel layer extending in a vertical direction and passing through the stacked structure, the conductive channel layer including a plurality of first conductive type semiconductor layers and a plurality of second conductive type semiconductor layers which are alternately stacked, wherein each of the second conductive type semiconductor layers is located at the same layer as the corresponding first dielectric layer, and each of the first conductive type semiconductor layers is located at the same layer as the corresponding control gate;

and the composite layer is formed on the surfaces and the side walls of the plurality of first dielectric layers and on the periphery of the semiconductor layer of the first conductivity type, and sequentially comprises a tunneling dielectric layer, a charge trapping layer and a grid dielectric layer from inside to outside.

Optionally, the three-dimensional NAND memory string further comprises:

a plurality of word line plugs formed on the control gate surfaces;

word lines formed on top of each of the word line plugs;

the second dielectric layer is formed on the laminated structure;

a bit line plug, said bit line plug penetrating said second dielectric layer and being connected to said conductive channel layer;

a bit line formed on top of the bit line plug.

Optionally, the conductive channel layer is racetrack shaped in a lateral direction.

Optionally, the material of the first dielectric layer includes one or a combination of two or more of the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

Optionally, the semiconductor layer of the first conductivity type includes polysilicon of the first conductivity type, and the semiconductor layer of the second conductivity type includes polysilicon of the second conductivity type.

Optionally, the material of the tunneling dielectric layer includes silicon oxide, the material of the charge trapping layer includes silicon nitride, the material of the gate dielectric layer includes silicon oxide, aluminum oxide or a high-K dielectric, and the material of the control gate includes tantalum nitride or tungsten.

As described above, according to the three-dimensional NAND memory string and the method for manufacturing the same of the present invention, the first conductive type element in the sacrificial layer containing the first conductive type element is diffused into the second conductive type semiconductor layer along the lateral direction through the annealing process, so that the second conductive type semiconductor layer is inverted into the first conductive type semiconductor layer, and at this time, the second conductive type semiconductor layer is disposed on the upper and lower sides of the first conductive type semiconductor layer, thereby forming the junction type memory cell, and the three-dimensional NAND memory string manufactured by the method for manufacturing the present embodiment is formed by connecting a plurality of memory cells in series, and the three-dimensional NAND memory string is a junction type memory string; in addition, the conductive channel layer and the composite layer are arranged to be in a track shape, the track shape is larger in circumference compared with the shape without an edge angle such as a circle, the contact area between the control gate and the composite layer is correspondingly increased, when the same voltage is applied to the control gate, the contact area between the control gate and the composite layer is relatively larger, so that the constraint capacity of charges in the charge trapping layer is enhanced, the charges are not easy to leak, the charge holding time of the NAND memory string can be effectively prolonged, and the memory performance of the NAND memory string is improved.

Drawings

FIG. 1 is a flow chart illustrating a method of fabricating a three-dimensional NAND memory string according to the present invention.

Fig. 2-18 show schematic diagrams of steps of a method of fabricating a three-dimensional NAND memory string in accordance with the present invention.

FIG. 19 is a schematic diagram of a three-dimensional NAND memory string according to the present invention.

Fig. 20 is a longitudinal sectional view taken along the broken line C-C in fig. 19.

FIG. 21 shows a schematic of the shape of the three-dimensional NAND memory string of the present invention in the horizontal direction.

FIG. 22 is a schematic diagram of a word line structure for a three dimensional NAND memory string in accordance with the present invention.

Description of the element reference numerals

10 semiconductor substrate

101 active region of a first conductivity type

11 Stacking Structure

110 first dielectric layer

111 sacrificial layer comprising elements of a first conductivity type

Layer of cattle

112 groove

113 groove

114 opening

120 semiconductor layer of a second conductivity type

121 semiconductor layer of a first conductivity type

13 composite layer

131 tunneling dielectric layer

132 charge trapping layer

133 gate dielectric layer

134 control gate

140 word line plug

141 word line

15 second dielectric layer

160 bit line plug

161 bit line

20 semiconductor layer

201 active region of a first conductivity type

21 laminated structure

210 first dielectric layer

211 control gate

22 conductive channel layer

220 semiconductor layer of the second conductivity type

221 semiconductor layer of a first conductivity type

23 composite layer

230 tunnel dielectric layer

231 charge trapping layer

232 grid dielectric layer

240 word line plug

241 word line

25 second dielectric layer

260 bit line plug

261 bit line

S1-S9

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 22. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example 1

As shown in fig. 1, in the present embodiment, a stacked structure including a plurality of first dielectric layers and a plurality of sacrificial layers containing a first conductive element is formed by alternately stacking, and the first conductive element in the sacrificial layers containing the first conductive element is diffused into a semiconductor layer of a second conductive type along a lateral direction by an annealing process, so that the semiconductor layer of the second conductive type is inverted into the semiconductor layer of the first conductive type, and at this time, the upper and lower sides of the semiconductor layer of the first conductive type are the semiconductor layers of the second conductive type, thereby forming a junction type memory cell, and the plurality of memory cells are connected in series to form the three-dimensional NAND memory string manufactured by the method of the present embodiment, and the three-dimensional NAND memory string is a junction type memory string.

Before the following description of the specific method is made, it should be noted that the horizontal direction and the vertical direction are defined with reference to the semiconductor substrate in this embodiment. In addition, the first conductive type and the second conductive type refer to N type or P type in the semiconductor field, and the preparation method in this embodiment is applicable to the first conductive type being N type and also applicable to P type as long as the opposite conductive types of the first conductive type and the second conductive type are ensured. Finally, the meaning in defining a sacrificial layer containing an element of the first conductivity type is that the entry of the element of the first conductivity type in the sacrificial layer into the semiconductor can invert the semiconductor to a semiconductor of the first conductivity type.

Specifically, as shown in fig. 2 to 18, schematic structural diagrams presented in each step of the method for manufacturing a three-dimensional NAND memory string in the present embodiment are illustrated.

As shown in fig. 1 and 2, step S1 is performed to provide a semiconductor substrate 10.

The semiconductor substrate 10 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or may be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator (SOI), which is not listed here. In this embodiment, the semiconductor substrate 10 is silicon.

As illustrated in fig. 2, isolation is typically provided in the semiconductor substrate 10 to form active regions on or in which subsequent components are formed. There are many ways to form active regions, such as forming shallow trench isolation in a semiconductor substrate, and also by using P-N junction isolation. In this embodiment, a P-N junction isolation manner is adopted, specifically, the semiconductor substrate 10 is a second conductive type semiconductor substrate, and ions of a first conductive type are implanted into the semiconductor substrate 10 by an ion implantation method, so as to form the active region 101 of the first conductive type.

As shown in fig. 1 and fig. 3, next, in step S2, a stacked structure 11 is formed on the semiconductor substrate 10, where the stacked structure 11 includes a plurality of first dielectric layers 110 and a plurality of sacrificial layers 111 containing the first conductive type element, which are alternately stacked.

As shown in fig. 3, in an actual process, the specific number of layers of the first dielectric layer 110 and the sacrificial layer 111 containing the first conductive type element may be selected according to needs, and only 3 layers of the first dielectric layer 110 and 3 layers of the sacrificial layer 111 containing the first conductive type element are illustrated in fig. 3.

In the stacked structure 11, the sacrificial layer 111 containing the first conductive type element is used to occupy a position for subsequently forming a control gate, the sacrificial layer 111 containing the first conductive type element is subsequently removed, and the control gate is formed in a position left after the sacrificial layer 111 containing the first conductive type element is removed. The first dielectric layer 110 is located between two adjacent control gates to achieve electrical isolation, and electrically isolates a subsequently formed conductive channel layer and a composite layer.

As an example, the first dielectric layer 110 and the sacrificial layer 111 containing the first conductive type element are made of different materials, so that in a subsequent process of removing the sacrificial layer 111 containing the first conductive type element, the sacrificial layer 111 containing the first conductive type element has a higher etching selection ratio relative to the first dielectric layer 110, thereby ensuring that the first dielectric layer 110 has a good appearance and an accurate size, and further ensuring that a subsequently formed control gate has a good appearance and an accurate size. In addition, since the sacrificial layer 111 containing the first conductive type element is to perform the function of diffusing the first conductive type element contained therein in the annealing process subsequently, it is preferable that the material of the sacrificial layer 111 containing the first conductive type element includes silicon glass containing the first conductive type element, and the material of the first dielectric layer 110 includes one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, so that the first conductive type element diffusion can be effectively achieved while the etching selection ratio between the two is ensured. For example, when the sacrificial layer 111 containing the first conductive type element is N-type, the sacrificial layer 111 containing the first conductive type element is phosphosilicate glass (PSG); when the sacrificial layer 111 containing the first conductive type element is P-type, the sacrificial layer 111 containing the first conductive type element is borosilicate glass (BSG for short). Of course, the sacrificial layer 111 containing the first conductive type element may be made of other materials as long as the requirement of diffusing the first conductive type element contained therein in the annealing process is satisfied.

As shown in fig. 1 and 4, step S3 is performed to form a groove 112 penetrating through the stacked structure 11.

To facilitate understanding of the process of the present manufacturing method, fig. 4 is a longitudinal sectional view taken along the a-a position in fig. 3, so that the inside of the groove 112 can be seen in fig. 4.

As an example, the process of forming the groove 112 is an anisotropic dry etching process, such as an anisotropic plasma etching process or a reactive ion etching process, and specifically, a patterned mask layer is formed on the stacked structure 11, where the patterned mask layer defines the position of the groove; etching the stacked structure 11 by using the patterned mask layer as a mask until the surface of the semiconductor substrate 10 is exposed, and forming the groove 112 penetrating through the stacked structure 11; and then, removing the patterned mask layer.

It should be noted that the material of the patterned mask layer is different from the material of the first dielectric layer 110 and the material of the sacrificial layer 111 containing the first conductive type element, so that in the process of etching the stacked structure 11, the first dielectric layer 110 and the sacrificial layer 111 containing the first conductive type element have a higher etching selectivity ratio with respect to the patterned mask layer, and the pattern of the patterned mask layer can be relatively stable. In addition, the patterned mask layer needs to be made of a material with a relatively high physical strength, so as to prevent the patterned mask layer from being completely removed during the etching of the stacked structure 11. In this embodiment, the material of the patterned mask layer includes amorphous carbon.

By way of example, as shown in the cross-sectional view of fig. 10, the groove 112 is shown as being racetrack shaped. The racetrack shape has a relatively large perimeter compared to the non-angular shape such as circular shape, so the contact area (termed Coupling) between the control gate and the composite layer formed subsequently around the recess 112 is correspondingly increased. The beneficial effect of increasing Coupling will be described in detail later, and will not be described herein.

As shown in fig. 1 and fig. 5, step S4 is performed to form a semiconductor layer 120 of the second conductivity type in the recess 112.

As an example, the material of the second conductive type semiconductor layer 120 includes a second conductive type polysilicon.

The method of forming the second conductive type semiconductor layer 120 includes: firstly, forming a semiconductor layer initial layer of a second conductivity type in the groove 112 and on the top surface of the stacked structure 11, wherein the process may be a chemical vapor deposition process or an epitaxial process; then, a planarization process, such as a chemical mechanical polishing process or a dry etching process, is used to remove the initial layer above the top surface of the stack 11, so as to form the semiconductor layer 120 of the second conductivity type filling the recess 112, wherein the semiconductor layer 120 of the second conductivity type is flush with the top surface of the stack 11.

As shown in fig. 1 and 6, step S5 is performed to laterally diffuse the first conductive type element in the sacrificial layer 111 containing the first conductive type element into the semiconductor layer 120 of the second conductive type by an annealing process, so that the semiconductor layer 120 of the second conductive type in the region laterally corresponding to the sacrificial layer containing the first conductive type element is inverted into the semiconductor layer 121 of the first conductive type, and the conductive channel layer 12 of the three-dimensional NAND memory string is formed by the semiconductor layer 121 of the first conductive type and the semiconductor layer 120 of the second conductive type.

As an example, the annealing temperature of the annealing process is between 700 ℃ and 900 ℃, and the annealing time of the annealing process is between 10min and 60 min; in this embodiment, the annealing temperature of the annealing process is 800 ℃, and the annealing time of the annealing process is 30 min. In the annealing process, the first dielectric layer 110 is an insulating structure, the semiconductor layer 120 of the second conductivity type is a semiconductor structure, and the semiconductor structure is more easily doped compared with the lattice structures of the two, and the insulating structure is relatively more stable, so that the semiconductor layer 120 of the second conductivity type is more easily doped and inverted during the annealing process, and relatively, the first dielectric layer 110 is stable in property and is not easily doped.

After step S5, the second conductivity-type semiconductor layer 120 is partially inverted into the first conductivity-type semiconductor layer 121, so that the upper and lower sides of each first conductivity-type semiconductor layer 121 are the second conductivity-type semiconductor layers 120, and this structure is a channel region (i.e., the first conductivity-type semiconductor layer 121) and a source-drain region (i.e., the second conductivity-type semiconductor layer 120) of each memory cell in the three-dimensional NAND memory string, and adjacent source-drain regions are shared, thereby forming the three-dimensional NAND memory string with a series structure.

As shown in fig. 1 and 7, step S6 is performed to form trench 113 penetrating and extending the entire stacked structure 11.

The method for forming the trench 113 is similar to the method for forming the recess 112, and therefore, the detailed description thereof is omitted here.

It should be noted that the trench 113 formed in the present embodiment extends over the entire stacked structure 11, and forms a canal shape with no control at both ends.

As shown in fig. 1 and fig. 8, step S7 is continued, in which the sacrificial layer 111 containing the first conductive type element is selectively removed, so as to form an opening 114 between two adjacent first dielectric layers 110, and the opening 114 exposes the peripheral side of the first conductive type semiconductor layer 121.

After step S7, the resulting structure resembles a fin.

As shown in fig. 1, 9 and 10, step S8 is performed to form a composite layer 13 on the surfaces and sidewalls of the first dielectric layers 110 and the periphery of the first conductive type semiconductor layer 121, where the composite layer 13 sequentially includes a tunnel dielectric layer 131, a charge-trapping layer 132 and a gate dielectric layer 133 (i.e., an ONO structure layer).

Fig. 10 is a transverse cross-sectional view taken along line B-B in fig. 9, and shapes of the semiconductor layer 121 of the first conductivity type and the composite layer 13 are sequentially increased racetrack shapes.

As an example, the process of forming the composite layer 13 includes an atomic layer deposition process, a chemical vapor deposition process, and the like, and in order to make the thickness of the composite layer 13 uniform and the shape good, a furnace tube process may be selected to form the composite layer 13. The material of the tunnel dielectric layer 131 comprises silicon oxide, the material of the charge trapping layer 132 comprises silicon nitride, and the material of the gate dielectric layer 133 comprises silicon oxide, aluminum oxide or high-K dielectric.

Here, since the composite layer 13 is an insulating layer, the composite layer formed on the surface of the conductive trench layer 12 and the composite layer formed on the surface of the semiconductor substrate 10 may be removed or not removed, and the removal or not removal may be selected according to the specific situation.

As shown in fig. 1 and fig. 11 to 13, step S9 is finally performed to form a control gate 134 in the opening 114.

The material of the control gate 134 includes tantalum nitride or tungsten, for example, but may be other metal materials.

As shown in fig. 11 and 12, the control gate 134 is formed by: as shown in fig. 11, an initial layer of the control gate 134 is formed in the trench 113 and the opening 114 by a Metal Organic Chemical Vapor Deposition (MOCVD); as shown in fig. 12, an initial layer of the control gate 134 formed in the trench 113 is removed by a dry etching process to form the control gate 134 in the opening 114.

Fig. 13 is a transverse cross-sectional view taken along line B-B in fig. 12, in which the conductive channel layer 12 and the composite layer 13 are both racetrack shaped, and the perimeter of the racetrack shaped is relatively larger than that of a non-angular shape such as a circle, so that the contact area (termed Coupling) between the control gate 134 and the composite layer 13 is correspondingly increased, and when the same voltage is applied to the control gate 134, the contact area (termed Coupling) between the control gate 134 and the composite layer 13 is relatively larger, so that the binding capability to charges in the charge trapping layer 132 is enhanced, the charges are not easy to leak, the charge retention time of the NAND memory string can be effectively prolonged, and the memory performance of the NAND memory string can be improved.

As an example, the process of forming the three-dimensional NAND memory string further includes a process of forming word lines and bit lines, specifically:

as shown in fig. 14 and 15, word line plugs 140 are formed on the surfaces of the control gates 134 and word lines 141 are formed on the top of the sub-line plugs, and preferably, the step of forming the word line plugs 140 includes: firstly, a plurality of layers of the first dielectric layer 110 and a plurality of layers of the control gates 134 are etched step by step to form a ladder-shaped structure so as to expose each layer of the control gates 134, and then the word line plugs 140 are formed on the surfaces of the exposed control gates 134;

as shown in fig. 16, a second dielectric layer 15 is formed on the stacked structure 11;

as shown in fig. 17, a bit line plug 160 is formed through the second dielectric layer 15 and connected to the conductive channel layer 12, and a bit line 161 is formed on top of the bit line plug 160.

Fig. 18 is a longitudinal cross-sectional view taken along line C-C in fig. 17, in which a dashed-line D frame is a memory cell on a three-dimensional NAND memory string, and each of the memory cells is a junction-type memory cell. Each memory cell is connected in series to form the three-dimensional NAND memory string.

As an example, in a string of the three-dimensional NAND memory string, the uppermost memory cell and the lowermost memory cell of the three-dimensional NAND memory string may be non-memory cells without memory function, i.e., select transistors, as the upper select gate and the lower select gate of the three-dimensional NAND memory string, and the middle memory cells may be memory cells with memory function.

Example 2

As shown in fig. 19 to 22, this embodiment provides a three-dimensional NAND memory string, which can be prepared by the preparation method described in embodiment 1, or by other methods, which are not limited herein. The three-dimensional NAND memory string includes at least:

a semiconductor substrate 20;

a NAND memory string disposed on the semiconductor substrate 20 in a vertical direction, the NAND memory string comprising:

the stacked structure comprises a plurality of first dielectric layers 210 and a plurality of control gates 211 which are stacked alternately;

a conductive channel layer 22 extending in a vertical direction and penetrating through the stacked structure, the conductive channel layer 22 including a plurality of first conductive type semiconductor layers 221 and a plurality of second conductive type semiconductor layers 220 alternately stacked, wherein each of the second conductive type semiconductor layers 220 is located at the same layer as the corresponding first dielectric layer 210, and each of the first conductive type semiconductor layers 221 is located at the same layer as the corresponding control gate 211;

a composite layer 23 formed on the surfaces and sidewalls of the plurality of first dielectric layers 210 and on the periphery of the first conductive type semiconductor layer 221, wherein the composite layer 23 sequentially includes a tunneling dielectric layer 230, a charge trapping layer 231, and a gate dielectric layer 232 from inside to outside.

Fig. 20 is a longitudinal cross-sectional view taken along line C-C in fig. 19, where a dashed line frame D is a memory cell on a three-dimensional NAND memory string, a channel region of the memory cell is formed by the first conductivity-type semiconductor layer 221 in each memory cell, source and drain regions of the memory cell are formed by upper and lower layers of the second conductivity-type semiconductor layer 220 on the first conductivity-type semiconductor layer 221, a charge storage region of the memory cell is formed by the composite layer 23, and a gate of the memory cell is formed by the control gate 211, so that the memory cell is formed as a junction-type memory cell. In addition, each memory cell shares a source drain, and adjacent memory cells are connected in series, so that a series-connected junction type three-dimensional NAND memory string is formed.

Fig. 21 is a transverse cross-sectional view taken along line B-B in fig. 20, in which the conductive channel layer 22 and the composite layer 23 are both racetrack shaped, and the perimeter of the racetrack shaped is relatively larger than that of a non-angular shape such as a circle, so that the contact area (termed Coupling) between the control gate 211 and the composite layer 23 is correspondingly increased, and when the same voltage is applied to the control gate 211, the contact area (termed Coupling) between the control gate 211 and the composite layer 23 is relatively larger, so that the binding capability to charges in the charge trapping layer 231 is enhanced, the charges are not easy to leak, the charge retention time of the NAND memory string can be effectively prolonged, and the memory performance of the NAND memory string can be improved.

As an example, as shown in fig. 19 and 22, the three-dimensional NAND memory string further includes:

a plurality of word line plugs 240, a plurality of word line plugs 240 being formed on a surface of each of the control gates 211;

word lines 241, the word lines 241 being formed on top of each of the word line plugs 240;

a second dielectric layer 25, the second dielectric layer 25 being formed on the laminated structure;

a bit line plug 260, said bit line plug 260 extending through said second dielectric layer 25 and being connected to said conductive channel layer 22;

a bit line 261, the bit line 261 being formed on top of the bit line plug 260.

The semiconductor substrate 20 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or may be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator (SOI), which is not listed here. In this embodiment, the semiconductor substrate 20 is silicon.

As illustrated in fig. 19, isolation is typically provided in the semiconductor substrate 20 to form active regions on or in which subsequent components are formed. There are many ways to form active regions, such as forming shallow trench isolation in a semiconductor substrate, and also by using P-N junction isolation. In this embodiment, a P-N junction isolation manner is adopted, specifically, the semiconductor substrate 20 is a second conductive type semiconductor substrate, and ions of a first conductive type are implanted into the semiconductor substrate 20 by an ion implantation method, so as to form an active region 201 of the first conductive type.

As an example, the material of the first dielectric layer 210 includes one or a combination of two or more of the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

As an example, the first conductive type semiconductor layer 221 includes a first conductive type polysilicon, and the second conductive type semiconductor layer 220 includes a second conductive type polysilicon.

As an example, the material of the tunnel dielectric layer 230 includes silicon oxide, the material of the charge trapping layer 231 includes silicon nitride, the material of the gate dielectric layer 232 includes silicon oxide, aluminum oxide or high-K dielectric, and the material of the control gate 211 includes tantalum nitride or tungsten.

In summary, according to the three-dimensional NAND memory string and the method for manufacturing the same of the present invention, the annealing process is performed to laterally diffuse the first conductive type element in the sacrificial layer containing the first conductive type element into the second conductive type semiconductor layer, so that the second conductive type semiconductor layer is inverted into the first conductive type semiconductor layer, and the second conductive type semiconductor layer is disposed on the upper and lower sides of the first conductive type semiconductor layer, thereby forming a junction type memory cell, and a plurality of memory cells are connected in series to form the three-dimensional NAND memory string manufactured by the method for manufacturing the present embodiment, and the three-dimensional NAND memory string is a junction type memory string; in addition, the conductive channel layer and the composite layer are arranged to be in a track shape, the track shape is larger in circumference compared with the shape without an edge angle such as a circle, the contact area between the control gate and the composite layer is correspondingly increased, when the same voltage is applied to the control gate, the contact area between the control gate and the composite layer is relatively larger, so that the constraint capacity of charges in the charge trapping layer is enhanced, the charges are not easy to leak, the charge holding time of the NAND memory string can be effectively prolonged, and the memory performance of the NAND memory string is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a three-dimensional NAND memory string is characterized by at least comprising the following steps:

providing a semiconductor substrate;

forming a groove through the stacked structure:

forming a semiconductor layer of a second conductivity type in the groove;

forming a trench through and extending the entire stack;

and forming a control gate in the opening.

2. The method of fabricating a three-dimensional NAND memory string in accordance with claim 1, further comprising:

forming a second dielectric layer on the stacked structure;

3. The method of claim 2, wherein the step of forming the word line plug comprises:

and forming the word line plug on the exposed surface of the control gate.

4. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: the annealing temperature of the annealing process is between 700 and 900 ℃, and the annealing time of the annealing process is between 10 and 60 minutes.

5. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: the shape of the groove in the transverse direction is a racetrack shape.

6. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: the semiconductor substrate comprises a semiconductor substrate of a second conduction type, active regions of a first conduction type are formed in the semiconductor substrate at intervals, and the three-dimensional NAND memory string is formed on the active regions of the first conduction type.

7. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: the material of the first dielectric layer comprises one or more of the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide, and the material of the sacrificial layer containing the first conductive element comprises silicon glass containing the first conductive element.

8. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: and forming the groove by adopting an anisotropic dry etching process, wherein the semiconductor layer of the second conduction type comprises polycrystalline silicon of the second conduction type.

9. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: the tunneling dielectric layer, the charge trapping layer and the grid dielectric layer are formed by adopting an atomic layer deposition process or a chemical vapor deposition process, the tunneling dielectric layer is made of silicon oxide, the charge trapping layer is made of silicon nitride, and the grid dielectric layer is made of silicon oxide, aluminum oxide or a high-K dielectric.

10. The method of fabricating a three-dimensional NAND memory string as recited in claim 1, wherein: and forming the control gate by adopting an organic metal chemical vapor deposition process, wherein the material of the control gate comprises tantalum nitride or tungsten.

11. A three-dimensional NAND memory string, comprising at least:

a semiconductor substrate;

12. The three-dimensional NAND memory string of claim 11, further comprising:

a plurality of word line plugs formed on the control gate surfaces;

word lines formed on top of each of the word line plugs;

the second dielectric layer is formed on the laminated structure;

a bit line formed on top of the bit line plug.

13. The three-dimensional NAND memory string of claim 11, wherein: the shape of the conductive channel layer in the transverse direction is a racetrack shape.

14. The three-dimensional NAND memory string of claim 11, wherein: the semiconductor substrate comprises a semiconductor substrate of a second conduction type, active regions of a first conduction type are formed in the semiconductor substrate at intervals, and the three-dimensional NAND memory string is formed on the active regions of the first conduction type.

15. The three-dimensional NAND memory string of claim 11, wherein: the material of the first dielectric layer comprises one or a combination of more than two of the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide.

16. The three-dimensional NAND memory string of claim 11, wherein: the semiconductor layer of the first conductivity type includes a polysilicon of the first conductivity type, and the semiconductor layer of the second conductivity type includes a polysilicon of the second conductivity type.

17. The three-dimensional NAND memory string of claim 11, wherein: the tunneling dielectric layer is made of silicon oxide, the charge trapping layer is made of silicon nitride, the grid dielectric layer is made of silicon oxide, aluminum oxide or high-K dielectric, and the control grid is made of tantalum nitride or tungsten.