CN109390348A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109390348A CN109390348A CN201811233678.9A CN201811233678A CN109390348A CN 109390348 A CN109390348 A CN 109390348A CN 201811233678 A CN201811233678 A CN 201811233678A CN 109390348 A CN109390348 A CN 109390348A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Semiconductor Memories (AREA)
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.3D memory device includes: substrate；Positioned at the laminated construction of the substrate, including the multiple grid conductors and multiple interlayer insulating films being alternately stacked, the grid conductor positioned at bottom is as bottom selection gate；Through multiple channel columns of the laminated construction；Through multiple false channel columns of the laminated construction；Positioned at the epitaxial layer of the multiple channel column and multiple false channel column bottoms, wherein the bottom selection gate and the epitaxial layer adjacent being located in the multiple channel column are not abutted with the epitaxial layer being located in the multiple false channel column.In the 3D memory device, the epitaxial layer of corresponding position and bottom selection gate are adjacent below channel column, the epitaxial layer of corresponding position is not abutted with bottom selection gate below false channel column, it fundamentally avoids and the problem of current leakage caused by bottom selection gate is connected to epitaxial layer occurs, to improve the yield and reliability of 3D memory device.
Description
Technical field
The present invention relates to memory technology fields, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor forms the storage unit with store function using single-groove road group (Single Channel Formation, SCF) structure
String.Since distribution density of the channel hole in each region of laminated construction is different, etch-rate to each region and
The polymer thickness generated in etching process will appear difference, cause the channel hole that formation is etched in each region width and
Depth is inconsistent, this phenomenon be commonly referred to as etching load effect (Etch loading effect).For example, being deposited in some 3D
In memory device, the channel pore size distribution density of fringe region is less than the channel pore size distribution density of intermediate region, leads to fringe region
The width in channel hole is greater than the channel hole width of intermediate region, is unfavorable for the growth of epitaxial layer；Further, since in fringe region
Hydrogen-rich or nitrogen ease gas are difficult to clean out completely, can equally hinder the growth of the epitaxial layer in fringe region, be easy to cause edge
There is phenomena such as height is insufficient, defect is excessive in the epitaxial layer in region.In grid conductor displacement sacrificial layer, has defective extension
Layer will lead to bottom selection gate (Bottom Select Gate, BSG) and the performance issues such as current leakage occurs.
It is expected that be further improved 3D memory device structure and its manufacturing method, with improve 3D memory device yield and can
By property.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of 3D memory device and its manufacturing methods, wherein channel
The epitaxial layer of corresponding position and bottom selection gate are adjacent below column, and the epitaxial layer of corresponding position and bottom are selected below false channel column
Grid is selected not abut, from avoid the problem that between bottom selection gate and epitaxial layer occur leakage of current.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: substrate；Positioned at the folded of the substrate
Layer structure, the laminated construction includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked, described in bottom
Grid conductor is as bottom selection gate；Through multiple channel columns of the laminated construction；Through the multiple of the laminated construction
False channel column；And the epitaxial layer positioned at the multiple channel column and multiple false channel column bottoms, wherein the bottom selection grid
Pole and the epitaxial layer adjacent being located in the multiple channel column, with the epitaxial layer being located in the multiple false channel column
It does not abut.
Preferably, the bottom selection gate includes at least one opening, at least one opening and the multiple vacation
The position of channel column is corresponding, and the opening is filled by the corresponding interlayer insulating film.
Preferably, the laminated construction includes intermediate region and the stepped area adjacent with the intermediate region.
Preferably, the channel column is located at the intermediate region of the laminated construction, and the vacation channel column is located at described
The intermediate region of laminated construction and/or the stepped area.
The epitaxial layer being preferably located in the channel column is extended to from the substrate positioned at the bottom selection grid
The corresponding position of the interlayer insulating film of pole upper surface.
Preferably, further includes: the cmos circuit in the substrate, the cmos circuit pass through conductive channel and outside
It is electrically connected between circuit.
According to another aspect of the present invention, a kind of manufacturing method of 3D memory device is provided, comprising: be formed on the substrate folded
Layer structure, the laminated construction includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked, described in bottom
Grid conductor is as bottom selection gate；Form the multiple channel columns for running through the laminated construction；It is formed and runs through the lamination knot
Multiple false channel columns of structure；And form the epitaxial layer for being located at the multiple channel column and multiple false channel column bottoms, wherein institute
The epitaxial layer adjacent stating bottom selection gate and being located in the multiple channel column, and is located in the multiple false channel column
The epitaxial layer do not abut.
Preferably, the step of laminated construction is formed on the substrate includes: the insulation sequentially formed above the substrate
Layer and bottom selection gate sacrificial layer；Formed run through the bottom selection gate at least one opening, it is described at least one open
Mouth is corresponding with the position of the multiple false channel column；Form the insulating laminate structure being located above the bottom selection gate, institute
Stating insulating laminate structure includes the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked, the bottom selection gate sacrificial layer
It is isolated with the multiple sacrificial layer by the interlayer insulating film；The multiple sacrificial layer is patterned step-like；And by institute
It states bottom selection gate sacrificial layer and the multiple sacrificial layer is replaced as the multiple grid conductor.
Preferably, the channel column is located at the intermediate region of the laminated construction, and the vacation channel column is located at the lamination
The intermediate region of structure and/or stepped area.
The epitaxial layer being preferably located in the channel column is extended to from the substrate positioned at the bottom selection grid
The corresponding position of the interlayer insulating film of pole upper surface.
Preferably, further includes: formed be located at the substrate in cmos circuit, the cmos circuit by conductive channel with
It is electrically connected between external circuit.
3D memory device provided by the invention and its manufacturing method are sacrificed in layer formation process in bottom selection gate, are gone
Bottom selection gate sacrificial layer in addition to being located at false channel column corresponding position, thus in 3D memory device, phase below channel column
Answer epitaxial layer and the bottom selection gate of position adjacent, the epitaxial layer and bottom selection gate of false channel column lower section corresponding position are not
It is adjacent.During in bottom, selection gate sacrificial layer is replaced as grid conductor, fundamentally avoid occur grid conductor with
Caused by epitaxial layer connection the problem of current leakage, to improve the yield and reliability of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device according to an embodiment of the present invention.
Fig. 3 a to 3k shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor forms the storage unit with store function using single-groove road group (Single Channel Formation, SCF) structure
String.It is formed after channel hole in stacked structure, due to etching load effect (Etch loading effect), will lead to side
The polymeric layer of edge thickeies.Further, since hydrogen-rich in edge isolation area or nitrogen ease gas are difficult to clean out completely, can hinder every
Growth from the epitaxial layer in area will appear the infull problem of growth so as to cause the epitaxial layer in edge isolation area, cause in grid
When the conductor displacement sacrificial layer of pole, grid conductor is connected to epitaxial layer, to bottom selection gate (Bottom Selective occur
Gate, BSG) be connected to epitaxial layer caused by current leakage the problem of.
Present inventor notices the problem of yield and reliability of above-mentioned influence 3D memory device, thus propose into
The improved 3D memory device of one step and its manufacturing method.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included
Grid conductor 122 and 123, memory transistor M1 to M4 respectively include grid conductor 121.Grid conductor 121,122 and 123 with deposit
The stacking order of transistor in storage unit string 100 is consistent, is separated each other using interlayer insulating film between adjacent grid conductor,
To form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 runs through gate stack knot
Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111
Layer 113 and block media layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor
Block media layer 114 is accompanied between 123 and channel layer 111, to form first choice transistor Q1 and the second selection transistor
Q2。
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride of the particle comprising metal or semiconductor, grid conductor 121,122 and 123 are made of metal, such as
Tungsten.Channel layer 111 is used to provide the channel region of control selection transistor and memory transistor, the doping type of channel layer 111 and choosing
It is identical with the type of memory transistor to select transistor.For example, for the selection transistor and memory transistor of N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used
Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors
And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed
The semiconductor layer and block media layer of two selection transistor Q2 and the semiconductor layer and block media of memory transistor M1 to M4
Layer.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string respectively includes respective channel column 110 and public grid is led
Body 121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100, adjacent
It is separated each other using interlayer insulating film between the grid conductor connect, to form rhythmic structure of the fence 120.Interlayer is being not shown in the figure
Insulating layer.
The internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.Channel column 110 is folded through grid
Layer structure 120, and it is arranged in array, the first end of multiple channel columns 110 of same row is commonly connected to same bit line (i.e.
One of bit line BL1 to BL4), second end is commonly connected to substrate 101, and second end forms common source via substrate 100 and connects.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 161
Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely
One of SSL4).
The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and
The grid conductor 121 of M4 is divided into different grid lines by grid line gap 161, then the grid line of same level is via respective conductive logical
Road 131 reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline (i.e. wordline WL1 is connected to via conductive channel 133
One of to WL4).
The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2
123 are divided into different grid lines by grid line gap 161, then grid line reaches interconnection layer 132 via respective conductive channel 131, from
And it is interconnected amongst one another, then via with the being connected to same selection line GSL of conductive channel 133.
Fig. 3 a to 3k shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.Described section
Face figure is intercepted along the AA line in Fig. 2.
This method starts from forming 153 (BSG Gate of bottom selection gate oxide layer in semiconductor substrate 101
OX) and the semiconductor structure of bottom selection gate sacrificial layer 154 (BSG SIN), as shown in Figure 3a.
Bottom selection gate oxide layer 153 is, for example, silica, and thickness is, for example, 180 angstroms, bottom selection gate sacrificial layer
154 be, for example, silicon nitride, and thickness is, for example, 390 angstroms.Form bottom selection gate oxide layer 153 and bottom selection gate sacrificial layer
154 method is, for example, atomic layer deposition (Atomic Layer Deposition, ALD), physical vapour deposition (PVD) (Physical
Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD), it is preferred to use
Plasma activated chemical vapour deposition.
Further, mask, including patterned photoresist mask are formed on bottom selection gate sacrificial layer 154
156 and hard mask 155, as shown in Figure 3b.
Photoresist mask 156 can be selectively cleared and have the thickness for being enough to prevent recess, photoresist
Mask 156 is, for example, praseodymium (Pr), and hard mask 155 is, for example, silicon oxynitride (SiON) or silica.Utilize photoresist mask
156 pattern etch hard mask 155 makes hard mask 155 have opening in corresponding position.Preferably, after the etching by
Removal photoresist mask 156 is dissolved or is ashed in solvent.
Further, using hard mask 155 in bottom selection gate oxide layer 153 and bottom selection gate sacrificial layer 154
On etch groove, as shown in Figure 3c.
In this embodiment it is possible to using anisotropic etching, for example, by using dry etching, such as ion beam milling etching, from
Sub- etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in the oxidation of bottom selection gate
153 inside of layer or the surface of substrate 101 nearby stop.
Further, hard mask 155 is removed, forms insulating layer 151 in the trench, as shown in Figure 3d.Remove hard mask 155
Method pass through control such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation for example, by using dry etching
Etching period nearby stops so that being etched in 154 surface of bottom selection gate sacrificial layer.The method for forming oxide is, for example, original
Sublayer deposition or chemical vapor deposition.
Further, planarization process is carried out to semiconductor structure, planarizes semicon-ductor structure surface, such as Fig. 3 e institute
Show.For example, by using chemically mechanical polishing (Chemical Mechanical Polishing, CMP) method.Preferably, in chemical machine
After tool polishing, further include the steps that removing remaining barrier layer 165 using isotropic etching, so that semiconductor structure
Surface planarisation.Isotropic etching can be using the wet etching or gas phase etching of selectivity.Erosion is used in wet etching
Etching solution is as etchant, wherein in the etch solution by semiconductor structure submergence.Made in gas phase etching using etching gas
For etchant, wherein semiconductor structure to be exposed in etching gas.
Further, insulating laminate structure is formed on semiconductor structure, as illustrated in figure 3f.The insulating laminate structure includes
The multiple interlayer insulating films 151 and multiple sacrificial layers 152 being alternately stacked.In this embodiment, semiconductor substrate 101 is, for example, single
Crystalline silicon substrate, interlayer insulating film 151 are for example made of silica, and sacrificial layer 152 is for example made of silicon nitride.
As described below, sacrificial layer 152 will be substituted for grid conductor, and grid conductor is further attached to wordline.For shape
At the conductive channel for reaching wordline from grid conductor, multiple sacrificial layers 152 are for example patterned step-like, that is, each sacrificial layer
152 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 152
Later, insulating laminate structure can be covered using insulating layer.In Fig. 3 g by the interlayer insulating film between multiple sacrificial layers 152
151 integrally show with the interlayer insulating film for covering insulating laminate structure.However, the invention is not limited thereto, it can be using multiple only
Vertical deposition step is formed between multiple sacrificial layers 152 and its interlayer insulating film of top.
Further, multiple channel holes 119 are formed in semiconductor structure and insulating laminate structure, as shown in figure 3g.
In this embodiment it is possible to using anisotropic etching, for example, by using dry etching, such as ion beam milling etching, from
Sub- etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched under the surface of substrate 101
Side nearby stops.
Further, epitaxial layer 116 is formed in channel hole 119, as illustrated in figure 3h.
Epitaxial layer 116 is, for example, silicon selective epitaxial growth layer (Silicon epitaxial growth, SEG).At this
Epitaxial layer 116 and bottom selection grid in embodiment, in the channel hole for being used to form false channel column of insulating laminate structure
Pole sacrificial layer 154 does not abut, epitaxial layer 116 and bottom in the channel hole for being used to form channel column of insulating laminate structure
Selection gate sacrificial layer 154 is adjacent.
Further, in the intermediate region (core region) of semiconductor structure and insulating laminate structure, formation runs through
The channel column 110 of insulating laminate structure, and false channel column 140, as shown in figure 3i.In a preferred embodiment, false channel column 140
It may be located in the stepped area (stair-step region) of insulating laminate structure.
In this embodiment, the epitaxial layer 116 Yu bottom selection gate sacrificial layer 154 of 110 lower section corresponding position of channel column
Adjacent, the epitaxial layer 116 of false 140 lower section corresponding position of channel column is not abutted with bottom selection gate sacrificial layer 154.
The lower part of channel column 110 includes epitaxial layer 116.Further, channel column 110 includes extending to extension from upper part
The channel layer 111 of layer 116.As shown, channel column 110 includes being sequentially stacked on channel layer in the middle section of channel column 110
Tunneling medium layer 112, charge storage layer 113 and block media layer 114 on 111, at the both ends of channel column 110, channel column 110
Including the block media layer 114 being stacked on channel layer 111 or epitaxial layer 116.The lower end of channel column 110 and semiconductor substrate
High pressure p-well 103 in 101 is in contact.In final 3D memory device, the upper end of channel column 110 is connected with bit line, thus
Form effective storage unit.
The internal structure of false channel column 140 and channel column 110 can be identical or different, and at least across rhythmic structure of the fence
In at least part grid conductor.In final 3D memory device, false channel column 140 is not connected with bit line, thus
It is provided solely for mechanical support effect, without being used to form selection transistor and memory transistor.Therefore, false channel column 140 does not have
To form effective storage unit.
In this embodiment, channel column 110 further includes the insulating layer 115 as core, channel layer 111, tunneling medium layer
112, charge storage layer 113 and block media layer 114 form the laminated construction for surrounding core.In alternate embodiments, channel
Insulating layer 115 can be saved in column 110.
Further, grid line gap 161 (referring to fig. 2) is formed in insulating laminate structure, using multiple interlayer insulating films
151 are used as etching stopping layer, pass through etching removal sacrificial layer 152 and bottom selection gate sacrificial layer 154 via grid line gap 161
To form cavity, and use metal layer filling cavity to form grid conductor 122, wherein multiple grid conductors 122 and multiple
Interlayer insulating film 151 is alternately stacked, so that multiple channel columns 110 run through rhythmic structure of the fence, as shown in Fig. 3 j.
When forming grid line gap 161, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in semiconductor lining
The surface at bottom 101 nearby stops.
In this embodiment, grid conductor 122 is divided into a plurality of grid line by grid line gap 161.For this purpose, grid line gap 161
Through insulating laminate structure.
It is folded using isotropic etching removal insulation using grid line gap 161 as etchant channel when forming cavity
Sacrificial layer 152 and bottom selection gate sacrificial layer 154 in layer structure is to form cavity.Isotropic etching can be using choosing
The wet etching or gas phase etching of selecting property.Use etching solution as etchant in wet etching, wherein by semiconductor structure
Submergence is in the etch solution.Use etching gas as etchant in gas phase etching, wherein semiconductor structure is exposed to erosion
It carves in gas.
What interlayer insulating film 151 and sacrificial layer 152 in insulating laminate structure were made of silica and silicon nitride respectively
Under situation, C can be used in gas phase etching using phosphoric acid solution as etchant in wet etching4F8、C4F6、
CH2F2And O2One of or it is a variety of.In an etching step, etchant is full of grid line gap 161.It is sacrificial in insulating laminate structure
The end of domestic animal layer 152 and bottom selection gate sacrificial layer 154 is exposed in the opening in grid line gap 161, therefore, sacrificial layer 152
Etchant is touched with bottom selection gate sacrificial layer 154.Etchant is from the opening in grid line gap 161 gradually to insulating laminate knot
The etched inside sacrificial layer 152 and bottom selection gate sacrificial layer 154 of structure.Due to the selectivity of etchant, the etching relative to
Interlayer insulating film 151 in insulating laminate structure removes sacrificial layer 152 and bottom selection gate sacrificial layer 154.
When forming grid conductor 122, using grid line gap 161 as deposit channel, using atomic layer deposition
(ALD), metal layer is filled in grid line gap 161 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4Or diborane B2H6.In the atomic layer deposition the step of, hexafluoro is utilized
Change tungsten WF6With silane SiH4Reaction product chemisorption obtain tungsten material realize deposition process.
In this embodiment, sacrificial layer 152 and bottom selection gate sacrificial layer 154 are replaced into after grid conductor 120, from
And the epitaxial layer 116 of 110 lower sidewalls corresponding position of channel column and bottom selection gate are adjacent, false 140 lower sidewalls of channel column
The epitaxial layer 116 of corresponding position is not abutted with bottom selection gate.
Further, for example including for driving selection crystal in the substrate semiconductor substrate 101 of the first array structure
The cmos circuit of pipe and memory transistor.Being electrically connected between cmos circuit and external circuit is provided using conductive channel, is such as schemed
Shown in 3k.Multiple conductive channels are for example positioned at the intermediate region of laminated construction, positioned at the stepped area of laminated construction, or are located at lining
Dielectric layer on bottom.Multiple conductive channels in the 3D memory device respectively include as core conductive column 131 and as every
The insulating layer 134 of absciss layer, the insulating layer 134 is for conductive column 131 and the conductive material of surrounding to be separated from each other.It is the multiple
Conductive channel is for example including conductive channel SL1, HV1.Conductive channel SL1 and HV1 respectively with P+ doped region 104 and N+ doped region
106 are in contact, to provide being electrically connected between common source line and high pressure N trap and external circuit.In this embodiment, conductive logical
Road is not abutted with bottom selection gate.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (11)
1. a kind of 3D memory device, comprising:
Substrate；
Positioned at the laminated construction of the substrate, the laminated construction includes the multiple grid conductors and multiple layers being alternately stacked
Between insulating layer, the grid conductor positioned at bottom is as bottom selection gate；
Through multiple channel columns of the laminated construction；
Through multiple false channel columns of the laminated construction；And
Positioned at the epitaxial layer of the multiple channel column and multiple false channel column bottoms,
Wherein, the bottom selection gate and the epitaxial layer adjacent being located in the multiple channel column are described more with being located at
The epitaxial layer in a vacation channel column does not abut.
2. 3D memory device according to claim 1, wherein the bottom selection gate includes at least one opening, institute
It is corresponding with the position of the multiple false channel column to state at least one opening, the opening is filled out by the corresponding interlayer insulating film
It fills.
3. 3D memory device according to claim 1, wherein the laminated construction include intermediate region and with the centre
The stepped area of area adjacency.
4. 3D memory device according to claim 3, wherein
The channel column is located at the intermediate region of the laminated construction,
It is described vacation channel column be located at the laminated construction the intermediate region and/or the stepped area.
5. 3D memory device according to claim 1, wherein the epitaxial layer in the channel column is from the lining
Bottom extends to the corresponding position of the interlayer insulating film positioned at bottom selection gate upper surface.
6. 3D memory device according to claim 1, further includes: the cmos circuit in the substrate, the CMOS
Circuit between conductive channel and external circuit by being electrically connected.
7. a kind of manufacturing method of 3D memory device, comprising:
Laminated construction is formed on the substrate, the laminated construction includes the multiple grid conductors being alternately stacked and multiple layer insulations
Layer, the grid conductor positioned at bottom is as bottom selection gate；
Form the multiple channel columns for running through the laminated construction；
Form multiple false channel columns through the laminated construction；And
The epitaxial layer for being located at the multiple channel column and multiple false channel column bottoms is formed,
Wherein, the bottom selection gate and the epitaxial layer adjacent being located in the multiple channel column are described more with being located at
The epitaxial layer in a vacation channel column does not abut.
8. manufacturing method according to claim 7, wherein the step of laminated construction is formed on the substrate include:
Sequentially form the insulating layer and bottom selection gate sacrificial layer being located above the substrate；
Form at least one opening for running through the bottom selection gate, at least one opening and the multiple false channel column
Position it is corresponding；
The insulating laminate structure being located above the bottom selection gate is formed, the insulating laminate structure includes being alternately stacked
Multiple sacrificial layers and multiple interlayer insulating films, the bottom selection gate sacrificial layer are exhausted by the interlayer with the multiple sacrificial layer
Edge layer isolation；
The multiple sacrificial layer is patterned step-like；And
The bottom selection gate sacrificial layer and the multiple sacrificial layer are replaced as the multiple grid conductor.
9. manufacturing method according to claim 8, wherein
The channel column is located at the intermediate region of the laminated construction,
The vacation channel column is located at intermediate region and/or the stepped area of the laminated construction.
10. manufacturing method according to claim 7, wherein the epitaxial layer in the channel column is from the lining
Bottom extends to the corresponding position of the interlayer insulating film positioned at bottom selection gate upper surface.
11. manufacturing method according to claim 7, further includes: the cmos circuit being located in the substrate is formed, it is described
Cmos circuit between conductive channel and external circuit by being electrically connected.
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