CN108847413A - 3D memory device - Google Patents
3D memory device Download PDFInfo
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- CN108847413A CN108847413A CN201811013350.6A CN201811013350A CN108847413A CN 108847413 A CN108847413 A CN 108847413A CN 201811013350 A CN201811013350 A CN 201811013350A CN 108847413 A CN108847413 A CN 108847413A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
A kind of 3D memory device is disclosed, including：Substrate；Laminated construction on the substrate, the laminated construction include the multiple conductor layers being alternately stacked and multiple insulating layers；Through multiple channel structures of the laminated construction；Positioned at the channel structure lower section and with the semiconductor layer of flat surfaces；Aperture of the channel structure at the semiconductor layer upper surface is less than the aperture of the semiconductor layer upper surface.The embodiment of the present invention below channel structure by being arranged the semiconductor layer with flat surfaces, and aperture of the channel structure at the semiconductor layer upper surface is less than the aperture of the semiconductor layer upper surface, not only expand the process window of semiconductor layer, make semiconductor layer that there is better high level of homogeneity and surface smoothness, current leakage can be reduced and be avoided, the electric property of device is improved.
Description
Technical field
The present invention relates to memory technology fields, in particular to 3D memory device.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The aperture of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density, develop
The memory device (that is, 3D memory device) of three-dimensional structure out.3D memory device includes the multiple storages stacked along vertical direction
Unit can double up integrated level on the chip of unit area, and can reduce cost.
Since the amount of storage needs of 3D memory device are higher and higher, memory device needs more grid lines higher to meet
Amount of storage, therefore the aperture (CD) of channel column has been reduced to meet higher cell density requirement.For the ditch of small size
For road column, further reduce and the shape optimum of aperture (CD) are the key that improve storage density.
For the 3D memory device of the prior art, there is an epitaxial layer in the bottom of channel hole (channel hole, CH),
For channel hole to be connected to substrate active area, and control first choice grid (Bottom Selective Gate, BSG).For
Avoid the electric current bridge between grid line (Gate Line, GL) and substrate active area, the height that epitaxial layer needs to have certain,
Extend to the top among first choice gate oxide；Epitaxial layer is also needed with flat surface, to reduce and channel pass layer
Contact surface resistance.In order to form the epitaxial layer of high quality, precleaning becomes more and more challenging, and needs strictly
Waiting time prevents outer layer growth to avoid native oxide, and the epitaxial layer grown in the prior art often has unevenness
Even height and uneven surface, the problems such as so as to cause epitaxial layer is uneven and current leakage.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of 3D memory device, the first laminated construction is interior to form half
Conductor layer, the semiconductor layer have sustained height and flat surfaces, solve due to semiconductor layer is highly non-uniform and surface not
Caused by flat the problems such as current leakage.
According to an aspect of the present invention, a kind of 3D memory device is provided, including：Substrate；Lamination on the substrate
Structure, the laminated construction include the multiple conductor layers being alternately stacked and multiple insulating layers；Through the multiple of the laminated construction
Channel structure；Positioned at the channel structure lower section and with the semiconductor layer of flat surfaces；The channel structure is partly led described
Aperture at body layer upper surface is less than the aperture of the semiconductor layer upper surface.
Preferably, the channel structure includes barrier insulating layer, electric charge capture layer, tunnel insulating layer and channel layer, described
Channel layer is connected to the semiconductor layer.
Preferably, the laminated construction includes：First laminated construction, first laminated construction include be alternately stacked
One insulating layer and the first conductor layer；Second laminated construction, second laminated construction include multiple second conductors being alternately stacked
Layer and multiple second insulating layers.
Preferably, the semiconductor layer runs through first laminated construction, and extends to the substrate interior.
Preferably, the bottom of the channel structure extends to inside the semiconductor layer.
Preferably, the second of the first insulating layer at the top of first laminated construction and second laminated construction bottom be absolutely
Edge layer is in contact.
Preferably, first conductor layer is isolated from each other with the semiconductor layer.
Preferably, the first conductor layer of the semiconductor layer and first laminated construction forms first choice transistor.
Preferably, the second conductor layer of the channel layer and second laminated construction forms memory transistor；And with
The third conductor layer of second laminated construction forms the second selection transistor.
Preferably, the semiconductor layer selected from least one of monocrystalline silicon, polysilicon by forming.
3D memory device provided by the invention, forms semiconductor layer in the first laminated construction, then in the first lamination knot
The second laminated construction is formed on structure and forms channel structure in the second laminated construction, expands the process window of semiconductor layer
Mouthful, make semiconductor layer that there is better high level of homogeneity and surface smoothness, it is possible to reduce and current leakage is avoided, improve device
Electric property.
Further, the semiconductor layer can be formed using atomic layer deposition mode, instead of existing selectivity outside
Prolong growth, reduce device cost, improves handling capacity.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 a and Fig. 1 b respectively illustrate the circuit diagram and structural schematic diagram of the memory cell string of 3D memory device；
Fig. 2 shows the perspective views of 3D memory device；
Fig. 3 shows the flow chart of the manufacturing method of the 3D memory device of the embodiment of the present invention；
Fig. 4 a to Fig. 4 m shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention；
3D memory device according to prior art and 3D memory according to an embodiment of the present invention is shown respectively in Fig. 5 a and 5b
The partial enlarged view of part, there is shown with a part of structures near semiconductor layer.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
" top " described in the present invention refers to positioned at the top of base plan, can refer to directly connecing between material
Touching is also possible to interval setting.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, including：First choice transistor
Q1, storage unit M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of storage unit M1 to M4 is respectively connected to word
The respective word of line WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include the second conductor layer 122 and third
Conductor layer 123, storage unit M1 to M4 respectively include the first conductor layer 121.First conductor layer 121, the second conductor layer 122 and
Three conductor layers 123 are consistent with the stacking order of transistor in memory cell string 100, each other using exhausted between adjacent conductor layer
Edge layer separates, to form rhythmic structure of the fence.
Further, memory cell string 100 includes storage string 110.Storage string 110 is adjacent with rhythmic structure of the fence or runs through
Rhythmic structure of the fence.Tunneling medium layer is accompanied between the middle section of storage string 110, the first conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form storage unit M1 to M4.At the both ends of storage string 110, second
Gate dielectric layer 114 is accompanied between conductor layer 122 and 123 and channel layer 111, to form the choosing of first choice transistor Q1 and second
Select transistor Q2.
Channel layer 111 is for example made of DOPOS doped polycrystalline silicon, and tunneling medium layer 112 and gate dielectric layer 114 are respectively by oxide
Composition, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, such as includes gold
The silicon nitride of the particle of category or semiconductor, the first conductor layer 121, the second conductor layer 122 and third conductor layer 123 are by metal group
At, such as tungsten.Channel layer 111 is used to provide selection transistor and control the channel region of transistor, the doping type of channel layer 111
It is identical as selection transistor and the control type of transistor.For example, selection transistor and control transistor for N-type, channel
Layer 111 can be the polysilicon of n-type doping.
In this embodiment, the core of storage string 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of storage string 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, storage unit M1 to M4 are used public
Total channel layer 111 and gate dielectric layer 114.In storage string 110, channel layer 111 provides the source-drain area and ditch of multiple transistors
Channel layer.In alternate embodiments, step independent of one another can be used, the choosing of first choice transistor Q1 and second is respectively formed
Select the semiconductor layer of transistor Q2 and the semiconductor layer and gate dielectric layer of gate dielectric layer and storage unit M1 to M4.In storage string
In 110, the semiconductor layer of first choice transistor Q1 and the second selection transistor Q2 and the semiconductor layer of storage unit M1 to M4
It is electrically connected to each other.
In write operation, memory cell string 100 writes data into storage unit M1 into M4 using FN tunneling efficiency
Selected memory cell.By taking storage unit M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to about zero volt
Voltage, so that the second selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage VDD,
So that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, and wordline WL2 is offset to volume
Journey voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only having the wordline of selected memory cell M2 electric
Pressure is higher than tunneling voltage, and therefore, the electronics of the channel region of storage unit M2 reaches charge storage via tunneling medium layer 112
Layer 113, so that data are transformed into charge storage in the charge storage layer 113 of storage unit M2.
In read operation, the conducting shape of selected memory cell of the memory cell string 100 according to storage unit M1 into M4
State judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking storage unit M2 as an example, wordline
WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of storage unit M2 and its threshold value electricity
Pressure is related, i.e., related to the quantity of electric charge in charge storage layer, to may determine that data according to the on state of storage unit M2
Value.Storage unit M1, M3 and M4 are in the conductive state always, and therefore, it is single that the on state of memory cell string 100 depends on storage
The on state of first M2.Control circuit judges the conducting of storage unit M2 according to the electric signal detected on bit line BL and source electrode line SL
State, to obtain the data stored in storage unit M2.
Fig. 2 respectively illustrates the perspective view of 3D memory device.For the sake of clarity, 3D memory device is not shown in Fig. 2
In each insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string 100 respectively includes respective channel column 110 and public first
Conductor layer 121, the second conductor layer 122 and third conductor layer 123.First conductor layer 121, the second conductor layer 122 and third conductor
Layer is 123 consistent with the stacking order of transistor in memory cell string 100, used each other between adjacent conductor layer insulating layer every
It opens, to form rhythmic structure of the fence 120.Insulating layer is being not shown in the figure.
The internal structure of storage string 110 is as shown in Figure 1 b, is no longer described in detail herein.In the centre of storage string 110
Part, the first conductor layer 121 and channel layer 111, tunneling medium layer 112, charge storage layer 113 and the grid inside storage string 110
Dielectric layer 114 together, forms storage unit M1 to M4.At the both ends of storage string 110, the second conductor layer 122 and third conductor layer
123 with inside storage string 110 channel layer 111 and gate dielectric layer 114 together, formed first choice transistor Q1 and second selection
Transistor Q2.
Channel column 110 runs through rhythmic structure of the fence 120, and is arranged in array, and the first of multiple storage strings 110 of same row
End is commonly connected to same bit line (i.e. one of BL1-BL4), and second end is commonly connected to substrate 410, and second end is via substrate
100 form common source connection.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 102
Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely
One of SSL4).
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap 161, then the grid line of same level is via respective
Conductive channel 131 reach interconnection layer 132, thus interconnected amongst one another, be then connected to same wordline via conductive channel 133
(i.e. one of wordline WL1 to WL4).
The grid conductor of ground selection transistor Q2 links into an integrated entity.If the grid conductor 123 of ground selection transistor Q2 by
Grid line gap 161 is divided into different grid lines, then grid line reaches interconnection layer 132 via respective conductive channel 131, thus each other
Interconnection, then via with the being connected to same selection line GSL of conductive channel 133.
Fig. 3 shows the flow chart of the manufacturing method of the 3D memory device of the embodiment of the present invention；Fig. 4 A to Fig. 4 M shows root
According to the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.
In step s 302, the first laminated construction is formed on the substrate, first laminated construction includes being alternately stacked
First insulating layer and the first sacrificial layer.
In the sectional view of the semiconductor structure shown in Fig. 4 A, semiconductor structure 400a has substrate 410, substrate 410
Material is, for example, silicon.The first laminated construction 420 is formed on substrate 410.First laminated construction 420 be alternately stacked multiple first
Insulating layer 421 and multiple first sacrificial layers 422, sacrificial layer 422 will be replaced by conductor layer in subsequent gate formation process.?
In the present embodiment, the first insulating layer 421 is for example made of silica, and the first sacrificial layer 422 is for example made of silicon nitride, can be adopted
It is successively alternately heavy on substrate 410 with chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods
Product silica and silicon nitride.
In step s 304, the groove for running through the first laminated construction is formed, the groove extends to the substrate interior.
The sectional view of the semiconductor structure exemplified by Fig. 4 B- Fig. 4 D illustrates the process of this step, first in semiconductor
The surface of structure 400a forms the first hard mask layer 430, to form semiconductor structure 400b.First hard mask layer 430 herein
It may include amorphous carbon layer (for example, patterned masking layer APFM (A-C)) and dielectric anti reflective layer (for example, silicon oxynitride (SiON)
Layer).It will be understood, however, that the first hard mask layer 430 can choose other materials.The number of plies of first hard mask layer 430 can also
Can there was only one layer or more than one layer with variation, such as the first hard mask layer 430.
Then, the first photoresist layer 440 is covered on the surface of semiconductor structure 400b, by first photoresist layer 440
It is exposed etching, the first required photoresist pattern is formed, obtains semiconductor structure 400c, wherein first photoresist layer 440
Including photoresist coating (Photo Resist Coating, PR) and/or bottom antireflective coating (Bottom Anti-
Reflection Coating)；Later, by first the first hard mask layer of photoresist pattern etch on semiconductor structure 400c
430 and first laminated construction 420 to form the groove 401, the groove 401 extends to substrate 401, forms the first depth
Silicon slot obtains semiconductor structure 400d.
Dry method is also carried out in a preferred embodiment, after etching to remove photoresist (Asher) and wet-cleaning (WET
Clean)。
In step S306, the semiconductor layer with flat surfaces is formed in the groove.
The sectional view of the semiconductor structure exemplified by Fig. 4 E- Fig. 4 G illustrates the process of this step, firstly, in the ditch
Semiconductor layer 402 is formed in slot 401.Wherein, the surface on the surface of the semiconductor layer 402 and first laminated construction 420
It flushes.Specifically, epitaxial layer is formed in the groove 401, to form semiconductor structure 400e.The material of the semiconductor layer
Material e.g. monocrystalline silicon, polysilicon.The mode for forming semiconductor layer may, for example, be selective epitaxial growth (Selective
Epitaxial Growth, SEG).
In a preferred embodiment, the deposited semiconductor material in the groove 401, such as polysilicon, thus shape
At semiconductor structure 400e.The material of the semiconductor layer is, for example, monocrystalline silicon, polysilicon.The mode for forming semiconductor layer can be with
E.g. atomic layer deposition (Atomic Layer Deposition, ALD).
Then, first sacrificial layer 422 at 420 top of the first laminated construction of removal is to expose partly leading with flat surfaces
Body layer 402 obtains semiconductor structure 400f.
Later, the deposition oxide on semiconductor structure 400f, such as silica form and cover the semiconductor layer 402
Interlayer insulating film, then remove part interlayer insulating film keep its surface flat and control semiconductor layer 402 extend to interlayer
The height of insulating layer, first insulating layer 421 of the interlayer insulating film as current first laminated construction, 420 top, is partly led
Body structure 400g.The method of removal part interlayer insulating film may, for example, be planarization, such as chemical mechanical grinding (CMP).
In step S308, the second laminated construction, second lamination packs are formed on first laminated construction
Include multiple second sacrificial layers being alternately stacked and multiple second insulating layers.
In the sectional view of the semiconductor structure shown in Fig. 4 H, the second laminated construction is formed on the first laminated construction 420
450.The multiple second insulating layers 451 and multiple second sacrificial layers 452 that second laminated construction 450 is alternately stacked, sacrificial layer 452 will
It is substituted for conductor layer.In the present embodiment, second insulating layer 451 is for example made of silica, and the second sacrificial layer 452 is for example by nitrogen
SiClx composition can successively be existed using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods
Replace deposited silicon nitride and silica on first laminated construction 420.
As shown at figure 4h, 450 bottom of the first insulating layer 421 and the second laminated construction at the top of the first laminated construction 420
Second sacrificial layer 452 is in contact.
In a preferred embodiment, first insulating layer 421 and the second laminated construction at 420 top of the first laminated construction
The second insulating layer 451 of 450 bottoms is in contact.
In step s310, the channel hole for running through the second laminated construction is formed, the bottom in the channel hole extends to described
Inside semiconductor layer.
The sectional view of the semiconductor structure exemplified by Fig. 4 I- Fig. 4 K illustrates the process of this step, first in semiconductor
The surface of structure 400h forms the second hard mask layer 460, to form semiconductor structure 400i.Second hard mask layer 460 herein
It may include amorphous carbon layer (for example, patterned masking layer APFM (A-C)) and dielectric anti reflective layer (for example, silicon oxynitride (SiON)
Layer).It will be understood, however, that the second hard mask layer 460 can choose other materials.The number of plies of second hard mask layer 460 can also
Can there was only one layer or more than two layers with variation, such as the second hard mask layer 460.
Then, the second photoresist layer 470 is covered on the surface of semiconductor structure 400i, by second photoresist layer 470
It is exposed etching, the second required photoresist pattern is formed, obtains semiconductor structure 400j, wherein second photoresist layer 470
Including photoresist coating (Photo Resist Coating, PR) and/or bottom antireflective coating (Bottom Anti-
Reflection Coating)；Later, by second the second hard mask layer of photoresist pattern etch on semiconductor structure 400c
460 and second laminated construction 450 to form the channel hole 403, the channel hole 403 extends to semiconductor layer 402, forms the
The groove of two depth obtains semiconductor structure 400k.
Dry method is also carried out in a preferred embodiment, after etching to remove photoresist (Asher) and wet-cleaning (WET
Clean)。
The aperture of 403 bottom of channel hole is less than the aperture of the semiconductor layer 402.
In step S312, channel structure is formed in the channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 4 L, for example, in channel hole 403 can also along its side wall and
Barrier insulating layer 404, electric charge capture layer 405, tunneling insulation layer 406, channel layer 407 and filled layer 408 are formed on bottom, selected
Material can be the single layer and/or multiple layer combination structure of oxidenitride oxide-polysilicon-oxide (ONOPO),
But not limited to this material and combination that place refers to.In some embodiments, it is sequentially depositing in channel hole 403 first
ONOPO layers, then the ONOPO structure of 403 bottom of channel hole is performed etching, until exposing semiconductor layer 402, then removes table
The PO layer in face, finally sequentially forms polysilicon layer (P layers) and oxide filled layer (O layers), and by the oxide on channel hole top
Filled layer replaces with polysilicon layer, to form semiconductor structure 400l.In some embodiments, semiconductor layer 402, which is crossed, carves
Lose certain depth.
Wherein, the channel structure includes barrier insulating layer 404, electric charge capture layer 405, tunneling insulation layer 406 and channel
Layer 407.In the example of Fig. 4 L, the exemplary materials of barrier insulating layer 404 and tunneling insulation layer 406 are silica, charge prisoner
The exemplary materials for obtaining layer 405 are silicon nitride, form oxide-nitride-oxide (ONO) structure；Channel layer 407 is exemplary
Material is polysilicon.It is to be understood that these layers can choose other materials.For example, the material of barrier insulating layer 404 can wrap
Include high K oxide layer；Electric charge capture layer 405 can be floating gate structure, for example including polycrystalline silicon material；The material of channel layer 407
Material may include monocrystalline silicon, monocrystalline germanium, SiGe, Si:C,SiGe:C,SiGe:The semiconductor materials such as H.Filled layer 408 it is exemplary
Material is silica.
In step S314, the first sacrificial layer in the first laminated construction is substituted for the first conductor layer, to form the
Three laminated construction；The first sacrificial layer in second laminated construction is substituted for the second conductor layer and third conductor layer, thus shape
At the 4th laminated construction；Wherein, the first conductor layer is isolated from each other with the semiconductor layer.
422 quilt of the first sacrificial layer in the sectional view of the semiconductor structure exemplified by Fig. 4 M, in the first laminated construction 420
It is substituted for the first conductor layer 482, to form third layer stack structure 480；The second sacrificial layer 452 in second laminated construction 450
It is replaced by the second conductor layer 492 and third conductor layer 493, to form the 4th laminated construction 490, the first conductor layer 482
It is isolated from each other with semiconductor layer 402.
Wherein, the semiconductor layer 402 and the first conductor layer 482 form first choice transistor；The channel layer 407 with
Multiple second conductor layers 492 form multiple memory transistors, and the channel layer 407 forms the second selection with third conductor layer 493
Transistor.
With reference to shown in Fig. 4 M, a kind of 3D memory device according to an embodiment of the invention, including substrate；Positioned at the substrate
On laminated construction, the laminated construction includes the multiple conductor layers being alternately stacked and multiple insulating layers；Through the lamination knot
Multiple channel structures of structure；Positioned at the channel structure lower section and with the semiconductor layer of flat surfaces；The channel structure exists
Aperture at the semiconductor layer upper surface is less than the aperture of the semiconductor layer upper surface.
Wherein, the channel structure includes barrier insulating layer 404, electric charge capture layer 405, tunnel insulating layer 406 and channel
Layer 407, the channel layer 407 is connected to the semiconductor layer 402.
The laminated construction includes third layer stack structure 480 and the 4th laminated construction 490, wherein third layer stack structure 480
Including the first insulating layer 481 being alternately stacked and the first conductor layer 482；4th laminated construction 490 is multiple including being alternately stacked
Second conductor layer 492 and third conductor layer 493 and multiple second insulating layers 491.
The semiconductor layer 402 is through the third layer stack structure 480 and extends to inside the substrate 410.The ditch
The bottom of road structure extends to inside the semiconductor layer 402.
First insulating layer 481 and the second of 490 bottom of the 4th laminated construction at 480 top of third layer stack structure
Conductor layer 492 is in contact.
In a preferred embodiment, first insulating layer 481 and the described 4th at 480 top of third layer stack structure
The second insulating layer 491 of 490 bottom of laminated construction is in contact.
First conductor layer 482 is isolated from each other with the semiconductor layer 402.
The semiconductor layer 402 and the first conductor layer 481 of the third layer stack structure 480 form first choice crystal
Pipe.Second conductor layer 491 of the channel layer 404 and the 4th laminated construction 490 forms memory transistor；And with it is described
The third conductor layer 493 of 4th laminated construction 490 forms the second selection transistor.
Other details of 3D memory device, such as structure, the periphery interconnection of storage array etc., and the emphasis of non-present invention,
Not reinflated description herein.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3DNAND flash memory.
3D memory device provided by the invention, forms semiconductor layer in the first laminated construction, then in the first lamination knot
The second laminated construction is formed on structure and forms channel structure in the second laminated construction, expands the process window of semiconductor layer
Mouthful, make semiconductor layer that there is better high level of homogeneity and surface smoothness, it is possible to reduce and current leakage is avoided, improve device
Electric property.
Further, the semiconductor layer can be formed using atomic layer deposition mode, instead of existing selectivity outside
Prolong growth, reduce device cost, improves handling capacity.
3D memory device according to prior art and 3D memory according to an embodiment of the present invention is shown respectively in Fig. 5 a and 5b
The partial enlarged view of part.
As shown in Figure 5 a, in 3D memory according to prior art, channel hole 403 is through multiple 481 Hes of insulating layer
In the laminated construction that multiple conductor layers 482 are alternately stacked, and extend to inside substrate 410.It is selected in the bottom in channel hole 403
Selecting property is epitaxially-formed semiconductor layer 402, then forms channel structure in channel hole 403.Due to selective epitaxial growth
Cause the upper surface of semiconductor layer 402 uneven, so that the contact resistance of channel structure and the semiconductor layer 402 increases,
So that the degradation of 3D memory.Meanwhile in 3D memory according to prior art, semiconductor layer 402 and first
Conductor layer 482 forms first choice transistor.The height disunity of semiconductor layer 402, in substrate 410 and the first conductor layer 482
Between formed electric current bridge so that 3D memory device fail.
As shown in Figure 5 b, in 3D memory according to an embodiment of the present invention, each semiconductor layer 402 extends to lining
Inside bottom 410, meanwhile, the bottom in channel hole 403 extends to inside the semiconductor layer 402.The semiconductor layer 402 and first
Conductor layer 482 forms first choice transistor.The first insulating layer at the top of first laminated construction covers the semiconductor layer 402.
The upper surface of semiconductor layer 402 is smooth, and can control the height that semiconductor layer 402 extends to interlayer insulating film.Forming the
The first laminated construction is etched before two laminated construction and forms groove 401, and deposited semiconductor material is in the groove 401 to form
Semiconductor layer 402.After the thickness of laminated construction is continuously increased, deposited semiconductor is formed without etching whole laminated construction
The groove 401 of layer 402 avoids the residue of the techniques such as the etching of channel hole 403 that 402 surface of semiconductor layer is caused to form vacancy etc. no
Good influence, the problem of avoiding 402 surface irregularity of semiconductor layer, to improve the yield and reliability of 3D memory device.
Meanwhile the characteristic size process window for etching the groove formed after the first laminated construction is larger, it is easily operated, so that
The high unity of semiconductor layer 402 is conducive to the realization of technique and the continuous improvement of integrated level.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.For example, certain
A little steps not necessarily, thus can be omitted, or replace with other steps.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained
Part.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of 3D memory device, including：
Substrate；
Laminated construction on the substrate, the laminated construction include the multiple conductor layers and multiple insulation being alternately stacked
Layer；
Through multiple channel structures of the laminated construction；
Positioned at the channel structure lower section and with the semiconductor layer of flat surfaces；
Aperture of the channel structure at the semiconductor layer upper surface is less than the aperture of the semiconductor layer upper surface.
2. 3D memory device according to claim 1, wherein the channel structure includes barrier insulating layer, electric charge capture
Layer, tunnel insulating layer and channel layer, the channel layer are connected to the semiconductor layer.
3. 3D memory device according to claim 1, wherein the laminated construction includes：
First laminated construction, first laminated construction include the first insulating layer being alternately stacked and the first conductor layer；
Second laminated construction, second laminated construction include multiple second conductor layers being alternately stacked and multiple second insulation
Layer.
4. 3D memory device according to claim 3, wherein the semiconductor layer runs through first laminated construction, and
Extend to the substrate interior.
5. 3D memory device according to claim 3, wherein the bottom of the channel structure extends to the semiconductor layer
It is internal.
6. 3D memory device according to claim 3, wherein the first insulating layer and institute at the top of first laminated construction
The second insulating layer for stating the second laminated construction bottom is in contact.
7. 3D memory device according to claim 3, wherein first conductor layer and the semiconductor layer each other every
From.
8. 3D memory device according to claim 3, wherein the first of the semiconductor layer and first laminated construction
Conductor layer forms first choice transistor.
9. manufacturing method according to claim 9, wherein the second conductor of the channel layer and second laminated construction
Layer forms memory transistor；And the second selection transistor is formed with the third conductor layer of second laminated construction.
10. 3D memory device according to claim 1, wherein the semiconductor layer is by monocrystalline silicon, polysilicon
At least one composition.
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