CN111446256A

CN111446256A - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN111446256A
Application number: CN202010211908.2A
Authority: CN
Inventors: 刘思敏; 杨川; 严龙翔; 彭爽爽
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-03-24
Filing date: 2020-03-24
Publication date: 2020-07-24

Abstract

The invention relates to the technical field of three-dimensional storage, and particularly provides a three-dimensional storage and a manufacturing method thereof, aiming at solving the problem that a laminated structure is easy to incline or collapse. The three-dimensional memory provided by the invention comprises a substrate, a laminated structure arranged on the substrate, and a channel hole and a grid line gap which penetrate through the laminated structure; a channel structure is arranged in the channel hole, and one end of the channel structure extends to the substrate; a structure insulating layer and a common source pole positioned in the structure insulating layer are arranged in the grid line gap; the common source pole sequentially comprises a first conducting layer, a stress adjusting layer and a core part from outside to inside, and the material of the core part comprises polycrystalline silicon. Therefore, the compressive stress generated by the stress adjusting layer in the common source pole is balanced or balanced with the tensile stress of the core part, the force applied by the common source pole to the laminated structure around the gap of the grid line is reduced, and the possibility of inclination or collapse of the laminated structure is reduced or avoided.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of three-dimensional storage, in particular to a three-dimensional memory and a manufacturing method thereof.

Background

With the development of planar memories, their storage capacity has approached the limit of practical scalability. To address the difficulties encountered with planar memories, three-dimensional memories having arrangements in horizontal and vertical arrays have been developed that enable higher storage capacities in smaller spaces by vertically stacking multiple layers of data storage units.

In the related art, the three-dimensional memory generally includes a stacked structure, and a channel structure and a common source post penetrating through the stacked structure, the common source post is located in a gate line gap of the stacked structure, the common source post generally includes a core portion filled in the gate line gap and a conductive pillar located above the core portion, wherein the core portion is generally formed by polysilicon. Further, the larger the number of layers of the stacked structure in the three-dimensional memory, the larger the storage capacity of the three-dimensional memory.

However, polysilicon has strong local stress, and when polysilicon is filled in the gate line gap, the polysilicon expands to generate tensile stress, and as the number of stacked layers increases, the tensile stress generated by polysilicon also increases, which easily causes the problem of inclination or collapse of the stacked structure.

Disclosure of Invention

Embodiments of the present invention provide a three-dimensional memory and a method for fabricating the same, which are used to reduce or avoid the possibility of collapse of a stacked structure.

In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:

in one aspect, an embodiment of the present invention provides a three-dimensional memory, including a substrate, a stacked structure disposed on the substrate, and a channel hole and a gate line gap penetrating through the stacked structure; a channel structure is arranged in the channel hole, and one end of the channel structure extends to the substrate; a structure insulating layer and a common source pole positioned in the structure insulating layer are arranged in the grid line gap; the common source pole sequentially comprises a first conducting layer, a stress adjusting layer and a core part from outside to inside, the first conducting layer and the stress adjusting layer penetrate through the laminated structure, and one end of the first conducting layer extends to the substrate and is electrically connected with one end of the channel structure extending to the substrate; the material of the core comprises polysilicon.

As with the three-dimensional memory described above, the core is a polysilicon core.

As described above, the core includes the first core and the second core which are stacked, and the first core is close to the substrate relative to the second core.

As in the three-dimensional memory described above, the first core portion is a silicon dioxide core portion and the second core portion is a polysilicon core portion.

As with the three-dimensional memory described above, the first core portion is a doped polysilicon core portion and the second core portion is a polysilicon core portion.

As with the three-dimensional memory described above, the doped polysilicon core is doped with impurity atoms at a concentration of at least 10%.

As described above, the impurity atoms include one or more of phosphorus atoms, arsenic atoms, and nitrogen atoms.

As in the three-dimensional memory described above, the stress adjustment layer is provided as a tungsten layer.

In the three-dimensional memory, the common source pole column further comprises a barrier layer located between the stress adjusting layer and the core.

The three-dimensional memory as described above, wherein the barrier layer comprises a titanium nitride layer.

In the three-dimensional memory, the common source pole column further includes a conductive pillar disposed on an end of the core portion away from the substrate.

As described above, the conductive pillars are tungsten pillars.

As described above, the common source pole column further includes a second conductive layer covering the circumferential sidewall of the conductive pillar and an end of the core portion away from the substrate.

The three-dimensional memory as described above, the second conductive layer comprises a titanium nitride layer.

The three-dimensional memory as described above, the first conductive layer includes a titanium layer and a titanium nitride layer.

In the three-dimensional memory, the first conductive layer is a hollow structure, one end of the hollow structure extending to the substrate is closed, and the other end of the hollow structure is provided with an opening for forming the stress adjustment layer and the core in the hollow structure.

In the three-dimensional memory, the structural insulating layer is provided with a through hole extending to the substrate, and the common source pole is located in the through hole.

According to the three-dimensional memory, along the extending direction of the common source pole, a plurality of accommodating grooves are formed in the inner side surface of the grid line gap at intervals; a plurality of extending parts are arranged on the structural insulating layer at intervals, and each extending part is embedded in one corresponding accommodating groove.

In the three-dimensional memory, the stacked structure includes a plurality of gate electrode layers and a plurality of insulating layers alternately arranged, and the gate line gap penetrates through each of the gate electrode layers and each of the insulating layers; and the accommodating groove is formed between the end part of any one of the grid electrode layers and two adjacent insulation layers of the grid electrode layer, in the end part of each grid electrode layer and the end part of each insulation layer in the grid line gap.

The three-dimensional memory as described above, a protective layer being provided between the substrate and the stacked structure; the protective layer is provided with a first opening and a second opening, the common source pole penetrates through the first opening and is electrically connected with the doped region of the substrate, and the channel structure penetrates through the second opening and is electrically connected with the epitaxial region of the substrate.

The three-dimensional memory provided by the embodiment of the invention has the following advantages: because the stress adjusting layer is arranged in the common source pole of the grid line gap and used for generating the compressive stress opposite to the tensile stress direction of the core part, the compressive stress generated by the stress adjusting layer can basically offset the tensile stress generated by the core part, so that the acting force of the common source pole on the surrounding laminated structure is reduced, and the possibility of stress inclination or collapse of the laminated structure is reduced or avoided.

On the other hand, the embodiment of the invention also provides a manufacturing method of the three-dimensional memory, which comprises the following steps:

providing a substrate;

forming a stacked structure on the substrate;

forming a channel hole and a gate line slit penetrating the laminated structure in the laminated structure;

forming a channel structure in the channel hole, wherein one end of the channel structure extends to the substrate;

forming a structural insulating layer in the gate line gap;

forming a through hole penetrating to the substrate in the structure insulating layer;

forming a common source pole in the through hole, wherein the common source pole sequentially comprises a first conductive layer, a stress adjusting layer and a core part from outside to inside, the first conductive layer and the stress adjusting layer penetrate through the laminated structure, and one end of the first conductive layer extends to the substrate and is electrically connected with one end of the channel structure extending to the substrate; the material of the core comprises polysilicon.

In the method for manufacturing the three-dimensional memory, the step of forming the common source pole in the through hole includes:

forming the first conductive layer, the stress adjusting layer and the barrier layer in the through hole in sequence;

forming the core, second conductive layer, and conductive post within the barrier layer.

In the method for manufacturing a three-dimensional memory, the step of sequentially forming the first conductive layer, the stress adjustment layer, and the barrier layer in the through hole includes:

depositing a layer of titanium and a layer of titanium nitride in the through hole and on the surface of the laminated structure far away from the substrate in sequence to form the first conducting layer;

depositing a layer of tungsten on the first conducting layer to form the stress adjusting layer, wherein the stress adjusting layer covers the first conducting layer;

and depositing a layer of titanium nitride on the stress adjusting layer to form the barrier layer, wherein the barrier layer covers the stress adjusting layer.

In the method for manufacturing a three-dimensional memory, the step of forming the core, the second conductive layer and the conductive pillar in the barrier layer includes:

forming the core in the through hole, wherein the core is positioned in the barrier layer, and one end of the core, which is far away from the substrate, is lower than one end, which is far away from the substrate, of the through hole in the vertical direction;

depositing titanium nitride on one end of the core part far away from the substrate, the barrier layer exposed outside the core part in the through hole and the surface of the laminated structure far away from the substrate to form the second conductive layer;

and depositing tungsten in the through hole to form the conductive column.

In the method for manufacturing a three-dimensional memory as described above, the step of forming a core in the through hole includes:

depositing polysilicon in the through hole and on the surface of the laminated structure far away from the substrate;

and etching to remove the polysilicon on the laminated structure and part of the polysilicon in the through hole, wherein the polysilicon remained in the through hole forms the core part.

depositing silicon dioxide on the substrate exposed in the through hole, the inner side wall of the through hole and the surface of the laminated structure, which is opposite to the substrate, along the direction from the bottom end to the top end of the through hole, and forming a first core part and a residual layer on the inner side wall of the through hole and the laminated structure;

etching to remove the allowance layer;

depositing polysilicon over the first core in the via and a surface of the stack remote from the substrate;

and etching to remove the polysilicon on the laminated structure and part of the polysilicon in the through hole, wherein the polysilicon left in the through hole forms a second core part.

depositing doped polysilicon in the through hole and on the surface of the laminated structure far away from the substrate, wherein the doped polysilicon is doped with impurity atoms with the concentration of at least 10%;

etching to remove the doped polysilicon on the laminated structure and part of the doped polysilicon in the through hole, wherein the residual doped polysilicon in the through hole forms a first core part;

and etching to remove the polysilicon on the laminated structure and part of the polysilicon in the barrier layer, wherein the polysilicon left in the through hole forms a second core part.

In the method for manufacturing the three-dimensional memory, the step of depositing tungsten on the second conductive layer to form the conductive pillar includes:

depositing tungsten on the second conductive layer, the tungsten covering the second conductive layer;

and chemically and mechanically grinding the tungsten on the laminated structure, wherein the tungsten in the through hole forms a conductive column.

In the method for manufacturing a three-dimensional memory, the step of forming the stacked structure on the substrate includes:

alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on the substrate;

forming the gate line slit penetrating the insulating layers and the sacrificial layers;

removing each sacrificial layer to form a plurality of cavities;

and filling a conductive material into each cavity to form a plurality of gate layers.

Before forming the structure insulating layer in the gate line gap, the method for manufacturing the three-dimensional memory further includes:

and forming a doped region on the substrate by taking the gate line gap as an ion implantation channel, wherein the doped region is electrically connected with the common source pole.

The method for manufacturing the three-dimensional memory provided by the embodiment of the invention is used for manufacturing the three-dimensional memory, and therefore, the method has the same advantages as those of the three-dimensional memory, and is not repeated herein.

In addition to the technical problems solved by the present invention, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems that can be solved by the three-dimensional memory and the manufacturing method thereof provided by the embodiments of the present invention, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.

Drawings

In order to illustrate embodiments of the invention or prior art solutions more clearly, the drawings that are needed in the description of the embodiments of the invention or prior art will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the invention, and that these drawings and the written description are not intended to limit the scope of the disclosed concept in any way, but rather to illustrate it to those skilled in the art by referring to specific embodiments, and that other drawings may be obtained from these drawings without inventive effort to those skilled in the art.

FIG. 1 is a schematic block diagram of a three-dimensional memory provided by an embodiment of the present invention;

FIG. 1a is an enlarged view of a portion of FIG. 1A;

FIGS. 1 b-1 f are schematic diagrams of various stages in a three-dimensional memory fabrication process according to an embodiment of the invention;

FIGS. 2 a-2 e are schematic diagrams of the core portion of the three-dimensional memory according to an embodiment of the invention at various stages in the fabrication process;

FIGS. 3 a-3 f are schematic diagrams of the core portion of the three-dimensional memory according to the second embodiment of the invention at various stages in the fabrication process;

FIGS. 4 a-4 f are schematic diagrams of the core portion fabrication process of the three-dimensional memory according to the third embodiment of the invention at various stages;

FIG. 5 is a graph of the linear relationship between the warpage of the wafer and the thickness of the stacked structure;

FIG. 6 is a flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention;

fig. 7 is a flowchart of S700 in fig. 6 for forming a common source pole in the via hole.

Description of reference numerals:

10-a substrate; 11-doped region; 20-a laminated structure;

21-an insulating layer; 22-gate layer; 23-a protective layer;

24-channel holes; 25-a grid line gap; 26-accommodating grooves;

27-channel structure; 30-a structural insulating layer; 31-a through hole;

40-common source pole; 41-a stress adjusting layer; 51-a first conductive layer;

52-a second conductive layer; 60-a core; 61-a first core;

62-a second core; 63-polycrystalline silicon; 64-silica;

65-doped polysilicon; 70-conductive post.

Detailed Description

The three-dimensional memory generally comprises a laminated structure and a common source pole penetrating through the laminated structure, wherein the common source pole is positioned in a grid line gap of the laminated structure, and the common source pole generally comprises a core part formed by polycrystalline silicon, and the polycrystalline silicon expands to generate tensile stress; when larger storage capacity is needed to be obtained in a unit area, the lamination number of the laminated structures in the three-dimensional storage is larger and larger, the polysilicon in the common source pole is also larger and larger, the increase of the polysilicon causes larger and larger tensile stress, and the increased tensile stress easily causes the inclination or collapse of the laminated structures. In order to solve the above problems, in the embodiment of the present invention, the stress adjustment layer is disposed in the gate line gap of the three-dimensional memory, and the stress adjustment layer can generate a compressive stress opposite to the tensile stress of the polysilicon, and the compressive stress is used to balance or offset the tensile stress, so as to avoid the problem of the inclination and even collapse of the stacked structure caused by the excessive tensile stress.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, fig. 1a, and fig. 1b to fig. 1f, a three-dimensional memory according to an embodiment of the present invention includes a substrate 10 and a stacked structure 20, wherein the stacked structure 20 is disposed on the substrate 10, and a channel hole 24 and a gate line slit 25 are disposed in the stacked structure 20 and penetrate through the stacked structure 20. A channel structure 27 is arranged in the channel hole 24, and one end of the channel structure 27 extends to the substrate 10; a structure insulating layer 30 and a common source pole 40 located in the structure insulating layer 30 are disposed in the gate line gap 25, and one end of the common source pole 40 extends to the substrate 10 and is electrically connected to one end of the channel structure 27 extending to the substrate 10.

The substrate 10 may be made of single crystal Silicon, or may be made of other materials, such as Silicon-germanium, or a Silicon-On-Insulator (SOI) thin film On an insulating substrate. In order to effectively protect the substrate 10 and the stacked structure 20, as shown in fig. 1, a protective layer 23 is further disposed between the substrate 10 and the stacked structure 20, and the material of the protective layer 23 may be the same as the material of the insulating layer 21 in the stacked structure 20.

The regions in the substrate 10 corresponding to the channel hole 24 and the gate line slit 25 are respectively provided with a first opening and a second opening, and the first opening and the second opening both extend through the protective layer 23, that is, the regions in the protective layer 23 corresponding to the first opening and the second opening are also respectively provided with openings. The first opening is located below the subsequently formed common source pole 40, and the common source pole 40 passes through the first opening to be electrically connected with the doped region 11 on the substrate 10; the second opening is located below a subsequently formed channel structure, and the channel structure is electrically connected to the epitaxial region on the substrate 10 through the second opening, so that the common source pole 40 and the channel structure 40 form a loop. The doped region 11 is used to reduce the contact resistance between the first conductive layer 51 in the subsequently formed common source post 40 and the substrate 10, and to reduce the contact resistance between the channel structure 27 and the substrate 10.

With continued reference to fig. 1, a stacked structure 20 is disposed on the substrate 10, and it is understood that one stacked structure 20 may be disposed on the substrate 10, or a plurality of stacked structures 20 may be disposed on the substrate. FIG. 1a is an enlarged view of a portion of FIG. 1A; as shown in fig. 1a, the stacked structure 20 includes a plurality of gate layers 22 and a plurality of insulating layers 21 alternately disposed, in some embodiments, the gate layers 22 are made of a conductive material, which may be a combination of one or more of tungsten, cobalt, copper, aluminum, doped silicon and metal silicide, or other suitable materials; the insulating layer 21 is made of an insulating material, and may be one or a combination of silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.

As shown in fig. 1b, a channel hole 24 is provided in the stacked structure 20 to penetrate through the stacked structure 20, that is, the channel hole 24 is formed in the stacked structure 20 and penetrates through each gate layer 22 and each insulating layer 21, and the channel hole 24 extends in a direction perpendicular or substantially perpendicular to the substrate 10, that is, the channel hole 24 is a through hole penetrating through each gate layer 22 and each insulating layer 21. The channel hole 24 extends to the substrate 10 toward one end of the substrate 10, i.e., the lower end of the channel hole 24 as shown in fig. 1. It should be noted that as shown in fig. 1b, the diameters of different portions of the channel hole 24 may be different in a direction perpendicular to the substrate 10, so that the substantially perpendicular direction in this embodiment means that the angle between the channel hole 24 and the substrate 10 is close to 90 °, i.e. may be slightly smaller than 90 ° or slightly larger than 90 °.

As shown in fig. 1c, a channel structure 27 is disposed in the channel hole 24, and the channel structure 27 may be, for example, a channel pillar, which penetrates the stacked structure 20. The channel structure 27 comprises a functional layer and a channel layer positioned in the functional layer, the channel layer is used as a core part of the channel structure 27, the functional layer comprises a tunneling dielectric layer, a charge storage layer and a gate dielectric layer which are arranged around the outer side of the core part, and the tunneling dielectric layer is positioned in an inner layer and is in contact with the channel layer in the tunneling dielectric layer, the charge storage layer and the gate dielectric layer; the gate dielectric layer is positioned on the outer layer and is in contact with the inner side surface of the channel hole 24; the charge storage layer is positioned between the tunneling dielectric layer and the gate dielectric layer and is respectively contacted with the tunneling dielectric layer and the gate dielectric layer.

Specifically, the channel structure 27 sequentially includes, from inside to outside, a channel layer, a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer, the gate dielectric layer is located between the channel layer and the gate layer 22 exposed in the channel hole 24, and the channel layer, the gate dielectric layer, and the gate layer 22 form a select transistor; meanwhile, the channel layer, the tunneling dielectric layer, the charge storage layer, the gate dielectric layer, and the gate layer 22 form a memory transistor.

Illustratively, the material of the channel layer may be polysilicon; the tunneling dielectric layer and the gate dielectric layer are made of oxide, such as silicon dioxide; the charge storage layer is composed of an insulating layer 21 containing quantum dots or nanocrystals, such as silicon nitride containing particles of a metal or a semiconductor; the channel layer is used for providing channel regions of the control transistor and the control transistor, the doping type of the channel layer is the same as that of the selection transistor and the control transistor, for example, the selection transistor and the control transistor are N-type, and the material of the channel layer can be N-type doped polysilicon. In this embodiment, the middle portion of the channel layer is made of silicon dioxide, and the two ends of the channel layer are made of single crystal silicon.

As shown in fig. 1b and 1c, a gate line slit 25 is further disposed in the stacked structure 20 and penetrates through the stacked structure 20, the gate line slit 25 extends to the substrate 10, and the gate line slit 25 extends in a direction perpendicular or substantially perpendicular to the substrate 10 in the stacked structure 20.

As shown in fig. 1a and 1d, a structural insulating layer 30 and a common source electrode post 40 are disposed in the gate line gap 25, and in one possible implementation, the structural insulating layer 30 is filled in the gate line gap 25, and a through hole 31 extending to the substrate 10 is formed in the middle of the structural insulating layer 30 along a direction perpendicular or substantially perpendicular to the substrate 10, and the common source electrode post 40 is located in the through hole 31. The structural insulating layer 30 is generally made of an insulating material such as silicon dioxide, and the common source electrode 40 is generally made of a conductive material.

In order to improve the bonding force between the structure insulating layer 30 and the gate line slit 25, illustratively, as shown in fig. 1b, 1c and 1d, a plurality of accommodating grooves 26 are spaced apart from each other on the inner side surface of the gate line slit 25 along the extending direction of the gate line slit 25, i.e., along the direction perpendicular or substantially perpendicular to the substrate 10, and each accommodating groove 26 is recessed into the stacked structure 20; correspondingly, a plurality of extending portions are disposed on the structural insulating layer 30 at intervals, and each extending portion is embedded in a corresponding one of the receiving grooves 26. Therefore, the contact area between the structural insulating layer 30 and the inner side surface of the gate line gap 25 can be increased, and the bonding force between the two is improved; meanwhile, since the extending portions of the structural insulating layer 30 are respectively embedded into the corresponding receiving grooves 26, an inter-engaging structure is formed, so that the structural insulating layer 30 is restricted from moving in a direction perpendicular or substantially perpendicular to the substrate 10, and the structural insulating layer 30 is prevented from falling off from the gate line slit 25.

The receiving groove 26 is a groove formed in the inner side surface of the gate line slit 25, and the receiving groove 26 may be exemplarily formed of one gate layer 22 and two insulating layers 21 on upper and lower sides of the gate layer 22, or one insulating layer 21 and two gate layers 22 on upper and lower sides of the insulating layer 21. For example, in the end portion of each gate electrode layer 22 and the end portion of each insulating layer 21 located in the gate line gap 25, the end portion of each gate electrode layer 22 is recessed with respect to the two adjacent insulating layers 21, or the extension length of the gate electrode layer 22 extending to the gate line gap 25 is smaller than the extension length of the gate line gap 25 of the insulating layer 21, a receiving groove 26 is formed between the end portion of the gate electrode layer 22 and the two adjacent insulating layers 21 of the gate electrode layer 22, the bottom of the receiving groove 26 is the end portion of the gate electrode layer 22 located in the gate line gap 25, and two side surfaces of the receiving groove 26 are respectively opposite side surfaces of the two insulating.

As shown in fig. 1a, the common source electrode post 40 is located in the structural insulating layer 30, the common source electrode post 40 sequentially includes a first conductive layer 51, a stress adjustment layer 41 and a core portion 60 from outside to inside, the first conductive layer 51 is formed in the through hole 31 of the structural insulating layer 30, specifically on the inner side surface of the through hole 31 and the substrate 10 exposed in the through hole 31, so as to electrically connect the first conductive layer 51 and the substrate 10.

As shown in fig. 1e, the first conductive layer 51 penetrates through the stacked structure 20, the first conductive layer 51 may be a hollow structure, one end of the hollow structure extending to the substrate 10 is closed, and a lower end of the first conductive layer 51 is a closed end, the closed end extends into the substrate 10 and contacts the doped region 11, and is electrically connected to one end of the channel structure 27 extending to the substrate 10; the other end of the first conductive layer 51 is provided with an opening for forming the stress adjusting layer 41 and the core 60 within the hollow structure, that is, the upper end of the first conductive layer 51 shown in fig. 1e is an open end provided with an opening from which material forming the stress adjusting layer 41 and the core 60 can be deposited into the hollow structure of the first conductive layer 51.

The first conductive layer 51 may include a layer of conductive material or multiple layers of conductive material, which may be titanium, titanium nitride, or a combination of the two. Illustratively, the first conductive layer 51 includes a layer of titanium and a layer of titanium nitride, which provides the benefits of: titanium forms a contact region with the doped region 11 located in the substrate 10, the contact region generates a polycrystalline compound of titanium and silicon, and the polycrystalline compound of titanium and silicon has conductivity, so that the first conductive layer 51 can form good ohmic contact with the doped region 11, and the contact resistance between the two is reduced. In addition, titanium nitride is formed inside the titanium layer for protecting the structural insulating layer 30.

It should be noted that, because the structure insulating layer 30 and the trench structure 27 are generally made of silicon dioxide, when the stress adjustment layer 41 or the metal layer is formed by subsequent deposition of tungsten, a chemical vapor deposition method is usually adopted, hydrogen fluoride gas is generated during the deposition process, and the hydrogen fluoride gas corrodes the silicon dioxide, so that the titanium nitride layer included in the first conductive layer 51 in this embodiment can block the hydrogen fluoride gas and prevent the structure insulating layer 30 and the trench structure 27 from being corroded by the hydrogen fluoride gas, that is, the titanium nitride layer can protect the structure insulating layer 30 and the trench structure 27.

As shown in fig. 1f, a stress adjustment layer 41 is formed in the first conductive layer 51, and the stress adjustment layer 41 covers the first conductive layer 51. Since the core 60 of the common source post 40 comprises polysilicon, the resulting tensile stress of the polysilicon may affect the stability of the stack 20 and thus the three-dimensional memory as a whole. The present embodiment provides the stress adjustment layer 41 between the first conductive layer 51 and the core 60 to adjust the stress generated by the core 60. The stress adjustment layer 41 is a metal layer capable of generating a shrinkage stress, for example, the material of the stress adjustment layer 41 may be tungsten, and may also be other suitable materials.

Illustratively, a layer of tungsten is deposited on the first conductive layer 51 to form the stress adjustment layer 41, on one hand, the tungsten forms a hard shell and plays a role of structural support for the gate line slit 25, so that the stacked structure 20 and the three-dimensional memory are more stable; on the other hand, tungsten can shrink when being formed into a solid state, so that a compressive stress which shrinks inwards in the radial direction of the through hole 31 is generated, and when the core part 60 is formed in the through hole 31, the tensile stress generated by the polysilicon in the core part 60 and the compressive stress generated by the tungsten are offset, so that the influence of the tensile stress on the inner wall of the through hole 31 is reduced, and the laminated structure 20 is prevented from inclining or collapsing towards two sides due to the stress action. In addition, tungsten has conductivity, and depositing tungsten on the first conductive layer 51 increases the metal area, reduces resistance, and improves the conductive efficiency.

The core portion 60 of the common source pole 40 is formed in the stress adjustment layer 41, and the common source pole 40 further includes a conductive pillar 70, and the conductive pillar 70 is also formed in the stress adjustment layer 41. Illustratively, as shown in fig. 1 and 1a, the conductive pillar 70 is disposed at an end of the core 60 away from the substrate 10, and a second conductive layer 52 is further disposed between the conductive pillar 70 and the core 60, where the second conductive layer 52 covers a circumferential sidewall of the conductive pillar 70 and an end of the core 60 away from the substrate 10.

In one possible embodiment, the material of the conductive post 70 is tungsten, and in some embodiments, the material of the second conductive layer 52 between the conductive post 70 and the core 60 includes titanium and/or titanium nitride. It should be noted that, since tungsten generates hydrogen fluoride gas during deposition, and hydrogen fluoride easily corrodes silicon dioxide, when the core portion 60 includes silicon dioxide, the core portion 60 can be prevented from being etched by hydrogen fluoride by using the titanium nitride layer included in the second conductive layer 52, i.e., the titanium nitride layer can protect the core portion 60.

It should be noted that the common source terminal 40 is used for interconnecting the memory cell strings in the three-dimensional memory, and the core 60 may be used as an Array Common Source (ACS), which is a structure with high conductivity requirement, and is usually formed by filling with tungsten or polysilicon. The core 60 in this embodiment comprises polysilicon, for example, the core 60 may be provided as a polysilicon core, as a core comprising silicon dioxide and polysilicon, or as a core comprising polysilicon and other suitable materials. The specific structure and material of the core 60 are described in the following embodiments, respectively.

Example one

In the three-dimensional memory provided by the first embodiment of the present invention, the core 60 of the common source pole 40 is configured as a polysilicon core.

FIGS. 1 b-1 f are schematic diagrams of various stages in a three-dimensional memory fabrication process according to an embodiment of the invention; FIGS. 2 a-2 e are schematic diagrams of the core portion of the three-dimensional memory according to an embodiment of the invention at various stages in the fabrication process; as shown in fig. 1b to 1f and fig. 2a to 2e, the three-dimensional memory includes a substrate 10, a stacked structure 20 disposed on the substrate 10, and a channel hole 24 and a gate line slit 25 penetrating the stacked structure 20; a channel structure 27 is arranged in the channel hole 24; a structural insulating layer 30 and a common source pole 40 positioned in the structural insulating layer 30 are arranged in the grid line gap 25; the common source pole 40 includes a first conductive layer 51, a stress adjustment layer 41, and a core 60, wherein a conductive pillar 70 is disposed at an end of the core 60 away from the substrate 10, and a second conductive layer 52 is disposed between the conductive pillar 70 and the core 60. The material of the core 60 in this embodiment is provided as polysilicon, i.e. as a polysilicon core.

Specifically, the material of the structural insulating layer 30 is silicon dioxide, a through hole 31 is formed in the structural insulating layer 30, and a first conductive layer 51, a stress adjustment layer 41, and a core 60 made of polysilicon are sequentially disposed in the through hole 31 from outside to inside. The first conductive layer 51 includes a titanium layer and a titanium nitride layer, the stress adjustment layer 41 is a tungsten layer, the core portion 60 is located in the tungsten layer, the second conductive layer 52 includes a titanium layer and a titanium nitride layer, and the conductive pillar 70 is a tungsten pillar. Additionally, a layer of titanium and/or titanium nitride may be disposed between the core 60 and the tungsten layer.

In the three-dimensional memory provided by the embodiment, the tungsten layer is arranged in the gate line gap 25 as the stress adjusting layer 41, and the compressive stress generated by the tungsten layer is used for balancing or offsetting the tensile stress generated by the core part 60 made of polysilicon in the common source pole 40, so that the acting force of the common source pole 40 on the surrounding laminated structure 20 is reduced, and the possibility of stress inclination or collapse of the laminated structure 20 is reduced or avoided.

Example two

In the three-dimensional memory provided by the second embodiment of the present invention, the core 60 of the common source pole 40 includes a first core 61 and a second core 62, the first core 61 is configured as a silicon dioxide core, and the second core 62 is configured as a polysilicon core.

FIGS. 1 b-1 f are schematic diagrams of various stages in a three-dimensional memory fabrication process according to an embodiment of the invention; FIGS. 3 a-3 f are schematic diagrams of the core portion of the three-dimensional memory according to the second embodiment of the invention at various stages in the fabrication process; as shown in fig. 1b to 1f and fig. 3a to 3f, the three-dimensional memory provided by the embodiment of the invention includes a substrate 10, a stacked structure 20 disposed on the substrate 10, and a channel hole 24 and a gate line slit 25 penetrating through the stacked structure 20; a channel structure 27 is arranged in the channel hole 24; a structural insulating layer 30 and a common source pole 40 positioned in the structural insulating layer 30 are arranged in the grid line gap 25; the common source pole 40 includes a first conductive layer 51, a stress adjustment layer 41 and a core 60, in the embodiment, the core 60 includes a first core 61 and a second core 62 stacked, and the first core 61 is close to the substrate 10 relative to the second core 62; an end of the second core part 62 remote from the first core part 61 is provided with a conductive pillar 70, and a second conductive layer 52 is further provided between the conductive pillar 70 and the second core part 62.

Specifically, the material of the structural insulating layer 30 is silicon dioxide, a through hole 31 is formed in the structural insulating layer 30, and a first conductive layer 51, a stress adjustment layer 41, and a core 60 are sequentially disposed in the through hole 31 from outside to inside. The first conductive layer 51 includes a titanium layer and a titanium nitride layer, the stress adjusting layer 41 is provided as a tungsten layer, the second conductive layer 52 includes a titanium layer and a titanium nitride layer, and the conductive pillar 70 is provided as a tungsten pillar.

In the present embodiment, the first core 61 is a silicon dioxide core formed at a portion close to the substrate 10, and the second core 62 is a polysilicon core formed at an end of the silicon dioxide core remote from the substrate 10. The depth of the silica core may be set to 1/5-1/3 of the depth of the through-hole 31 in the direction perpendicular to the substrate 10, and specifically, the depth of the silica core is 1/4 of the depth of the through-hole 31. In addition, a layer of titanium and/or titanium nitride may be disposed between the silicon dioxide core and the polysilicon core for adhering and isolating the silicon dioxide core and the polysilicon core.

The common source electrode column 40 in this embodiment further includes a barrier layer, which is located between the silicon dioxide core and the tungsten layer, and the barrier layer may be a titanium nitride layer, or a composite layer composed of a titanium layer and a titanium nitride layer, and the titanium nitride layer is used to protect the silicon dioxide core and prevent the silicon dioxide core from being corroded by hydrogen fluoride gas generated when tungsten is deposited.

In the three-dimensional memory provided by the embodiment, the tungsten layer is arranged in the gate line gap 25 to serve as the stress adjusting layer 41, and the compressive stress generated by the tungsten layer is utilized to balance or offset the tensile stress generated by the polysilicon in the common source pole 40, so that the acting force of the common source pole 40 on the surrounding laminated structure 20 is reduced; moreover, since the silicon dioxide is soft and generates less local stress, the present embodiment reduces the tensile stress generated by the conventional polysilicon core by combining the silicon dioxide core with the polysilicon core, thereby further reducing the acting force on the laminated structure 20 and reducing or avoiding the possibility of the laminated structure 20 being inclined or collapsed due to stress.

EXAMPLE III

In the three-dimensional memory provided by the third embodiment of the present invention, the core 60 of the common source pole 40 includes a first core 61 and a second core 62, the first core 61 is configured as a doped polysilicon core, and the second core 62 is configured as a polysilicon core.

FIGS. 1 b-1 f are schematic diagrams of various stages in a three-dimensional memory fabrication process according to an embodiment of the invention; FIGS. 4 a-4 f are schematic diagrams of the core portion fabrication process of the three-dimensional memory according to the third embodiment of the invention at various stages; as shown in fig. 1b to 1f and fig. 4a to 4f, the three-dimensional memory provided by the embodiment of the invention includes a substrate 10, a stacked structure 20 disposed on the substrate 10, and a channel hole 24 and a gate line slit 25 penetrating through the stacked structure 20; a channel structure 27 is arranged in the channel hole 24; a structural insulating layer 30 and a common source pole 40 positioned in the structural insulating layer 30 are arranged in the grid line gap 25; the common source pole 40 includes a first conductive layer 51, a stress adjustment layer 41 and a core 60, in the embodiment, the core 60 includes a first core 61 and a second core 62 stacked, and the first core 61 is close to the substrate 10 relative to the second core 62; an end of the second core part 62 remote from the first core part 61 is provided with a conductive pillar 70, and a second conductive layer 52 is provided between the conductive pillar 70 and the second core part 62.

Specifically, the material of the structural insulating layer 30 is silicon dioxide, a through hole 31 is formed in the structural insulating layer 30, and a first conductive layer 51, a stress adjustment layer 41, and a core 60 are sequentially disposed in the through hole 31 from outside to inside. The first conductive layer 51 includes a titanium layer and a titanium nitride layer, the second conductive layer 52 includes a titanium layer and a titanium nitride layer, and the conductive pillars 70 are provided as tungsten pillars. In the present embodiment, the core portion 60 may be provided directly in the first conductive layer 51 without providing a stress adjustment layer in the through hole 31.

In this embodiment, the first core 61 is a doped polysilicon core formed at a location close to the substrate 10 and the second core 62 is a polysilicon core formed at an end of the doped polysilicon core remote from the substrate 10. Furthermore, a layer of titanium and/or titanium nitride may be disposed between the doped polysilicon core and the polysilicon core for adhering and isolating the silicon dioxide core and the polysilicon core.

Since the doped polysilicon generates a smaller tensile stress than the undoped polysilicon, by providing the first core 61 as doped polysilicon in the present embodiment, the tensile stress generated by the first core 61 is reduced, ensuring stability of the stacked structure 20 adjacent to the core close to the substrate 10. When the doped polysilicon has a depth equal to or slightly greater than 1/5 of the depth of the via 31, the core and adjacent stack 20 tend to stabilize. The depth of the doped polysilicon core in the direction perpendicular to the substrate 10 in this embodiment may be set to 1/5-1/3 of the depth of the via 31 in the structural insulating layer 30, for example, the depth of the doped polysilicon core is 1/4 of the depth of the via 31.

In a general process, when undoped polysilicon is used as a core to fill the gate line gap 25, the stacked structure 20 may be deformed to cause warpage of the wafer, which affects subsequent bonding connection with other circuit devices, but in the embodiment of the present invention, the doped polysilicon is changed in its own characteristics, and the generated local stress is also changed, that is, in this embodiment, the doped polysilicon doped with impurity atoms of a certain concentration is used as the first core 61, so as to change the stress applied to the stacked structure 20, thereby reducing or eliminating the warpage of the wafer.

In the process of manufacturing the three-dimensional memory, the wafer may be divided into an X direction and a Y direction perpendicular to each other, and the Y direction may be set as a vertical direction. Then, two points with a certain distance are taken in the Y direction, the distance between the projections of the two points is measured, and whether the wafer is warped or not and the warping degree can be judged by using the change of the projection distance. When the doping concentration of the impurity atoms is changed, the change of the warping degree of the wafer is judged through multiple times of measurement, so that the warping degree of the wafer is adjusted to be within the range required by the process.

Fig. 5 is a linear relationship graph of the measured warpage of the wafer in the Y direction and the thickness of the stacked structure 20, as shown in fig. 5, when the doping concentration is 10% or more of the impurity atoms, the warpage of the wafer is not significantly changed with the thickness of the stacked structure 20, that is, when the thickness of the stacked structure 20 is gradually increased, the doped polysilicon has a lower influence on the stacked structure 20, so that the structure of the three-dimensional memory is more stable, and the warpage of the wafer due to the stress unevenness is reduced, compared to the undoped polysilicon or the polysilicon with the doping concentration of 5% or less.

Thus, in the embodiment, the doped polysilicon core is doped with impurity atoms with a concentration greater than or equal to 10%, the impurity atoms include one or more of phosphorus atoms, arsenic atoms and nitrogen atoms, for example, the doped polysilicon core can be doped with phosphorus atoms with a concentration of 10%, or doped with arsenic atoms with a concentration of 15%; when doping, silane can be used as silicon base, NH is used₃、PH₃Or AsH₃As a doping element, thereby forming doped polysilicon having impurity atoms.

The three-dimensional memory provided by the embodiment comprises a first core part 61 made of doped polysilicon and a second core part 62 made of polysilicon, wherein the doped polysilicon is softer and generates less local stress, and the doped polysilicon core part and the polysilicon core part are combined to reduce the tensile stress generated by the traditional polysilicon core part, so that the acting force generated on the laminated structure 20 is reduced, and the possibility of inclination or collapse of the laminated structure 20 under stress is reduced or avoided; moreover, the doped polysilicon core is doped with impurity atoms, so that the warping degree of the wafer is reduced.

In summary, in the three-dimensional memory provided in this embodiment, tungsten is deposited in the gate line gap 25 as the stress adjustment layer 41, and the compressive stress generated after the tungsten is cured is used to balance or offset the tensile stress generated by the polysilicon in the common source electrode 40, so that the acting force of the common source electrode 40 on the surrounding stacked structure 20 is reduced, and the possibility of stress inclination or collapse of the stacked structure 20 is reduced or avoided.

As shown in fig. 6, an embodiment of the present invention further provides a method for manufacturing a three-dimensional memory, which is used for manufacturing the three-dimensional memory according to the foregoing embodiments, and the method includes the following steps:

s100, providing a substrate 10; illustratively, the substrate 10 may be a single crystal silicon substrate, or may be a silicon germanium substrate or a germanium substrate.

S200, forming a stacked structure 20 on the substrate 10, wherein the step of forming the stacked structure 20 on the substrate 10 includes alternately stacking a plurality of insulating layers 21 and a plurality of sacrificial layers on the substrate 10, the insulating layers 21 and the sacrificial layers may be formed by using a thin film deposition process, including but not limited to a Chemical Vapor Deposition (CVD) method or an atomic layer deposition (a L D), and after forming the gate line slit 25 in the subsequent step S300, the gate line slit 25 is used as a channel, each sacrificial layer in the stacked structure 20 may be removed by dry etching or wet etching, a plurality of cavities are formed, a conductive material is filled into each cavity, and a gate layer 22 is formed between every two adjacent insulating layers 21.

S300, forming a channel hole 24 and a grid line gap 25 penetrating through the laminated structure 20 in the laminated structure 20; the structure formed in this step is shown in fig. 1b, and the channel hole 24 and the gate line slit 25 extend from the surface of the stacked structure 20 away from the substrate 10, through the plurality of insulating layers 21 and the plurality of sacrificial layers in the stacked structure 20, and into the surface of the substrate 10 or into the substrate 10 in a direction perpendicular or substantially perpendicular to the substrate 10. The manner of forming the trench hole 24 and the gate line slit 25 may be photolithography or dry etching.

It should be noted that after the gate line slit 25 is formed, the method for manufacturing the three-dimensional memory generally further includes: and forming a doped region 11 on the substrate 10 by using the gate line slit 25 as an ion implantation channel, wherein the doped region 11 is used for electrically connecting with a subsequently formed common source pole 40.

S400, forming a channel structure 27 in the channel hole 24, wherein one end of the channel structure 27 extends to the substrate 10 and is electrically connected with the doped region 11; the structure formed in this step is shown in FIG. 1 c. The channel structure 27 may be provided as a channel pillar, and may be formed in the channel hole 24 by a chemical vapor deposition method. A channel pillar is formed in the channel hole 24 and extends through the stacked structure 20, with a lower end of the channel pillar extending to a surface of the substrate 10 or into the substrate 10. The channel structure 27 includes a functional layer and a channel layer located inside the functional layer, the channel layer is used as a core of the channel structure 27, the functional layer includes a tunneling dielectric layer, a charge storage layer and a gate dielectric layer disposed around the outer side of the core, and the specific arrangement and function may refer to the above description.

In one possible embodiment, after the channel structure 27 is formed in the communication hole 24, the method for manufacturing the three-dimensional memory further includes: the surface of the laminated structure 20 remote from the substrate 10 is polished flat, and a planarization layer (the topmost layer in fig. 1 c) is formed on the surface of the polished laminated structure 20 remote from the substrate 10, and an opening is provided in a region of the protection layer corresponding to the gate line slit 25 to expose the gate line slit 25.

S500, forming a structural insulating layer 30 in the gate line gap 25; the structure formed after this step is shown in fig. 1d, and the connection manner and function of the structure insulating layer 30 and the gate line slit 25 can refer to the related description above, and will not be described again here. The structural insulating layer 30 may be formed in various manners, for example, the structural insulating layer 30 may be formed by thermal growth and/or thin film deposition, and the material of the structural insulating layer 30 may be silicon dioxide.

S600, forming a through hole 31 penetrating through the substrate 10 in the structural insulating layer 30; specifically, the through hole 31 in the structural insulating layer 30 may be formed by using photolithography, a dry etching process or a wet etching process, as shown in fig. 1d, where the through hole 31 penetrates through the structural insulating layer 30 and extends to the surface of the substrate 10. Note that, in this step, after the through hole 31 is formed, the doped region 11 on the substrate 10 is exposed in the through hole 31.

S700, forming a common source pole 40 in the through hole 31; the common source pole 40 is located in the through hole 31, and the lower end thereof is electrically connected to the doped region in the substrate 10. The common source electrode post 40 includes a first conductive layer 51, a stress adjustment layer 41 and a core portion 60, wherein the first conductive layer 51 penetrates through the stacked structure 20, and one end of the first conductive layer 51 extends to the substrate 10 to be electrically connected with the doped region 11, and is thereby electrically connected with one end of the channel structure 27 extending to the substrate 10.

In the method for manufacturing the three-dimensional memory provided in this embodiment, tungsten is deposited in the through hole 31 of the structural insulating layer 30, and when the tungsten is cured to form the hard shell-shaped stress adjustment layer 41, stress that contracts inward along the radial direction of the through hole 31 is generated; the present embodiment utilizes the balance or offset between the compressive stress generated by the stress adjustment layer 41 made of tungsten and the tensile stress generated by the polysilicon in the core portion 60, so as to reduce the acting force on the surrounding laminated structure 20 and reduce or avoid the possibility of the laminated structure 20 being tilted or collapsed due to stress.

As shown in fig. 7, the step S700 generally includes:

s710, depositing a titanium layer and a titanium nitride layer in the through hole 31 and on the surface of the stacked structure 20 away from the substrate 10 in sequence to form the first conductive layer 51, as shown in fig. 1e, the first conductive layer 51 covers the inner sidewall of the through hole 31, the surface of the substrate 10 (or the surface of the doped region 11) exposed in the through hole 31, and the surface of the stacked structure 20 away from the substrate 10. In this step, the titanium layer and the titanium nitride layer may be deposited by chemical vapor deposition or physical vapor deposition.

S720, depositing tungsten on the first conductive layer 51 to form the stress adjustment layer 41, as shown in fig. 1f, the stress adjustment layer 41 covers the first conductive layer 51, that is, the stress adjustment layer 41 covers a portion of the first conductive layer 51 located in the through hole 31 and another portion of the first conductive layer 51 located on the surface of the stacked structure 20 away from the substrate 10. The stress adjustment layer 41 is made of a metal material that can generate compressive stress or tensile stress, and the stress adjustment layer 41 may be provided as a tungsten layer and may be deposited by using a chemical vapor deposition method.

S730, depositing titanium nitride on the stress adjusting layer 41 to form a barrier layer, wherein the barrier layer covers the stress adjusting layer 41; the barrier layer formed of titanium nitride serves to block between tungsten and the subsequently formed core 60, preventing the core 60 from being corroded by hydrogen fluoride gas. In addition to serving as a conductive and adhesive core 60, the barrier layer may be provided as a titanium nitride layer alone or as a composite layer including a titanium layer and a titanium nitride layer.

S740, forming a core part 60 on the inner side surface and the bottom surface of the stress adjusting layer 41 or on the inner side surface and the bottom surface of the barrier layer; the structure formed in this step can be referred to fig. 1 and 1 a. It should be noted that, after the above steps are completed, the first conductive layer 51, the stress adjustment layer 41 and the barrier layer are sequentially formed on the inner side wall of the through hole 31 and the substrate 10 exposed at the bottom end of the through hole 31 from outside to inside, in this step, the core 60 is formed in the through hole 31 and is located in the space enclosed by the barrier layer in the through hole 31 and is in contact with the barrier layer, and one end of the core 60 away from the substrate 10 is vertically lower than one end of the through hole 31 away from the substrate, so as to leave a space for forming the conductive post 70 in the through hole 31 subsequently.

In this step, there are various ways to form the core portion 60, and please refer to the specific steps described in the preparation methods provided in the following fourth, fifth and sixth embodiments for the three-dimensional memory provided in different embodiments, respectively.

S750, depositing titanium nitride on one end of the core 60 far away from the substrate 10, the barrier layer exposed outside the core 60 in the through hole 31 and the surface of the laminated structure 20 far away from the substrate 10 to form a second conductive layer 52; the structure formed in this step is shown in fig. 1a, and the position and function of the second conductive layer 52 can refer to the related description above, and are not repeated herein. The second conductive layer 52 may include titanium and/or titanium nitride, and the titanium layer and the titanium nitride layer may be deposited by chemical vapor deposition or physical vapor deposition, for example.

S760, depositing tungsten on the second conductive layer 52 to form the conductive pillar 70. As shown in fig. 1, the conductive column is located above one end of the core 60 away from the substrate 10, i.e., above the upper end of the core 60 in the present embodiment. The method specifically comprises the following steps:

tungsten is deposited on the inner side surface of the second conductive layer 52 located in the through hole 31 and the surface of the second conductive layer 52 located on the stacked structure 20, and the deposition may be specifically performed by using a chemical vapor deposition method: the precursor source used in the deposition may be tungsten hexafluoride WF₆The reducing gas used may be silane SiH₄Or diborane B₂H₆Specifically, tungsten hexafluoride WF can be used₆With silane SiH₄The chemical adsorption of the reaction product to obtain the tungsten material to realize the deposition process.

It should be noted that the method for forming the stress adjustment layer 41 or other structures by depositing tungsten in this embodiment or other embodiments can be made according to the above method. After depositing the tungsten, the tungsten on the stacked structure 20 is subjected to chemical mechanical polishing, and the tungsten in the through hole 31 is remained, so that the conductive pillar 70 is formed.

In the above step S740, there are various ways of forming the core 60, and the method of forming the core 60 will be described in detail below by way of example four, example five, and example six for different core structures.

Example four

On the basis of the foregoing embodiments, the present embodiment is used for manufacturing the three-dimensional memory provided in the first embodiment, and specifically, please refer to fig. 1b to fig. 1f and fig. 2a to fig. 2e, where fig. 2a to fig. 2e are schematic structural diagrams of various stages in a core manufacturing process of the three-dimensional memory provided in the first embodiment of the present invention, which correspond to various steps of the manufacturing method of the three-dimensional memory provided in the present embodiment.

For the three-dimensional memory provided in the first embodiment, as shown in fig. 1e, after depositing titanium and titanium nitride in the through hole 31 of the structural insulating layer 30 to form the first conductive layer 51, as shown in fig. 1f, a layer of tungsten is deposited on the first conductive layer 51 to form the stress adjustment layer 41; a barrier layer of titanium nitride may then be deposited on the tungsten layer. On this basis, step S740 includes:

depositing polysilicon 63 in the via 31 and on the surface of the stack 20 remote from the substrate 10; the structure formed in this step is shown in fig. 2a, the polysilicon 63 is formed in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, that is, the polysilicon 63 covers the inner side and the bottom surface of the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, and the manner of depositing the polysilicon 63 in this step may be an atomic layer deposition process.

The polysilicon 63 on the stacked structure 20 and the portion of the polysilicon 63 in the via 31 are etched away, and the remaining portion of the polysilicon 63 in the via 31 forms the core 60. The structure formed in this step is shown in fig. 2b, and the etching removal refers to performing etching back on a part of the polysilicon 63, and the etching back mode may be dry etching or gas etching.

In the present embodiment, the polysilicon 63 on the stacked structure 20 and the portion of the polysilicon 63 in the through hole 31 are removed by etching back, and the portion of the polysilicon 63 in the through hole 31 is remained, specifically, an end of the remained polysilicon 63 away from the substrate 10 is lower than an end of the through hole 31 away from the substrate in the vertical direction, so as to leave a space for forming the conductive pillar 70 in the through hole 31 later.

On the basis of this, titanium and/or titanium nitride is deposited on the top of the core 60, the inner side walls of the through holes 31 exposed outside the core 60, and the surface of the laminated structure 20 away from the substrate 10 to form the second conductive layer 52, and the structure formed in this step is shown in fig. 2 c.

Tungsten is then deposited over the second conductive layer 52, covering the second conductive layer 52, and the resulting structure is shown in fig. 2 d; the surface of the stack 20 remote from the substrate 10 is then planarized, and may be subjected to a chemical mechanical polishing process, which results in a structure as shown in fig. 2e, wherein tungsten in the via 31 is retained, and a conductive pillar 70 is formed.

In the three-dimensional memory manufactured by the method for manufacturing a three-dimensional memory provided in this embodiment, the compressive stress generated by the stress adjustment layer 41 made of tungsten and the tensile stress generated by the core 60 made of polysilicon are balanced or offset, so that the acting force generated on the laminated structure 20 is reduced, and the possibility that the laminated structure 20 is stressed to incline or collapse is reduced or avoided.

EXAMPLE five

On the basis of the foregoing embodiments, this embodiment is used for manufacturing the three-dimensional memory provided in the second embodiment, and specifically, please refer to fig. 1 b-1 f and fig. 3 a-3 f, where fig. 3 a-3 f are schematic structural diagrams of various stages in a core manufacturing process of the three-dimensional memory provided in the second embodiment of the present invention, which correspond to various steps of the manufacturing method of the three-dimensional memory provided in this embodiment.

For the three-dimensional memory provided in the second embodiment, as shown in fig. 1e, after depositing titanium and titanium nitride in the through hole 31 of the structural insulating layer 30 to form the first conductive layer 51, as shown in fig. 1f, a layer of tungsten is deposited on the first conductive layer 51 to form the stress adjustment layer 41; a titanium nitride layer is then deposited on the tungsten layer to form a barrier layer, which is not shown. On this basis, step S740 includes:

depositing silicon dioxide 64 along the direction from the bottom end to the top end of the through hole 31 by a bottom-up growth process, wherein the step forms a structure as shown in fig. 3a, the silicon dioxide 64 is formed on the substrate 10 exposed in the through hole 31, on the inner side walls of the through hole 31 and on the surface of the laminated structure 20 facing away from the substrate 10, thereby forming a first core part 61 and remaining layers on the inner side walls of the through hole 31 and on the laminated structure 20; when the first core 61 is formed by filling the silicon dioxide 64 in the through hole 31 and the depth of the first core 61 is 1/5-1/3, preferably 1/4 of the depth of the through hole 31, the tensile stress generated by the first core 61 formed of the silicon dioxide 64 is small, and the stacked structure 20 and the three-dimensional memory structure can be kept stable.

Etching to remove the allowance layer; as shown in fig. 3b, the structure formed in this step is formed by a bottom-up growth process, which forms a thin silicon dioxide layer 64, i.e., a residual layer, on the barrier layer exposed outside the first core 61 and on the surface of the stacked structure 20 away from the substrate 10, and then affects the electrical connection between the gate electrode layers 22 and the substrate 10, so that the excess silicon dioxide layer 64 needs to be removed by wet etching, for example, using hydrofluoric acid.

After the first core 61 is formed, a layer of titanium and/or titanium nitride may be deposited on the end of the first core 61 away from the substrate 10 and on the inner side of the barrier layer in the through hole 31 to conduct electricity and adhere the first core 61 to the second core 62 formed later.

Depositing polysilicon 63 over the first core portion 61 in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, wherein the polysilicon 63 is formed in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, that is, the polysilicon 63 covers the inner side surface of the through hole 31 and the top end of the first core portion 61 and the surface of the stacked structure 20 away from the substrate 10, and the structure formed in this step is as shown in fig. 3c, and the manner of depositing the polysilicon 63 may be an atomic layer deposition process.

The polysilicon 63 on the stacked structure 20 and a portion of the polysilicon 63 in the via 31 are etched away, and the remaining polysilicon in the via 31 forms the second core 62. The structure formed in this step is shown in fig. 3d, where the etching removal refers to performing etching back on a portion of the polysilicon 63, and the etching back manner may be dry etching or gas etching. In the present embodiment, a portion of polysilicon 63 in through hole 31 is retained, and specifically, one end of retained polysilicon 63 away from substrate 10 is lower than one end of through hole 31 away from the substrate in the vertical direction, so as to leave a space for forming conductive pillar 70 in through hole 31 later.

On the basis, titanium and/or titanium nitride is deposited on the top of the second core part 62, the inner side wall of the through hole 31 exposed outside the second core part 62 and the surface of the laminated structure 20 far away from the substrate 10 to form a second conductive layer 52; then, depositing tungsten on the second conductive layer 52 to cover the second conductive layer 52, wherein the structure formed in this step is as shown in fig. 3 e; the surface of the stack 20 remote from the substrate 10 is then planarized, and may be subjected to a chemical mechanical polishing process, which results in a structure as shown in fig. 3f, wherein the tungsten in the via 31 is retained, thereby forming the conductive pillar 70.

In the preparation method of the three-dimensional memory provided by the embodiment, when the three-dimensional memory is manufactured, the first core part 61 made of the silicon dioxide 64 is soft in texture, and the generated stress is small; by providing the first core 61 of silicon dioxide 64 in combination with the second core 62 of polysilicon, the tensile stress generated by the conventional polysilicon core is reduced, thereby further reducing the forces applied to the laminated structure 20 and reducing or avoiding the possibility of the laminated structure 20 being stressed to tilt or collapse.

EXAMPLE six

On the basis of the foregoing embodiments, this embodiment is used for manufacturing the three-dimensional memory provided in the third embodiment, and specifically, please refer to fig. 1b to fig. 1f and fig. 4a to fig. 4f, where fig. 4a to fig. 4f are schematic structural diagrams of various stages in a core manufacturing process of the three-dimensional memory provided in the third embodiment of the present invention, which correspond to various steps of the manufacturing method of the three-dimensional memory provided in this embodiment.

For the three-dimensional memory provided in the third embodiment, as shown in fig. 1e, after depositing titanium and titanium nitride in the through hole 31 of the structural insulating layer 30 to form the first conductive layer 51, as shown in fig. 1f, a layer of tungsten is deposited on the first conductive layer 51 to form the stress adjustment layer 41; and then a titanium nitride layer can be deposited on the tungsten layer to form a barrier layer. In addition, in this embodiment, the stress adjustment layer 41 may not be deposited, the core portion 60 may be formed directly inside the first conductive layer 51, and since the first conductive layer 51 includes a titanium layer and a titanium nitride layer, when the stress adjustment layer 41 is not deposited, there is no need to provide a barrier layer. On this basis, step S740 includes:

depositing doped polysilicon 65 in the through hole 31 and on the surface of the stacked structure 20 away from the substrate 10, the doped polysilicon 65 being doped with impurity atoms at a concentration of at least 10%; the doped polysilicon 65 is formed in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, that is, the doped polysilicon 65 covers the inner side and the bottom of the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, and the manner of depositing the doped polysilicon 65 in this step may be an atomic layer deposition process. The structure formed in this step is shown in FIG. 4 a; when impurity atoms are doped, silane can be used as a silicon substrate, and NH is used₃、PH₃Or AsH₃As a doping element, thereby forming doped polysilicon 65 having impurity atoms.

Etching to remove the doped polysilicon 65 on the stacked structure 20 and a part of the doped polysilicon 65 in the through hole 31, wherein the remaining part of the polysilicon 63 in the through hole 31 forms the first core 61; the structure formed in this step is shown in fig. 4b, and the doped polysilicon 65 may be etched by gas etching, for example, C₄F₈、C₄F₆、CH₂F₂And O₂Is etched, and after the etching is completed, the first core section 61 is formed.

Depositing polysilicon 63 over the first core portion 61 in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, wherein the polysilicon 63 is formed in the through hole 31 and the surface of the stacked structure 20 away from the substrate 10, that is, the polysilicon 63 covers the inner side surface of the through hole 31 and the top end of the first core portion 61 and the surface of the stacked structure 20 away from the substrate 10, and the structure formed in this step is as shown in fig. 4c, and the manner of depositing the polysilicon 63 may be an atomic layer deposition process.

The polysilicon 63 on the stacked structure 20 and a portion of the polysilicon 63 in the via 31 are etched away, and the remaining polysilicon 63 in the via 31 forms the second core 62. The structure formed in this step is shown in fig. 4d, where the etching removal refers to performing etching back on a portion of the polysilicon 63, and the etching back manner may be dry etching or gas etching. In the present embodiment, a portion of polysilicon 63 in through hole 31 is retained, and specifically, one end of retained polysilicon 63 away from substrate 10 is lower than one end of through hole 31 away from the substrate in the vertical direction, so as to leave a space for forming conductive pillar 70 in through hole 31 later.

On the basis, titanium and/or titanium nitride is deposited on the top of the second core part 62, the inner side wall of the through hole 31 exposed outside the second core part 62 and the surface of the laminated structure 20 far away from the substrate 10 to form a second conductive layer 52; then, depositing tungsten on the second conductive layer 52 to cover the second conductive layer 52, wherein the structure formed in this step is as shown in fig. 4 e; the surface of the stack 20 remote from the substrate 10 is then planarized, and may be subjected to a chemical mechanical polishing process, which results in a structure as shown in fig. 4f, wherein the tungsten in the via 31 is retained, thereby forming the conductive pillar 70.

In the preparation method of the three-dimensional memory provided by the embodiment, when the three-dimensional memory is manufactured, the first core part 61 made of the doped polysilicon 65 is soft in texture, and the generated stress is small; by providing the first core 61 of doped polysilicon 65 in combination with the second core 62 of polysilicon, the tensile stress generated by the conventional polysilicon core is reduced, thereby further reducing the applied force to the laminated structure 20 and reducing or avoiding the possibility of the laminated structure 20 being stressed to tilt or collapse; in addition, since the first core portion 61 made of the doped polysilicon 65 is doped with impurity atoms at a concentration of 10%, the degree of wafer warpage is reduced.

The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the description of the present specification, reference to the description of the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples", etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional memory is characterized by comprising a substrate, a laminated structure arranged on the substrate, and a channel hole and a grid line gap penetrating through the laminated structure;

a channel structure is arranged in the channel hole, and one end of the channel structure extends to the substrate; a structure insulating layer and a common source pole positioned in the structure insulating layer are arranged in the grid line gap;

the common source pole sequentially comprises a first conducting layer, a stress adjusting layer and a core part from outside to inside, the first conducting layer and the stress adjusting layer penetrate through the laminated structure, and one end of the first conducting layer extends to the substrate and is electrically connected with one end of the channel structure extending to the substrate; the material of the core comprises polysilicon.

2. The three-dimensional memory according to claim 1, wherein the core is a polysilicon core.

3. The three-dimensional memory according to claim 1, wherein the core comprises a first core and a second core arranged in a stack, and the first core is proximate to the substrate relative to the second core.

4. The three-dimensional memory according to claim 3, wherein the first core is a silicon dioxide core and the second core is a polysilicon core.

5. The three-dimensional memory according to claim 3, wherein the first core is a doped polysilicon core and the second core is a polysilicon core.

6. The three-dimensional memory according to claim 5, wherein the doped polysilicon core is doped with impurity atoms at a concentration of at least 10%.

7. The three-dimensional memory according to claim 6, wherein the impurity atoms comprise one or more of phosphorus atoms, arsenic atoms, and nitrogen atoms.

8. The three-dimensional memory according to claim 1, wherein the stress adjustment layer is provided as a tungsten layer.

9. The three-dimensional memory according to any one of claims 1-8, wherein the common source post further comprises a barrier layer located between the stress-modulating layer and the core.

10. The three-dimensional memory according to claim 9, wherein the barrier layer comprises a titanium nitride layer.

11. The three-dimensional memory according to claim 9, wherein the common source pole further comprises a conductive pillar disposed on an end of the core away from the substrate.

12. The three-dimensional memory according to claim 11, wherein the conductive pillars are tungsten pillars.

13. The three-dimensional memory according to claim 12, wherein the common source pole further comprises a second conductive layer covering the circumferential sidewall of the conductive pillar and an end of the core away from the substrate.

14. The three-dimensional memory according to claim 13, wherein the second conductive layer comprises a titanium nitride layer.

15. The three-dimensional memory according to claim 1, wherein the first conductive layer comprises a titanium layer and a titanium nitride layer.

16. The three-dimensional memory according to claim 1 or 15, wherein the first conductive layer is a hollow structure, and one end of the hollow structure extending to the substrate is closed, and the other end is provided with an opening for forming the stress adjustment layer and the core in the hollow structure.

17. The three-dimensional memory according to claim 1, wherein the structural insulating layer is provided with a via extending to the substrate, the common source post being located within the via.

18. The three-dimensional memory according to claim 17, wherein a plurality of receiving grooves are arranged at intervals on the inner side surface of the gate line gap along the extending direction of the common source pole; a plurality of extending parts are arranged on the structural insulating layer at intervals, and each extending part is embedded in one corresponding accommodating groove.

19. The three-dimensional memory according to claim 18, wherein the stacked structure comprises a plurality of gate layers and a plurality of insulating layers alternately arranged, and the gate line slit penetrates through each of the gate layers and each of the insulating layers; and the accommodating groove is formed between the end part of any one of the grid electrode layers and two adjacent insulation layers of the grid electrode layer, in the end part of each grid electrode layer and the end part of each insulation layer in the grid line gap.

20. The three-dimensional memory according to claim 1, wherein a protective layer is disposed between the substrate and the stacked structure;

the protective layer is provided with a first opening and a second opening, the common source pole penetrates through the first opening and is electrically connected with the doped region of the substrate, and the channel structure penetrates through the second opening and is electrically connected with the epitaxial region of the substrate.

21. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

providing a substrate;

forming a stacked structure on the substrate;

forming a structural insulating layer in the gate line gap;

22. The method of claim 21, wherein the step of forming a common source post in the via hole comprises:

23. The method of claim 22, wherein the step of sequentially forming the first conductive layer, the stress adjustment layer, and the barrier layer in the via hole comprises:

24. The method of fabricating a three-dimensional memory as in claim 23, wherein the step of forming the core, second conductive layer and conductive pillar within the barrier layer comprises:

and depositing tungsten in the through hole to form the conductive column.

25. The method of fabricating a three-dimensional memory according to claim 24, wherein the step of forming a core in the via hole comprises:

26. The method of fabricating a three-dimensional memory according to claim 24, wherein the step of forming a core in the via hole comprises:

etching to remove the allowance layer;

27. The method of fabricating a three-dimensional memory according to claim 24, wherein the step of forming a core in the via hole comprises:

and etching to remove the polysilicon on the laminated structure and the polysilicon in the through hole, wherein the polysilicon left in the through hole forms a second core part.

28. The method of claim 24, wherein depositing tungsten on the second conductive layer to form a conductive pillar comprises:

29. The method of claim 21, wherein the step of forming the stacked structure on the substrate comprises:

removing each sacrificial layer to form a plurality of cavities;

30. The method of claim 21, wherein before forming the structural insulating layer in the gate line gap, the method further comprises: