TWI773086B - Method for forming three-dimensional memory device - Google Patents

Abstract

A 3D memory device and a method for forming the same are disclosed. In an example, a method for forming a 3D memory element is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stacked layer are sequentially formed on the substrate. A channel structure extending vertically through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the first polysilicon layer is formed. An opening is formed vertically extending through the dielectric stack layer and the second polysilicon layer and vertically extending into or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer, and a polysilicon spacer along a portion of the sidewall of the opening. The dielectric sacrificial layer is replaced by a third polysilicon layer between the first and second polysilicon layers through the opening.

Description

Method for forming a three-dimensional (3D) memory device

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Scale down planar memory cells to smaller sizes by improving process technology, circuit design, programming algorithms and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become increasingly challenging and expensive. Therefore, the memory density of planar memory cells is approaching the upper limit.

The three-dimensional storage architecture can address the density limit in planar storage cells. A three-dimensional storage architecture includes a storage array and peripheral components for controlling signals accessing the storage array.

Embodiments of 3D memory elements and methods for forming the same are disclosed herein.

In one example, a method for forming a 3D memory element is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stack layer are sequentially formed on the substrate. A channel structure is formed extending vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. forming a vertical extension through the dielectric stack layer and the second polysilicon layer and extending vertically into the dielectric An opening in the electrical sacrificial layer or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer, and a polysilicon spacer along a portion of the sidewall of the opening. The dielectric sacrificial layer is replaced with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening.

In another example, a method for forming a 3D memory element is disclosed. A stop layer, a dielectric layer, a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack layer are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. An opening is formed extending vertically through the dielectric stack layer and the second polysilicon layer and vertically into or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer. The dielectric sacrificial layer is replaced with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer. A source contact opening is formed extending vertically through the stop layer and the dielectric layer to expose a portion of the first polysilicon layer. A source contact structure in the source contact opening and an interconnect layer connected to the source contact structure are simultaneously formed.

In yet another example, a 3D memory device includes a polysilicon layer, a memory stack including alternating stacked conductive layers and stacked dielectric layers, a channel structure, and a slit structure. The channel structure extends vertically through the memory stack and into the polysilicon layer and includes the memory film and semiconductor channels. A portion of the semiconductor channel along the sidewalls of the channel structure is in contact with the sublayer of the polysilicon layer. The slit structure extends vertically through the memory stack layer and the sub-layers of the polysilicon layer.

In some of the embodiments of the present invention, a method for forming a three-dimensional (3D) memory device is provided, comprising sequentially forming a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer on a substrate polysilicon layer and a dielectric stack layer, forming vertically extending through the dielectric stack layer, the first Two polysilicon layers and the dielectric sacrificial layer and into a channel structure into the first polysilicon layer, forming (i) vertically extending through the dielectric stack and the second polysilicon layer , and an opening extending vertically into or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer, and forming (ii) an opening along the opening a polysilicon spacer on a portion of the sidewall, and through the opening, replacing the dielectric sacrificial with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer Floor.

In some of the embodiments of the invention, forming the opening and the polysilicon spacer includes forming the opening extending vertically through the dielectric stack and into the second polysilicon layer, along the forming the polysilicon spacers along the sidewalls of the openings and extending the openings further through the second polysilicon layer and into the dielectric sacrificial layer or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, the polysilicon spacer adjoins the dielectric stack layer but not the dielectric sacrificial layer.

In some of the embodiments of the present invention, after replacing the dielectric layer with the third polysilicon layer, replacing the dielectric stack layer with a memory stack layer through the opening.

In some of the embodiments of the present invention, further comprising: forming a slit structure in the opening after replacing the dielectric stack layer with the memory stack layer.

In some embodiments of the present invention, forming the dielectric sacrificial layer includes sequentially depositing a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.

In some of the embodiments of the present invention, forming the dielectric sacrificial layer includes depositing a single layer of silicon oxide.

In some of the embodiments of the present invention, forming the channel structure includes forming a vertical extension through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the first A channel hole in the polysilicon layer, and a memory film and a semiconductor channel are sequentially formed along the sidewalls of the channel hole.

In some of the embodiments of the present invention, replacing the dielectric sacrificial layer with the third polysilicon layer includes removing the dielectric sacrificial layer through the opening to form on the first polysilicon layer a cavity between the second polysilicon layer and the second polysilicon layer, removing a portion of the memory film through the opening to expose a portion of the semiconductor via along the sidewall of the via hole, and depositing a polysilicon material into the cavity through the opening to form the third polysilicon layer.

In some of the embodiments of the present invention, at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant, And the method further includes: diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer.

In some of the embodiments of the present invention, a method for forming a three-dimensional (3D) memory device is provided, comprising sequentially forming a stop layer, a dielectric layer, a first multi-layered layer at a first side of a substrate silicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stack layer formed vertically extending through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer layer, and into the a channel structure in the first polysilicon layer forming vertically extending through the dielectric stack layer and the second polysilicon layer and extending vertically into the dielectric sacrificial layer or through the dielectric electrical sacrificial layer to expose an opening of a portion of the dielectric sacrificial layer, through the opening, utilizing a third polysilicon layer between the first polysilicon layer and the second polysilicon layer A layer of silicon replaces the dielectric sacrificial layer, removes the substrate from a second side opposite the first side of the substrate, stops at the stop layer, forming a vertical extension through the stop layer and the dielectric layer to expose a source contact opening of a portion of the first polysilicon layer, and a source contact structure simultaneously formed in the source contact opening, and connected to the source An interconnect layer of the pole contact structure.

In some of the embodiments of the present invention, simultaneously forming the source contact structure and the interconnect layer includes forming in the source contact opening in contact with an exposed portion of the first polysilicon layer, forming A silicide layer, and removing the stop layer to expose the dielectric layer, and depositing a metal layer into the source contact openings and on the dielectric layer.

In some embodiments of the present invention, forming the stop layer and the dielectric layer sequentially includes: sequentially depositing a first silicon oxide layer, a first silicon nitride layer and a second oxide layer on the substrate silicon layer.

In some embodiments of the present invention, forming the sacrificial dielectric layer includes sequentially depositing a third silicon oxide layer, a second silicon nitride layer and a fourth silicon oxide layer.

In some of the embodiments of the present invention, forming the dielectric sacrificial layer includes depositing a single layer of silicon oxide.

In some of the embodiments of the invention, forming the opening includes forming the opening extending vertically through the dielectric stack and into the second polysilicon layer, along a portion of the opening Sidewalls form a polysilicon spacer, and the openings extend further through the second polysilicon layer and into or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, further comprising: replacing the dielectric stack layer with a memory stack layer through the opening after replacing the dielectric layer with the third polysilicon layer.

In some of the embodiments of the present invention, further comprising: forming an insulating structure in the opening after replacing the dielectric stack layer with the memory stack layer.

In some of the embodiments of the present invention, wherein forming the channel structure includes forming a vertical extension through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the dielectric layer A channel hole in the first polysilicon layer, and a memory film and a semiconductor channel are sequentially formed along a sidewall of the channel hole.

In some of the embodiments of the present invention, replacing the dielectric sacrificial layer with the third polysilicon layer includes removing the dielectric sacrificial layer through the opening to form on the first polysilicon layer a cavity between the second polysilicon layer and the second polysilicon layer, removing a portion of the memory film through the opening to expose a portion of the semiconductor via along the sidewall of the via hole, and depositing a polysilicon material into the cavity through the opening to form the third polysilicon layer.

100: 3D Memory Components

101: Component area

102: Dielectric layer

103: Surrounding area

104: polysilicon layer

105: Upper Sublayer

106: Memory stack layer

107: Polysilicon Layer

108: Stacked conductive layers

109: Sublayer

110: Stacked Dielectric Layers

111: Interlayer dielectric layer

112: Channel Structure

114: Memory film

116: Semiconductor channel

118: Overlay

119: Dielectric Sacrificial Layer

120: channel plug

122: Parallel slit structure

124: gate dielectric layer

126: Insulator Core

127: first silicon oxide layer

128: source contact structure

129: silicon nitride layer

130: Interconnect layer

131: The second silicon oxide layer

132: silicide layer

133: source contact

134: Contact pad

135: Spacer

136: Area

137: Monolayer silicon oxide layer

202: Substrate

203: Stop Layer

205: Dielectric Layer

207: First polysilicon layer

208: Dielectric stack layers

209: First sacrificial layer

210: Stacked Dielectric Layers

211: Second sacrificial layer

212: Stacked Layer Sacrificial Layer

213: The third sacrificial layer

214: Channel Structure

215: Second polysilicon layer

216: Memory Film

218: Semiconductor channel

220: Overlay

222: Channel Plug

224: Slit

226: cavity

228: Polysilicon Spacer

230: Third polysilicon layer

234: Memory stack layer

236: Stacked conductive layers

238: gate dielectric layer

240: Insulation Core

242: Insulation structure

244: source contact opening

246: silicide layer

248: Interconnect layer

250: Source Contact Structure

252: Silicon oxide layer

254: Etch Mask

300: Method

302: Operation steps

304: Operation steps

306: Operation steps

308: Operation steps

310: Operation steps

312: Operation steps

314: Operation steps

316: Operation steps

318: Operation steps

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure .

Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased for clarity of discussion.

1A shows a side view of a cross-section in an exemplary element region of a 3D memory element according to various embodiments of the present disclosure.

1B shows a side view of a cross-section in an exemplary peripheral region of a 3D memory element according to various embodiments of the present disclosure.

1C shows a plan view of a cross-section of an exemplary 3D memory element according to various embodiments of this disclosure.

1D illustrates a side view of a cross-section in another exemplary peripheral region of a 3D memory element in accordance with various embodiments of the present disclosure.

1E shows a side view of a cross-section in another exemplary element region of a 3D memory element according to various embodiments of the present disclosure.

2A-2P illustrate a manufacturing process for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure.

3 shows a flowchart of a method for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure.

The features and advantages of this disclosure will become more apparent from the detailed description set forth below when read in conjunction with the accompanying drawings. Obviously, like reference characters identify corresponding elements therein. In the drawings, like reference numerals generally identify identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

While specific configurations and arrangements are discussed, it should be understood that this has been done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present teachings may also be employed in various other applications.

Note that references in this specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiment may include the particular feature, structure, or characteristic, but each Implementations may not necessarily include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it will be within the knowledge of one skilled in the relevant art to implement such feature, structure or characteristic in conjunction with other embodiments, whether explicitly described or not.

Generally, terms can be understood, at least in part, from their usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a combination of features, structures or characteristics in the plural depending at least in part on context . Similarly, terms such as "a", "an", and "the" may again be understood to convey a singular usage or to convey a plural usage, depending at least in part on context. Furthermore, again The term "based on" may be understood, at least in part, by context, as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described.

It should be readily understood that the meanings of "on", "on" and "on" in this summary should be construed in the broadest possible manner, such that "on" not only Means "directly on something", but also includes the meaning of "on something" with intervening features or layers, and "on" or "over" means not only The meaning of "over something" or "over something", but can also include it "over something" or "over something" without intervening features or layers (i.e., directly on something).

In addition, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc., may be used herein for ease of description to describe an element or The relationship of a feature to other elements or features as shown in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to include different orientations of elements during use or processing steps. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a number of semiconductor materials (eg, silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material (eg glass, plastic or sapphire wafer).

As used herein, the term "layer" refers to a portion of material comprising a region of thickness point. A layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes thereon. The layers may extend horizontally, vertically and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, over it, and/or under it. Layers may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect via (VIA) contacts are formed) and one or more dielectric layers.

As used herein, the term "nominal/nominal" refers to a desired or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as higher and/or lower than expected values range of values. The range of values may be due to slight variations in manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor element. Based on the particular technology node, the term "about" may indicate a given amount of value that varies, eg, within 10-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

As used herein, the term "3D memory element" refers to vertically oriented strings (referred to herein as "memory strings" such as NAND memory strings) having memory cell transistors on a laterally oriented substrate of semiconductor elements, so that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical/perpendicular" means nominally perpendicular to the lateral surface of the substrate.

In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of the channel structure (eg, referred to as sidewall selective epitaxial growth (SEG)). with under the channel structure Compared to another type of semiconductor plug formed at the end (eg, bottom SEG), the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom surface of the via hole (also known as "SONO" punching), thereby increasing the process window, especially when using advanced technologies to manufacture 3D NAND memory devices (eg, 96 or more levels with a multi-die architecture). In addition, sidewall SEG structures can be combined with backside processing to form source contacts from the backside of the substrate to avoid leakage current and parasitic capacitances between frontside source contacts and wordlines and to increase active device area.

In forming the sidewall SEG structure, a sacrificial layer needs to be formed first to open the memory film and expose the semiconductor channel on the sidewall of the channel structure, which is later replaced by a layer (eg, a polysilicon layer) that includes the sidewall SEG structure. The sacrificial layer is usually made of polysilicon. However, the use of a polysilicon sacrificial layer requires complex spacer structures on the sidewalls of openings (eg, gate line slits (GLS)) to replace the polysilicon sacrificial layer, and the etching of the openings stops within the polysilicon sacrificial layer. These challenges limit yield and increase the cost of 3D NAND memory devices with sidewall SEG structures.

Various embodiments in accordance with the present disclosure provide improved 3D memory devices and methods of fabricating the same. By changing the material of the sacrificial layer used to form the sidewall SEG structure from polysilicon to a dielectric layer (eg, silicon nitride or silicon oxide), the material and structure of the spacer on the sidewall of the opening (eg, GLS) can be simplified , thereby reducing costs. Furthermore, the dielectric sacrificial layer allows a larger etch window for openings (eg, GLS) compared to the polysilicon sacrificial layer because the etch can now stop within the dielectric sacrificial layer or extend further through the dielectric sacrificial layer. Therefore, the process can be simplified, and the yield can be increased.

1A shows a side view of a cross-section in an exemplary element region of a 3D memory element 100 in accordance with various embodiments of the present disclosure. 1B shows a side view of a cross-section in an exemplary peripheral region of 3D memory element 100 in accordance with various embodiments of the present disclosure. Figure 1C shows according to A plan view of a cross-section of an exemplary 3D memory element of various embodiments of this disclosure. In some of these embodiments of the present invention, the 3D memory device 100 in FIGS. 1A and 1B includes a substrate (not shown), which may include silicon (eg, monocrystalline silicon), silicon germanium (SiGe), arsenide Gallium (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some of these embodiments of the invention, the substrate is a thinned substrate (eg, a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof.

Note that the x- , y- , and z -axes are included in FIGS. 1A-1C to illustrate the spatial relationship of the components in the 3D memory element 100 . The substrate includes two lateral surfaces extending laterally in the x - y plane: a front surface on the front side of the wafer and a rear surface on the back side opposite the front side of the wafer. The x- and y -directions are two orthogonal directions in the wafer plane: the x -direction is the word line direction, and the y -direction is the bit line direction. The z -axis is perpendicular to both the x- and y -axis. As used herein, a feature is defined in the z -direction (the vertical direction perpendicular to the x - y plane) relative to the substrate of the semiconductor element when the substrate is located in the lowermost plane of the semiconductor element in the z -direction (e.g. , layer or element) is "on", "over" or "under" another component (eg, layer or element) of a semiconductor element (eg, 3D memory element 100). The same concepts used to describe spatial relationships apply throughout this summary.

In some of these embodiments of the present invention, the 3D memory device 100 is part of a non-monolithic 3D memory device in which the components are formed separately on different substrates and then are mounted face-to-face, face-to-back, or back-to-back Bond. Peripheral components (not shown) (eg, any suitable digital, analog, and/or mixed-signal peripheral circuitry) used to facilitate the operational steps of 3D memory device 100 may be on a separate peripheral component substrate than the memory array substrate Forming, the components shown in FIGS. 1A and 1B are formed on a memory array substrate. It should be understood that the memory array substrate may be removed from the 3D memory device 100 as described in detail below, and the peripheral device substrate may become the substrate of the 3D memory device 100 . further It is understood that the memory array element (eg, as shown in FIGS. 1A and 1B ) may be in the original position or may be in the 3D memory element 100 depending on how the peripheral element substrate and the memory array element substrate are bonded Flip upside down. For ease of reference, FIGS. 1A and 1B depict a state of 3D memory element 100 in which the memory array element is in its original position (ie, flipped upside down). It should be understood, however, that in some examples, the memory array elements shown in FIGS. 1A and 1B may be flipped upside down in 3D memory element 100 and their relative positions may be changed accordingly. The same concepts used to describe spatial relationships apply throughout this summary.

As shown in 1C, in plan view, the 3D memory device 100 may include a device region 101 in which a memory stack layer (and its stepped structure) and a channel structure are formed. The element region 101 is divided in the y -direction (eg, the bit line direction) into a plurality of regions 136 (eg, blocks) by parallel slit structures 122, each parallel slit structure 122 is in the x -direction (eg, the word line direction) ) extends laterally. The 3D memory device 100 may also include one or more peripheral regions 103 outside the device region 101 in which the memory stack layer 106 (eg, in FIG. 1A ) is formed. According to some embodiments, the peripheral region 103 is at the edge of the 3D memory element 100 . In some of these embodiments of the invention, contact pads 134 for pad extraction are formed in the peripheral region 103 .

As shown in FIG. 1A , the 3D memory device 100 may include a dielectric layer 102 in the device region 101 . Dielectric layer 102 may include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which interconnect lines and vertical interconnect vias (VIAs) may be formed touch. The dielectric layer 102 is, for example, an interlayer dielectric layer (ILD layer), which may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k (low-k) dielectrics, or any combination thereof . In some of the embodiments of the present invention, the dielectric layer 102 includes silicon oxide. As shown in FIG. 1B , the dielectric layer 102 may extend laterally into the perimeter region 103 . In other words, the dielectric layer 102 may be formed on the element region 101 and the periphery of the 3D memory element 100 A continuous layer (eg, a continuous silicon oxide layer) in the edge region 103 .

As shown in FIG. 1A , the 3D memory device 100 may further include a polysilicon layer 104 over the dielectric layer 102 in the device region 101 . According to some embodiments, the polysilicon layer 104 includes an N-type doped polysilicon layer. That is, the polysilicon layer 104 may be doped with any suitable N-type dopant (eg, phosphorous (P), arsenic (Ar), or antimony (Sb)) that contributes free electrons and increases the intrinsic semiconductor (pure conductivity of semiconductors). As described in detail below, due to the diffusion process, the polysilicon layer 104 may have a uniform doping concentration profile in the vertical direction. In some of these embodiments of the present invention, the doping concentration of the polysilicon layer 104 is between about 10 ¹⁹ cm ^-3 and about 10 ²² cm ^-3 , such as between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 ( For example 10 ¹⁹ cm ^-3 , 2×10 ¹⁹ cm ^-3 , 3×10 ¹⁹ cm ^-3 , 4×10 ¹⁹ cm ^-3 , 5×10 ¹⁹ cm ^-3 , 6×10 ¹⁹ cm ^-3 , 7×10 ¹⁹ cm ^-3 , 8×10 ¹⁹ cm ^-3 , 9×10 ¹⁹ cm ^-3 , 10 ²⁰ cm ^-3 , 2×10 ²⁰ cm ^-3 , 3×10 ²⁰ cm ^-3 , 4×10 ²⁰ cm ^-3 , 5×10 ²⁰ cm ^-3 , 6×10 ²⁰ cm ^-3 , 7×10 ²⁰ cm ^-3 , 8×10 ²⁰ cm ^-3 , 9×10 ²⁰ cm ^-3 , 10 ²¹ cm ^-3 , 2×10 ²¹ cm ^-3 , 3×10 ²¹ cm ^-3 , 4×10 ²¹ cm ^-3 , 5×10 ²¹ cm ^-3 , 6×10 ²¹ cm ^-3 , 7×10 ²¹ cm ^-3 , 8×10 ²¹ cm -3 ^-3 , 9×10 ²¹ cm ^-3 , 10 ²² cm ^-3 , any range bounded by either of these values by the lower end or in any range bounded by any two of these values). Although FIG. 1A shows polysilicon layer 104 over dielectric layer 102, as discussed above, it should be understood that dielectric layer 102 may be over polysilicon layer 104 in some examples, as the memory array element shown in FIG. 1A may be are flipped upside down, and their relative positions can be changed accordingly in the 3D memory element 100 . In some of these embodiments of the invention, the memory array element shown in FIG. 1A is flipped upside down (in the top) and bonded to the peripheral elements (in the bottom) in the 3D memory element 100 such that the dielectric layer 102 is over polysilicon layer 104 .

As shown in FIG. 1A , the 3D memory device 100 may further include an interconnect layer 130 under the dielectric layer 102 . According to some embodiments, the interconnect layer 130 is at the opposite side of the polysilicon layer 104 relative to the dielectric layer 102 (ie, the backside), and is thus referred to as a "backside interconnect layer." The interconnect layer 130 may include a plurality of interconnects (in Also referred to herein as "contacts"), including lateral interconnect lines and VIA contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnect (eg, back end of line ((BEOL) interconnect). Interconnect lines and VIA contacts in interconnect layers can include conductive materials , including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. As shown in FIG. 1B , the interconnect layer 130 may extend laterally to the peripheral region 103 In other words, the interconnect layer 130 may be a continuous layer (eg, a continuous Al layer) in the element region 101 and the peripheral region 103 of the 3D memory device 100. In some of the embodiments of the present invention, the interconnect Layer 130 includes one or more contact pads 134 for pad extraction in peripheral region 103, as shown in Figures IB and 1C.

In some of these embodiments of the invention, the 3D memory device 100 further includes vertically extending through the dielectric layer 102 from the opposite side of the polysilicon layer 104 relative to the dielectric layer 102 (ie, the backside) to contact the polysilicon layer 104 source contact structure 128. It should be understood that the depth to which the source contact structures 128 extend into the polysilicon layer 104 may vary in different examples. The source contact structure can electrically connect the sources of the NAND memory strings of the 3D memory element 100 to surrounding elements from the backside of the memory array substrate (removed) through the polysilicon layer 104, and thus can also be referred to herein as Referred to as "backside source pick up". The source contact structure 128 may comprise any suitable type of contact. In some of these embodiments of the invention, the source contact structure 128 includes a VIA contact. In some of these embodiments of the invention, the source contact structures 128 include laterally extending wall contacts.

In some of the embodiments of the present invention, the source contact structure 128 includes a silicide layer 132 in contact with the polysilicon layer 107, which can reduce the contact resistance between the polysilicon and the metal. The silicide layer 132 may include any suitable metal silicide (eg, nickel silicide (NiSi)). As shown in FIG. 1A , the source contact structure 128 may also include a portion of the interconnect layer 130 (eg, an Al layer) under and in contact with the silicide layer 132 . In other words, according to some embodiments, the interconnect layer 130 is connected to the source Pole contact structure 128 . As described in more detail below with respect to the fabrication process, source contact structure 128 may include source contact openings in which silicide layer 132 and interconnect layer 130 are deposited. Therefore, the source contact structure 128 and the interconnect layer 130 may include the same metal material (eg, Al).

In some of the embodiments of the invention, the 3D memory element 100 is a NAND flash memory element, wherein the memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string may include channel structures 112 extending through a plurality of pairs, each pair including a stacked conductive layer 108 and a stacked dielectric layer 110 (referred to herein as a "conductive/dielectric layer pair"). The conductive/dielectric layer pair of the stack is also referred to herein as the memory stack 106 . The number of conductive/dielectric layer pairs (eg, 32, 64, 96, 128, 160, 192, 224, 256, etc.) in the memory stack layer 106 determines the number of memory cells in the 3D memory element 100 . Although not shown in FIG. 1A , it should be understood that in some of these embodiments of the present invention, the memory stack layer 106 may have a multi-stack architecture, eg, including a lower memory stack and an upper memory on the lower memory stack Double lamination architecture of body laminations. The number of pairs of stacked conductive layers 108 and stacked dielectric layers 110 in each memory stack may be the same or different.

The memory stack 106 may include a plurality of interleaved stacked conductive layers 108 and stacked dielectric layers 110 over the polysilicon layer 104 in the device region 101 . The stacked conductive layers 108 and the stacked dielectric layers 110 in the memory stack 106 may alternate in the vertical direction. In other words, in addition to the layers at the top or bottom of the memory stack 106, each stack conductive layer 108 may be adjoined by two stack dielectric layers 110 on both sides, and each stack dielectric layer 110 The conductive layers 108 may be adjoined by two stacked layers on both sides. The stacked layer conductive layer 108 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stacked layer conductive layer 108 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer 124 . The gate electrodes of the stacked conductive layer 108 may extend laterally as word lines, in one or more stepped structures (not shown) of the memory stack 106 . shown) to terminate. The stacked layer dielectric layer 110 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIG. 1A , each channel structure 112 extends vertically through the memory stack layer 106 and into the polysilicon layer 104 in the device region 102 . That is, the channel structure 112 may include two portions: a lower portion surrounded by the polysilicon layer 104 (ie, below the interface between the polysilicon layer 104 and the memory stack layer 106 ), and a lower portion surrounded by the memory stack layer 106 ( That is, above the interface between the polysilicon layer 104 and the memory stack layer 106 ) surrounded by the upper portion. As described herein, when the substrate is in the lowest plane of the 3D memory element 100, the "upper portion/end" of the feature (eg, channel structure 112) is the portion/end that is further away from the substrate in the y -direction, And the "lower portion/end" of the component (eg, channel structure 112) is the portion/end that is closer to the substrate in the y -direction.

Channel structure 112 may include via holes filled with semiconductor material (eg, as semiconductor channel 116 ) and dielectric material (eg, as memory film 114 ). In some of these embodiments of the invention, the semiconductor channel 116 includes silicon (eg, amorphous silicon, polysilicon, or monocrystalline silicon). In one example, the semiconductor channel 116 includes polysilicon. In some of these embodiments of the invention, the memory film 114 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the via hole may be partially or fully filled with an overlying layer 118 including a dielectric material (eg, silicon oxide and/or air gaps). The channel structure 112 may have a cylindrical shape (eg, a column shape). According to some embodiments, the overlying layer 118 , the semiconductor channel 116 , the tunneling layer of the memory film 114 , the storage layer, and the barrier layer are arranged in this order along the direction from the center of the pillar toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, the memory film 114 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). in one of the inventions In some embodiments, the channel structure 112 also includes a channel plug 120 at the top of the upper portion of the channel structure 112 . The channel plug 120 may include a semiconductor material (eg, polysilicon). In some of the embodiments of the present invention, the channel plug 120 functions as the drain of the NAND memory string.

As shown in FIG. 1A , a portion of semiconductor channel 116 along sidewalls of channel structure 112 (eg, in a lower portion of channel structure 112 ) is in contact with sublayer 109 of polysilicon layer 104 , according to some embodiments. That is, according to some embodiments, the memory film 114 is separated in the lower portion of the channel structure 112 adjoining the sublayer 109 of the polysilicon layer 104 , exposing the semiconductor channel 116 to contact the surrounding sublayer 109 of the polysilicon layer 104 . Thus, the sublayer 109 of the polysilicon layer 104 surrounding and in contact with the semiconductor channel 116 may serve as a "sidewall SEG" for the channel structure 112 to replace the "bottom SEG" as described above, which may alleviate (eg, overlay control, epitaxy) layer formation and SONO punching). As described in detail below, according to some embodiments, sublayer 109 of polysilicon layer 104 is formed separately from the remainder of polysilicon layer 104 . It should be understood, however, that sublayer 109 of polysilicon layer 104 may have the same polysilicon material as the remainder of polysilicon layer 104, and that the doping concentration may be nominally uniform in polysilicon layer 104 after diffusion, sublayer 109 may Indistinguishable from the rest of the polysilicon layer 104 in the 3D memory device 100 . Nonetheless, sublayer 109 refers to the portion of polysilicon layer 104 in the lower portion of channel structure 112 that is in contact with semiconductor channel 116 and not the portion that is in contact with memory film 114 . As shown in FIG. 1A, in addition to sublayer 109, the remainder of polysilicon layer 104 may also include upper sublayer 105 and lower sublayer 107 above and below sublayer 109, respectively, although sublayers 105, 107, and The boundaries between 109 may be indistinguishable because sublayers 105, 107 and 109 may have the same polysilicon material with nominally uniform doping concentrations.

As shown in FIG. 1A , the 3D memory device 100 may further include a slit structure 122 in the device region 101 . As also shown in FIG. 1C, each slit structure 122 may extend laterally in the x -direction (eg, the word line direction) to divide the memory stack layer 106 in the device region 101 into a plurality of regions 136 (eg, piece). For example, the memory stack layer 106 may be divided into a plurality of memory blocks by the slit structure 122 such that the array of channel structures 112 may be divided into individual memory blocks. In some of these embodiments of the present invention, the slit structure 122 is an insulating structure that does not include any contacts therein (ie, does not function as a source contact). As shown in FIG. 1A, each slit structure 122 includes an opening (eg, a slit) that is filled with one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each slit structure 122 may be filled with silicon oxide as an insulator core 126 and a high-k dielectric connected to the gate dielectric layer 124 .

The slit structures 122 each extend vertically through the interleaved stacked conductive layers 108 and the stacked dielectric layers 110 of the memory stack 106 and into the polysilicon layer 104 . The slit structure 122 may extend vertically into or through the sublayer 109 . As shown in FIG. 1A , in some of these embodiments of the invention, slit structures 122 may extend through upper sublayer 105 and sublayer 109 into lower sublayer 107 such that slit structures 122 abut the entire thickness of sublayer 109 . It should be appreciated that in some examples, slit structures 122 may extend through upper sublayer 105 and into sublayer 109 such that slit structures 122 abut a portion of the entire thickness of sublayer 109 . That is, due to the enlarged process window used to etch the slit opening of slit structure 122, the lower end of slit structure 122 may stop anywhere at sublayer 109 or lower sublayer 107 (but not at upper sublayer 105). ), as described in detail below with respect to the manufacturing process.

In some of the embodiments of the present invention, by doping the polysilicon layer 104 with N-type dopants, ie, eliminating the P-well as a source of holes, according to some embodiments, the 3D memory device 100 is configured such that when an erase is performed A gate-to-drain leakage (GIDL) auxiliary body bias is generated during the operation step. The GIDL around the source select gate of the NAND memory string can generate hole current into the NAND memory string to raise the body potential for the erase operation step. In addition, by eliminating the P-well as a source of holes, it is also possible to The control of the source select gate during the operation step is simplified because the inversion channel is no longer required when the read operation step is performed by the 3D memory device 100 .

It should be appreciated that in some examples, the slit structures 122 may include source contact structures (eg, also referred to as "front-side source pick up") disposed at the same side of the memory stack layer 106 . That is, instead of the insulating structure filled with a dielectric material as described in FIG. 1A , the slit structure 122 may be filled with a conductive material to become a source contact structure. For example, as shown in FIG. 1E, the slit structure 122 may be a source contact structure including spacers 135 and source contacts 133 that each extend vertically through the memory stack layer 106 and into the in the polysilicon layer 104 . Spacer 135 may include a dielectric material (eg, silicon oxide) laterally between source contact 133 and memory stack 106 to conduct source contact 133 to surrounding stacks in memory stack 106 Layer 108 is electrically separated. On the other hand, spacers 135 may be arranged along the sidewalls of the slit structures 122 but not at the bottom of the slit structures 122 so that the source contacts 133 may be in contact with the polysilicon layer 104 to establish the semiconductor channel 116 with the channel structure 112 electrical connection. In some of these embodiments of the invention, the source contact 133 includes an adhesive layer and a conductive layer surrounded by the adhesive layer. The adhesion layer may include one or more conductive materials (eg, titanium nitride (TiN)) over and in contact with the polysilicon layer 104 to establish electrical connection with the polysilicon layer 104 . In some of these embodiments of the invention, the conductive layer includes polysilicon in a lower portion thereof and metal (eg, W) in an upper portion thereof for contacting metal interconnects (not shown). In some of the embodiments of the present invention, an adhesion layer (eg, TiN) is in contact with both the polysilicon layer 104 and the metal (eg, W) of the conductive layer to be formed on the polysilicon layer 104 (eg, as a source of NAND memory strings) electrical connection between the pole) and the metal interconnection.

Referring to FIGS. 1A and 1B , a portion of polysilicon layer 104 that does not include sublayer 109 (ie, upper sublayer 105 and lower sublayer 107 ) may also extend laterally into perimeter region 103 . In other words, the upper sublayer 105 Each of the and lower sublayers 107 may be a continuous layer (eg, a continuous polysilicon layer) in the device region 101 and the peripheral region 103 in the 3D memory device 100 . As shown in FIG. 1B , the 3D memory device 100 may include a dielectric sacrificial layer 119 sandwiched between the upper sublayer 105 and the lower sublayer 107 , ie, the polysilicon layer 104 in the peripheral region 103 that does not include the sublayer 109 . part. In some of these embodiments of the invention, the dielectric sacrificial layer 119 is coplanar with the sublayer 109 . That is, according to some embodiments, sublayer 109 and dielectric sacrificial layer 119 are in different regions (eg, element region 101 and peripheral region 103 ) but in the same plane (eg, AA as shown in FIGS. 1A-1C ) 'plane) in the layer. As described in detail below with respect to the fabrication process, the sublayer 109 and the dielectric sacrificial layer 119 originate from the same dielectric sacrificial layer extending laterally in both the element region 101 and the peripheral region 103 , and the dielectric sacrificial layer in the element region 101 A portion of the layer will subsequently be replaced by sublayer 109, while a portion of the dielectric sacrificial layer in peripheral region 103 remains intact in the final product of 3D memory element 100 (as dielectric sacrificial layer 119).

In some embodiments as shown in FIG. 1B , the dielectric sacrificial layer 119 is a composite dielectric layer including a first silicon oxide layer 127 , a silicon nitride layer 129 and a second silicon oxide layer 131 . That is, the dielectric sacrificial layer 119 may include the silicon nitride layer 129 sandwiched between the first silicon oxide layer 127 and the second silicon oxide layer 131 , which can reduce the silicon nitride and the silicon nitride in the silicon nitride layer 129 Stress between polysilicon in sublayers 107 and 105 . It should be understood that in some examples, dielectric sacrificial layer 119 may include a single silicon nitride layer 129 without silicon oxide layer 127 and silicon oxide layer 131 . It should also be understood that, in some examples, the dielectric sacrificial layer 119 may include a single layer of silicon oxide layer 137, as shown in FIG. ID. Nonetheless, the dielectric sacrificial layer 119 in the peripheral region 103 of the 3D memory device 100 may include one or more dielectric materials (eg, silicon nitride or silicon oxide). It should also be understood that the memory stack layers 106 in the device region 101 may not extend laterally into the peripheral region 103 . Alternatively, as shown in FIG. 1B , the 3D memory device 100 may include an interlayer dielectric layer 111 over and in contact with the upper sublayer 105 in the peripheral region 103 , which may be in contact with the upper sublayer 105 in the element region 101 . The memory stack layers 106 are coplanar.

2A-2P illustrate a manufacturing process for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure. FIG. 3 shows a flowchart of a method 300 for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure. Examples of 3D memory elements depicted in Figures 2A-2P and 3 include 3D memory element 100 depicted in Figures 1A-1C. Figures 2A-2P and Figure 3 will be described together. It should be understood that the operational steps shown in method 300 are not exclusive, that is, there may be other operational steps that may also be performed before, after, or between any of the illustrated operational steps. Furthermore, some operational steps may be performed simultaneously or in a different order than that shown in FIG. 3 .

Referring to FIG. 3, method 300 begins at operation 302 in which a stop layer, a dielectric layer, a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric are sequentially formed at a first side of the substrate stacked layers. The substrate may be a silicon substrate or a carrier substrate made of any suitable material (eg, glass, sapphire, plastic, to name a few) to reduce the cost of the substrate. The first side may be the front side of the substrate on which the semiconductor elements may be formed. In some of the embodiments of the present invention, in order to form the stop layer and the dielectric layer, a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are sequentially deposited on the substrate. In some of the embodiments of the present invention, in order to form the dielectric sacrificial layer, a third silicon oxide layer, a second silicon nitride layer and a fourth silicon oxide layer are sequentially formed. In some of the embodiments of the invention, to form the dielectric sacrificial layer, a single layer of silicon oxide is deposited. The dielectric stack may include a plurality of interleaved stacked sacrificial layers and stacked dielectric layers.

As shown in FIG. 2A , a stop layer 203 , a dielectric layer 205 , a first polysilicon layer 207 , a first sacrificial layer 209 , a second sacrificial layer 211 , a third sacrificial layer 213 and a Two polysilicon layers 215 . Substrate 202 may be a silicon substrate or a carrier substrate made of any suitable material (eg, glass, sapphire, plastic, to name a few examples). In some of the embodiments of the present invention, The stop layer 203 and the dielectric layer 205 include silicon nitride and silicon oxide, respectively. As described in more detail below, stop layer 203 may act as a stop layer when substrate 202 is removed from the backside, and thus may include any other suitable material in addition to the material of substrate 202 . It should be appreciated that, in some examples, a pad oxide layer (eg, a silicon oxide layer) may be formed between the substrate 202 and the stop layer 203 to relieve stress therebetween.

The first sacrificial layer 209, the second sacrificial layer 211, and the third sacrificial layer 213 may be collectively referred to herein as dielectric sacrificial layers. In some of the embodiments of the present invention, the first sacrificial layer 209, the second sacrificial layer 211 and the third sacrificial layer 213 include silicon oxide, polysilicon and silicon oxynitride, respectively. It should be understood that, in some examples, one or both of the first sacrificial layer 209 and the third sacrificial layer 213 may include silicon oxynitride. It should also be understood that, in some examples, the first sacrificial layer 209, the second sacrificial layer 211, and the third sacrificial layer 213 may be replaced by a single layer of silicon oxide layer 252 with dielectric sacrificial layers described in detail below (eg, as shown in FIG. 2O shown). Nonetheless, unlike known processes that use polysilicon as the material for the second sacrificial layer 211, the dielectric sacrificial layers disclosed herein, particularly the second sacrificial layer 211, include a dielectric material (eg, silicon nitride or silicon oxide) .

Referring back to FIG. 2A, the stop layer 203, the dielectric layer 205, the first polysilicon layer 207, the first sacrificial layer 209, the second sacrificial layer 211, the third sacrificial layer 213, and the second polysilicon layer 215 (or in the Any other layers in between) can be deposited by using one or more thin film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating , any other suitable deposition process, or a combination thereof) is formed by sequentially depositing corresponding materials in multiple loops in this order. In some of these embodiments of the present invention, at least one of the first polysilicon layer 207 and the second polysilicon layer 215 is doped with an N-type dopant (eg, P, As, or Sb). In one example, at least one of the first polysilicon layer 207 and the second polysilicon layer 215 may be doped using an ion implantation process after deposition of the polysilicon material. In another example, in-situ doping of N-type dopants may be performed when polysilicon is deposited to form at least one of the first polysilicon layer 207 and the second polysilicon layer 215 . It should be understood that In some examples, neither the first polysilicon layer 207 nor the second polysilicon layer 215 are doped with N-type dopants at this stage.

As shown in FIG. 2A, a plurality of pairs of a first dielectric layer (also referred to as a "stacked sacrificial layer 212") and a second dielectric layer (also referred to as a "stacked layer") are formed on the second polysilicon layer 215 layer dielectric layer 210") of the dielectric stack layer 208. According to some embodiments, the dielectric stack layer 208 includes an interleaved stacked layer sacrificial layer 212 and a stacked layer dielectric layer 210 . A stacked layer dielectric layer 210 and a stacked layer sacrificial layer 212 may optionally be deposited on the second polysilicon layer 215 to form the dielectric stack layer 208 . In some of the embodiments of the present invention, each of the stacked layer dielectric layers 210 includes a layer of silicon oxide, and each of the stacked layer sacrificial layers 212 includes a layer of silicon nitride. The dielectric stack layer 208 may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some of these embodiments of the invention, a pad oxide layer (eg, a silicon oxide layer not shown) is formed between the second polysilicon layer 215 and the dielectric stack layer 208 .

The method 300 proceeds to operation 304, shown in FIG. 3, wherein a channel is formed extending vertically through the dielectric stack, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer structure. In some of the embodiments of the present invention, to form the channel structure, a channel hole is formed extending vertically through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the first polysilicon layer, A memory film and a semiconductor channel are sequentially formed along the sidewall of the channel hole. In some of the embodiments of the invention, a channel plug is formed over and in contact with the semiconductor channel.

As shown in FIG. 2A , the via holes extend vertically through the dielectric stack layer 208 , the second polysilicon layer 215 and the sacrificial layer 213 , the sacrificial layer 211 and the sacrificial layer 209 and into the first polysilicon layer 207 Open your mouth. In some of the embodiments of the invention, a plurality of openings are formed such that each opening becomes The location where the track structure 214 will grow in a later process. In some of the embodiments of the present invention, the fabrication process used to form the channel holes of the channel structure 214 includes wet etching and/or dry etching processes (eg, deep reactive ion etching (DRIE)). According to some embodiments, the etching of the via hole continues until extending into the first polysilicon layer 207 . In some of these embodiments of the present invention, etch conditions (eg, etch rate and time) can be controlled to ensure that each via hole reaches and stops in the first polysilicon layer 207 to minimize The gouging varies among the channel holes and channel structures 214 formed therein.

As shown in FIG. 2A, a memory film 216 (including a barrier layer, a storage layer, and a tunneling layer) and a semiconductor channel 218 are sequentially formed in this order along the sidewalls and bottom surfaces of the via holes. In some of these embodiments of the present invention, first, a memory film 216 is deposited along the sidewalls and bottom surfaces of the via holes, and then a semiconductor channel 218 is deposited over the memory film 216 . The barrier layer, storage layer, and tunneling layer can then be used in this order using one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process or any combination thereof) to form the memory film 216 . The semiconductor material ( For example, polysilicon) is deposited over the tunneling layer of memory film 216 to form semiconductor channel 218 . In some of the embodiments of the present invention, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are subsequently deposited to form the memory film 216 and the semiconductor channel 218.

As shown in FIG. 2A, an overcladding layer 220 is formed in the via hole and over the semiconductor via 218 to fully or partially fill the via hole (eg, without or with air gaps). The dielectric may be deposited by using one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) An electrical material (eg, silicon oxide) is used to form the overlying layer 220 . Then, a channel plug 222 may be formed in the upper portion of the channel hole. In some of these embodiments of the invention, portions of the memory film 216, the semiconductor channel 218, and the overlying layer 220 on the top surface of the dielectric stack 208 are removed and treated by chemical mechanical polishing (CMP), wet The etching and/or dry etching process is planarized. Recesses may then be formed in the upper portion of the via hole by wet etching and/or dry etching a portion of the semiconductor channel 218 and overlying layer 220 in the upper portion of the via hole. The semiconductor material (eg, polysilicon) may then be deposited onto the A channel plug 222 is formed in the groove. According to some embodiments, channel structure 214 is thus formed through dielectric stack layer 208 , second polysilicon layer 215 and sacrificial layer 213 , sacrificial layer 211 and sacrificial layer 209 and into first polysilicon layer 207 .

The method 300 proceeds to operation 306, shown in FIG. 3, wherein (i) is formed extending vertically through the dielectric stack layer and the second polysilicon layer and into the dielectric sacrificial layer or through the dielectric sacrificial layer layer to expose a portion of the dielectric sacrificial layer, and to form (ii) polysilicon spacers along a portion of the sidewalls of the opening. In some of the embodiments of the invention, to form the openings and polysilicon spacers, an opening is formed extending vertically through the dielectric stack and into the second polysilicon layer, and polysilicon spacers are formed along the sidewalls of the openings , and extending the opening further through the second polysilicon layer and into or through the dielectric sacrificial layer. In some of the embodiments of the present invention, the polysilicon spacers adjoin the dielectric stack layer and not adjoin the dielectric sacrificial layer.

As shown in FIG. 2B , the slit 224 is an opening formed vertically extending through the dielectric stack layer 208 and into the second polysilicon layer 215 . According to some embodiments, the slit 224 does not extend further through the second polysilicon layer 215 into the second sacrificial layer 211 at this stage. In some of these embodiments of the invention, the fabrication process used to form the slits 224 includes a wet etch and/or dry etch process (eg, DRIE). In some of the embodiments of the present invention, first, the stack dielectric layer 210 and the stack layer sacrificial layer 212 of the dielectric stack layer 208 are etched. Etching the dielectric stack layer 208 does not stop at the top surface of the second polysilicon layer 215 and extends further into the second polysilicon layer 215 . In some of these embodiments of the invention, a second etch process may be performed to etch a portion of the second polysilicon layer 215 before reaching the third sacrificial layer 213 (eg, by controlling the etch rate and/or etch time).

As shown in FIG. 2C , polysilicon spacers 228 are formed along sidewalls and bottom surfaces of the slits 224 . In some of these embodiments of the invention, one or more thin film deposition processes (eg, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) are used to deposit a layer of Polysilicon material is deposited into the slits 224 and on the dielectric stack 208 to form polysilicon spacers 228 . Unlike known processes that use complex spacer structures (eg, composite dielectric layers with multiple sub-layers of different dielectric materials), polysilicon spacers 228 include a single polysilicon layer that can be combined with silicon nitride (eg, a second layer of polysilicon) Two sacrificial layers 211) or dielectric sacrificial layers of silicon oxide are used.

As shown in FIG. 2D , the slit 224 further extends into the second sacrificial layer 211 to expose a portion of the second sacrificial layer 211 . Thus, polysilicon spacers 228 adjoin dielectric stack layer 208 without adjoining sacrificial layer 213 , sacrificial layer 211 , or sacrificial layer 209 , according to some embodiments. That is, the polysilicon spacers 228 can protect the dielectric stack layer 208 during subsequent processes before being removed, while not blocking access to the second sacrificial layer 211 through the slits 224 . In some of these embodiments of the invention, a portion of the polysilicon spacer 228 at the bottom surface of the slit 224 is first etched (eg, using RIE) to expose a portion of the second polysilicon layer 215 through the slit 224 . The slit 224 can then be extended further by etching the slit 224 again in the vertical direction. It should be understood that the process window for the second etch process applied to the slit 224 can be relatively large, as the etch can stop within the second sacrificial layer 211 (eg, shown in FIG. 2D ), or through the sacrificial layer 213 , The sacrificial layer 211 and the sacrificial layer 209 enter the first polysilicon layer 207 (not shown), as long as a part of the second sacrificial layer 211 can be exposed through the slit 224 after the second etching process. In other words, the second etch process applied to slit 224 can create vias through slit 224 to sacrificial layer 213 , sacrificial layer 211 or sacrificial layer 209 , and polysilicon overlying dielectric stack 208 but not sacrificial layer 211 Spacer 228.

As shown in FIGS. 2O and 2P, in some embodiments where the dielectric sacrificial layer includes a single layer of silicon oxide layer 252, a similar etch process for forming slits 224 and for forming polysilicon spacers 228 may also be applied. A deposition process to form a vertical extension through the dielectric stack layer 208 and the second polysilicon layer 215 and into the silicon oxide layer 252 (eg, shown in FIG. 20 ) or through the silicon oxide layer 252 into the first Slits 224 in a polysilicon layer 207 (eg, shown in FIG. 2P ), and polysilicon spacers are formed along a portion of the sidewalls of the slits 224 that adjoin the dielectric stack 208 but not the silicon oxide layer 252 228. It should be understood that portions of the polysilicon spacers 228 at the bottom surfaces of the slits 224 may also be removed in the dielectric stack layer 208 (eg, in FIG. 2D ) when the second etch process is performed to extend the slits 224 part of the polysilicon spacer 228 on the shown). In some embodiments where the dielectric sacrificial layer includes a single layer of silicon oxide layer 252, in order to protect the dielectric stack layer 208 that also includes silicon oxide at the top of the dielectric stack layer 208, when inside or through the oxide layer 252 As the peroxide layer 252 etches the slits 224 , a protective layer is formed on the dielectric stack layer 208 . In one example as shown in FIG. 20, after removing a portion of the polysilicon spacer 228 at the bottom surface of the slit 224, for example by controlling the angle, direction and/or extent of the etch process or by during the etch process Covering a portion of the polysilicon spacer 228 on the dielectric stack layer 208, a portion of the polysilicon spacer 228 on the dielectric stack layer 208 may remain. In another example as shown in FIG. 2P , after removing a portion of the polysilicon spacers 228 on the dielectric stack layer 208 , an etch mask 254 (eg, a soft mask) may be formed on the dielectric stack layer 208 and/or hard mask).

The method 300 proceeds to operation 308, as shown in FIG. 3, wherein the use of A third polysilicon layer between the first and second polysilicon layers replaces the dielectric sacrificial layer. In some of the embodiments of the invention, in order to replace the dielectric sacrificial layer with a third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first and second polysilicon layers, through the opening A portion of the memory film is removed to expose a portion of the semiconductor channel along the sidewalls of the channel hole, and polysilicon is deposited into the cavity through the opening to form a third polysilicon layer. In some of the embodiments of the invention, at least one of the first, second and third polysilicon layers is doped with an N-type dopant. N-type dopants may be diffused in the first, second and third polysilicon layers.

As shown in FIG. 2E , the sacrificial layer 211 (eg, shown in FIG. 2D ) is removed by wet and/or dry etching to form the cavity 226 . In some of the embodiments of the present invention, the second sacrificial layer 211 includes silicon nitride, the polysilicon spacers 228 include polysilicon, the first sacrificial layer 209 and the third sacrificial layer 203 each include silicon oxide, and the through slits 224 An etchant with phosphoric acid is applied to etch the second sacrificial layer 211 , which can be stopped by polysilicon spacers 228 . That is, the removal of the second sacrificial layer 211 does not affect the dielectric stack layer 208 protected by the polysilicon spacers 228, according to some embodiments. Similarly, silicon oxide layer 252 (as a dielectric sacrificial layer) in FIGS. 2O and 2P can be removed by applying an etchant with hydrofluoric acid through slit 224 , which can be stopped by polysilicon spacer 228 .

As shown in FIG. 2F , a portion of the memory film 216 exposed in the cavity 226 is removed to expose a portion of the semiconductor channel 218 along the sidewalls of the channel structure 214 . In some of these embodiments of the invention, the barrier layer is etched by applying an etchant (eg, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) through slit 224 and cavity 226 (eg, including silicon oxide), a storage layer (eg, including silicon nitride), and a portion of the tunneling layer (eg, including silicon oxide). Etching can be stopped by polysilicon spacers 228 and semiconductor channels 218 . That is, according to some embodiments, the removal of a portion of the memory film 216 exposed in the cavity 226 does not affect the dielectric stack layer 208 (interpolated by the polysilicon spacer 228 protection) and a semiconductor via 218 comprising polysilicon and an overlying layer 220 exposed by the semiconductor via 218. In some of the embodiments of the present invention, the first sacrificial layer 209 and the third sacrificial layer 213 (including silicon oxide) are also removed by the same etching process.

As shown in FIG. 2G , a third polysilicon layer 230 is formed between the first polysilicon layer 207 and the second polysilicon layer 215 . In some of these embodiments of the present invention, by using one or more thin film deposition processes (eg, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) through Slit 224 deposits polysilicon into cavity 226 (shown in FIG. 2F ) to form third polysilicon layer 230 . In some of these embodiments of the present invention, in-situ doping of N-type dopants (eg, P, As, or Sb) is performed when the polysilicon is deposited to form the third polysilicon layer 230 . The third polysilicon layer 230 may fill the cavity 226 to contact the exposed portion of the semiconductor channel 218 of the channel structure 214 . It should be understood that the third polysilicon layer 230 may be doped or undoped, depending on whether at least one of the first polysilicon layer 207 and the second polysilicon layer 215 is doped with N-type doping material, because at least one of the first polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer 230 may need to be doped with an N-type dopant. In some of the embodiments of the present invention, a thermal diffusion process (eg, annealing) is used to diffuse in the first polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer 230 in the first polysilicon layer. N-type dopants in at least one of the polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer 230, so that the first polysilicon layer 207, the second polysilicon layer 215 and the A uniform doping concentration profile in the vertical direction is realized in the third polysilicon layer 230 . For example, the doping concentration after diffusion may be between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 . As described above, the interfaces between the first polysilicon layer 207, the second polysilicon layer 215 and the third polysilicon layer 230 may become indistinguishable because the first polysilicon layer 207, the second polysilicon layer 230 Each of the crystalline silicon layer 215 and the third polycrystalline silicon layer 230 includes the same polycrystalline silicon material with nominally the same doping concentration. Therefore, the first polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer 230 may be collectively regarded as polysilicon layers after diffusion.

Although not shown, it should be understood that in some examples, for example, by forming slits 224 only in the memory region of the 3D memory element and not the perimeter region, and controlling the etching of the dielectric sacrificial layer to not extend to the perimeter area, the dielectric sacrificial layers (eg, sacrificial layers 209, 211 and 213 or oxide layers 209, 211 and 213 or oxide layers) may be replaced with the third polysilicon layer 230 only in the memory area of the 3D memory element and not in the peripheral area of the 3D memory element silicon layer 252). Thus, a portion of the dielectric sacrificial layers (eg, sacrificial layers 209, 211 and 213 or silicon oxide layer 252) in the peripheral region may remain in the final product of the 3D memory device after fabrication.

As shown in FIG. 2H, the sidewalls of the third polysilicon layer 230 (eg, shown in FIG. 2G) along the slit 224 and at the dielectric stack layer are removed using, for example, dry etching and/or wet etching. A portion on 208 and polysilicon spacer 228 (eg, shown in FIG. 2G ) to expose dielectric stack 208 through slit 224 . The etch process can be controlled (eg, by controlling the etch rate and/or time) so that the third polysilicon layer 230 remains between the first polysilicon layer 207 and the second polysilicon layer 215 and with the channel structure 214 The semiconductor channel 218 contacts.

The method 300 proceeds to operation 310, shown in FIG. 3, in which the dielectric stack is replaced with a memory stack through the opening using a so-called "gate replacement process". As shown in FIG. 2I, the memory stack layer 234 may be formed through a gate replacement process (ie, replacing the stacked layer sacrificial layer 212 with the stacked layer conductive layer 236). The memory stack layer 234 may thus include the interleaved stacked layer conductive layer 236 and the stacked layer dielectric layer 210 on the second polysilicon layer 215 . In some of the embodiments of the present invention, to form the memory stack layer 234, the stack layer sacrificial layer 212 is removed by applying an etchant through the slits 224 to form a plurality of lateral grooves. Then, by using one or more thin film deposition processes (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof) One or more conductive materials are deposited to deposit the stacked layer conductive layer 236 into the lateral grooves. According to some embodiments, the channel structure 214 thus extends vertically through the memory stack layer 234 and into the polysilicon layer including the first polysilicon layer 215 , the third polysilicon layer 230 and the second polysilicon layer 207 .

Method 300 proceeds to operation 312, shown in FIG. 3, wherein insulating structures are formed in the openings. In some of the embodiments of the invention, to form the insulating structure, one or more dielectric materials are deposited into the openings to fill the openings.

As shown in FIG. 2J, insulating structures 242 are formed in the slits 224 (eg, shown in FIG. 2I). One or more dielectric materials (eg, high A k-dielectric (also as gate dielectric layer 238) and silicon oxide as insulating core 240 are deposited into slits 224 to fully or partially fill slits 224 with or without air gaps to form insulation Structure 242.

The method 300 proceeds to operation 314, shown in FIG. 3, where the substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer. The second side may be the backside of the substrate.

As shown in Figure 2K, the substrate 202 is removed from the backside (eg, shown in Figure 2J). Although not shown in Figure 2K, it should be understood that the intermediate structure in Figure 2J could be flipped upside down to have the substrate 202 on top of the intermediate structure. In some of these embodiments of the invention, chemical mechanical polishing (CMP), grinding, wet etching, and/or dry etching are used to completely remove substrate 202 until stopped by stop layer 203 (eg, a silicon nitride layer). In some of these embodiments of the present invention, the substrate 202 (silicon substrate) is removed using silicon chemical mechanical polishing (Si-CMP), which reaches a stop having materials other than silicon. The stop layer 203 is automatically stopped, ie, acts as a backside chemical mechanical polishing (CMP) stop layer. In some of these embodiments of the invention, wet etch through tetramethylammonium hydroxide (TMAH) is used to remove substrate 202 (silicon substrate), which automatically stops when a stop layer 203 having a material other than silicon is reached, i.e. , which acts as a backside etch stop. The stop layer 203 can ensure complete removal of the substrate 202 without concerns about thickness uniformity after thinning.

Method 300 continues with operation 316, shown in FIG. 3, in which source contact openings extending vertically through the stop layer and the dielectric layer are formed to expose a portion of the first polysilicon layer. As shown in FIG. 2L , the source contact opening 244 extends vertically through the stop layer 203 and the dielectric layer 205 to expose a portion of the first polysilicon layer 207 . The source contact openings 244 may be formed using dry etching and/or wet etching (eg, RIE) to etch the stop layer 203 and the dielectric layer 205 . It should be understood that the etch may continue into the first polysilicon layer 207 to remove a portion of the first polysilicon layer 207 in some examples.

The method 300 proceeds to operation 318, shown in FIG. 3, wherein a source contact structure in the source contact opening and an interconnect layer connected to the source contact structure are simultaneously formed. In some of the embodiments of the present invention, in order to form the source contact structure and the interconnect layer at the same time, a silicide layer is formed in the source contact opening in contact with the exposed portion of the first polysilicon layer, and the stop layer is removed to The dielectric layer is exposed, and a metal layer is deposited into the source contact openings and on the dielectric layer.

As shown in FIG. 2M , a silicide layer 246 is formed at the bottom surface of the source contact opening 244 in contact with the first polysilicon layer 207 . The silicide layer 246 (eg, NiSi) may be formed by depositing a metal layer (eg, Ni) into the source contact opening 244 to contact the first polysilicon layer 207, followed by an annealing process. As shown in FIG. 2M , the stop layer 203 is removed using wet and/or dry etching to expose the dielectric layer 205 . The formation of silicide layer 246 may be performed before or after removal of stop layer 203 . It should be understood that in a In some examples, the formation of silicide layer 246 may be skipped.

As shown in FIG. 2N, a metal layer (eg, Al layer) is deposited into the source contact openings 244 on the silicide layer 246 and on the dielectric layer 205 to simultaneously form the interconnect layer 248 and include the silicide layer 246 and the metal layer (ie, the interconnect layer 248) in the same process. The source contact structure 250 of the connecting layer 248). Thus, according to some embodiments, interconnect layer 248 is connected to source contact structure 250 . Although not shown, it should be understood that, in some examples, the interconnect layer 248 may be patterned to form contact pads in peripheral regions of the 3D memory element.

Although not shown, it should be understood that in some examples, prior to removal of the substrate, by using one or more thin film deposition processes (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition ( ALD) or any combination thereof) depositing one or more conductive materials in the openings to form front-side source contact structures in the openings (eg, slits 224). Front-side source contact structures may replace back-side source contact structures (eg, source contact structures 250 ) and front-side insulating structures (eg, insulating structures 242 ).

In summary, some of the features and advantages of the present invention are as follows:

In forming the sidewall SEG structure, a sacrificial layer needs to be formed first to open the memory film and expose the semiconductor channel on the sidewall of the channel structure, which is later replaced by a layer (eg, a polysilicon layer) that includes the sidewall SEG structure. The sacrificial layer is usually made of polysilicon. However, the use of a polysilicon sacrificial layer requires complex spacer structures on the sidewalls of openings (eg, gate line slits (GLS)) to replace the polysilicon sacrificial layer, and the etching of the openings stops within the polysilicon sacrificial layer. These challenges limit production and increase the cost of 3D NAND memory devices with sidewall SEG structures.

Various embodiments in accordance with the present disclosure provide improved 3D memory devices and methods of fabricating the same. By changing the material of the sacrificial layer used to form the sidewall SEG structure from polysilicon to a dielectric layer (eg, silicon nitride or silicon oxide), the material and structure of the spacer on the sidewall of the opening (eg, GLS) can be simplified , thereby reducing costs. Furthermore, the dielectric sacrificial layer allows a larger etch window for openings (eg, GLS) compared to the polysilicon sacrificial layer because the etch can now stop within the dielectric sacrificial layer or extend further through the dielectric sacrificial layer. Therefore, the process can be simplified, and the yield can be increased.

In order to facilitate the comparison of readers, the elements listed in the description of the present invention and their labels are compared as follows. It is worth noting that some labels may correspond to more than one element name at the same time, which will be represented by brackets ( ). It means that the element may have different names due to idioms or its corresponding positions, but actually still belong to the same element number.

100.................................3D Memory Components

101.................................Component area

102.................................Dielectric layer

103................................. Surrounding area

104.................................Polysilicon layer

105 .................................Upper sublayer (sublayer)

106.................................Memory Stack Layer

107.................................Polysilicon layer (lower sublayer, sublayer)

108.................................Stacked Conductive Layers

109.................................Sublayers

110.................................Stacked Dielectric Layers

111.................................Interlayer Dielectric Layer

112......................................Channel structure

114.................................Memory Film

116.................................Semiconductor Channels

118 ................................. Overcladding

119.................................Dielectric Sacrificial Layer

120.................................Channel Plug

122.................................Parallel slit structure (slit structure)

124.................................Gate Dielectric Layer

126.................................Insulator Core

127.................................First silicon oxide layer (silicon oxide layer)

128.................................Source Contact Structure

129.................................Silicon Nitride Layer

130.................................Interconnect Layer

131.................................Second Silicon Oxide Layer (Silicon Oxide Layer)

132.................................Silicide layer

133.................................Source Contact

134.................................Contact pads

135.................................Spacer

136.................................area (block)

137.................................Single-layer silicon oxide layer (silicon oxide layer)

202 .................................................Basic

203.................................Stop Layer

205.................................Dielectric layer

207.................................First polysilicon layer

208.................................Dielectric stack layers

209.................................First sacrificial layer (sacrificial layer)

210.................................Stacked Dielectric Layer (Second Dielectric Layer)

211.................................Second sacrificial layer (sacrificial layer)

212.................................Stacked sacrificial layer (first dielectric layer)

213.................................The third sacrificial layer (sacrificial layer)

214.................................Channel structure

215.................................Second polysilicon layer

The above 209, 211, 215 are collectively referred to as the dielectric sacrificial layer

216.................................Memory Film

218................................Semiconductor Channel

220 ................................. Overcladding

222.................................Channel Plug

224................................................Slit

226.................................Cavity

228.................................polysilicon spacer

230.................................Third polysilicon layer

234.................................Memory Stack Layer

236.................................Stacked Conductive Layers

238.................................Gate Dielectric Layer

240.................................Insulating Core

242.................................Insulation Construction

244.................................Source Contact Opening

246.................................Silicide layer

248.................................Interconnect Layer

250.................................Source Contact Structure

252.................................Silicon oxide layer

254.................................Etch Mask

300.................................Method

302.................................Operation steps

304.................................Operation steps

306.................................Operation steps

308.................................Operation steps

310.................................Operation steps

312.................................Operation steps

314.................................Operation steps

316.................................Operation steps

318.................................Operation steps

In some of the embodiments of the present invention, a method for forming a three-dimensional (3D) memory device is provided, comprising sequentially forming a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer on a substrate polysilicon layer and a dielectric stack formed vertically extending through the dielectric stack, the second polysilicon layer and the dielectric sacrificial layer and into the first polysilicon layer a channel structure forming (i) vertically extending through the dielectric stack layer and the second polysilicon layer, and extending vertically into the dielectric sacrificial layer or extending vertically through the dielectric an opening of the sacrificial layer to expose a portion of the dielectric sacrificial layer, and to form (ii) a polysilicon spacer along a portion of a sidewall of the opening body, and through the opening, replacing the dielectric sacrificial layer with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer.

In some of the embodiments of the invention, forming the opening and the polysilicon spacer includes forming the opening extending vertically through the dielectric stack and into the second polysilicon layer, along the forming the polysilicon spacers along the sidewalls of the openings and extending the openings further through the second polysilicon layer and into the dielectric sacrificial layer or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, the polysilicon spacer adjoins the dielectric stack layer but not the dielectric sacrificial layer.

In some of the embodiments of the present invention, after replacing the dielectric layer with the third polysilicon layer, replacing the dielectric stack layer with a memory stack layer through the opening.

In some of the embodiments of the present invention, further comprising: forming a slit structure in the opening after replacing the dielectric stack layer with the memory stack layer.

In some embodiments of the present invention, forming the dielectric sacrificial layer includes sequentially depositing a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.

In some of the embodiments of the present invention, forming the dielectric sacrificial layer includes depositing a single layer of silicon oxide.

In some of the embodiments of the present invention, forming the channel structure includes forming a vertical extension through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first A channel hole in the polysilicon layer, and a memory film and a semiconductor channel are sequentially formed along the sidewalls of the channel hole.

In some of the embodiments of the present invention, replacing the dielectric sacrificial layer with the third polysilicon layer includes removing the dielectric sacrificial layer through the opening to form on the first polysilicon layer a cavity between the second polysilicon layer and the second polysilicon layer, removing a portion of the memory film through the opening to expose a portion of the semiconductor via along the sidewall of the via hole, and depositing a polysilicon material into the cavity through the opening to form the third polysilicon layer.

In some of the embodiments of the present invention, at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant, And the method further includes: diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer.

In some of the embodiments of the present invention, a method for forming a three-dimensional (3D) memory device is provided, comprising sequentially forming a stop layer, a dielectric layer, a first multi-layered layer at a first side of a substrate silicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stack layer formed vertically extending through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer layer and into the first polysilicon layer forming a channel structure extending vertically through the dielectric stack and the second polysilicon layer and into the dielectric sacrificial layer an opening in or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer, through the opening, utilizing between the first polysilicon layer and the second polysilicon layer A third polysilicon layer in between replaces the dielectric sacrificial layer from the base A second side of the bottom opposite the first side removes the substrate, stops at the stop layer, and forms a vertical extension through the stop layer and the dielectric layer to expose the first multiple A source contact opening of a portion of the crystalline silicon layer, and a source contact structure formed in the source contact opening at the same time, and an interconnect layer connected to the source contact structure.

In some of the embodiments of the present invention, simultaneously forming the source contact structure and the interconnect layer includes forming in the source contact opening in contact with an exposed portion of the first polysilicon layer, forming A silicide layer, and removing the stop layer to expose the dielectric layer, and depositing a metal layer into the source contact openings and on the dielectric layer.

In some embodiments of the present invention, forming the stop layer and the dielectric layer sequentially includes: sequentially depositing a first silicon oxide layer, a first silicon nitride layer and a second oxide layer on the substrate silicon layer.

In some embodiments of the present invention, forming the sacrificial dielectric layer includes sequentially depositing a third silicon oxide layer, a second silicon nitride layer and a fourth silicon oxide layer.

In some of the embodiments of the present invention, forming the dielectric sacrificial layer includes depositing a single layer of silicon oxide.

In some of the embodiments of the invention, forming the opening includes forming the opening extending vertically through the dielectric stack and into the second polysilicon layer, along a portion of the opening Sidewalls form a polysilicon spacer, and the openings extend further through the second polysilicon layer and into or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, further comprising: replacing the dielectric stack layer with a memory stack layer through the opening after replacing the dielectric layer with the third polysilicon layer.

In some of the embodiments of the present invention, further comprising: forming an insulating structure in the opening after replacing the dielectric stack layer with the memory stack layer.

In some of the embodiments of the present invention, wherein forming the channel structure includes forming a vertical extension through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the dielectric layer A channel hole in the first polysilicon layer, and a memory film and a semiconductor channel are sequentially formed along a sidewall of the channel hole.

In some of the embodiments of the present invention, replacing the dielectric sacrificial layer with the third polysilicon layer includes removing the dielectric sacrificial layer through the opening to form on the first polysilicon layer a cavity between the second polysilicon layer and the second polysilicon layer, removing a portion of the memory film through the opening to expose a portion of the semiconductor via along the sidewall of the via hole, and depositing a polysilicon material into the cavity through the opening to form the third polysilicon layer.

According to one aspect of this disclosure, a method for forming a 3D memory element is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stack layer are sequentially formed on the substrate. A channel structure is formed extending vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. forming an opening extending vertically through the dielectric stack layer and the second polysilicon layer and into or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer, and along sidewalls of the opening part of the polysilicon spacer. Use through openings in the first and second A third polysilicon layer between the two polysilicon layers replaces the dielectric sacrificial layer.

In some of the embodiments of the invention, to form the openings and polysilicon spacers, an opening is formed extending vertically through the dielectric stack and into the second polysilicon layer, polysilicon spacers are formed along sidewalls of the opening, and extending the opening further through the second polysilicon layer and into or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, the polysilicon spacers adjoin the dielectric stack layer and not adjoin the dielectric sacrificial layer.

In some of the embodiments of the present invention, after replacing the dielectric layer with a third polysilicon layer, the dielectric stack layer is replaced with a memory stack layer through the opening.

In some of the embodiments of the present invention, a slit structure is formed in the opening after replacing the dielectric stack layer with a memory stack layer.

In some of the embodiments of the present invention, to form the dielectric sacrificial layer, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are sequentially deposited.

In some of the embodiments of the invention, to form the dielectric sacrificial layer, a single layer of silicon oxide is deposited.

In some of the embodiments of the present invention, to form the channel structure, a channel is formed that extends vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. A channel hole, and a memory film and a semiconductor channel are sequentially formed along the sidewall of the channel hole.

In some of the embodiments of the invention, in order to replace the dielectric sacrificial layer with the third polysilicon layer, the dielectric sacrificial layer is removed through the opening to form a cavity between the first and second polysilicon layers , removing a portion of the memory film through the opening to expose a portion of the semiconductor channel along the sidewalls of the via hole, and depositing polysilicon into the cavity through the opening to form a third polysilicon layer.

In some of the embodiments of the invention, at least one of the first, second and third polysilicon layers is doped with an N-type dopant. In some of the embodiments of the present invention, N-type dopants are diffused in the first, second and third polysilicon layers.

According to another aspect of this disclosure, a method for forming a 3D memory element is disclosed. A stop layer, a dielectric layer, a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack layer are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. An opening is formed extending vertically through the dielectric stack layer and the second polysilicon layer and vertically into or through the dielectric sacrificial layer to expose a portion of the dielectric sacrificial layer. The dielectric sacrificial layer is replaced through the opening with a third polysilicon layer between the first and second polysilicon layers. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer. A source contact opening is formed extending vertically through the stop layer and the dielectric layer to expose a portion of the first polysilicon layer. A source contact structure in the source contact opening and an interconnect layer connected to the source contact structure are simultaneously formed.

In some of the embodiments of the present invention, in order to form the source contact structure and the interconnect layer at the same time, a silicide layer is formed in the source contact opening in contact with the exposed portion of the first polysilicon layer, the removal of The stop layer is removed to expose the dielectric layer, and a metal layer is deposited into the source contact openings and on the dielectric layer.

In some of the embodiments of the present invention, in order to sequentially form the stop layer and the dielectric layer, a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are sequentially deposited on the substrate.

In some of the embodiments of the present invention, to form the dielectric sacrificial layer, a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer are sequentially deposited.

In some of the embodiments of the invention, to form the dielectric sacrificial layer, a single layer of silicon oxide is deposited.

In some of the embodiments of the invention, to form the opening, an opening is formed extending vertically through the dielectric stack and into the second polysilicon layer, polysilicon spacers are deposited along the sidewalls of the opening, and the opening is further Extends through the second polysilicon layer and into or through the dielectric sacrificial layer.

In some of the embodiments of the present invention, after replacing the dielectric layer with a third polysilicon layer, the dielectric stack layer is replaced with a memory stack layer through the opening.

In some of the embodiments of the present invention, insulating structures are formed in the openings after replacing the dielectric stack layers with memory stack layers.

In some of the embodiments of the present invention, to form the channel structure, a channel is formed that extends vertically through the dielectric stack layer, the second polysilicon layer, and the dielectric sacrificial layer and into the first polysilicon layer. A channel hole is formed, and a memory film and a semiconductor channel are sequentially formed along the sidewall of the channel hole.

In some of the embodiments of the invention, in order to replace the dielectric sacrificial layer with the third polysilicon layer, the dielectric sacrificial layer is removed through the opening to form a cavity between the first and second polysilicon layers , removing a portion of the memory film through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole, and depositing polysilicon into the cavity through the opening to form a third polysilicon layer.

In some of the embodiments of the invention, at least one of the first, second and third polysilicon layers is doped with an N-type dopant. In some of the embodiments of the present invention, N-type dopants are diffused in the first, second and third polysilicon layers.

According to yet another aspect of the present disclosure, a 3D memory device includes a polysilicon layer, a memory stack including alternating stacked conductive layers and stacked dielectric layers, a channel structure, and a slit structure. The channel structure extends vertically through the memory stack and into the polysilicon layer and includes the memory film and semiconductor channels. A portion of the semiconductor channel along the sidewalls of the channel structure is in contact with the sublayer of the polysilicon layer. The slit structure extends vertically through the memory stack layer and the sub-layers of the polysilicon layer.

In some of the embodiments of the present invention, the 3D memory device further includes a dielectric layer in contact with the polysilicon layer, a source contact structure extending vertically through the dielectric layer and in contact with the polysilicon layer, and connected to the source contact structure the interconnect layer.

In some of these embodiments of the invention, the source contact structure and the interconnect layer comprise the same metal.

In some of the embodiments of the present invention, the 3D memory device further includes a dielectric sacrificial layer coplanar with the sub-layer of the polysilicon layer and in a peripheral region outside the memory stack layer.

In some of the embodiments of the present invention, the dielectric sacrificial layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

In some of the embodiments of the present invention, the sacrificial dielectric layer comprises a single layer of silicon oxide.

In some of the embodiments of the invention, the dielectric sacrificial layer is sandwiched between a portion of the polysilicon layer that does not include the sublayer and extends laterally into the perimeter region.

In some of the embodiments of the invention, the interconnect layer includes contact pads in the peripheral region.

In some of the embodiments of the invention, the polysilicon layer includes an N-type doped polysilicon layer.

The technical solutions in the embodiments of the present invention will be described above with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Obviously, the described embodiments are only some, but not all, embodiments of the invention. Features in the various embodiments may be exchanged and/or combined. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts will fall within the scope of the present invention.

Reference will be made in detail to the exemplary embodiments of the present invention illustrated in the accompanying drawings. where possible Hereinafter, the same reference numbers will be used throughout the drawings to refer to the same or like elements.

The above disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of elements and arrangements are described above for the purpose of simplifying this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the above description, the formation of a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed Embodiments between the first and second features such that the first and second features may not be in direct contact. Furthermore, this summary may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself determine the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms, such as "below," "under," "lower," "over," "over," and the like, may be used herein to describe one element or feature as illustrated in the figures with respect to another element or feature. feature relationship. Spatially relative terms are intended to encompass different orientations of elements in steps of use or operation (in addition to the orientation shown in the figures). The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

While specific configurations and arrangements are discussed, it should be understood that this has been done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present teachings may also be used in various other applications.

Note that in this specification, "one embodiment", "an embodiment", "an example" References to "an embodiment", "some embodiments", etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that various embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not Not necessarily the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it will be within the knowledge of those skilled in the relevant art to affect such a characteristics, structure or properties.

In general, terms can be understood at least in part from their usage above. For example, based at least in part on the above, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a feature, structure or characteristic in the plural. combination of features. Similarly, based at least in part on the above, terms such as "a", "an", and "the" may again be understood to convey a singular usage or to convey a plural usage. Furthermore, again based at least in part on the above, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described.

It should be readily understood that the meanings of "on", "on" and "on" in this summary should be construed in the broadest possible manner, such that "on" not only Means "directly on something", but also includes the meaning of "on something" with intervening features or layers, and "on" or "over" means not only The meaning of "over something" or "over something", but can also include it "over something" or "over something" without intervening features or layers (i.e., directly on something).

In addition, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc., may be used herein for ease of description to describe an element or The relationship of a feature to other elements or features as shown in the drawings. except as depicted in the accompanying drawings In addition to the orientation of the device, the spatially relative terms are intended to include different orientations of the device during use or processing steps. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is generally where the semiconductor devices are formed, and thus the semiconductor devices are formed at the top side of the substrate, unless otherwise specified. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a number of semiconductor materials (eg, silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region of thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively remote from the substrate. A layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any set of levels thereon. The layers may extend horizontally, vertically and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, over it, and/or under it. Layers may include multiple layers. For example, the interconnect layers may include one or more conductive and contact layers (wherein contacts, interconnect lines and/or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

In this summary, for ease of description, "row" is used to refer to a row along a vertical direction Elements of substantially the same height. For example, wordlines and underlying gate dielectric layers may be referred to as "rows," wordlines and underlying insulating layers may be collectively referred to as "rows," and wordlines of substantially the same height may be referred to as "rows" A line of word lines" or similar terms, etc.

As used herein, the term "nominal (nominal)/nominal (nominal)" refers to a desired or target value of a characteristic or parameter of an element or process step set during the design phase of a product or process, Along with a range of values above and/or below the desired value. The range of values may be due to slight variations in manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may indicate a given amount of value that varies, eg, within 10-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

As used herein, the term "nominal/nominal" refers to a desired or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, and higher and/or lower The range of values to expect. The range of values may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor element. Based on a particular technology node, the term "about" may indicate a given amount of value, which varies, for example, within 10%-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

In this context, the term "horizontal/horizontal/lateral/laterally" means nominally parallel to the lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to the lateral surface of the base.

As used herein, the term "3D memory" refers to a A three-dimensional (3D) semiconductor device of vertically oriented strings of memory cell transistors (referred to herein as "memory strings", eg, NAND strings) such that the memory strings extend in a vertical direction relative to the substrate.

The foregoing disclosure provides various embodiments or examples for implementing various features of the presented subject matter. Specific examples of elements and arrangements are described above to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, references in the description above to form a first feature on or over a second feature may include embodiments in which the first and second features are directly contactable features, and may also include Embodiments in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. Furthermore, the present invention may reuse digits and/or letters as reference numerals in the various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

The foregoing description of specific embodiments will so disclose the general nature of this disclosure that others, by applying knowledge of the art, can readily modify and/or adapt such specific embodiments to various applications without Excessive experimentation without departing from the general concept of this disclosure. Therefore, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments, based on the teachings and guidelines presented herein. It is to be understood that the phrases or terms herein are for the purpose of description and not of limitation so that the terms or phrases of this specification will be construed by the skilled artisan in light of the teachings and guidelines.

The foregoing description of specific embodiments will thus disclose the general nature of the disclosure of such specific embodiments by others, by applying knowledge within the skill in the art, to the ease with which such specific embodiments may be modified and/or adapted for various applications without departing from this disclosure. general concept. Therefore, based on the teachings presented in this paper guidance and guidance, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology herein is for the purpose of description and not limitation so that the terminology or phraseology of this specification should be interpreted by a skilled artisan in accordance with the teaching and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of the specified functions and relationships thereof. The boundaries of these functional building blocks are arbitrarily defined herein for convenience of description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are properly performed.

The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the disclosure and the scope of the appended claims in any way.

The breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments, but should be limited only in accordance with the appended claims and their equivalents.

While the principles and implementations of the invention have been described in this specification by using specific examples, the foregoing description of the examples is intended only to aid in an understanding of the invention. Additionally, the features of the various foregoing embodiments may be combined to form additional embodiments. Those skilled in the art can make modifications to the described specific implementation manner and application scope according to the idea of the present invention. Therefore, the contents of the specification should not be construed as limiting the present invention.

The foregoing description of specific embodiments will thus disclose the general nature of the present disclosure of such specific embodiments that others, by applying knowledge within the skill in the art, may readily modify and/or adapt for various applications without undue experimentation. , without departing from the general concept of the present disclosure. because Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not limitation so that the terminology or phraseology of this specification should be interpreted by a skilled artisan in accordance with the teaching and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of the specified functions and relationships thereof. The boundaries of these functional building blocks are arbitrarily defined herein for convenience of description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are properly performed.

The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the disclosure and the scope of the appended claims in any way.

The breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments, but should be limited only in accordance with the scope of the following claims and their equivalents.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: 3D Memory Components

101: Component area

102: Dielectric layer

104: polysilicon layer

105: Upper Sublayer

106: Memory stack layer

107: Polysilicon Layer

108: Stacked conductive layers

109: Sublayer

110: Stacked Dielectric Layers

112: Channel Structure

114: Memory film

116: Semiconductor channel

118: Overlay

120: channel plug

122: Parallel slit structure

124: gate dielectric layer

126: Insulator Core

128: source contact structure

130: Interconnect layer

132: silicide layer

Claims (20)

A method for forming a three-dimensional (3D) memory device, comprising: sequentially forming a first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer and a dielectric stack layer on a substrate forming a channel structure extending vertically through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the first polysilicon layer; forming (i) vertical extending through the dielectric stack layer and the second polysilicon layer and vertically into the dielectric sacrificial layer or vertically through the dielectric sacrificial layer to expose the dielectric sacrificial layer an opening of a portion of the opening, and forming (ii) a polysilicon spacer along a portion of a sidewall of the opening; and through the opening, utilizing the first polysilicon layer and the second polysilicon A third polysilicon layer between the silicon layers replaces the dielectric sacrificial layer. The method of claim 1, wherein forming the openings and the polysilicon spacers comprises forming the openings extending vertically through the dielectric stack and into the second polysilicon layer forming the polysilicon spacers along the sidewalls of the openings; and extending the openings further through the second polysilicon layer and into the dielectric sacrificial layer or through the Dielectric sacrificial layer. The method of claim 1, wherein the polysilicon spacer adjoins the dielectric stack layer but not the dielectric sacrificial layer. The method of claim 1, further comprising: after replacing the dielectric layer with the third polysilicon layer, replacing the dielectric stack layer with a memory stack layer through the opening. The method of claim 4, further comprising: forming a slit structure in the opening after replacing the dielectric stack layer with the memory stack layer. The method of claim 1, wherein forming the dielectric sacrificial layer comprises sequentially depositing a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer. The method of claim 1, wherein forming the dielectric sacrificial layer comprises depositing a single layer of silicon oxide. The method of claim 1, wherein forming the channel structure comprises forming a vertical extension through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the dielectric layer a via hole in the first polysilicon layer; and a memory film and a semiconductor via are sequentially formed along sidewalls of the via hole. The method of claim 8, wherein replacing the dielectric sacrificial layer with the third polysilicon layer comprises removing the dielectric sacrificial layer through the opening to form the first polysilicon layer on the first polysilicon layer. a cavity between the crystalline silicon layer and the second polysilicon layer; removing a portion of the memory film through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole part; and A polysilicon material is deposited into the cavity through the opening to form the third polysilicon layer. The method of claim 1, wherein at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant , and the method further includes: diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer. A method for forming a three-dimensional (3D) memory device, comprising: sequentially forming a stop layer, a dielectric layer, a first polysilicon layer, a dielectric sacrificial layer, a dielectric layer at a first side of a substrate, a second polysilicon layer and a dielectric stack layer; forming vertically extending through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the first polysilicon layer a channel structure in the crystalline silicon layer; forming vertically extending through the dielectric stack layer and the second polysilicon layer and extending vertically into or through the dielectric sacrificial layer , to expose an opening of a portion of the dielectric sacrificial layer; through the opening, replace with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer the dielectric sacrificial layer; removing the substrate from a second side opposite the first side of the substrate, stopping at the stop layer; forming a vertical extension through the stop layer and the a dielectric layer to expose a source contact opening of a portion of the first polysilicon layer; and a source contact structure simultaneously formed in the source contact opening and connected to the source contact structure an interconnect layer. The method of claim 11, wherein simultaneously forming the source contact structure and the interconnect layer comprises: in the source contact opening in contact with an exposed portion of the first polysilicon layer , forming a silicide layer; and removing the stop layer to expose the dielectric layer; and depositing a metal layer into the source contact opening and on the dielectric layer. The method of claim 11, wherein forming the stop layer and the dielectric layer sequentially comprises: depositing a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer on the substrate in sequence Silicon oxide layer. The method of claim 11, wherein forming the dielectric sacrificial layer comprises sequentially depositing a third silicon oxide layer, a second silicon nitride layer and a fourth silicon oxide layer. The method of claim 11, wherein forming the dielectric sacrificial layer comprises depositing a single layer of silicon oxide. The method of claim 11, wherein forming the opening comprises: forming the opening extending vertically through the dielectric stack and into the second polysilicon layer; along the opening A polysilicon spacer is formed on a sidewall of the second polysilicon layer; and the opening further extends through the second polysilicon layer and into or through the dielectric sacrificial layer. The method of claim 11, further comprising: after replacing the dielectric layer with the third polysilicon layer, replacing the dielectric stack layer with a memory stack layer through the opening. The method of claim 17, further comprising: forming an insulating structure in the opening after replacing the dielectric stack layer with the memory stack layer. The method of claim 11, wherein forming the channel structure comprises forming a vertical extension through the dielectric stack layer, the second polysilicon layer and the dielectric sacrificial layer and into the dielectric layer a channel hole in the first polysilicon layer; and a memory film and a semiconductor channel are sequentially formed along a sidewall of the channel hole. The method of claim 19, wherein replacing the dielectric sacrificial layer with the third polysilicon layer comprises removing the dielectric sacrificial layer through the opening to form the first polysilicon layer on the first polysilicon layer. a cavity between the crystalline silicon layer and the second polysilicon layer; removing a portion of the memory film through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole and depositing a polysilicon material into the cavity through the opening to form the third polysilicon layer.

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