TWI756745B - Methods for forming three-dimensional memory devices - Google Patents

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, the method for forming the 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer and a dielectric stack layer are sequentially formed on a first side of a substrate. A channel structure vertically extending through the dielectric stack layer, the second polysilicon layer, the sacrificial layer and the first polysilicon layer and stopping at the stop layer is formed. An opening extending through the dielectric stack layer and the second polysilicon layer and stopping at the sacrificial layer is formed to expose a part of the sacrificial layer. A third polysilicon layer between the first polysilicon layer and the second polysilicon layer is used to replace the sacrificial layer through the opening. The substrate is removed from a second side of the substrate opposite to the first side and is stopped at the stop layer.

Description

Method for forming a three-dimensional (3D) memory device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims International Application No. PCT/CN2020/084600, filed on April 14, 2020, entitled "THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT", and entitled "METHOD FOR FORMING THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT" International Application No. PCT/CN2020/084603, filed on April 27, 2020, entitled "THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME" the benefit of priority from PCT/CN2020/087295 and International Application No. PCT/CN2020/087296, filed on April 27, 2020, entitled "three-dimensional memory device and method for forming the same", all of which Incorporated herein by reference in its entirety.

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Scale down planar memory cells to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become increasingly challenging and expensive. Therefore, the memory density of planar memory cells is approaching the upper limit.

3D memory architectures can address density limitations in planar memory cells. 3D memory rack The structure includes a memory array and peripheral components for controlling signals to and from the memory array.

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

In one example, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer. An opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. The sacrificial layer is replaced by a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

In another example, a method for forming a 3D memory device is disclosed. A stop layer, a buffer layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically into the buffer layer through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer. An opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. The sacrificial layer is replaced by a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

In yet another example, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer. The sacrificial layer is replaced with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer. At least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant. Diffusion of N in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer type dopant. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

100, 101, 101a, 105, 107: 3D memory devices

102,244,350: Dielectric Layer

103,303: Stop Layer

104: polysilicon layer

106,234,334: Memory Stack

108,236,336: Stacked Conductive Layers

109: Sublayer

110, 210, 310: Stacked Dielectric Layers

112, 113, 214, 314: Channel Structure

114, 216, 316: Memory Films

116, 218, 318: Semiconductor Channels

118, 220, 320: Overcladding

120, 222, 322: channel plugs

122,242,342: Insulation structure

124,238,338: Gate Dielectric Layer

126, 240, 340: Insulator Core

128, 130, 246, 346: Source Contact Structure

132: source contact

134, 228, 328: Separator

202,302: Substrate

203: First stop layer

205: Second stop layer

207,307: First polysilicon layer

208,308: Dielectric Stacks

209,309: First sacrificial layer

211, 311: Second sacrificial layer

212,312: Stacked Sacrificial Layers

213,313: The third sacrificial layer

215,315: Second polysilicon layer

224, 324: Slit

226, 326: Cavity

230,330: Third polysilicon layer

305: Buffer layer

400,500: Method

402, 404, 406, 408, 410, 412, 414, 416, 502, 504, 506, 508, 510, 512, 514, 516, 518: Steps

x,y: axis

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the disclosure, and together with the description, serve to further explain the principles of the disclosure and enable those skilled in the relevant art to make and use the disclosure.

1A-1E illustrate cross-sectional side views of various exemplary 3D memory devices in accordance with various embodiments of this disclosure.

2A-2L illustrate a manufacturing process for forming an exemplary 3D memory device according to some embodiments of the present disclosure.

3A-3J illustrate a fabrication process for forming another exemplary 3D memory device in accordance with some embodiments of this disclosure.

4 illustrates a flowchart of a method for forming an exemplary 3D memory device in accordance with some embodiments of this disclosure.

5 illustrates a flowchart of a method for forming another exemplary 3D memory device in accordance with some embodiments of this disclosure.

Embodiments of the present disclosure will be described with reference to the drawings.

While specific configurations and arrangements are discussed, it should be understood that this has been done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

Note that references in this specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiment may include the particular feature, structure, or characteristic, but each An implementation may not necessarily include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in connection with an embodiment, it will be within the knowledge of one skilled in the relevant art to affect such feature, structure or characteristic in connection with other embodiments, whether explicitly described or not.

Generally, terms can be understood, at least in part, from their usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a combination of features, structures or characteristics in the plural depending at least in part on context . Similarly, terms such as "a", "an", and "the" may again be understood to convey a singular usage or to convey a plural usage, depending at least in part on context. Furthermore, again at least in part depending on context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described.

It should be readily understood that the meanings of "on", "on" and "over" in this summary are to be taken in the broadest sense is interpreted in such a way that "on" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers, and " On" or "over" not only means "above something" or "over something," but can also include it "over something" The meaning of "on" or "over something" without intervening features or layers (ie, directly on something).

Additionally, spatially relative terms such as "below", "below", "lower", "above", "upper", etc. may For ease of description, it is used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be The same is explained accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a number of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a width that is less than the width of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes thereon. The layers may extend horizontally, vertically and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, over it, and/or under it. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

As used herein, the term "nominal/nominal" refers to a desired or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process along with values above and/or below the desired value range. The range of values may be due to slight variations in manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the particular technology node associated with the subject semiconductor element. Based on the particular technology node, the term "about" may indicate a given amount of value that varies, eg, within 10-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

As used herein, the term "3D memory device" refers to vertically oriented strings (referred to herein as "memory strings" such as NAND memory strings) having memory cell transistors on a laterally oriented substrate of semiconductor elements, so that the memory strings extend in a vertical direction relative to the substrate. as in As used herein, the term "perpendicular/perpendicularly" means nominally perpendicular to the lateral surface of the substrate.

In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of the channel structures, eg, known as sidewall selective epitaxial growth (SEG). The formation of sidewall SEGs avoids etching of the memory film and semiconductor vias at the bottom surface of the via hole (also known as a bottom SEG) compared to another type of semiconductor plug formed at the lower end of the via structure, such as a bottom SEG. "SONO" hole punching), thereby increasing the process window, especially when manufacturing 3D NAND memory devices with advanced technologies, such as 96 or more levels with a multi-die architecture. In addition, sidewall SEG structures can be combined with backside processing to form source contacts from the backside of the substrate to avoid leakage currents and parasitic capacitances between frontside source contacts and word lines and increase effective device area.

However, because the backside process requires thinning of the substrate, it faces two main challenges: thickness uniformity is difficult to control at the wafer level during thinning, and high Concentration doping is difficult to achieve. These challenges limit the yield of 3D NAND memory devices with sidewall SEG structures and backside processes.

Various embodiments in accordance with the present disclosure provide improved 3D NAND memory devices and methods of fabricating the same. A stop layer can be formed on the substrate to automatically stop the backside thinning process so that the substrate can be completely removed to avoid wafer thickness uniformity control issues and reduce the fabrication complexity of the backside process. In some embodiments, the same stop layer or another stop layer is used to automatically stop the via hole etch, which can better control gouge variations between different via structures and further increase the backside process window. Also, the deposited polysilicon layer can replace the single crystal silicon in the removed silicon substrate for sidewall SEGs. Because the deposited polysilicon layer can be more easily doped to the desired doping concentration than the thinned silicon substrate, backside process complexity can be further reduced and yield can be increased.

1A-1E illustrate cross-sectional side views of various exemplary 3D memory devices in accordance with various embodiments of this disclosure. In some implementations, the 3D memory device 100 in FIG. 1A includes a substrate (not shown), which may include silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), Germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate is a thinned substrate (eg, a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. Note that the x and y axes are included in FIG. 1A to further illustrate the spatial relationship of the components in the 3D memory device 100 . The base of the 3D memory device 100 includes two lateral surfaces (eg, top and bottom surfaces) that extend laterally in the x-direction (ie, the lateral direction). As used herein, a feature (eg, layer or device) is "on," "over," or "under" another component (eg, a layer or device) of a 3D memory device (eg, 3D memory device 100). The same concepts used to describe spatial relationships apply throughout this summary.

In some embodiments, the 3D memory device 100 is part of a non-monolithic 3D memory device in which components are formed separately on different substrates and then bonded face-to-face, face-to-back, or back-to-back. Peripherals (not shown) (eg, any suitable digital, analog, and/or mixed-signal peripheral circuitry used to facilitate operation of the 3D memory device 100) may be formed on a separate peripheral substrate than the memory array substrate, The components described in FIG. 1A are formed on the memory array substrate. It should be understood that the memory array substrate can be removed from the 3D memory device 100 , as described in more detail below, and the peripheral equipment substrate can become the substrate of the 3D memory device 100 . Furthermore, it should be understood that depending on how the peripheral device substrate and the memory array element substrate are bonded, the memory array elements (eg, as shown in FIG. 1A ) may be in their original position or may be upside-down in the 3D memory device 100 flip. For ease of reference, FIG. 1A depicts the state of the 3D memory device 100 in which the memory array elements are in their original positions (ie, not flipped upside down). It should be understood, however, that in some examples, the memory array elements shown in FIG. 1A may be flipped upside down in 3D memory device 100 and their relative positions may be changed accordingly. The same concepts used to describe spatial relationships apply throughout this summary.

As shown in FIG. 1A, the 3D memory device 100 may include a dielectric layer 102 and a Stop layer 103 on 102 . Dielectric layer 102 may include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which interconnect lines and VIA contacts may be formed. formed in the layer. The ILD layer of the dielectric layer 102 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k (low-k) dielectrics, or any combination thereof. In some embodiments, the dielectric layer 102 includes silicon oxide. The stop layer 103 may be disposed directly on the dielectric layer 102 . In some embodiments, stop layer 103 includes a high-k (high-k) dielectric layer. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide, to name a few. In one example, stop layer 103 may include aluminum oxide. As described in more detail below, because the function of stop layer 103 is to stop the etching of the channel holes, it should be understood that stop layer 103 may comprise a relatively high etch selectivity (eg, greater than about 5) with respect to the materials in the layers described above. any other suitable material. In some embodiments, in addition to serving as an etch stop layer, stop layer 103 also serves as a backside substrate thinning stop layer, and thus has a material other than that of the memory array substrate (eg, silicon).

The 3D memory device 100 may also include a polysilicon layer 104 over the stop layer 103 . In some embodiments, the polysilicon layer 104 is disposed directly on the stop layer 103 . In some embodiments, a pad oxide layer (eg, a silicon oxide layer) is disposed between the stop layer 103 and the polysilicon layer 104 to relieve stress between the polysilicon layer 104 and the stop layer 103 (eg, an aluminum oxide layer). According to some embodiments, the polysilicon layer 104 includes an N-type doped polysilicon layer. That is, the polysilicon layer 104 may be doped with any suitable N-type dopant that contributes free electrons and increases the conductivity of the intrinsic semiconductor, such as phosphorus (P), arsenic (Ar), or antimony (Sb). As described in more detail below, due to the diffusion process, the polysilicon layer 104 may have a uniform dopant concentration profile in the vertical direction. In some embodiments, the doping concentration of the polysilicon layer 104 is between about 10 ¹⁹ cm ^-3 and about 10 ²² cm ^-3 , eg, between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 (eg, 10 ¹⁹ cm -3 ) ^-3 , 2×10 ¹⁹ cm ^-3 , 3×10 ¹⁹ cm ^-3 , 4×10 ¹⁹ cm ^-3 , 5×10 ¹⁹ cm ^-3 , 6×10 ¹⁹ cm ^-3 , 7×10 ¹⁹ cm ^-3 , 8×10 ¹⁹ cm ^-3 , 9×10 ¹⁹ cm ^-3 , 10 ²⁰ cm ^-3 , 2×10 ²⁰ cm ^-3 , 3×10 ²⁰ cm ^-3 , 4×10 ²⁰ cm ^-3 , 5×10 ²⁰ cm ^-3 , 6×10 ²⁰ cm ^-3 , 7×10 ²⁰ cm ^-3 , 8×10 ²⁰ cm ^-3 , 9×10 ²⁰ cm ^-3 , 1021 cm ^-3 , 2×10 ²¹ cm ^-3 , 3 ×10 ²¹ cm ^-3 , 4×10 ²¹ cm ^-3 , 5×10 ²¹ cm ^-3 , 6×10 ²¹ cm ^-3 , 7×10 ²¹ cm ^-3 , 8×10 ²¹ cm ^-3 , 9×10 ²¹ cm ^-3 , ¹⁰²² cm ^-3 , any range bounded lower by any of these values, or in any range bounded by any two of these values). Although FIG. 1A shows polysilicon layer 104 over stop layer 103, as described above, it should be understood that stop layer 103 may be over polysilicon layer 104 in some examples because the memory array element shown in FIG. 1A may be upside-down flipped, and their relative positions can be changed accordingly in the 3D memory device 100 . In some embodiments, the memory array element shown in FIG. 1A is flipped upside down (in the top) and bonded to peripherals (in the bottom) in the 3D memory device 100 such that the stop layer 103 is in the polysilicon layer 104 and above.

In some embodiments, the 3D memory device 100 also includes extending vertically through the dielectric layer 102 and the stop layer 103 from the opposite side of the polysilicon layer 104 relative to the stop layer 103 (ie, the backside) to contact the polysilicon layer 104 source contact structure 128. It should be understood that the depth to which the source contact structures 128 extend into the polysilicon layer 104 may vary in different examples. The source contact structure can electrically connect the sources of the NAND memory strings of the 3D memory device 100 to peripheral equipment from the backside of the memory array substrate (removed) through the polysilicon layer 104, and may therefore also be referred to herein as for "Backside Source Pickup". The source contact structure 128 may include any suitable type of contact. In some embodiments, the source contact structure 128 includes a VIA contact. In some embodiments, the source contact structures 128 include laterally extending wall contacts. The source contact structure 128 may include one or more conductive layers, such as metal layers, such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al) or formed by an adhesive layer such as silicon nitride (TiN). )) surrounded by a silicide layer.

In some implementations, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string may include channel structures 112 extending through a plurality of pairs, each pair including stacked conductive layers 108 and stacked dielectric layers 110 (referred to herein as "conductive/dielectric layer pairs"). The stacked conductive/dielectric layer pair is also referred to herein as the memory stack 106 . The number of conductive/dielectric layer pairs (eg, 32, 64, 96, 128, 160, 192, 224, 256, etc.) in the memory stack 106 determines the number of memory cells in the 3D memory device 100 quantity. Although not shown in FIG. 1A , it should be understood that in some embodiments, the memory stack 106 may have a multi-stack architecture, such as one including a lower memory stack and an upper memory stack on the lower memory stack. Double lamination architecture. The number of pairs of stacked conductive layers 108 and stacked dielectric layers 110 in each memory stack may be the same or different.

The memory stack 106 may include a plurality of alternating stacked conductive layers 108 and stacked dielectric layers 110 and polysilicon layers 104 . The stacked conductive layers 108 and stacked dielectric layers 110 in the memory stack 106 may alternate in the vertical direction. In other words, except for the layers at the top or bottom of the memory stack 106, each stacked conductive layer 108 may be adjoined by two stacked dielectric layers 110 on both sides, and each stacked dielectric layer 110 may be adjoined by two stacked conductive layers 110 on both sides. The stacked conductive layer 108 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stacked conductive layer 108 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer 124 . The gate electrodes of the stacked conductive layers 108 may extend laterally as word lines terminating at one or more stepped structures (not shown) of the memory stack 106 . The stacked dielectric layer 110 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIG. 1A , each channel structure 112 extends vertically through the memory stack 106 and the polysilicon layer 104 , stopping at the stop layer 103 . That is, the channel structure 112 may include two parts: a lower part surrounded by the polysilicon layer 104 (ie below the interface between the polysilicon layer 104 and the stop layer 103 ) and a lower part surrounded by the memory stack 106 (ie under the polysilicon layer 103 ) above the interface between layer 104 and memory stack 106 ). As used herein, when the substrate is in the lowest plane of the 3D memory device 100, the "upper portion/end" of a component (eg, channel structure 112) is the portion/end that is further away from the substrate in the y-direction, and The "lower portion/end" of a component (eg, channel structure 112) is the portion/end that is closer to the substrate in the y-direction. In some embodiments, each channel structure 112 does not extend further beyond the stop layer 103 because the etching of the channel holes is stopped by the stop layer 103 . For example, the lower end of the channel structure 112 may be nominally flush with the top surface of the stop layer 103 . As a result, the gouges among the array of channel structures 112 vary Can be controlled and minimized by stop layer 103 .

The channel structure 112 may include via holes filled with semiconductor material (eg, as semiconductor channel 116 ) and dielectric material (eg, as memory film 114 ). In some embodiments, the semiconductor channel 116 includes silicon, such as amorphous silicon, polysilicon, or monocrystalline silicon. In one example, the semiconductor channel 116 includes polysilicon. In some embodiments, the memory film 114 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. The remaining space of the via hole may be partially or fully filled with an overlying layer 118 including a dielectric material such as silicon oxide and/or air gaps. The channel structure 112 may have a cylindrical shape (eg, a column shape). According to some embodiments, the overlying layer 118 , the semiconductor channel 116 , the tunneling layer of the memory film 114 , the storage layer, and the barrier layer are radially arranged in this order from the center of the pillar toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, the memory film 114 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In some embodiments, the channel structure 112 also includes a channel plug 120 at the top of the upper portion of the channel structure 112 . The channel plug 120 may include a semiconductor material (eg, polysilicon). In some embodiments, the channel plug 120 functions as the drain of the NAND memory string.

As shown in FIG. 1A , portions of semiconductor channel 116 along sidewalls of channel structure 112 (eg, in a lower portion of channel structure 112 ) are in contact with sublayer 109 of polysilicon layer 104 , according to some embodiments. That is, according to some embodiments, the memory film 114 is separated at the lower portion of the channel structure 112 adjoining the sublayer 109 of the polysilicon layer 104 , exposing the semiconductor channel 116 to contact the surrounding sublayer 109 of the polysilicon layer 104 . Thus, the sub-layer 109 of the polysilicon layer 104 surrounding and in contact with the semiconductor channel 116 may serve as the "side SEG" of the channel structure 112 in place of the "bottom SEG" described above, which may alleviate, eg, coverage control, epitaxy The problem of crystal layer formation and SONO drilling. As described in more detail below, according to some embodiments, the sublayer 109 of the polysilicon layer 104 is formed separately from the remainder of the polysilicon layer 104 . However, it should be understood that the sub-layer 109 of the polysilicon layer 104 may have the same phase as the remainder of the polysilicon layer 104 The same polysilicon material, and the doping concentration may be uniform in the polysilicon layer 104 after diffusion, the sublayer 109 may be indistinguishable from the rest of the polysilicon layer 104 in the 3D memory device 100 . However, the sublayer 109 refers to the portion of the polysilicon layer 104 in the lower portion of the channel structure 112 that is in contact with the semiconductor channel 116 rather than the memory film 114 .

As shown in FIG. 1A , the 3D memory device 100 may also include insulating structures 122 each extending vertically through the interleaved stacked conductive layers 108 and stacked dielectric layers 110 of the memory stack 106 . Unlike channel structure 112 , which extends through the entire thickness of polysilicon layer 104 and stops at stop layer 103 , insulating structure 122 extends into polysilicon layer 104 , stopping at sublayer 109 of polysilicon layer 104 , according to some embodiments. That is, according to some embodiments, the insulating structure 122 does not extend through the entire thickness of the polysilicon layer 104 and is not in contact with the stop layer 103 . In some embodiments, the lower end of insulating structure 122 is nominally flush with the top surface of sublayer 109 of polysilicon layer 104 . Each insulating structure 122 may also extend laterally to divide the channel structure 112 into multiple pieces. That is, the memory stack 106 may be divided into a plurality of memory blocks by the insulating structure 122 such that the array of channel structures 112 may be divided into each memory block. Unlike the slit structures in some 3D NAND memory devices, which include front-side source contact structures, according to some embodiments, the insulating structures 122 do not include any contacts therein (ie, do not function as source contacts) and Therefore, no parasitic capacitance and leakage current are introduced into the conductive layer 108 (including word lines). In some implementations, each insulating structure 122 includes an opening (eg, a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 122 may be filled with silicon oxide as an insulator core 126 and a high-k dielectric connected to the gate dielectric layer 124 .

In some embodiments, by doping the polysilicon layer 104 with N-type dopants, ie, eliminating the P-wells, which are sources of holes, according to some embodiments, the 3D memory device 100 is configured to generate when an erase operation is performed The gate induced drain leakage (GIDL) assisted body bias. GIDL around the source select gate of a NAND string can generate hole current into the NAND string for erasing operation to increase the body potential. Furthermore, by eliminating the P-well as a source of holes, the control of the source select gate can also be simplified during read operations, since the inversion channel is no longer required when a read operation is performed by the 3D memory device 100 .

As described above and described in further detail below, according to some embodiments, the stop layer 103 , the polysilicon layer 104 , the memory stack 106 , the channel structure 112 , and the insulating structure 122 are formed thereon are removed from the 3D memory device 100 . A memory array substrate, the 3D memory device 100 does not include a memory array substrate. In some embodiments in which the removed memory array substrate comprises monocrystalline silicon, each channel structure 112 is not in contact with the monocrystalline silicon layer that is part of the memory array substrate (eg, after thinning) .

It should be understood that in some embodiments, the stop layer 103 may be removed from the final product of the 3D memory device. For example, as shown in FIG. 1B , 3D memory device 101 may be the same as 3D memory device 100 , except that 3D memory device 101 may not include a stop layer between polysilicon layer 104 and dielectric layer 102 . Alternatively, the polysilicon layer 104 is disposed directly on the dielectric layer 102 , and the source contact structure 128 extends vertically through the dielectric layer 102 to contact the polysilicon layer 104 . Similar to the 3D memory device 100, the channel structure 112 may stop at the interface between the polysilicon layer 104 and the dielectric layer 102 and not extend beyond the polysilicon layer 104 due to the etch stop effect of the stop layer 103 during the fabrication process Outside (ie, the lower end of the channel structure 112 is nominally flush with the bottom surface of the polysilicon layer 104 ), the polysilicon layer 104 is later removed from the 3D memory device 101 . It should be understood that other identical structural details in 3D memory devices 101 and 100 are not repeated for ease of description.

It is also understood that in some embodiments, when fabricating a 3D memory device, the stop layer 103 may not be formed in the first place. For example, as shown in FIG. 1C, 3D memory device 101a may be identical to 3D memory device 101, except that one or more channel structures 113 extend out of polysilicon layer 104 and due to the absence of stop layer 103 during the fabrication process penetrates into and out of the dielectric layer 102 . That is, according to some embodiments, the lower end of the one or more channel structures 113 is lower than the bottom surface of the polysilicon layer 104 . It should be understood that Details of other identical structures in 3D memory devices 101a and 101 are not repeated for ease of description.

Furthermore, it should be understood that in some embodiments, the backside source contact structures 128 in the 3D memory device 100, 101, or 101a may be replaced with frontside source contact structures disposed at the same side of the memory stack 106 (eg, Also known as "front-side source pickup"). That is, instead of the insulating structure 122 filled with a dielectric material, the slit structure may be filled with a conductive material to become a source contact structure. For example, as shown in FIG. 1D , 3D memory device 105 may be identical to 3D memory device 100 except that backside source contact structure 128 and insulating structure 122 may be used to extend vertically into polysilicon layer 104 through memory stack 106 The source contact structure 130 is replaced outside. In some embodiments, the source contact structure 130 stops at the sublayer 109 of the polysilicon layer 104 . It should be understood that other identical structural details in 3D memory devices 105 and 100 are not repeated for ease of description.

The source contact structures 130 may also extend vertically (eg, in directions perpendicular to the x and y directions) to divide the memory stack 106 into blocks. Source contact structure 130 may include spacers 134 and source contacts 132 , each extending vertically into polysilicon layer 104 through memory stack 106 . Spacer 134 may include a dielectric material (eg, silicon oxide) laterally between source contact 132 and memory stack 106 to electrically separate source contact 132 from surrounding stacks in memory stack 106 Conductive layer 108 . On the other hand, the spacers 134 may be arranged along the sidewalls of the source contact structure 130, but not at the bottom of the source contact structure 130, so that the source contact 132 may be over and in contact with the polysilicon layer 104 to An electrical connection to the semiconductor channel 116 of the channel structure 112 is established. In some embodiments, the source contact 132 includes an adhesive layer and a conductive layer surrounded by the adhesive layer. The adhesive layer may include one or more conductive materials, such as titanium nitride (TiN), over and in contact with the polysilicon layer 104 to establish electrical connection with the polysilicon layer 104 . In some embodiments, the conductive layer includes polysilicon in its lower portion and metal (eg, W) in its upper portion that contacts metal interconnects (not shown). In some embodiments, the adhesive layer (eg, TiN) is in contact with both the polysilicon layer 104 and the metal (eg, W) of the conductive layer to form between the polysilicon layer 104 (eg, as the source of the NAND memory strings) and the metal interconnects electrical connection between.

Furthermore, it should be understood that the design of replacing the backside source contact structure 128 and the insulating structure 122 with the frontside source contact structure 130 can be similarly applied to a 3D memory device without the stop layer 103 . For example, as shown in FIG. 1E , 3D memory device 107 may be the same as 3D memory device 105 , except that 3D memory device 107 does not include stop layer 103 . Although FIG. 1E shows channel structures 112 not extending beyond polysilicon layer 104 , it should be understood that one or more channel structures 113 (like in 3D memory device 101 a in FIG. 1C ) may extend beyond polysilicon layer 104 and further into the dielectric layer 102 . It should be understood that other identical structural details in 3D memory devices 107 and 105 are not repeated for ease of description.

2A-2L illustrate a manufacturing process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. 4 shows a flowchart of a method 400 for forming an exemplary 3D memory device in accordance with some embodiments of this disclosure. Examples of 3D memory devices depicted in FIGS. 2A-2L and 4 include 3D memory device 100 depicted in FIGS. 1A and 1B . 2A-2L and FIG. 4 will be described together. It should be understood that the steps shown in method 400 are not exclusive, and that other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously or in a different order than that shown in FIG. 4 .

4, method 400 begins at step 402 in which a stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at a first side of a substrate. The substrate may be a silicon substrate or carrier substrate made of any suitable material such as glass, sapphire, plastic (to name a few) to reduce the cost of the substrate. The first side may be the front side of the substrate on which the semiconductor elements are formed. In some embodiments, to form the stop layer, the first stop layer and the second stop layer are sequentially formed. The first stop layer can include silicon nitride, and the second stop layer can include a high-k dielectric. In some embodiments, to form the sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed. The first sacrificial layer may include silicon oxynitride, the second sacrificial layer may include polysilicon, and the third sacrificial layer may include silicon oxynitride. The dielectric stack may include a plurality of interleaved stacked sacrificial layers and stacked dielectric layers.

As shown in FIG. 2A, the first stop layer 203, the second stop layer 205, the first polysilicon layer 207, the first sacrificial layer 209, the second sacrificial layer 211, the third sacrificial layer 213 and the second polysilicon layer 215 are formed successively at the front side of the substrate. Substrate 202 may be a silicon substrate or carrier substrate made of any suitable material such as glass, sapphire, plastic, to name a few. The first stop layer 203 and the second stop layer 205 may be collectively referred to herein as stop layers. In some embodiments, the first stop layer 203 and the second stop layer 205 include silicon nitride and a high-k dielectric, such as aluminum oxide, respectively. As described in detail below, the first stop layer 203 can act as a stop layer when the substrate 202 is removed from the backside, and thus can include any other suitable material other than the material of the substrate 202 . Similarly, the second stop layer 205 can act as a stop layer when etching via holes from the front side, and thus can include a high etch relative to polysilicon (the material of the first polysilicon layer 207 on the second stop layer 205 ) Any other suitable material of selectivity (eg greater than about 5). It should be understood that in some examples, one of the first stop layer 203 and the second stop layer 205 may be skipped, meaning that the other of the first stop layer 203 and the second stop layer 205 may serve as a source for backside reduction Thin and front etched stop layers. For example, the stop layer may include only a high-k dielectric layer, such as an aluminum oxide layer. It should also be understood that in some embodiments, a pad oxide layer (eg, a silicon oxide layer) may be formed between the substrate 202 and the first stop layer 203 and/or between the first stop layer 203 and the second stop layer 205 to relieve the stress between the different layers. Similarly, another pad oxide layer can be formed between the second stop layer 205 and the first polysilicon layer 207 to relieve stress therebetween.

The first sacrificial layer 209, the second sacrificial layer 211, and the third sacrificial layer 213 may be collectively referred to herein as sacrificial layers. In some embodiments, the first sacrificial layer 209, the second sacrificial layer 211, and the third sacrificial layer 213 include silicon oxynitride, polysilicon, and silicon oxynitride, respectively. As described in more detail below, the third sacrificial layer 213 can act as a stop layer when etching the slit openings from the front side, and can be selectively removed later, and thus can be included relative to polysilicon (in the third sacrificial layer material of the second polysilicon layer 215 on 213) any other suitable material with a high etch selectivity (eg, greater than about 5). The second sacrificial layer 211 can be selectively removed later and thus can include high etch relative to dielectrics such as polysilicon or carbon Any other suitable material of selectivity (eg greater than about 5). The first sacrificial layer 209 may act as a stop layer when etching the second sacrificial layer 211 and may be selectively removed later, and thus may include relative 207) any other suitable material with high etch selectivity (eg, greater than about 5).

The first stop layer 203, the second stop layer 205, the first polysilicon layer 207, the first sacrificial layer 209, the second sacrificial layer 211, the third sacrificial layer 213, and the second polysilicon layer 215 (or among them) Any other layers in between) can be in this order in multiple loops by using one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) ), electroplating, electroless deposition, any other suitable deposition process, or any combination thereof) depositing the corresponding materials to form successively. In some embodiments, at least one of the first polysilicon layer 207 and the second polysilicon layer 215 is doped with an N-type dopant, such as P, As, or Sb. In one example, at least one of the first polysilicon layer 207 and the second polysilicon layer 215 may be doped using an ion implantation process after depositing the polysilicon material. In another example, in-situ doping of N-type dopants may be performed when polysilicon is deposited to form at least one of the first polysilicon layer 207 and the second polysilicon layer 215 . It should be appreciated that in some examples, neither the first polysilicon layer 207 nor the second polysilicon layer 215 are doped with N-type dopants at this stage.

As shown in FIG. 2A , a plurality of pairs of a first dielectric layer (referred to as a “stacked sacrificial layer 212 ”) and a second dielectric layer (referred to as a “stacked dielectric layer”) are formed on the second polysilicon layer 215 The dielectric stack 208 of the dielectric layer 210"). According to some embodiments, the dielectric stack 208 includes a stacked sacrificial layer 212 and a stacked dielectric layer 210 that are staggered. Stacked dielectric layers 210 and stacked sacrificial layers 212 may be alternately deposited on second polysilicon layer 215 to form dielectric stack 208 . In some embodiments, each stacked dielectric layer 210 includes a layer of silicon oxide, and each stacked sacrificial layer 212 includes a layer of silicon nitride. Dielectric stack 208 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, a pad oxide layer (eg, a silicon oxide layer not shown) is formed between the second polysilicon layer 215 and the dielectric stack 208 .

The method 400 proceeds to step 404 as shown in FIG. 4 in which a stop at stop layer is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer and the first polysilicon layer channel structure. In some embodiments, to form the channel structure, a via hole is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, and along sidewalls of the via hole A memory film and a semiconductor channel are formed successively. In some embodiments, a channel plug is formed over and in contact with the semiconductor channel.

As shown in FIG. 2A, via holes extend vertically through the dielectric stack 208, the second polysilicon layer 215, the sacrificial layers 213, 211, and 209, and the first polysilicon layer 207, at a second stop The opening that stops at layer 205. In some embodiments, multiple openings are formed such that each opening becomes a location for growing individual channel structures 214 in a later process. In some embodiments, the fabrication process used to form the channel holes of the channel structure 214 includes wet etching and/or dry etching processes, such as deep ion reactive etching (DRIE). According to some embodiments, the etching of the via hole continues until the second stop layer 205 (eg, aluminum oxide) and the material of the first polysilicon layer 207 (eg, polysilicon) are blocked by the second stop layer due to the etch selectivity between the materials of the first polysilicon layer 207 (eg, polysilicon). 205 (eg, a high-k dielectric layer (eg, an aluminum oxide layer)) until it stops. In some embodiments, the etch conditions (eg, etch rate and time) can be controlled to ensure that each via hole reaches and is stopped by the second stop layer 205 such that the via hole and the via formed therein Gouge variation among structures 214 is minimized. It should be understood that, depending on the particular etch selectivity, one or more via holes may extend to a small extent into the second stop layer 205, which is still considered to be stopped by the second stop layer 205 in the context of the present disclosure, and enables the Its lower end is nominally flush with the top surface of the second stop layer 205 .

As shown in FIG. 2A, a memory film 216 (including a barrier layer, a storage layer, and a tunneling layer) and a semiconductor channel 218 are sequentially formed in this order along the sidewalls and bottom surfaces of the channel holes. In some embodiments, the memory film 216 is first deposited along the sidewalls and bottom surfaces of the via holes, and the semiconductor channel 218 is then deposited over the memory film 216 . The barrier, storage, and tunneling layers may then be in this order using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination) to deposit to form the memory film 216. The semiconductor channel may then be formed by depositing a semiconductor material (eg, polysilicon) over the tunneling layer of the memory film 216 using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) 218. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are subsequently deposited to form the memory film 216 and the semiconductor channel 218 .

As shown in FIG. 2A, an overcladding layer 220 is formed in the via hole and over the semiconductor via 218 to fully or partially fill the via hole (eg, without or with an air gap). Overlay 220 may be formed by depositing a dielectric material (eg, silicon oxide) using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). A channel plug 222 may then be formed in the upper portion of the channel hole. In some embodiments, portions of the memory film 216 , semiconductor channels 218 , and overlying layer 220 on the top surface of the dielectric stack 208 are removed and removed by a CMP, wet etch, and/or dry etch process Flatten. Recesses may then be formed in the upper portion of the via hole by wet etching and/or dry etching portions of the semiconductor channel 218 and overlying layer 220 in the upper portion of the via hole. The channel plug 222 may then be formed by depositing a semiconductor material (eg, polysilicon) into the recess through one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof). According to some embodiments, the channel structure 214 is thus formed through the dielectric stack 208 , the second polysilicon layer 215 , the sacrificial layers 213 , 211 and 209 and the first polysilicon layer 207 , at the second stop layer 205 . stop there.

The method 400 proceeds to step 406 as shown in FIG. 4 in which an opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. In some embodiments, an opening is formed that stops at the third sacrificial layer.

As shown in FIG. 2B, slit 224 is an opening formed vertically extending through dielectric stack 208 and second polysilicon layer 215, stopping at third sacrificial layer 213, exposing the third sacrificial layer Section 213. In some embodiments, the fabrication process used to form the slits 224 includes a wet etch and/or dry etch process, such as DRIE. In some embodiments, the stack dielectric of dielectric stack 208 is first etched layer 210 and stacked sacrificial layer 212 . Etching of the dielectric stack 208 may not stop at the top surface of the second polysilicon layer 215 and extend further into the second polysilicon layer 215 at various depths (ie, gouge variations). Therefore, a second etch process (sometimes referred to as a post-etch process) may be performed to etch the second polysilicon layer 215 until the third sacrificial layer 213 (eg, silicon oxynitride layer) and the second polysilicon layer are The etch selectivity between materials 215 (eg, polysilicon) is stopped by a third sacrificial layer 213 (eg, a silicon oxynitride layer).

The method 400 proceeds to step 408 as shown in FIG. 4 in which the sacrificial layer is replaced by a third polysilicon layer between the first and second polysilicon layers through the opening. In some embodiments, to replace the sacrificial layer with the third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first and second polysilicon layers, the memory film is removed through the opening to expose portions of the semiconductor channel along the sidewalls of the channel hole, and polysilicon is deposited into the cavity through the opening to form a third polysilicon layer. In some embodiments, at least one of the first, second, and third polysilicon layers is doped with an N-type dopant. N-type dopants may be diffused in the first, second and third polysilicon layers.

Spacers 228 are formed along the sidewalls of the slits 224 by depositing one or more dielectrics (eg, high-k dielectrics) along the sidewalls of the slits 224 as shown in FIG. 2C . A wet etch and/or dry etch process may be used to open the bottom surface of the spacer 228 (and the portion of the third sacrificial layer 213 in the slit 224, if still remaining) to expose the portion of the second sacrificial layer 211 (in the slit 224). 2B, eg a polysilicon layer). In some embodiments, the sacrificial layer 211 is then removed by wet etching and/or dry etching to form the cavity 226 . In some embodiments, the second sacrificial layer 211 includes polysilicon, the spacer 228 includes a high-k dielectric, the first sacrificial layer 209 and the third sacrificial layer 213 each include silicon oxynitride, and the second sacrificial layer 211 penetrates through Slot 224 is etched by applying tetramethylammonium hydroxide (TMAH) etchant, which is stopped by high-k dielectric spacer 228 and first sacrificial layer 209 and third sacrificial layer 213 of silicon oxynitride. That is, according to some embodiments, the removal of the second sacrificial layer 211 does not affect the dielectric stack 208 and the first polysilicon protected by the spacer 228 and the first and third sacrificial layers 209 and 213, respectively layer 207 and second polysilicon layer 215.

As shown in FIG. 2D , the portion of the memory film 216 exposed in the cavity 226 is removed to expose the portion of the semiconductor channel 218 along the sidewalls of the channel structure 214 . In some embodiments, the barrier layer (eg, including silicon oxide) is etched by applying an etchant (eg, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) through slit 224 and cavity 226 ), the storage layer (for example comprising silicon nitride) and the tunneling layer (for example comprising silicon oxide). Etching can be stopped by spacer 228 and semiconductor channel 218 . That is, according to some embodiments, the removal of the portion of the memory film 216 exposed in the cavity 226 does not affect the dielectric stack 208 (protected by the spacer 228 ) and the semiconductor channel 218 including polysilicon and the semiconductor channel 218 , which is protected by the spacer 228 The upper cladding 220 surrounded by 218. In some embodiments, the first sacrificial layer 209 and the third sacrificial layer 213 (including silicon oxynitride) are also removed by the same etching process.

As shown in FIG. 2E , a third polysilicon layer 230 is formed between the first polysilicon layer 207 and the second polysilicon layer 215 . In some embodiments, the third film is formed by depositing polysilicon through slit 224 into cavity 226 (shown in FIG. 2D ) using one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) Polysilicon layer 230 . In some embodiments, when the polysilicon is deposited to form the third polysilicon layer 230 , in-situ doping of N-type dopants such as P, As, or Sb is performed. The third polysilicon layer 230 may fill the cavity 226 to contact the exposed portion of the semiconductor channel 218 of the channel structure 214. It should be understood that the third polysilicon layer 230 may be doped or undoped, depending on the first polysilicon layer 207 and the second polysilicon layer Whether at least one of the silicon layers 215 is doped with N-type dopants, because at least one of the first polysilicon layer 207 , the second polysilicon layer 215 and the third polysilicon layer 230 may need to be doped with N-type dopant. In some embodiments, the N-type dopant in at least one of the first polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer 230 is diffused in the In the first polysilicon layer 207, the second polysilicon layer 215 and the third polysilicon layer 230, a thermal diffusion process (such as annealing) is used to form the first polysilicon layer 207, the second polysilicon layer A uniform dopant concentration profile is achieved in the vertical direction among the third polysilicon layer 215 and the third polysilicon layer 230. For example, the dopant concentration after diffusion may be between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 . As described above, in The interfaces between the first polysilicon layer 207, the second polysilicon layer 215 and the third polysilicon layer 230 may become indistinguishable because the first polysilicon layer 207, the second polysilicon layer 215 and the Each of the third polysilicon layers 230 includes the same polysilicon material with nominally the same doping concentration. Thus, the first polysilicon layer 207, the second polysilicon layer 215, and the third polysilicon layer Layer 230 may collectively be considered a polysilicon layer after diffusion.

The method 400 proceeds to step 410 as shown in FIG. 4, wherein the dielectric stack is replaced with a memory stack through the opening using a so-called "gate replacement process". As shown in Figure 2F, wet and/or dry etching is used to remove portions of the third polysilicon layer 230 and any remaining spacers 228 formed along the sidewalls of the slits 224 (shown in Figure 2E) , to expose the stacked sacrificial layer 212 of the dielectric stack 208 through the slit 224 . The etch process can be controlled (eg, by controlling the etch rate and/or time) such that the third polysilicon layer 230 will remain between the first polysilicon layer 207 and the second polysilicon layer 215 and with the channel structure 214 The semiconductor channel 218 contacts.

As shown in FIG. 2G, the memory stack 234 may be formed through a gate replacement process (ie, using the stacked conductive layer 236 in place of the stacked sacrificial layer 212). The memory stack 234 may thus include alternating stacked conductive layers 236 and stacked dielectric layers 210 on the second polysilicon layer 215 . In some embodiments, to form the memory stack 234, the stack sacrificial layer 212 is removed by applying an etchant through the slits 224 to form a plurality of lateral grooves. The stacked conductive layer 236 may then be deposited into the lateral grooves by depositing one or more conductive materials using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof). According to some embodiments, the channel structure 214 thus extends vertically through the memory stack 234 and the polysilicon layer including the first polysilicon layer 207, the second polysilicon layer 215 and the third polysilicon layer 230, at the The second stop layer 205 stops.

The method 400 proceeds to step 412 as shown in FIG. 4 where insulating structures are formed in the openings. In some embodiments, to form insulating structures, one or more dielectric materials are deposited into the openings to fill the openings. As shown in FIG. 2H, insulating structures 242 are formed in slits 224 (shown in FIG. 2G). One or more dielectric materials (eg, high-k dielectrics) (also serving as gate dielectric layer 238 ) may be deposited using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof) and silicon oxide as an insulator core 240 is deposited into the slits 224 to completely or partially fill the slits 224 with or without air gaps to form insulating structures 242 .

The method 400 proceeds to step 414 as shown in FIG. 4, wherein the substrate is removed from a second side opposite the first side of the substrate, which stops at the stop layer. The second side may be the backside of the substrate. As shown in Figure 2I, the substrate 202 (shown in Figure 2H) is removed from the backside. Although not shown in Figure 2I, it should be understood that the intermediate structure in Figure 2H may be flipped upside down to have the substrate 202 on top of the intermediate structure. In some embodiments, the substrate 202 is completely removed using CMP, grinding, wet etching, and/or dry etching until stopped by the first stop layer 203 (eg, a silicon nitride layer). In some embodiments, the substrate 202 (silicon substrate) is removed using silicon CMP, which automatically stops upon reaching the first stop layer 203 having a material other than silicon (ie, serving as a backside CMP stop layer). In some implementations, the substrate 202 (silicon substrate) is removed through TMAH using a wet etch that automatically stops upon reaching the first stop layer 203 having a material other than silicon (ie, serving as a backside etch stop layer). As described above, in some embodiments, the stop layer may include a single layer (eg, first stop layer 203 or second stop layer 205) that may function as a front side etch stop layer and a back side CMP/etch stop layer. However, the stop layer including the first stop layer 203 and/or the second stop layer 205 can ensure complete removal of the substrate 202 regardless of thickness uniformity after thinning.

The method 400 proceeds to step 416 as shown in FIG. 4, wherein a source contact structure extending vertically through the stop layer is formed in contact with the first polysilicon layer. As shown in FIG. 2J , the first stop layer 203 is removed using wet etching and/or dry etching to expose the second stop layer 205 . A dielectric material may be formed on the second stop layer 205 by depositing a dielectric material (eg, silicon oxide) on top of the second stop layer 205 using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof) Electrical layer 244 .

As shown in FIG. 2K , a backside source contact structure 246 is formed extending vertically through the dielectric layer 244 and the second stop layer 205 to contact the first polysilicon layer 207 . In some embodiments, the first The openings extending vertically into the first polysilicon layer 207 are etched through the dielectric layer 244 and the second stop layer 205 by using wet etching and/or dry etching (eg, RIE), and then through the sidewalls and An adhesive layer is formed over the bottom surface (eg, by depositing TiN using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof)) to form source contact structures 246 . The source can then be formed by forming a conductive layer over the adhesive layer (eg, by depositing a metal (eg, W) using one or more thin film deposition processes (eg, PVD, CVD, ALD, electroplating, electroless plating, or any combination thereof)) Contact structure 246 .

It should be understood that in some examples other than step 416 in FIG. 4, the stop layer may be removed after the substrate is removed such that the source contact structure extends perpendicularly through the dielectric layer but not the stop layer to A polysilicon layer contacts. In some embodiments, the stop layer is removed after the substrate is removed, a dielectric layer is formed in contact with the first polysilicon layer, and a source contact structure extending vertically through the dielectric layer is formed as in contact with the first polysilicon layer.

As shown in FIG. 2L , both the first stop layer 203 and the second stop layer 205 are removed using wet and/or dry etching to expose the first polysilicon layer 207 . The first polysilicon layer may be formed by depositing a dielectric material (eg, silicon oxide) on top of the first polysilicon layer 207 using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof) A dielectric layer 244 is formed on 207 .

As shown in FIG. 2L , a backside source contact structure 246 is formed extending vertically through the dielectric layer 244 to contact the first polysilicon layer 207 . In some embodiments, openings extending vertically into first polysilicon layer 207 through dielectric layer 244 are first etched using wet and/or dry etching (eg, RIE), and then through the sidewalls of the openings. The source contact structure 246 is formed by forming an adhesive layer (eg, by depositing TiN using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof)) over the bottom surface. The source can then be formed by forming a conductive layer over the adhesive layer (eg, by depositing a metal (eg, W) using one or more thin film deposition processes (eg, PVD, CVD, ALD, electroplating, electroless plating, or any combination thereof)) Contact structure 246 .

Although now shown, it should be understood that in some examples, one or more conductive materials may be deposited in the openings by using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof) prior to removal of the substrate to form front-side source contact structures in openings such as slits 224 . Front-side source contact structures may replace back-side source contact structures (eg, source contact structures 246 ) and front-side insulating structures (eg, insulating structures 242 ).

3A-3J illustrate a fabrication process for forming another exemplary 3D memory device in accordance with some embodiments of this disclosure. 5 illustrates a flowchart of a method 500 for forming another exemplary 3D memory device in accordance with some embodiments of this disclosure. Examples of 3D memory devices depicted in Figures 3A-3J and Figure 5 include 3D memory device 101a depicted in Figure 1C. 3A-3J and FIG. 5 will be described together. It should be understood that the steps shown in method 500 are not exclusive, and that other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed concurrently or in a different order than that shown in FIG. 5 .

Referring to FIG. 5, method 500 begins at step 502 in which a stop layer, a buffer layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric layer are sequentially formed at a first side of the substrate. Electric stack. The substrate may be a silicon substrate or carrier substrate made of any suitable material such as glass, sapphire, plastic (to name a few) to reduce the cost of the substrate. The first side may be the front side of the substrate on which the semiconductor elements are formed. In some embodiments, the stop layer includes silicon nitride, and the buffer layer includes silicon oxide. In some embodiments, to form the sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed. The first sacrificial layer may include silicon oxynitride, the second sacrificial layer may include polysilicon, and the third sacrificial layer may include silicon oxynitride. The dielectric stack may include a plurality of interleaved stacked sacrificial layers and stacked dielectric layers.

As shown in FIG. 3A , the stop layer 303 , the buffer layer 305 , the first polysilicon layer 307 , the first sacrificial layer 309 , the second sacrificial layer 311 , the third sacrificial layer 313 and the second polysilicon layer 315 are formed on the substrate 302 formed successively on the front. Substrate 302 can be made of any suitable material (eg, glass, sapphire, plastic (just to name a few). Several examples)) made of silicon substrates or carrier substrates. In some embodiments, stop layer 303 and buffer layer 305 include silicon nitride and silicon oxide, respectively. As described in detail below, stop layer 303 may serve as a stop layer when substrate 302 is removed from the backside, and thus may comprise any other suitable material in addition to the material of substrate 302 . It should be understood that in some embodiments, a pad oxide layer (eg, a silicon oxide layer) may be formed between the substrate 302 and the stop layer 303 to relieve stress therebetween.

The first sacrificial layer 309, the second sacrificial layer 311, and the third sacrificial layer 313 may be collectively referred to herein as sacrificial layers. In some embodiments, the first sacrificial layer 309, the second sacrificial layer 311, and the third sacrificial layer 313 include silicon oxynitride, polysilicon, and silicon oxynitride, respectively. As described in more detail below, the third sacrificial layer 313 can act as a stop layer when etching the slit openings from the front side, and can be selectively removed later, and thus can include relative to polysilicon (in the third sacrificial layer The material of the second polysilicon layer 315 on 313) is any other suitable material with a high etch selectivity (eg, greater than about 5). The second sacrificial layer 311 may be selectively removed later, and thus may comprise any other suitable material with a high etch selectivity (eg, greater than about 5) relative to a dielectric (eg, polysilicon or carbon). The first sacrificial layer 309 can act as a stop layer when etching the second sacrificial layer 311 and can be selectively removed later, and thus can include relative to polysilicon (second sacrificial layer 311 and first polysilicon layer 307) any other suitable material with high etch selectivity (eg, greater than about 5).

stop layer 303, buffer layer 305, first polysilicon layer 307, first sacrificial layer 309, second sacrificial layer 311, third sacrificial layer 313, and second polysilicon layer 315 (or any other in between) layer) can be deposited in multiple loops in this order by using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless deposition, any other suitable deposition process, or any combination thereof) to deposit the corresponding materials are formed successively. In some embodiments, at least one of the first polysilicon layer 307 and the second polysilicon layer 315 is doped with an N-type dopant, such as P, As, or Sb. In one example, at least one of the first polysilicon layer 307 and the second polysilicon layer 315 may be doped using an ion implantation process after the polysilicon material is deposited. In another example, when polysilicon is deposited to form the first polysilicon layer 307 and at least one of the second polysilicon layer 315, in-situ doping of N-type dopants may be performed. It should be understood that in some examples, neither the first polysilicon layer 307 nor the second polysilicon layer 315 are doped with N-type dopants at this stage.

As shown in FIG. 3A , a plurality of pairs of a first dielectric layer (referred to as a “stacked sacrificial layer 312 ”) and a second dielectric layer (referred to as a “stacked dielectric layer”) are formed on the second polysilicon layer 315 The dielectric stack 308 of the dielectric layer 310"). According to some embodiments, the dielectric stack 308 includes a stacked sacrificial layer 312 and a stacked dielectric layer 310 that are staggered. Stacked dielectric layers 310 and stacked sacrificial layers 312 may be alternately deposited on second polysilicon layer 315 to form dielectric stack 308 . In some embodiments, each stacked dielectric layer 310 includes a layer of silicon oxide, and each stacked sacrificial layer 312 includes a layer of silicon nitride. Dielectric stack 308 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, a pad oxide layer (eg, a silicon oxide layer not shown) is formed between the second polysilicon layer 315 and the dielectric stack 308 .

The method 500 proceeds to step 504 as shown in FIG. 5 in which a channel structure is formed extending vertically into the buffer layer through the dielectric stack, the second polysilicon layer, the sacrificial layer and the first polysilicon layer . In some embodiments, to form the channel structure, a channel hole is formed extending vertically into the buffer layer through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, and along the The sidewalls of the via holes successively form memory films and semiconductor vias. In some embodiments, a channel plug is formed over and in contact with the semiconductor channel.

As shown in FIG. 3A, via holes extend vertically into buffer layer 305 through dielectric stack 308, second polysilicon layer 315, sacrificial layers 313, 311 and 309, and first polysilicon layer 307 Open your mouth. In some embodiments, multiple openings are formed such that each opening becomes a location for growing individual channel structures 314 in a later process. In some embodiments, the fabrication process used to form the channel holes of the channel structure 314 includes a wet etch and/or dry etch process (eg, DRIE). The etching of the via holes may not stop at the bottom surface of the first polysilicon layer 307 and further at various depths (ie, gouge variations) The ground extends into the buffer layer 305 . That is, the buffer layer 305 can accommodate gouge variations between via holes to ensure that each via hole extends through the first polysilicon layer 307 .

As shown in FIG. 3A, a memory film 316 (including a barrier layer, a storage layer, and a tunneling layer) and a semiconductor channel 318 are sequentially formed in this order along the sidewalls and bottom surfaces of the channel holes. In some embodiments, the memory film 316 is first deposited along the sidewalls and bottom surfaces of the via holes, and the semiconductor channel 318 is then deposited over the memory film 316 . The barrier, storage, and tunneling layers may then be deposited in that order using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) to form memory film 316 . The semiconductor channel may then be formed by depositing a semiconductor material (eg, polysilicon) over the tunneling layer of the memory film 316 using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) 318. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are subsequently deposited to form the memory film 316 and the semiconductor channel 318 .

As shown in FIG. 3A, an overlying layer 320 is formed in the via hole and over the semiconductor via 318 to fully or partially fill the via hole (eg, without or with air gaps). Overlay 320 may be formed by depositing a dielectric material (eg, silicon oxide) using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). A channel plug 322 may then be formed in the upper portion of the channel hole. In some embodiments, portions of the memory film 316, semiconductor channels 318, and overlying layer 320 on the top surface of the dielectric stack 308 are removed and subjected to a CMP, wet etch, and/or dry etch process is flattened. Recesses may then be formed in the upper portion of the via hole by wet etching and/or dry etching portions of the semiconductor channel 318 and overlying layer 320 in the upper portion of the via hole. The channel plug 322 may then be formed by depositing a semiconductor material (eg, polysilicon) into the recess through one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof). Channel structure 314 is thus formed into buffer layer 305 through dielectric stack 308 , second polysilicon layer 315 , sacrificial layers 313 , 311 and 309 and first polysilicon layer 307 according to some embodiments.

The method 500 proceeds to step 506 as shown in FIG. 5, wherein an opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. In some embodiments, an opening is formed that stops at the third sacrificial layer.

As shown in FIG. 3B, slit 324 is an opening formed vertically extending through dielectric stack 308 and second polysilicon layer 315, stopping at third sacrificial layer 313, exposing the third sacrificial layer Section 313. In some embodiments, the fabrication process used to form the slits 324 includes a wet etch and/or dry etch process (eg, DRIE). In some embodiments, the stacked dielectric layer 310 and the stacked sacrificial layer 312 of the dielectric stack 308 are first etched. Etching of the dielectric stack 308 may not stop at the top surface of the second polysilicon layer 315 and extend further into the second polysilicon layer 315 at various depths (ie, gouge variations). Therefore, a second etch process (sometimes referred to as a post-etch process) may be performed to etch the second polysilicon layer 315 until the third sacrificial layer 313 (eg, silicon oxynitride layer) and the second polysilicon layer are The etch selectivity between materials 315 (eg, polysilicon) is stopped by a third sacrificial layer 313 (eg, a silicon oxynitride layer).

The method 500 proceeds to step 508 as shown in FIG. 5, wherein the sacrificial layer is replaced by a third polysilicon layer between the first and second polysilicon layers through the opening. In some embodiments, to replace the sacrificial layer with the third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first and second polysilicon layers, the memory film is removed through the opening to expose portions of the semiconductor channel along the sidewalls of the channel hole, and polysilicon is deposited into the cavity through the opening to form a third polysilicon layer. In some embodiments, at least one of the first, second, and third polysilicon layers is doped with an N-type dopant. N-type dopants may be diffused in the first, second and third polysilicon layers.

Spacers 328 are formed along the sidewalls of the slits 324 by depositing one or more dielectrics (eg, high-k dielectrics) along the sidewalls of the slits 324 as shown in FIG. 2C . A wet etch and/or dry etch process may be used to open the bottom surface of the spacer 328 (and the portion of the third sacrificial layer 313 in the slit 324, if still remaining) to expose the portion of the second sacrificial layer 311 (in the slit 324). 3B, eg a polysilicon layer). In a In some embodiments, the sacrificial layer 311 is then removed by wet etching and/or dry etching to form the cavity 326 . In some embodiments, the second sacrificial layer 311 includes polysilicon, the spacer 328 includes a high-k dielectric, the first sacrificial layer 309 and the third sacrificial layer 313 each include silicon oxynitride, and the second sacrificial layer 311 penetrates through Slot 324 is etched by applying TMAH etchant, which is stopped by high-k dielectric spacer 328 and first sacrificial layer 309 and third sacrificial layer 313 of silicon oxynitride. That is, according to some embodiments, the removal of the second sacrificial layer 311 does not affect the dielectric stack 308 and the first polysilicon protected by the spacer 328 and the first sacrificial layer 309 and the third sacrificial layer 313, respectively layer 307 and third polysilicon layer 315.

As shown in FIG. 3D , the portion of the memory film 316 exposed in the cavity 326 is removed to expose the portion of the semiconductor channel 318 along the sidewalls of the channel structure 314 . In some embodiments, the barrier layer (eg, including silicon oxide) is etched by applying an etchant (eg, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) through slit 324 and cavity 326 ), the storage layer (for example comprising silicon nitride) and the tunneling layer (for example comprising silicon oxide). Etching can be stopped by spacer 328 and semiconductor channel 318 . That is, according to some embodiments, removal of the exposed portion of memory film 316 in cavity 326 does not affect dielectric stack 308 (protected by spacer 328 ) and semiconductor channel 318 comprising polysilicon and by semiconductor Overlay 320 surrounded by channel 318 . In some embodiments, the first sacrificial layer 309 and the third sacrificial layer 313 (including silicon oxynitride) are also removed by the same etching process.

As shown in FIG. 3E , a third polysilicon layer 330 is formed between the first polysilicon layer 307 and the second polysilicon layer 315 . In some embodiments, the third film is formed by depositing polysilicon through slit 324 into cavity 326 (shown in FIG. 3D ) using one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) Polysilicon layer 330 . In some embodiments, when the polysilicon is deposited to form the third polysilicon layer 330, in-situ doping of an N-type dopant (eg, P, As, or Sb) is performed. The third polysilicon layer 330 may fill the cavity 326 to contact the exposed portion of the semiconductor channel 318 of the channel structure 314 . It should be understood that the third polysilicon layer 330 may be doped or undoped, depending on whether at least one of the first polysilicon layer 307 and the second polysilicon layer 315 is doped with N-type doping dopant, since at least one of the first polysilicon layer 307, the second polysilicon layer 315, and the third polysilicon layer 330 may need to be doped with an N-type dopant. In some embodiments, the N-type dopant in at least one of the first polysilicon layer 307, the second polysilicon layer 315, and the third polysilicon layer 330 is diffused in the first polysilicon layer 307. In the second polysilicon layer 315 and the third polysilicon layer 330, a thermal diffusion process (eg, annealing) is used to A uniform doping concentration distribution in the vertical direction is realized in the silicon layer 330 . For example, the doping concentration may be between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 after diffusion. As described above, the interfaces between the first polysilicon layer 307, the second polysilicon layer 315, and the third polysilicon layer 330 may become indistinguishable because the first polysilicon layer 307, the second polysilicon layer 307, the second polysilicon layer Each of the crystalline silicon layer 315 and the third polycrystalline silicon layer 330 includes the same polycrystalline silicon material with nominally the same doping concentration. Therefore, the first polysilicon layer 307, the second polysilicon layer 315, and the third polysilicon layer 330 may be collectively regarded as polysilicon layers after diffusion.

The method 500 proceeds to step 510 as shown in FIG. 5, where the dielectric stack is replaced with a memory stack through the opening using a so-called "gate replacement process". As shown in Figure 3F, wet and/or dry etching is used to remove portions of the third polysilicon layer 330 and any remaining spacers 328 formed along the sidewalls of the slits 324 (shown in Figure 3E) , to expose the stacked sacrificial layer 312 of the dielectric stack 308 through the slit 324 . The etch process can be controlled (eg, by controlling the etch rate and/or time) such that the third polysilicon layer 330 will remain between the first polysilicon layer 307 and the second polysilicon layer 315 and with the channel structure 314 The semiconductor channel 318 contacts.

As shown in FIG. 3G, the memory stack 334 may be formed through a gate replacement process (ie, using a stacked conductive layer 336 in place of the stacked sacrificial layer 312). The memory stack 334 may thus include staggered stacked conductive layers 336 and stacked dielectric layers 310 on the second polysilicon layer 315 . In some embodiments, to form memory stack 334, stack sacrificial layer 312 is removed by applying an etchant through slit 324 to form a plurality of lateral grooves. A stacked conductive layer 336 may then be deposited into the lateral grooves by depositing one or more conductive materials using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof). According to some embodiments, the channel structure 314 thus passes through the memory stack 334 and includes the first multiple The polysilicon layers of the crystalline silicon layer 307 , the second polysilicon layer 315 and the third polysilicon layer 330 extend vertically into the buffer layer 305 .

The method 500 proceeds to step 512 as shown in FIG. 5, wherein insulating structures are formed in the openings. In some embodiments, to form insulating structures, one or more dielectric materials are deposited into the openings to fill the openings. As shown in FIG. 3H, insulating structures 342 are formed in slits 324 (shown in FIG. 3G). One or more dielectric materials (eg, a high-k dielectric (also serving as gate dielectric layer 338 )) and as a Silicon oxide of insulator core 340 is deposited into slit 324 to completely or partially fill slit 324 with or without air gaps to form insulating structure 342 .

The method 500 proceeds to step 514 as shown in FIG. 5, wherein the substrate is removed from a second side opposite the first side of the substrate, which stops at the stop layer. The second side may be the backside of the substrate. As shown in Figure 3I, the substrate 302 (shown in Figure 3H) is removed from the backside. Although not shown in Figure 3I, it should be understood that the intermediate structure in Figure 3H could be flipped upside down to have the substrate 302 on top of the intermediate structure. In some embodiments, the substrate 302 is completely removed using CMP, grinding, wet etching, and/or dry etching until stopped by a stop layer 303 (eg, a silicon nitride layer). In some implementations, silicon CMP is used to remove substrate 302 (silicon substrate), which automatically stops upon reaching stop layer 303 having a material other than silicon (ie, serving as a backside CMP stop layer). In some implementations, substrate 302 (silicon substrate) is removed through TMAH using a wet etch, which automatically stops upon reaching stop layer 303 having a material other than silicon (ie, serving as a backside etch stop). The stop layer 303 can ensure complete removal of the substrate 302 regardless of thickness uniformity after thinning.

The method 500 proceeds to step 516 as shown in FIG. 5, where the stop layer is removed and a dielectric layer is formed in contact with the first polysilicon layer. As shown in FIG. 3J, the stop layer 303 is removed to expose the buffer layer 305 using wet etching and/or dry etching. Dielectric materials such as silicon oxide can be deposited on the buffer layer by using one or more thin film deposition processes such as PVD, CVD, ALD, or any combination thereof On top of the buffer layer 305, a dielectric layer 350 is formed. In some embodiments where buffer layer 305 includes the same material as dielectric layer 350 (eg, silicon oxide), buffer layer 305 becomes the portion of dielectric layer 350 that is in contact with first polysilicon layer 307 . In some embodiments, no additional dielectric layers are formed, and the buffer layer 305 itself becomes the dielectric layer 350 in contact with the first polysilicon layer 307 .

The method 500 proceeds to step 518 as shown in FIG. 5, wherein a source contact structure extending vertically through the dielectric layer is formed in contact with the first polysilicon layer. As shown in FIG. 3J , a backside source contact structure 346 is formed extending vertically through the dielectric layer 350 to contact the first polysilicon layer 307 . In some embodiments, openings extending vertically into the first polysilicon layer 307 are etched through the dielectric layer 350 by first etching through the dielectric layer 350 using wet and/or dry etching (eg, RIE), and then through the sidewalls of the openings. The source contact structure 346 is formed by forming an adhesive layer (eg, by depositing TiN using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof)) over the bottom surface and the bottom surface. The source can then be formed by forming a conductive layer over the adhesive layer (eg, by depositing a metal (eg, W) using one or more thin film deposition processes (eg, PVD, CVD, ALD, electroplating, electroless plating, or any combination thereof)) Contact structure 346 .

Although now shown, it should be understood that in some examples, one or more conductive materials may be deposited in the openings by using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof) prior to removal of the substrate to form front-side source contact structures in openings such as slits 324 . Front-side source contact structures may replace back-side source contact structures (eg, source contact structures 346 ) and front-side insulating structures (eg, insulating structures 342 ).

According to one aspect of this disclosure, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer. An opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. through the opening The sacrificial layer is replaced with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

In some embodiments, insulating structures are formed in the openings prior to removing the substrate.

In some embodiments, a memory stack is used instead of a dielectric stack through the opening.

In some embodiments, after removing the substrate, a source contact structure extending vertically through the stop layer is formed to contact the first polysilicon layer.

In some embodiments, after removing the substrate, removing the stop layer, forming a dielectric layer in contact with the first polysilicon layer, and forming a source contact structure extending vertically through the dielectric layer to in contact with the first polysilicon layer.

In some embodiments, to form the stop layer, the first stop layer and the second stop layer are sequentially formed. In some embodiments, the first stop layer includes silicon nitride, and the second stop layer includes a high-k dielectric. In some embodiments, forming the channel structure stops at the second stop layer, and removing the substrate stops at the first stop layer.

In some embodiments, to form the sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed. In some embodiments, the first sacrificial layer includes silicon oxynitride, the second sacrificial layer includes polysilicon, and the third sacrificial layer includes silicon oxynitride. In some embodiments, forming the opening stops at the third sacrificial layer.

In some embodiments, to form the channel structure, a via hole is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, and along sidewalls of the via hole A memory film and a semiconductor channel are successively formed.

In some embodiments, to replace the sacrificial layer with the third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first polysilicon layer and the second polysilicon layer, and the sacrificial layer is removed through the opening to form a cavity between the first polysilicon layer and the second polysilicon layer. Portions of the memory film are removed to expose portions of the semiconductor channels along the sidewalls of the via holes, and polysilicon is deposited into the cavity through the openings to form a third polysilicon layer.

In some implementations, at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant. An N-type dopant is diffused in the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer.

In some embodiments, source contact structures are formed in the openings prior to removing the substrate.

According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A stop layer, a buffer layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically into the buffer layer through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer. An opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose portions of the sacrificial layer. The sacrificial layer is replaced by a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

In some embodiments, insulating structures are formed in the openings prior to removing the substrate.

In some embodiments, a memory stack is used instead of a dielectric stack through the opening.

In some embodiments, after removing the substrate, removing the stop layer, forming a dielectric layer in contact with the first polysilicon layer, and forming a source contact structure extending vertically through the dielectric layer to in contact with the first polysilicon layer.

In some embodiments, the first stop layer includes silicon nitride, and the second stop layer includes a high-k dielectric.

In some embodiments, to form the sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed. In some embodiments, the first sacrificial layer includes silicon oxynitride, the second sacrificial layer includes polysilicon, and the third sacrificial layer includes silicon oxynitride. In some embodiments, forming the opening stops at the third sacrificial layer.

In some embodiments, to form the channel structure, a channel hole is formed extending vertically into the buffer layer through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, and along the A memory film and a semiconductor channel are successively formed along the sidewalls of the via hole.

In some embodiments, to replace the sacrificial layer with the third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first polysilicon layer and the second polysilicon layer, and the sacrificial layer is removed through the opening to form a cavity between the first polysilicon layer and the second polysilicon layer. A portion of the memory film is removed to expose portions of the semiconductor channel along the sidewalls of the via hole, and polysilicon is deposited into the cavity through the opening to form a third polysilicon layer.

In some implementations, at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant. An N-type dopant is diffused in the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer.

According to yet another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at the first side of the substrate. A channel structure is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer. The sacrificial layer is replaced with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer. At least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant. An N-type dopant is diffused in the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer. The substrate is removed from a second side opposite the first side of the substrate, stopping at the stop layer.

In some embodiments, before replacing the sacrificial layer with the third polysilicon layer, an opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose the sacrificial layer part so that the sacrificial layer is replaced by a third polysilicon layer through the opening.

In some embodiments, insulating structures are formed in the openings prior to removing the substrate.

In some embodiments, a memory stack is used instead of a dielectric stack through the opening.

In some embodiments, after removing the substrate, a source contact structure extending vertically through the stop layer is formed to contact the first polysilicon layer.

In some embodiments, after removing the substrate, the stop layer is removed to form a A dielectric layer in contact with the crystalline silicon layer, and a source contact structure extending vertically through the dielectric layer is formed to be in contact with the first polycrystalline silicon layer.

In some embodiments, to form the stop layer, the first stop layer and the second stop layer are sequentially formed. In some embodiments, the first stop layer includes silicon nitride, and the second stop layer includes a high-k dielectric. In some embodiments, forming the channel structure stops at the second stop layer, and removing the substrate stops at the first stop layer.

In some embodiments, to form the sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed. In some embodiments, the first sacrificial layer includes silicon oxynitride, the second sacrificial layer includes polysilicon, and the third sacrificial layer includes silicon oxynitride. In some embodiments, forming the opening stops at the third sacrificial layer.

In some embodiments, to form the channel structure, a via hole is formed extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, and along sidewalls of the via hole A memory film and a semiconductor channel are successively formed.

In some embodiments, to replace the sacrificial layer with the third polysilicon layer, the sacrificial layer is removed through the opening to form a cavity between the first polysilicon layer and the second polysilicon layer, through the opening Portions of the memory film are removed to expose portions of the semiconductor vias along the sidewalls of the via holes, and polysilicon is deposited into the cavity through the openings to form a third polysilicon layer.

The foregoing descriptions of specific embodiments will thus reveal that those skilled in the art, by applying knowledge within the skill in the art, can readily modify and/or alter the invention of such specific embodiments for various applications without undue experimentation. general nature without departing from the general concept of the present disclosure. Therefore, such changes and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not limitation so that the terminology or phraseology of this specification should be interpreted by a skilled artisan in accordance with the teaching and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of the specified functions and relationships thereof. The boundaries of these functional building blocks are arbitrarily defined herein for ease of description. Alternate boundaries may be defined so long as the specified functions and relationships are properly performed.

The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the disclosure and the scope of the appended claims in any way.

The breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

202: Substrate

203: First stop layer

205: Second stop layer

207: First polysilicon layer

208: Dielectric Stack

209: First sacrificial layer

211: Second sacrificial layer

212: Stacked Sacrificial Layers

213: The third sacrificial layer

214: Channel Structure

215: Second polysilicon layer

216: Memory Film

218: Semiconductor channel

220: Overlay

222: Channel Plug

x,y: axis

Claims (20)

A method for forming a three-dimensional (3D) memory device comprising sequentially forming a stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack at a first side of a substrate , wherein forming the stop layer comprises sequentially forming a first stop layer and a second stop layer, and the first stop layer and the second stop layer comprise different materials; forming through the dielectric stack , the second polysilicon layer, the sacrificial layer and the first polysilicon layer extending vertically, stopping at the second stop layer, a channel structure; forming through the dielectric stack an opening extending perpendicular to the second polysilicon layer and stopping at the sacrificial layer to expose portions of the sacrificial layer; utilizing the first polysilicon layer and the sacrificial layer through the opening a third polysilicon layer between second polysilicon layers replaces the sacrificial layer; and removing the substrate from a second side opposite the first side of the substrate, at the first stop stop at the layer. The method of claim 1, further comprising: forming an insulating structure in the opening before removing the substrate. The method of claim 1, further comprising forming a source contact structure extending vertically through the stop layer to contact the first polysilicon layer after removing the substrate. The method of claim 1, further comprising: after removing the substrate: removing the stop layer; forming a dielectric layer in contact with the first polysilicon layer; and forming a dielectric layer through the a source contact structure with a dielectric layer extending vertically to connect with the first polysilicon layer contact. The method of claim 1, wherein the second stop layer comprises a material having an etch selectivity with respect to polysilicon. The method of claim 5, wherein the first stop layer comprises silicon nitride and the second stop layer comprises a high-k (high-k) dielectric. The method of claim 1, wherein forming the sacrificial layer includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer; and forming the opening stops at the third sacrificial layer. The method of claim 7, wherein the first sacrificial layer comprises silicon oxynitride, the second sacrificial layer comprises polysilicon, and the third sacrificial layer comprises silicon oxynitride. The method of claim 1 wherein forming the channel structure comprises forming through the dielectric stack, the second polysilicon layer, the sacrificial layer and the first polysilicon layer vertically extending via holes; and sequentially forming memory films and semiconductor vias along sidewalls of the via holes. The method of claim 9, wherein replacing the sacrificial layer with the third polysilicon layer comprises removing the sacrificial layer through the opening to form on the first polysilicon layer and the cavity between the second polysilicon layer; removing portions of the memory film through the openings to expose portions of the semiconductor channels along the sidewalls of the via holes; and depositing polysilicon into the cavity through the openings, to form the third polysilicon layer. The method of claim 1, wherein at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant , and the method further includes: diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer. A method for forming a three-dimensional (3D) memory device comprising sequentially forming a stop layer, a buffer layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric at a first side of a substrate a dielectric stack, wherein the stop layer and the buffer layer comprise different materials; formed through the dielectric stack, the second polysilicon layer, the sacrificial layer and the first poly A silicon layer extends vertically into a channel structure within the buffer layer; an opening is formed extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose a portion of the sacrificial layer; replacing the sacrificial layer with a third polysilicon layer between the first polysilicon layer and the second polysilicon layer through the opening; and A second side of the substrate opposite the first side removes the substrate, stopping at the stop layer. The method of claim 12, further comprising forming an insulating structure in the opening before removing the substrate. The method of claim 12, further comprising: after removing the substrate: removing the stop layer; forming a dielectric layer in contact with the first polysilicon layer; and forming through the A source contact structure with a dielectric layer extending vertically to contact the first polysilicon layer. The method of claim 12, wherein the stop layer comprises silicon nitride and the buffer layer comprises silicon oxide. The method of claim 12, wherein forming the sacrificial layer comprises sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer; and forming the opening stops at the third sacrificial layer. The method of claim 12, wherein forming the channel structure comprises forming through the dielectric stack, the second polysilicon layer, the sacrificial layer and the first polysilicon The layer extends vertically to a via hole in the buffer layer; and a memory film and a semiconductor channel are sequentially formed along sidewalls of the via hole. The method of claim 17, wherein replacing the sacrificial layer with the third polysilicon layer comprises removing the sacrificial layer through the opening to form on the first polysilicon layer a cavity between the second polysilicon layer and the second polysilicon layer; removing portions of the memory film through the openings to expose portions of the semiconductor vias along the sidewalls of the via holes; and Polysilicon is deposited into the cavity through the opening to form the third polysilicon layer. The method of claim 12, wherein at least one of the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer is doped with an N-type dopant , and the method further includes: diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer and the third polysilicon layer. A method for forming a three-dimensional (3D) memory device comprising sequentially forming a stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack at a first side of a substrate , wherein forming the stop layer comprises sequentially forming a first stop layer and a second stop layer, and the first stop layer and the second stop layer comprise different materials; forming through the dielectric stack , the second polysilicon layer, the sacrificial layer and the first polysilicon layer extend vertically and stop at the second stop layer of the channel structure; using the first polysilicon layer A third polysilicon layer between the second polysilicon layer and the sacrificial layer replaces the sacrificial layer, wherein the first polysilicon layer, the second polysilicon layer and the third polysilicon layer at least one of the silicon layers is doped with an N-type dopant; diffusing the N-type dopant in the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer a dopant; and removing the substrate from a second side opposite the first side of the substrate, stopping at the first stop layer.

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