TWI746228B - Three-dimensional memory devices and method for forming the same - Google Patents

Abstract

The embodiment of a 3D memory device and method for forming the same is provided in the application. In one embodiment, the 3D memory device includes an insulating layer, a semiconductor layer, storage layer stack with alternating conductive layers and dielectric layers, source contacts vertically extending through the insulating layer from the side opposite to the semiconductor layer and contacting the semiconductor layer, and a channel structure vertically extending into the insulating layer or source contact through the storage layer stack and the semiconductor layer.

Description

Three-dimensional memory element and method for forming three-dimensional memory element

The embodiment of the content of this case relates to a three-dimensional (3D) memory device and a manufacturing method thereof.

By improving the process technology, circuit design, programming algorithm and manufacturing process, the planar storage unit is reduced to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. As a result, the storage density for the planar storage unit approaches the upper limit.

The 3D memory architecture can solve the density limitation in the planar storage unit. The 3D memory architecture includes a memory array and peripheral devices used to control signals to and from the memory array.

Disclosed herein are embodiments of 3D memory devices and methods for manufacturing 3D memory devices.

In one example, a 3D memory device includes an insulating layer, a semiconductor layer, a storage stack layer composed of interlaced conductive layers and dielectric layers, and a source contact structure. From the opposite side of the insulating layer to the semiconductor layer It extends vertically through the insulating layer to contact the semiconductor layer, and a channel structure that extends vertically through the storage stack layer and the semiconductor layer into the insulating layer or the source contact structure.

In another example, a 3D memory device includes an insulating layer, a semiconductor layer, a storage stack layer composed of interlaced conductive layers and dielectric layers, and a channel structure extending vertically through the storage stack layer and the semiconductor layer . The channel structure includes a memory film and a semiconductor channel, and the semiconductor channel is in contact with a sublayer of the semiconductor layer along a part of the sidewall of the channel structure. The 3D memory device further includes an insulating structure that extends vertically through the storage stack layer into the semiconductor layer, wherein the bottom surface of the insulating structure is flush with the top surface of the insulating layer.

In yet another example, it discloses a method for forming a 3D memory device. A stop layer, a first insulating layer, a sacrificial layer, a first semiconductor layer, and a dielectric stack layer are sequentially formed on the first side of the substrate. A channel structure is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer. An opening is formed that extends vertically through the dielectric stack layer and the first semiconductor layer and stops at the sacrificial layer to expose a portion of the sacrificial layer. Through the opening, the sacrificial layer is replaced with a second semiconductor layer between the first semiconductor layer and the first insulating layer. The substrate is removed from the second side opposite to the first side of the substrate and stopped at the stop layer.

In yet another example, it discloses a method for forming a 3D memory device. A first insulating layer, a sacrificial layer, a first semiconductor layer, and a dielectric stack layer are sequentially formed on the substrate. A channel structure is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer. The sacrificial layer is replaced with a second semiconductor layer between the first semiconductor layer and the first insulating layer. At least one of the first semiconductor layer and the second semiconductor layer is doped with N-type dopants. N-type dopants diffuse in the first semiconductor layer and the second semiconductor layer.

Although specific configurations and settings are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and settings can be used without departing from the spirit and scope of the disclosure of this case. It will be obvious to those skilled in the related art that the disclosure of this case can also be used in various other applications.

It should be noted that references to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. in the specification indicate that the described embodiment may include specific features, structures, or characteristics. However, each embodiment may not necessarily include the specific feature, structure or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether it is explicitly described or not, it is within the knowledge of those skilled in the relevant art to implement such a feature, structure, or characteristic in combination with other embodiments.

Generally, terms can be understood at least partially from the usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a feature, structure, or combination of characteristics in the plural. . Similarly, depending at least in part on the context, terms such as "a", "an" or "the" can also be understood as conveying singular usage or conveying plural usage. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the existence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

It should be easy to understand that the meaning of "on", "above" and "above" in the disclosure of this case should be interpreted in the broadest way, so that "on" Not only does it mean "directly on something", but also includes "on something" with the meaning of intermediate features or layers in between, and "above" or "above" not only means The meaning of “above something” or “above something” and can include the meaning of “above something” or “above On something).

In addition, for the convenience of description, spatial relative terms such as "below", "below", "lower", "above", "upper", etc. can be used in this article to describe such as The relationship between one element or feature shown in the figure and another element or feature. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used herein can also be interpreted accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire lower layer or the overlying structure, or may have a range smaller than the range of the lower layer or the overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure, which has a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnection layer may include one or more conductor and contact layers (where interconnection lines and/or vertical interconnection via contacts are formed) and one or more dielectric layers.

As used herein, the term "nominal/nominal" refers to the expected value or target value, and higher and/or lower than expected value of a characteristic or parameter set during the design phase of a product or process for a component or process operation The range of values. The value range can be caused by slight changes in manufacturing processes or tolerances. As used herein, the term "about" indicates a given amount of value that can vary based on the specific technology node associated with the subject semiconductor element. Based on a specific technical node, the term "approximately" may indicate a value of a given amount that varies within, for example, 10-30% of the value (for example, ±10%, ±20%, or ±30% of the value).

As used herein, the term "3D memory device" refers to a string of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) that have vertical orientation on a laterally oriented substrate. The semiconductor device makes the memory string extend in the vertical direction relative to the substrate. As used herein, the term "vertical/perpendicularly" means nominally perpendicular to the lateral surface of the substrate.

In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of the channel structure, for example, it is called sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plug (such as bottom SEG) formed at the lower end of the channel structure, forming the sidewall SEG can avoid etching the memory film and Semiconductor channels, thereby increasing the operating space of the process, especially when using advanced technology to manufacture 3D NAND memory devices (for example, a multi-layer structure with 96 or more levels). In addition, the sidewall SEG structure can be combined with the backside process to form a source contact structure from the backside of the substrate to avoid leakage current and parasitic capacitance between the front source contact structure and the word line and increase the effective device area.

Since the backside process needs to thin the substrate, this will face challenges such as difficulty in controlling the thickness uniformity at the wafer level during the thinning process. These challenges limit the yield of 3D NAND memory devices with sidewall SEG structures and backside processes.

In addition, the existing 3D memory device usually includes a plurality of memory blocks separated by a parallel slot structure (for example, a gate line slot (GLS)). For example, as shown in FIG. 1, the 3D memory device 100 includes a plurality of block storage areas 101 separated by gap structures 122 extending laterally in the x direction (for example, the character line direction). In each block storage area 101, a slit structure 122 with "H" cuts (not shown) also divides the block storage area 101 into a plurality of memory fingers 103, where each finger storage area includes An array of channel structures 112. It should be noted that the x and y axes are included in Figure 1 to illustrate two orthogonal directions in the wafer plane. The x direction is the word line direction, and the y direction is the bit line direction. Adjacent block storage areas 101 arranged in the y direction (for example, the bit line direction) are separated by respective slit structures 122 that extend laterally in the x direction (for example, the character line direction).

When manufacturing a 3D memory device, the shape and size of the slot structure 122 may be susceptible to fluctuations, thereby potentially affecting the performance of the final device. The gap structure 122 filled with conductive material (for example, tungsten (W)) may also introduce significant stress and cause the wafer to bend or twist. The long continuous gap opening of the gap structure 122 between the block storage areas 101 before being filled with the filling material may also cause the adjacent stacked structure to collapse during the manufacturing process, thereby reducing the yield. Therefore, in some 3D memory devices, a support structure 123 (for example, a dummy channel structure) filled with an insulating material (for example, silicon dioxide) that is different from the material filling the gap structure 122 is formed in the gap structure 122, This makes the 3D memory device less likely to be deformed or damaged during the manufacturing process, and adjust the stress of the 3D memory device after manufacturing.

However, when the support structure 123 is formed in the slot structure 122, the overlap between the support structure 123 and the slot structure 122 (it is necessary to ensure the overlap between the support structure and the slot structure 122) will be due to the etching and the etching used to form the insulating structure. The planing process becomes a weakness. For example, as shown in Figure 2, the intermediate structure during the manufacturing of the 3D memory device 100 includes a substrate 102 and a semiconductor layer 104 with the following three sub-layers: the top semiconductor layer 104-1, which will be replaced in the final product The sacrificial layer 104-2 of the other semiconductor layer, and the bottom semiconductor layer 104-3. Fig. 2 shows a cross-section of the overlapping portion of the slot structure 122 and the support structure 123 in Fig. 1 in the y direction (for example, the bit line direction). Both the slit structure 122 and the support structure 123 extend vertically through the dielectric stack layer (not shown) into the semiconductor layer 104. For example, during manufacturing, the overlap portion 202 of the slit structure 122 and the support structure 123 will be etched deeper than the slit structure 122 or the support structure 123, and enter the bottom semiconductor layer 104-3, because the overlap portion 202 is applied Two etching processes were performed. The overlapping portion 202 is over-etched and penetrates into the bottom semiconductor layer 104-3, which may cause the bottom semiconductor layer 104-3 to be unintentionally removed when the sacrificial layer 104-2 is removed later, thereby reducing the yield.

Various embodiments according to the content of this case provide an improved 3D memory device and a manufacturing method thereof. A dielectric layer (that is, an insulating layer) can be formed under the sacrificial polysilicon layer instead of the bottom semiconductor layer, so that the bottom surface of the overlap between the gap structure and the support structure falls on the dielectric layer instead of the semiconductor layer to avoid sacrificing Weaknesses that occurred during the layer removal process, as described above. In addition, when forming the channel structure, the channel hole etching can be stopped in the dielectric layer. This can also increase the process operation space of the via hole. In some embodiments, a stop layer is also formed on the substrate to automatically stop the backside thinning process so that the substrate can be completely removed to avoid wafer thickness uniformity control problems and reduce the manufacturing complexity of the backside process.

Figures 3A and 3B show cross-sectional views of various exemplary 3D memory devices according to various embodiments of the content of the present case. In some embodiments, the 3D memory device 300 in Figure 3A includes a substrate (not shown). The substrate may include silicon (for example, single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-coated insulator (SOI), germanium-coated insulator (GOI), or any other suitable material. In some embodiments, the substrate is a thinned substrate (for example, a semiconductor layer), which is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. Note that the y and z axes are included in FIG. 3A to further illustrate the spatial relationship of the components in the 3D memory device 300. The substrate of the 3D memory device 300 includes two lateral surfaces (for example, a top surface and a bottom surface) extending laterally in the y direction (ie, the bit line direction). As the user in the text, a 3D memory device (such as 3D memory device 100) is "on", "above", or "below" another device (such as a layer or device). It is determined relative to the substrate of the 3D memory device in the z direction (ie, the vertical direction) when the substrate is placed on the lowest plane of the 3D memory device in the z direction. The content of this case uses the same concept to describe the spatial relationship.

In some embodiments, the 3D memory device 300 is a part of a non-monolithic 3D memory device in which the components are formed separately on different substrates and then joined in a face-to-face manner, a face-to-back manner, or a back-to-back manner . A peripheral element (not shown) for facilitating the operation of the 3D memory element 300 may be formed on a separate peripheral element substrate different from the memory array substrate on which the components shown in Figure 3A are formed, for example, any suitable Digital, analog, and/or mixed signal peripheral circuits. It should be understood that the memory array substrate can be removed from the 3D memory device 300, as described in detail below, and the peripheral device substrate can become the substrate of the 3D memory device 300. It should also be understood that, depending on how the peripheral device substrate and the memory array device substrate are joined, the memory array device (as shown in FIG. 3A) may be in the original position or may be upside down in the 3D memory device 300. For simplicity of reference, FIG. 3A depicts the state of the 3D memory device 300 in which the memory array device is in the original position (that is, not upside down). However, it should be understood that in some examples, the memory array element shown in FIG. 3A may be upside down in the 3D memory element 300, and its relative position may be changed accordingly. The content of this case uses the same concept to describe the spatial relationship.

As shown in FIGS. 3A and 3B, the 3D memory device 300 may include a dielectric layer (ie, an insulating layer) 302. The dielectric layer 302 may include one or more interlayer dielectric layers (ILD, also referred to as "intermetal dielectric layer (IMD)"), in which interconnect lines and VIA contacts may be formed. The ILD layer of the dielectric layer 302 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k (low-k) dielectric, or any combination thereof. In some embodiments, the dielectric layer 302 includes silicon oxide.

The 3D memory device 300 may also include a semiconductor layer 304 above the dielectric layer 302. In some embodiments, the semiconductor layer 304 is directly disposed on the dielectric layer 302. In some embodiments, the semiconductor layer 304 includes polysilicon. For example, according to some embodiments, the semiconductor layer 304 includes an N-type doped polysilicon layer. That is, the semiconductor layer 304 may be doped with any appropriate N-type dopants, for example, phosphorus (P), arsenic (Ar) or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. As described in detail below, due to the diffusion process, the semiconductor layer 304 may have a nominally uniform doping concentration distribution in the vertical direction. In some embodiments, the doping concentration of the semiconductor layer 304 is between about 10 ¹⁹ cm ^-3 and about 10 ²² cm ^-3 , for example, between 10 ¹⁹ cm ^-3 and 10 ²² cm -3 (for example, 10 ^{19 cm -3 ). cm -3, 2 × 10 19 cm} -3, 3 × 10 19 cm -3, 4 × 10 19 cm -3, 5 × 10 19 cm -3, 6 × 10 19 cm -3, 7 × 10 19 cm - ³ , 8×10 ¹⁹ cm ^-3 , 9×10 ¹⁹ cm ^-3 , 10 ²⁰ cm ^-3 , 2×10 ²⁰ cm ^-3 , 3×10 ²⁰ cm ^-3 , 4×10 ²⁰ cm ^-3 , 5× ^{10 20 cm -3, 6 × 10} 20 cm -3, 7 × 10 20 cm -3, 8 × 10 20 cm -3, 9 × 10 20 cm -3, 10 21 cm -3, 2 × 10 21 cm - ³ , 3×10 ²¹ cm ^-3 , 4×10 ²¹ cm ^-3 , 5×10 ²¹ cm ^-3 , 6×10 ²¹ cm ^-3 , 7×10 ²¹ cm ^-3 , 8×10 ²¹ cm ^-3 , 9×10 ²¹ cm ^-3 , 10 ²² cm ^-3 , any range at the lower end is defined by any one of these values, or any range defined by any two of these values). Although FIG. 3A shows that the semiconductor layer 304 is above the dielectric layer 302, as described above, it should be understood that in some examples, the dielectric layer 302 may be above the semiconductor layer 304. This is because of FIGS. 3A and 3B. The memory array elements shown in the figure can be upside down, and their relative positions can be changed in the 3D memory element 300 accordingly. In some embodiments, the memory array elements shown in FIGS. 3A and 3B are turned upside down (at the top) and joined to peripheral elements in the 3D memory element 300 (at the bottom), so that the dielectric layer 302 Above the semiconductor layer 304.

In some embodiments, the 3D memory device 300 further includes a source contact structure 328 that extends perpendicularly through the dielectric layer 304 from the opposite side (ie, the back surface) of the dielectric layer 302. The layer 302 is in contact with the semiconductor layer 304. The top surface of the source contact structure 328 may be nominally flush with the bottom surface of the semiconductor layer 304 or extend further into the semiconductor layer 304. The source contact structure 328 can electrically connect the source of the NAND memory string of the 3D memory device 300 from the backside of the memory array substrate (removed) to the peripheral device through the semiconductor layer 304, and therefore can also be used herein. It is called "rear source pick-up". The source contact structure 328 may include any suitable type of contact. In some embodiments, the source contact structure 328 includes VIA contacts. In some embodiments, the source contact structure 328 includes laterally extending wall-shaped contacts. The source contact structure 328 may include one or more conductive layers, such as metal layers, such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al), or a conductive adhesive layer (such as titanium nitride ( TiN)) Surrounding silicide layer.

In some embodiments, the 3D memory device 300 is a NAND flash memory device, in which storage cells are provided in an array of NAND memory strings. Each NAND memory string may include a channel structure 312 that extends through multiple pairs, each pair including a stacked conductive layer 308 and a stacked dielectric layer 310 (referred to herein as "conductive layer/dielectric layer right"). The stacked conductive layer/dielectric layer pair is also referred to as the storage stack 306 herein. The number of conductive layer/dielectric layer pairs in the storage stack 306 (for example, 32, 64, 96, 128, 160, 192, 224, 256, etc.) determines the number of storage cells in the 3D memory device 300. Although not shown in FIGS. 3A and 3B, it should be understood that, in some embodiments, the storage stack 306 may have a multi-deck structure, for example, including a lower memory layer and on the lower memory layer The two-layer architecture of the upper memory layer. The number of pairs of stacked conductive layers 308 and stacked dielectric layers 310 in each memory layer may be the same or different.

The storage stack 306 may include a plurality of staggered stacked conductive layers 308 and stacked dielectric layers 310. The stacked conductive layers 308 and stacked dielectric layers 310 in the storage stacked layer 306 may alternate in the vertical direction. In other words, in addition to the layers on the top or bottom of the storage stacked layer 306, each stacked conductive layer 308 may be abutted by two stacked dielectric layers 310 on both sides, and each stacked dielectric layer 310 may be abutted on both sides. The two stacked conductive layers 308 adjoin. The stacked conductive layer 308 may include conductive materials, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stacked conductive layer 308 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer 324. The gate electrode of the stacked conductive layer 308 may extend laterally as a word line and stop at one or more stepped structures (not shown) of the storage stacked layer 306. The stacked dielectric layer 310 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIGS. 3A and 3B, each channel structure 312 extends vertically through the storage stack 306 and the semiconductor layer 304 into the dielectric layer 302. That is, the channel structure 312 can include three parts: the lower part surrounded by the dielectric layer 302 (that is, under the interface between the semiconductor layer 304 and the dielectric layer 302), and the middle part surrounded by the semiconductor layer 304 (that is, in the semiconductor layer). Between the top and bottom surfaces of 304), and the upper portion surrounded by the storage stack 306 (that is, above the interface between the semiconductor layer 304 and the storage stack 306). As used herein, the "upper/upper end" of an element (such as the channel structure 312) is the part/end away from the substrate in the z direction when the substrate is placed in the lowest plane of the 3D memory element 300, and the element ( For example, the "lower/lower end" of the channel structure 312) is the portion/end that is closer to the substrate in the z direction when the substrate is placed in the lowest plane of the 3D memory device 300. In some embodiments, each channel structure 312 extends vertically into the dielectric layer 302. For example, the lower end of the channel structure 312 may be lower than the top surface of the dielectric layer 302. Therefore, the process operation space of the channel structure 312 can be increased accordingly.

In some embodiments as shown in FIG. 3A, the channel structure 312 is laterally spaced apart from the source contact structure 328 in the dielectric layer 302. For example, as shown in FIG. 3A, the lower portion of the channel structure 312 surrounded by the dielectric layer 302 is separated from the source contact structure 328 in the dielectric layer 302 in the y direction. In some embodiments as shown in FIG. 3B, the channel structure 312 extends into the source contact structure 328 instead of extending into the dielectric layer 302. Therefore, the source contact structure 328 may be in contact with the semiconductor channel 316 in the lower portion of the channel structure 312. By allowing the channel structure 312 to extend to and directly contact the source contact structure 328, the feature size of the source contact structure 328 can be increased, thereby also increasing the coverage margin of the channel structure 312.

The channel structure 312 may include a channel hole filled with a semiconductor material (for example, as a semiconductor channel 316) and a dielectric material (for example, as a memory film 314). In some embodiments, the semiconductor channel 316 includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In one example, the semiconductor channel 316 includes polysilicon. In some embodiments, the memory film 314 is a composite layer including a tunneling layer, a storage layer (also referred to as a “charge trapping layer”), and a blocking layer. The remaining space of the via hole may be partially or completely filled with a cover layer 318, which includes a dielectric material, such as silicon oxide and/or an air gap. The channel structure 312 may have a cylindrical shape (for example, a cylindrical shape). According to some embodiments, the capping layer 318, the semiconductor channel 316, the tunneling layer of the memory film 314, the storage layer, and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 314 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In some embodiments, the channel structure 312 also includes a channel plug 320 on top of the upper portion of the channel structure 312. The channel plug 320 may include a semiconductor material (for example, polysilicon). In some embodiments, the channel plug 320 is used as the drain of the NAND memory string.

As shown in FIGS. 3A and 3B, according to some embodiments, the semiconductor channel 316 is in contact with the sublayer 309 of the semiconductor layer 304 along a portion of the sidewall of the channel structure 312 (for example, in the middle portion of the channel structure 312). That is, according to some embodiments, the memory film 314 is disconnected in the middle portion of the channel structure 312 adjacent to the sublayer 309 of the semiconductor layer 304, so that the semiconductor channel 316 is exposed to contact the surrounding sublayer 309 of the semiconductor layer 304. Therefore, the sub-layer 309 of the semiconductor layer 304 surrounding and in contact with the semiconductor channel 316 can be used as the "sidewall SEG" of the channel structure 312 instead of the "bottom SEG" described above, which can alleviate such things as coverage control, epitaxial layer formation and SONO perforation and the like. As described in detail below, according to some embodiments, the sub-layer 309 of the semiconductor layer 304 is formed separately from the rest of the semiconductor layer 304. However, it should be understood that since the sub-layer 309 of the semiconductor layer 304 may have the same polysilicon material as the rest of the semiconductor layer 304, and the doping concentration in the semiconductor layer 304 may be nominally uniform after diffusion. Therefore, the sub-layer 309 may not be distinguished from the rest of the semiconductor layer 304 in the 3D memory device 300. However, the sub-layer 309 refers to a portion of the semiconductor layer 304 that is in contact with the semiconductor channel 316 (rather than in contact with the memory film 314) in the middle portion of the channel structure 312.

As shown in FIGS. 3A and 3B, the 3D memory device 300 may also include insulating structures 322, each insulating structure extending vertically through the interleaved stacked conductive layers 308 and stacked dielectric layers in the storage stack 306 310. The insulating structure 322 may be an example of the slot structure 122 in FIG. 1, which is filled with a dielectric substance and does not include conductive contacts therein. According to some embodiments, the insulating structure 322 extends through the entire thickness of the semiconductor layer 304 and stops at the top surface of the dielectric layer 302. That is, according to some embodiments, the bottom surface of the insulating structure 322 is nominally flush with the top surface of the dielectric layer 302. Each insulating structure 322 may also extend laterally to partition the channel structure 312 into a plurality of block storage areas (for example, as an example of the slot structure 122 in FIG. 1). That is, the storage stack layer 306 can be divided into a plurality of block storage areas by the insulating structure 322, so that the array of the channel structure 312 can be divided into each block storage area. According to some embodiments, unlike the gap structure in some 3D NAND memory devices that include a front source contact structure, the insulating structure 322 does not include any contacts (that is, does not serve as a source contact structure), and therefore does not incorporate The parasitic capacitance and leakage current of the stacked conductive layer 308 (including the word line). In some embodiments, each insulating structure 322 includes openings (such as gaps) filled with one or more dielectric materials including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 322 may be filled with silicon oxide as an insulator core 326 and a high-k dielectric connected to the gate dielectric layer 324 surrounding the stacked conductive layer 308.

In some embodiments, by doping the semiconductor layer 304 with N-type dopants, (ie, eliminating the P-well as the source of the hole), the 3D memory device 300 is configured to be generated when the erase operation is performed according to some embodiments. Body bias assisted by gate-induced drain leakage (GIDL). The GIDL around the source selection gate of the NAND memory string can generate a hole current to the NAND memory string to increase the body potential for the erase operation.

As shown in FIGS. 3A and 3B, the insulating structure 322 extends vertically through the storage stack 306 and the entire semiconductor layer 304 so that the bottom surface of the insulating structure 322 falls on the top surface of the dielectric layer 302.

For example, as shown in Figure 4, the intermediate structure during the manufacture of the 3D memory device 300 includes a dielectric layer 302 and a semiconductor layer 304, as described above. Fig. 4 shows a cross-section of the overlapping portion of the insulating structure 322 and the supporting structure 323 (for example, corresponding to the supporting structure 123 in Figs. 1 and 2). Both the insulating structure 322 and the supporting structure 323 extend vertically through the storage stack 306 (not shown) and the entire semiconductor layer 304, so that the bottom surface of the insulating structure 322 and the supporting structure 323 falls on the top surface of the dielectric layer 302 . During manufacturing, the overlapping portion 402 of the insulating structure 322 and the supporting structure 323 falls on the dielectric layer 302 instead of a part of the semiconductor layer 304 (for example, the bottom semiconductor layer 104-3 in Figure 2). As described above, this can avoid weaknesses that occur during the sacrificial layer removal process, and can avoid lowering the yield caused by unintentionally removing the bottom semiconductor layer (for example, the bottom semiconductor layer 104-3 in FIG. 2).

As described above and described in further detail below, according to some embodiments, the memory array substrate on which the dielectric layer 302, the semiconductor layer 304, the storage stack layer 306, the channel structure 312, and the insulating structure 322 are formed is from a 3D memory The device 300 is removed so that the 3D memory device 300 does not include a memory array substrate.

Figures 5A to 5K illustrate a manufacturing process for forming an exemplary 3D memory device according to some embodiments of the content of this case. FIG. 6 shows a flowchart of a method 600 for forming an exemplary 3D memory device according to some embodiments of the content of the present case. Examples of the 3D memory device depicted in FIGS. 5A to 5K and 6 include the 3D memory device 300 depicted in FIGS. 3A and 3B. Figures 5A to 5K and Figure 6 will be described together. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed at the same time or in a different order from that shown in Figure 6.

Referring to FIG. 6, the method 600 starts at operation 602. In operation 602, a stop layer, a first dielectric layer (ie, a first insulating layer), a sacrificial layer, a first semiconductor layer, and a first semiconductor layer are sequentially formed on the first side of the substrate. Dielectric stacking layer. The substrate can be a silicon substrate or a carrier substrate made of any suitable material (for example, glass, sapphire, plastic, to name a few) to reduce the cost of the substrate. The first side may be the front surface of the substrate, and semiconductor elements may be formed on the front surface. In some embodiments, the stop layer may include silicon nitride. The dielectric layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, in order to form the sacrificial layer, the first sacrificial layer and the second sacrificial layer are sequentially formed. The first sacrificial layer may include polysilicon or silicon nitride, and the second sacrificial layer may include silicon oxynitride. The dielectric stack layer may include a plurality of staggered stacked sacrificial layers and stacked dielectric layers. In some embodiments, the first semiconductor layer includes polysilicon.

As shown in Figure 5A, a stop layer 503, a first dielectric layer (ie, a first insulating layer) 505, a first sacrificial layer 507, a second sacrificial layer 509, and a first semiconductor layer 511 are sequentially formed on the front surface of the substrate 502. And the dielectric stack layer 508. The substrate 502 may be a silicon substrate, or a carrier substrate made of any suitable material (for example, glass, sapphire, plastic, to name a few). In some embodiments, the stop layer 503 includes silicon nitride. As described in detail below, when the substrate 502 is removed from the backside, the stop layer 503 may be used as a stop layer, and thus may include any other suitable material in addition to the material of the substrate 502. It should be understood that, in some embodiments, a pad oxide layer (such as a silicon oxide layer) may be formed between the substrate 502 and the stop layer 503 to relieve the stress between different layers. Similarly, another pad oxide layer can be formed between the stop layer 503 and the first dielectric layer 505 to relieve the stress between them.

The first sacrificial layer 507 and the second sacrificial layer 509 may be collectively referred to as sacrificial layers herein. In some embodiments, the first sacrificial layer 507 and the second sacrificial layer 509 include polysilicon or silicon nitride and silicon oxynitride, respectively. As described in detail below, the first sacrificial layer 507 can be selectively removed later, and therefore can include any other suitable material that has a high etch selectivity (for example, greater than about 5) relative to silicon oxide, such as polysilicon, nitrogen Silica, or carbon. The second sacrificial layer 509 may be used as a stop layer when etching the first sacrificial layer 507, and may be selectively removed later, and therefore may include materials relative to polysilicon (the first sacrificial layer 507 and the first semiconductor layer 511). ) Any other suitable material with high etch selectivity (for example, about greater than 5).

The stop layer 503, the first dielectric layer 505, the first sacrificial layer 507, the second sacrificial layer 509, and the first semiconductor layer 511 (or any other layer in between) can be achieved by using one or more thin film deposition processes (including but Not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless deposition, any other suitable deposition process or any combination thereof) in multiple process loops The corresponding materials are deposited sequentially in this order to form. In some embodiments, the first semiconductor layer 511 is doped with N-type dopants, such as P, As, or Sb. In one example, an ion implantation process can be used to dope the first semiconductor layer 511 after the polysilicon material is deposited. In another example, when polysilicon is deposited to form the first semiconductor layer 511, in-situ doping of N-type dopants may be performed. It should be understood that, in some examples, the first semiconductor layer 511 is not doped with N-type dopants at this stage.

As shown in Figure 5A, a plurality of pairs of first dielectric layers (called "stacked sacrificial layers 512") and second dielectric layers (called "stacked dielectric layers") are formed on the first semiconductor layer 511. 510″) dielectric stack 508. According to some embodiments, the dielectric stack 508 includes interleaved stacked sacrificial layers 512 and stacked dielectric layers 510. The stacked dielectric layer 510 and the stacked sacrificial layer 512 may alternatively be deposited on the first semiconductor layer 511 to form the dielectric stacked layer 508. In some embodiments, each stacked dielectric layer 510 includes a silicon oxide layer, and each stacked sacrificial layer 512 includes a silicon nitride layer. The dielectric stack 508 may be formed by one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, a pad oxide layer (for example, a silicon oxide layer, not shown) is formed between the first semiconductor layer 511 and the dielectric stack layer 508.

As shown in Figure 6, the method 600 proceeds to operation 604, in which a channel structure is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first dielectric layer . In some embodiments, in order to form a channel structure, a channel hole extending vertically through the dielectric stack layer, the first semiconductor layer and the sacrificial layer into the first dielectric layer is formed, and the memory is sequentially formed along the sidewall of the channel hole Membrane and semiconductor channels. In some embodiments, a channel plug is formed over and in contact with the semiconductor channel. As mentioned above and described in detail below, in some embodiments, instead of extending into the dielectric layer, the channel structure may also extend into the source contact structure. For example, the source contact structure may be formed later in the dielectric layer, extending laterally to contact the portion of the channel structure within the dielectric layer. The channel structure can be viewed as extending into the source contact structure and stopping within the source contact structure.

As shown in FIG. 5A, the via hole is an opening that extends vertically through the dielectric stack 508, the first semiconductor layer 511, and the sacrificial layers 509 and 507, and stops in the first dielectric layer 505. In some embodiments, multiple openings are formed so that each opening becomes a location for growing various channel structures 514 in a later process. In some embodiments, the manufacturing process for forming the channel hole of the channel structure 514 includes a wet etching and/or dry etching process, such as deep reactive ion etching (DRIE). According to some embodiments, the etching of the channel hole will continue until it stops in the first dielectric layer 505, for example, the channel hole extends below the top surface of the first dielectric layer 505. In some embodiments, the etching conditions (for example, etching rate and time) can be controlled to ensure that each via hole has reached the first dielectric layer 505 and stopped in the first dielectric layer 505, so as to increase the processing space of the via hole. And the channel structure 514 formed in the channel hole.

As shown in FIG. 5A, a memory film 516 (including a barrier layer, a storage layer, and a tunneling layer) and a semiconductor channel 518 are sequentially formed along the sidewall and bottom surface of the via hole in this order. In some embodiments, the memory film 516 is deposited along the sidewall and bottom surface of the via hole first, and then the semiconductor channel 518 is deposited on the memory film 516. Subsequently, one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof) may be used to sequentially deposit the barrier layer, the storage layer, and the tunnel layer in this order to form the memory film 516. The semiconductor channel can then be formed by depositing a semiconductor material (such as polysilicon) on the tunnel layer of the memory film 516 using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof) 518. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are subsequently deposited to form the memory film 516 and the semiconductor channel 518.

As shown in FIG. 5A, a capping layer 520 is formed in the channel hole and over the semiconductor channel 518 to completely or partially fill the channel hole (for example, without or with an air gap). The capping layer 520 may be formed by depositing a dielectric material (such as silicon oxide) using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof). The channel plug 522 may then be formed in the upper portion of the channel hole. In some embodiments, the portions of the memory film 516, the semiconductor channel 518, and the capping layer 520 on the top surface of the dielectric stack 508 are removed and planarized by CMP, wet etching, and/or dry etching processes. The recesses may then be formed in the upper portion of the channel hole by wet etching and/or dry etching of the semiconductor channel 518 and the portion of the capping layer 520 in the upper portion of the channel hole. Subsequently, one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof) may be used to form the channel plug 522 by depositing a semiconductor material (such as polysilicon) into the recess. According to some embodiments, a channel structure 514 passing through the dielectric stack layer 508, the first semiconductor layer 511, and the sacrificial layers 509 and 507 into the first dielectric layer 505 is thereby formed.

As shown in Figure 6, the method 600 proceeds to operation 606, in which an opening is formed that extends vertically through the dielectric stack layer and the first semiconductor layer and stops at the sacrificial layer to expose a portion of the sacrificial layer . In some embodiments, forming the opening stops at the second sacrificial layer.

As shown in FIG. 5B, the slit 524 is an opening formed to extend vertically through the dielectric stack 508 and the first semiconductor layer 511 and stop at the second sacrificial layer 509, and the opening exposes the second sacrificial layer 509 a part of. In some embodiments, the manufacturing process for forming the gap 524 includes a wet etching and/or dry etching process, such as DRIE. In some embodiments, the stacked dielectric layer 510 and the stacked sacrificial layer 512 of the dielectric stack layer 508 are etched first. The etching of the dielectric stack layer 508 may not stop on the top surface of the first semiconductor layer 511, and may further extend into the first semiconductor layer 511 at various depths (ie, gouging variations). Therefore, due to the etching selectivity between the material (for example, polysilicon) of the second sacrificial layer 509 and the first sacrificial layer 507, a second etching process (sometimes referred to as a post-etching process) may be performed to etch the first semiconductor layer 511 is stopped by the second sacrificial layer 509 (for example, a silicon oxynitride layer).

As shown in Figure 6, the method 600 proceeds to operation 608, in which the sacrificial layer is replaced with a second semiconductor layer between the first semiconductor layer and the first dielectric layer through the opening. In some embodiments, the second semiconductor layer includes polysilicon. In some embodiments, in order to replace the sacrificial layer with the second semiconductor layer, the sacrificial layer is removed through the opening to form a cavity between the first semiconductor layer and the first dielectric layer, and the memory film is removed through the opening To expose a portion of the semiconductor channel along the sidewall of the via hole, and deposit polysilicon into the cavity through the opening to form a second semiconductor layer. In some embodiments, at least one of the first or second semiconductor layers is doped with N-type dopants. N-type dopants may diffuse in the first semiconductor layer and the second semiconductor layer.

As shown in FIG. 5C, spacers 528 are formed along the sidewalls of the gap 524 by depositing one or more dielectrics (for example, high-k dielectrics) along the sidewalls of the gap 524. The bottom surface of the spacer 528 (and a part of the second sacrificial layer 509 in the gap 524 (if still remaining)) can be opened using a wet etching and/or dry etching process to expose a part of the first sacrificial layer 507 (such as As shown in Figure 5B, for example a polysilicon layer). In some embodiments, the first sacrificial layer 507 is subsequently removed by wet etching and/or dry etching to form the cavity 526. In some embodiments, the first sacrificial layer 507 includes polysilicon, the spacer 528 includes a high-k dielectric, and the second sacrificial layer 509 includes oxynitride etched by applying a tetramethylammonium hydroxide (TMAH) etchant through the gap 524 For silicon, the etching can be stopped by the high-k dielectric of the spacer 528 and the silicon oxynitride of the second sacrificial layer 509. That is, according to some embodiments, the removal of the first sacrificial layer 507 does not affect the dielectric stack layer 508 and the first semiconductor layer 511 protected by the spacer 528 and the second sacrificial layer 509, respectively.

As shown in FIG. 5D, the exposed portion of the memory film 516 in the cavity 526 is removed to expose the portion of the semiconductor channel 518 along the sidewall of the channel structure 514. In some embodiments, a part of the barrier layer (for example, including silicon oxide), the storage layer (for example, including silicon nitride), and the tunneling layer (for example, including silicon oxide) is applied through the gap 524 and the cavity 526 by applying etchant (for example, using Phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) for etching. The etching can be stopped by the spacer 528 and the semiconductor channel 518. That is, according to some embodiments, removing the exposed portion of the memory film 516 in the cavity 526 will not affect the dielectric stack layer 508 (protected by the spacer 528) and the semiconductor channel 518 including polysilicon and the semiconductor channel 518. Sealed cover layer 520. In some embodiments, the second sacrificial layer 509 (including silicon oxynitride) is also removed through the same etching process.

As shown in FIG. 5E, a second semiconductor layer 530 is formed between the first semiconductor layer 511 and the first dielectric layer 505. In some embodiments, one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof) are used to deposit polysilicon into the cavity 526 (as shown in Figure 5D) through the gap 524 to form the first Two semiconductor layer 530. In some embodiments, the polysilicon remaining in the lower portion of the gap 524 is removed so that the bottom surface of the gap 524 is flush with the top surface of the first dielectric layer 505, and a portion of the first dielectric layer 505 is removed from the gap. 524 is exposed, as shown in Figure 5F. In some embodiments, when polysilicon is deposited to form the second semiconductor layer 530, in-situ doping of N-type dopants (such as P, As, or Sb) is performed. The second semiconductor layer 530 may fill the cavity 526 to contact the exposed portion of the semiconductor channel 518 of the channel structure 514. It should be understood that depending on whether the first semiconductor layer 511 is doped with N-type dopants, the second semiconductor layer 530 may be doped or undoped, because at least one of the first semiconductor layer 511 and the second semiconductor layer 530 One may need to be doped with N-type dopants. In some embodiments, a thermal diffusion process (such as annealing) is used to diffuse N-type dopants in at least one semiconductor layer of the first semiconductor layer 511 and the second semiconductor layer 530 to vertically spread the N-type dopants in the first semiconductor layer 511 and the second semiconductor layer 530. A uniform doping concentration distribution is achieved in the second semiconductor layer 530. For example, the doping concentration after diffusion may be between 10 ¹⁹ cm ^-3 and 10 ²² cm ^-3 . As described above, since each of the first semiconductor layer 511 and the second semiconductor layer 530 includes the same polysilicon material with nominally the same doping concentration, the difference between the first semiconductor layer 511 and the second semiconductor layer 530 The interface may become indistinguishable. Therefore, the first semiconductor layer 511 and the second semiconductor layer 530 may be collectively regarded as a semiconductor layer after diffusion.

As shown in Figure 6, the method 600 proceeds to operation 610, in which a so-called "gate replacement process" is used to replace the dielectric stack with the storage stack through the opening. As shown in Figure 5F, wet etching and/or dry etching are used to remove a portion of the second semiconductor layer 530 and any remaining spacers 528 formed along the sidewalls of the gap 524 as shown in Figure 5E (to pass The gap 524 exposes the stacked sacrificial layer 512 of the dielectric stacked layer 508. The portion of the second semiconductor layer 530 on the first dielectric layer 505 along the gap 524 (shown in Figure 5E) also uses wet etching and/or dry etching to Removed so that the gap 524 stops at the top surface of the first dielectric layer 505. The etching process can be controlled (for example, by controlling the etching rate and/or time) so that the remaining part of the second semiconductor layer 530 remains in the first A semiconductor layer 511 and the first dielectric layer 505 are in contact with the semiconductor channel 518 of the channel structure 514.

As shown in FIG. 5G, the storage stacked layer 534 can be formed by a gate replacement process (ie, replacing the stacked sacrificial layer 512 with the stacked conductive layer 536). The storage stack 534 may therefore include a staggered stacked conductive layer 536 and a stacked dielectric layer 510 on the first semiconductor layer 511. In some embodiments, in order to form the storage stacked layer 534, the stacked sacrificial layer 512 is removed by applying an etchant through the slit 524 to form a plurality of lateral recesses. The stacked conductive layer 536 can then be deposited into the lateral recesses by depositing one or more conductive materials using one or more thin film deposition processes (eg, PVD, CVD, ALD, or any combination thereof). According to some embodiments, the channel structure 514 thus extends vertically through the storage stack 534 and the semiconductor layer including the first semiconductor layer 511 and the second semiconductor layer 530, stopping at the first dielectric layer 505.

As shown in Figure 6, the method 600 proceeds to operation 612, in which an insulating structure is formed in the opening. In some embodiments, to form an insulating structure, one or more dielectric materials are deposited into the opening to fill the opening. As shown in FIG. 5H, an insulating structure 542 is formed in the gap 524 (shown in FIG. 5G). One or more dielectric materials (such as high-k dielectric (also used as gate dielectric layer 538) and Silicon oxide) is used as the insulating core 540 to completely or partially fill the gap 524 with or without an air gap to form the insulating structure 542.

As shown in Figure 6, the method 600 proceeds to operation 614, in which the substrate is removed from the second side opposite the first side of the substrate and stopped at the stop layer. The second side can be the back of the substrate. As shown in Figure 5I, the base 502 (shown in Figure 5H) is removed from the back side. Although not shown in Figure 51, it should be understood that the intermediate structure in Figure 5H may be upside down to have a base 502 on top of the intermediate structure. In some embodiments, CMP, grinding, wet etching, and/or dry etching are used to completely remove the substrate 502 until stopped by the stop layer 503 (eg, a silicon nitride layer). In some embodiments, silicon CMP is used to remove the substrate 502 (silicon substrate), where the silicon CMP automatically stops when it reaches the stop layer 503 having a material other than silicon, that is, it is used as a backside CMP stop layer. In some embodiments, wet etching by TMAH is used to remove the substrate 502 (silicon substrate). The wet etching stops automatically when it reaches the stop layer 503 with a material other than silicon, that is, it is used as a backside etching stop layer. . However, the stop layer 503 can ensure that the substrate 502 is completely removed without considering the thickness uniformity after thinning.

As shown in Figure 6, the method 600 proceeds to operation 616, in which a source contact structure that extends vertically through the dielectric layer and stops at the semiconductor layer is formed. The source contact structure is in contact with the second semiconductor layer. As shown in FIG. 5J, wet etching and/or dry etching are used to remove the stop layer 503 to expose the first dielectric layer 505. A dielectric material (such as silicon oxide) can be deposited on top of the first dielectric layer 505 by using one or more thin film deposition processes (such as PVD, CVD, ALD, or any combination thereof) to deposit a dielectric material (such as silicon oxide) on the second dielectric layer 505. A second dielectric layer (ie, a second insulating layer) 506 is formed on the side. In some embodiments, since each of the first dielectric layer 505 and the second dielectric layer 506 includes the same dielectric material (such as silicon oxide), the first dielectric layer 505 and the second dielectric layer 506 The interface between the dielectric layers 506 may become indistinguishable. Therefore, the first dielectric layer 505 and the second dielectric layer 506 may be collectively referred to as a dielectric layer (ie, an insulating layer) 544 after being deposited.

In some embodiments, as shown in FIG. 5K, a backside source contact structure 546 extending vertically through the dielectric layer 544 to contact the second semiconductor layer 530 is formed. The source contact structure 546 is laterally spaced apart from the channel structure 514 in the first dielectric layer 505 of the dielectric layer 544. In some embodiments, the source contact structure 546 is formed by first using wet etching and/or dry etching (such as RIE) to etch the opening extending vertically through the dielectric layer 544 into the second semiconductor layer 530 Then, for example, by using one or more thin film deposition processes (such as PVD, CVD, ALD, or any combination thereof) to deposit TiN to form an adhesion layer on the sidewall and bottom surface of the opening. Then, for example, by using one or more thin film deposition processes (such as PVD, CVD, ALD, electroplating, electroless plating, or any combination thereof) to deposit a metal (such as W) to form a conductive layer on the adhesion layer to form the source contact structure 546.

In some embodiments, as shown in FIG. 5L, a source contact structure 546 is formed. The source contact structure 546 extends vertically through the dielectric layer 544 to contact the second semiconductor layer 530 and the channel structure 514. The portion of the first dielectric layer 505 adjacent to the dielectric layer 544 is in contact.

For example, the source contact structure 546 is formed by first etching an opening extending vertically through the dielectric layer 544 into the second semiconductor layer 530. The source contact structure 546 is also formed by removing the portion of the memory film 516 adjacent to the first dielectric layer 505 to expose the portion of the semiconductor channel 518 adjacent to the first dielectric layer 505 to contact the source contact structure 546. In some embodiments, when a part of the memory film 516 is etched, the barrier layer (for example, including silicon oxide), the storage layer (for example, including silicon nitride), and the tunneling layer (for example, including silicon oxide) are passed through An etchant (such as phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) is applied to the opening where the source contact structure 546 is formed to perform etching. The etching can be stopped by the semiconductor channel 518. That is, according to some embodiments, removing the portion of the memory film 516 in the first dielectric layer 505 does not affect the semiconductor channel 518 including polysilicon and the cover layer 520 encapsulated by the semiconductor channel 518. The remaining part of the semiconductor channel 518 can therefore be used as a stop layer to prevent any additional etching of the channel structure 514.

According to one aspect of this case, a 3D memory device includes: an insulating layer, a semiconductor layer, a storage stack layer of interlaced conductive layers and dielectric layers, and a source contact structure perpendicular to the opposite side of the insulating layer with respect to the semiconductor layer The ground extends through the insulating layer to contact the semiconductor layer, and the channel structure extends vertically through the storage stack layer and the semiconductor layer into the insulating layer or the source contact structure.

In some embodiments, the channel structure extends vertically into the insulating layer and is spaced laterally from the source contact structure in the insulating layer.

In some embodiments, the channel structure extends vertically into the source contact structure.

In some embodiments, the 3D memory device further includes an insulating structure extending vertically through the storage stack layer into the semiconductor layer.

In some embodiments, at least a portion of the bottom surface of the insulating structure is flush with the top surface of the insulating layer.

In some embodiments, the channel structure includes a memory film and a semiconductor channel, and the semiconductor channel is in contact with a sublayer of the semiconductor layer along a portion of the sidewall of the channel structure.

In some embodiments, the semiconductor layer includes polysilicon.

In some embodiments, the semiconductor layer includes an N-type doped polysilicon layer.

According to another aspect of the present case, a 3D memory device includes: an insulating layer, a semiconductor layer, a memory with interlaced conductive layers, a channel structure vertically extending through the storage stack layer and the semiconductor layer; and vertically extending through The insulating structure of the semiconductor layer through the storage stack layer. The channel structure includes a memory film and a semiconductor channel, and the semiconductor channel is in contact with a sublayer of the semiconductor layer along a part of the sidewall of the channel structure. The 3D memory device also includes an insulating structure that extends vertically through the storage stack into the semiconductor layer. The bottom surface of the insulating structure is flush with the top surface of the insulating layer.

In some embodiments, the 3D memory device further includes a source contact structure that extends vertically through the insulating layer from an opposite side of the insulating layer relative to the semiconductor layer to contact the semiconductor layer.

In some embodiments, the channel structure extends vertically into the insulating layer and is spaced laterally from the source contact structure in the insulating layer.

In some embodiments, the channel structure extends vertically into the source contact structure.

In some embodiments, the semiconductor layer includes polysilicon.

In some embodiments, the semiconductor layer includes an N-type doped polysilicon layer.

According to another aspect of the content of this case, it discloses a method for forming a 3D memory device. A stop layer, a first insulating layer, a sacrificial layer, a first semiconductor layer, and a dielectric stack layer are sequentially formed on the first side of the substrate. A channel structure is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer. An opening is formed that extends vertically through the dielectric stack layer and the first semiconductor layer and stops at the sacrificial layer to expose a portion of the sacrificial layer. Through the opening, the sacrificial layer is replaced with a second semiconductor layer between the first semiconductor layer and the first insulating layer. Remove the substrate from the second side opposite the first side of the substrate and stop at the stop layer.

In some embodiments, in order to form a channel structure, a channel hole is formed vertically extending through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer, and a memory film along the sidewall of the channel hole is sequentially formed And semiconductor channels.

In some embodiments, the stop layer is removed to form a second insulating layer contacting the first insulating layer, and a source contact structure extending vertically through the first and second insulating layers to contact the second semiconductor layer.

In some embodiments, the source contact structure is spaced apart from the channel structure in the first insulating layer.

In some embodiments, in order to form the source contact structure, the portion of the memory film of the channel structure in the first insulating layer is removed and stopped at the semiconductor of the channel structure.

In some embodiments, the stop layer includes silicon nitride, and the first insulating layer includes silicon oxide.

In some embodiments, in order to form the sacrificial layer, a first sacrificial layer and a second sacrificial layer are formed, and the formation of the opening stops at the second sacrificial layer.

In some embodiments, the first sacrificial layer includes polysilicon, and the second sacrificial layer includes silicon oxynitride.

In some embodiments, in order to replace the sacrificial layer with the second semiconductor layer, the sacrificial layer is removed through the opening to form a cavity between the first semiconductor layer and the first insulating layer. A portion of the memory film is removed through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole, and polysilicon is deposited into the cavity through the opening to form a second semiconductor layer.

In some embodiments, at least one of the first semiconductor layer and the second semiconductor layer is doped with N-type dopants. N-type dopants diffuse in the first semiconductor layer and the second semiconductor layer.

In some embodiments, before removing the substrate, an insulating structure is formed in the opening. The insulating structure is in contact with the first insulating layer.

According to another aspect of the content of this case, it discloses a method for forming a 3D memory device. A first insulating layer, a sacrificial layer, a first semiconductor layer, and a dielectric stack layer are sequentially formed on the substrate. A channel structure is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer. The sacrificial layer is replaced with a second semiconductor layer between the first semiconductor layer and the first insulating layer. At least one of the first semiconductor layer and the second semiconductor layer is doped with N-type dopants. N-type dopants diffuse in the first semiconductor layer and the second semiconductor layer.

In some embodiments, before replacing the sacrificial layer with the second semiconductor layer, an opening is formed that extends vertically through the dielectric stack layer and the first semiconductor layer and stops at the sacrificial layer to expose a portion of the sacrificial layer to The sacrificial layer is replaced with a second semiconductor layer through the opening.

In some embodiments, to form a channel structure, a channel hole is formed that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer. The memory film and the semiconductor channel along the sidewall of the channel hole are sequentially formed.

In some embodiments, a stop layer between the substrate and the first insulating layer is formed. Remove the substrate from the opposite side of the substrate from the stop layer and stop at the stop layer.

In some embodiments, after removing the substrate, the stop layer is removed, and a second insulating layer in contact with the first insulating layer is formed. A source contact structure is formed, and the second source contact structure vertically extends through the first insulating layer and the second insulating layer to contact the second semiconductor layer.

In some embodiments, the source contact structure is spaced apart from the channel structure in the first insulating layer.

In some embodiments, in order to form the source contact structure, the portion of the memory film of the channel structure in the first insulating layer is removed and stopped at the semiconductor of the channel structure.

In some embodiments, before removing the substrate, an insulating structure is formed in the opening through the second semiconductor layer. The insulating structure is in contact with the first insulating layer.

In some embodiments, the stop layer includes silicon nitride.

In some embodiments, in order to form the sacrificial layer, the first sacrificial layer and the second sacrificial layer are sequentially formed. An opening that stops at the second sacrificial layer is formed.

In some embodiments, the first sacrificial layer includes polysilicon or silicon nitride, and the second sacrificial layer includes silicon oxynitride.

In some embodiments, in order to replace the sacrificial layer with the second semiconductor layer, the sacrificial layer is removed through the opening to form a cavity between the first semiconductor layer and the first insulating layer. A portion of the memory film is removed through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole. Polysilicon is deposited into the cavity through the opening to form a second semiconductor layer.

In some embodiments, each of the first and second semiconductor layers includes polysilicon.

The above description of the specific embodiment will therefore reveal the general nature of the case, so that others can easily modify and/or adjust this specific embodiment for various applications by using knowledge within the technical scope of the art, without the need Excessive experimentation, and does not deviate from the general concept of the case. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the terms or terms in this document are used for illustrative purposes, not for limitation, so that the terms or terms in this specification will be interpreted by the skilled person in accordance with the teaching and guidance.

The embodiments of this case have been described above with the help of functional building blocks, which exemplify the implementation of specified functions and their relationships. In this article, the boundaries of these functional building blocks are arbitrarily defined for the purpose of convenience of description. It is possible to define alternative boundaries, as long as the specified functions and their relationships are appropriately performed.

The summary and abstract section may describe one or more exemplary embodiments of the case envisaged by the inventor, but not all exemplary embodiments, and therefore, are not intended to limit the disclosure of the case and the attached application in any way Patent scope. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: 3D memory device 101: block storage area 102: Base 103: Refers to the storage area 104: semiconductor layer 104-1: Top semiconductor layer 104-2: Sacrifice layer 104-3: bottom semiconductor layer 112: Channel structure 122: gap structure 123: Supporting structure 202: Overlap 300: 3D memory device 302: Dielectric layer 304: semiconductor layer 306: Storage Stack Layer 308: Stacked conductive layers 309: sublayer 310: stacked dielectric layer 312: Channel Structure 314: Memory Film 316: Semiconductor channel 318: Overlay 320: channel plug 322: Insulation structure 323: support structure 324: gate dielectric layer 326: Insulator core 328: Source contact structure 402: Overlap 502: Base 503: stop layer 505: first dielectric layer 506: second dielectric layer 507: (First) Sacrificial Layer 508: Dielectric stack layer 509: (Second) Sacrifice Layer 510: stacked dielectric layer 511: first semiconductor layer 512: Stacked Sacrificial Layer 514: Channel Structure 516: Memory Film 518: Semiconductor channel 520: Overlay 522: channel plug 524: gap 526: cavity 528: Spacer 530: second semiconductor layer 534: Storage Stack Layer 536: Stacked conductive layers 538: gate dielectric layer 540: Insulating core 542: Insulation Structure 544: Dielectric layer 546: source contact structure 600: method 602,604,606,608,610,612,614,616: Operation

The drawings incorporated herein and forming a part of the specification illustrate embodiments of the disclosure of the case, and together with the specification are further used to explain the principle of the disclosure of the case and enable those skilled in the relevant art to implement and use the disclosure of the case. FIG. 1 shows a plan view of a 3D memory device with a gap structure between block storage areas in various embodiments according to the content of the present application. FIG. 2 shows a cross-sectional view of the intermediate structure during the manufacture of the 3D memory device in FIG. 1. FIG. Figures 3A and 3B show cross-sectional views of various exemplary 3D memory devices in various embodiments according to the content of the present case. FIG. 4 shows a cross-sectional view of an exemplary 3D memory device with an insulating structure located between block storage areas in various embodiments according to the content of the present case. Figures 5A to 5L show a manufacturing process for forming an exemplary 3D memory device in some embodiments according to the content of the present case. FIG. 6 shows a flowchart of a method for forming an exemplary 3D memory device in some embodiments according to the content of the present case. Hereinafter, embodiments of the content of this case will be described with reference to the drawings.

300: 3D memory device

302: Dielectric layer

304: semiconductor layer

306: Storage Stack Layer

308: Stacked conductive layers

309: sublayer

310: stacked dielectric layer

312: Channel Structure

314: Memory Film

316: Semiconductor channel

318: Overlay

320: channel plug

322: Insulation structure

324: gate dielectric layer

326: Insulator core

328: Source contact structure

Claims (20)

A three-dimensional (3D) memory device including: Insulation; Semiconductor layer Storage stacks including interlaced conductive layers and dielectric layers; A source contact structure extending perpendicularly through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer; and A channel structure, which extends vertically through the storage stack layer and the semiconductor layer into the insulating layer or the source contact structure. The 3D memory device according to claim 1, wherein the channel structure extends vertically into the insulating layer and is laterally spaced apart from the source contact structure in the insulating layer. The 3D memory device according to claim 1, wherein the channel structure extends vertically into the source contact structure. The 3D memory device according to item 1 of the scope of patent application further includes an insulating structure that extends vertically through the storage stack layer into the semiconductor layer. The 3D memory device according to claim 4, wherein the bottom surface of the insulating structure is flush with the top surface of the insulating layer. The 3D memory device according to item 1 of the scope of patent application, wherein the channel structure includes a memory film and a semiconductor channel, and a portion of the semiconductor channel along the sidewall of the channel structure and the semiconductor layer Layer contact. The 3D memory device according to the first item of the scope of patent application, wherein the semiconductor layer includes polysilicon. A three-dimensional (3D) memory device including: Insulation; Semiconductor layer Storage stacks including interlaced conductive layers and dielectric layers; Channel structure, the channel structure vertically extends through the storage stack layer and the semiconductor layer, wherein the channel structure includes a memory film and a semiconductor channel, and the semiconductor channel along the sidewall of the channel structure Partially in contact with the sublayer of the semiconductor layer; and An insulating structure that extends vertically through the storage stack layer into the semiconductor layer, wherein the bottom surface of the insulating structure is flush with the top surface of the insulating layer. The 3D memory device according to item 8 of the scope of patent application, further comprising a source contact structure extending vertically from the opposite side of the insulating layer with respect to the semiconductor layer through the The insulating layer is in contact with the semiconductor layer. The 3D memory device according to the 9th patent application, wherein the channel structure extends vertically into the insulating layer and is laterally spaced apart from the source contact structure in the insulating layer. The 3D memory device according to item 9 of the scope of patent application, wherein the channel structure extends vertically into the source contact structure. The 3D memory device according to item 8 of the scope of patent application, further includes an insulating structure that extends vertically through the storage stack layer into the semiconductor layer, wherein the bottom surface of the insulating structure is connected to The top surface of the insulating layer is flush. The 3D memory device according to item 8 of the scope of patent application, wherein the semiconductor layer includes polysilicon. A method for forming three-dimensional (3D) memory devices, including: Sequentially forming a stop layer, a first insulating layer, a sacrificial layer, a first semiconductor layer, and a dielectric stack layer on the first side of the substrate; Forming a channel structure that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer; Forming an opening that extends vertically through the dielectric stack layer and the first semiconductor layer and stops at the sacrificial layer to expose a portion of the sacrificial layer; Replacing the sacrificial layer between the first semiconductor layer and the first insulating layer with a second semiconductor layer through the opening; and The substrate is removed from the second side opposite to the first side of the substrate and stopped at the stop layer. The method for forming a 3D memory device according to item 14 of the scope of patent application, wherein forming the channel structure includes: Forming a via hole that extends vertically through the dielectric stack layer, the first semiconductor layer, and the sacrificial layer into the first insulating layer; and A memory film and a semiconductor channel are sequentially formed along the sidewall of the channel hole. The method for forming a 3D memory device according to item 15 of the scope of patent application further includes, after removing the substrate: Remove the stop layer; Forming a second insulating layer in contact with the first insulating layer; and A source contact structure is formed that extends vertically through the first insulating layer and the second insulating layer to contact the second semiconductor layer. The method for forming a 3D memory device according to the 16th patent application, wherein the source contact structure is spaced apart from the channel structure in the first insulating layer. The method for forming a 3D memory device according to the 16th patent application, wherein forming the source contact structure further includes: removing the memory film of the channel structure on the first insulating layer The part in the channel structure stops at the semiconductor channel of the channel structure. The method for forming a 3D memory device according to item 14 of the scope of patent application further includes: before removing the substrate, forming an insulating structure in the opening through the second semiconductor layer, wherein The insulating structure is in contact with the first insulating layer. The method for forming a 3D memory device according to the 14th patent application, wherein each of the first semiconductor layer and the second semiconductor layer includes polysilicon.

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