TW201640652A - Method for forming a semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a buffer layer on a buried layer. Next, a first opening is formed through the stack and through a portion of the buffer layer. Thereafter, a spacer is formed on a sidewall of the first opening.

Description

Method of forming semiconductor structure 【0001】

The disclosure relates to a method of forming a semiconductor structure. More particularly, the present disclosure relates to a method of forming a semiconductor structure in which a spacer is formed on one of the sidewalls of one of the openings of the semiconductor structure.

【0002】

Recently, as the demand for more excellent memory elements has gradually increased, various three-dimensional (3D) memory elements have been provided, such as Single-Gate Vertical-Channel (SGVC) having a multi-layer stacked structure. Three-dimensional inverse (NAND) memory components. Such three-dimensional memory components can achieve higher storage capacity and have superior electronic characteristics, such as good data storage reliability and operation speed.

[0003]

In a U-shaped SGVC 3D NAND memory device, an inversion gate is used to assist control. During the fabrication of this inversion gate, over-etching may occur and the structure of the memory element may be damaged. Therefore, it is quite important to improve the formation of the inversion gate in the memory device.

[0004]

In the present disclosure, a method of forming a semiconductor structure is provided to address at least some of the above problems.

[0005]

According to an embodiment, a method of forming a semiconductor structure includes the following steps. First, a buffer layer is formed stacked on a buried layer, the stack being composed of alternating a plurality of conductive layers and a plurality of insulating layers. Next, a first opening is formed through the stack and a portion of the buffer layer. Thereafter, a spacer is formed on a sidewall of the first opening.

[0006]

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

[0029]

100‧‧‧Substrate
110‧‧‧ buried layer
113‧‧‧First etchant
115‧‧‧Second etchant
120‧‧‧buffer layer
121, 221‧‧ ‧ reverse gate
122‧‧‧ first opening
126, 226‧‧‧ second opening
130‧‧‧Stacking
131‧‧‧Insulation
133‧‧‧ Conductive layer
140‧‧‧First hard mask layer
150‧‧‧Second hard mask layer
160, 260‧‧‧ spacers
211‧‧‧ etching process
224‧‧‧ trench
W ₁ , W ₂ ‧ ‧ width

【0007】

1A to 1E are cross-sectional views showing a method of forming a semiconductor device in accordance with an embodiment of the present disclosure.
2A to 2F are cross-sectional views showing a method of forming a semiconductor device in accordance with another embodiment of the present disclosure.

[0008]

In the following detailed description, for the purposes of illustration However, it should be understood that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and elements are shown in schematic form in order to simplify the drawings.

【0009】

A method of forming the semiconductor structure will be described below. For ease of explanation, the following embodiments will be exemplified by a three-dimensional memory component (for example, a three-dimensional vertical channel memory component, particularly a U-shaped SGVC 3D NAND memory component). However, the invention is not limited thereto, and the method can be applied to other non-volatile memories, general memories, or general semiconductor structures, for example.

[0010]

1A to 1E illustrate a method of forming a semiconductor device in accordance with an embodiment of the present disclosure.

[0011]

Referring to FIG. 1A, a substrate 100 is provided that is selectively associated with layers and/or components formed thereon. A buried layer 110 may be formed over the substrate 100. A buffer layer 120 can be formed over the buried layer 110. A stack 130 is formed on the buffer layer 120. The stack 130 is composed of an alternating plurality of insulating layers 131 and a plurality of conductive layers 133. In an embodiment, the top and bottom layers of the stack 130 are both insulating layers 131.

[0012]

The buried layer 110 and the insulating layer 131 may be formed of an oxide. The thickness of each of the insulating layers may be, for example, 200 Å. The buffer layer 120 may be formed of a conductive semiconductor material, such as an N-type doped (for example, phosphorous or arsenic doped) polysilicon or P-type doped (for example, boron doped). Polycrystalline germanium. The conductive layer 133 may be formed of a conductive semiconductor material, such as a P-type doped polysilicon doped with boron. The thickness of the buffer layer 120 may be greater than the thickness of each of the conductive layers 133. In an embodiment, the thickness of the buffer layer 120 may be between 1500 Å and 2000 Å, and the thickness of each of the conductive layers 133 may be 400 Å. The conductive layer 133 can serve as a word line and a ground selection line in the semiconductor structure.

[0013]

Optionally, a first hard mask layer 140 may be formed on the stack 130, and a second hard mask layer 150 may be formed on the first hard mask layer 140. The first hard mask layer 140 may be formed of tantalum nitride (SiN). The first hard mask layer 140 can be used to protect the semiconductor structure from bending or collapse, and/or can serve as a stop layer in the steps of Chemical Mechanical Polishing (CMP). The second hard mask 150 may be formed of an oxide and may protect the first hard mask layer 140 during a subsequent step (eg, applying a second etchant, as shown in FIG. 1E).

[0014]

Referring to FIG. 1B, a first opening 122 may be formed through the stack 130 and a portion of the buffer layer 120. The first opening 122 is stopped on the buffer layer 120, and the remaining portion of the buffer layer 120 still covers the buried layer 110. That is, the surface of the buried layer 110 is not exposed. The formation of the first opening 122 can be patterned as a word line. In addition, the first opening 122 can also pass through the first hard mask layer 140 and the second hard mask layer 150 . The first opening 122 can be formed by an etching process.

[0015]

Referring to FIG. 1C, a spacer 160 may be formed on one of the sidewalls of the first opening 122. The thickness of the spacer 160 may be in the range of 300 Å to 400 Å. The material of the spacer 160 may be tantalum nitride (SiN), germanium telluride (SiGe), or germanium (Ge). In one embodiment, the spacers 160 may be formed by a deposition process, and an etching process may be performed after the deposition process. In this etching process, etching can pass through the deposited material and stop on the second hard mask layer 150 and the buffer layer 120 to form the spacers 160.

[0016]

Referring to FIG. 1D, a first etchant 113 can be applied to form a second opening 126 that stops on the buried layer 110. After the step of forming the second opening 126, the buffer layer 120 may be changed into a plurality of separate inversion gates 121. The second opening 126 may be formed by wet etching with the first etchant 113. The first etchant 113 may comprise ammonium (NH ₄ OH) or tetramethylammonium hydroxide (TMAH), such as a diluted ammonium solution or a diluted tetramethylammonium hydroxide solution. The first etchant 113 has a first etch rate and a second etch rate for the buried layer 110 and the buffer layer 120, respectively, and the second etch rate is greater than the first etch rate. In one embodiment, the second etch rate is much greater than the first etch rate such that the first etchant 113 selectively etches the buffer layer 120 leaving the buried layer 110 substantially intact.

[0017]

Referring to FIG. 1E, a second etchant 115 may be applied to remove the spacers 160. In some cases, the first hard mask layer 140 may be cut away by the second etchant 115. The second etchant 115 may be phosphoric acid (H ₃ PO ₄ ), such as hot phosphoric acid.

[0018]

After the step of removing the spacers 160, a memory layer (not shown) may be formed on the sidewalls of the first opening 122 and the second opening 126. The memory layer may have an Oxide-Nitride-Oxide (ONO) structure or an Oxide-Nitride-Oxide-Nitride-Oxide (Oxide-Nitride-Oxide-Nitride-Oxide, ONONO) structure. Next, a conductor (not shown) may be formed over the memory layer to form a channel layer. This conductor may be polysilicon or other suitable channel material. Thereafter, a chemical mechanical polishing process can be selectively performed. Performing this chemical mechanical polishing process removes excess material when forming a memory layer (not shown) and a conductor (not shown). This chemical mechanical polishing process is stopped at the first hard mask layer 140. In this case, the first hard mask layer 140 can serve as a stop layer in a chemical mechanical polishing process. The first hard mask layer 140 and the second hard mask layer 150 may be removed after the chemical mechanical polishing process.

[0019]

2A to 2F illustrate a method of forming a semiconductor device in accordance with another embodiment of the present disclosure. This embodiment differs from the embodiment shown in FIGS. 1A to 1E in the spacer 260, and the step of adding an etching process 211 before the application of the first etchant 113. Therefore, similar descriptions will not be repeated here.

[0020]

Referring to FIGS. 2A to 2B, the first opening 122 may be formed. Thereafter, referring to FIG. 2C, a spacer 260 may be formed on the sidewall of the first opening 122. The thickness of the spacer 260 can be in the range of 100 Å to 200 Å. The material of the spacer 260 may be tantalum nitride, tantalum or niobium. In an embodiment, the spacers 260 can be formed by a deposition process.

[0021]

Referring to FIG. 2D, an etching process 211 may be performed before the first etchant 113 is applied, and a trench 224 may be formed in the buffer layer 120. The etch process 211 can include dry etch, such as high selectivity dry etch. After the etching process 211 is performed, the trenches 224 may have a taper profile. The spacer 260 can protect the stack 130 from damage by the etching process 211.

[0022]

Referring to FIG. 2E, a first etchant 113 can be applied to form a second opening 226 that stops on the buried layer 120. After the first etchant 113 is applied, the trench 224 can be changed to the second opening 226. By forming the second opening 226, the buffer layer 120 is separated and a plurality of inversion gates 221 are formed. At this time, the inclined profile of the buffer layer 120 may disappear. The second opening 226 may be formed by wet etching using the first etchant 113, for example, isotropic etching. The spacer 260 may not be damaged by the first etchant 113, and the spacer 260 may protect the stack 130 from being damaged by the first etchant 113. Spacer 260 may be nearly intact in an alkaline solution.

[0023]

After the etching process 211 is performed on the first opening 122, the buffer layer 120 has a first pitch (for example, a width W ₁ ), and after the first etchant 113 is applied, the buffer layer 120 has a second pitch (for example, Width W ₂ ), and this second spacing is greater than this first spacing.

[0024]

Referring to FIG. 2F, a second etchant 115 can be applied to remove the spacers 260. In some cases, the first hard mask layer 140 may be ablated by the second etchant 115. The second etchant 115 may be phosphoric acid (H ₃ PO ₄ ), such as hot phosphoric acid.

[0025]

After the step of removing the spacers 260, a memory layer (not shown) may be formed on the sidewalls of the first opening 122 and the second opening 226. Next, a conductor (not shown) may be formed over the memory layer to form a channel layer.

[0026]

In accordance with an embodiment of the present invention, a method of forming a semiconductor structure is provided. By forming a spacer (160 or 260) on the sidewall of the first opening (122), the stack (130) composed of alternating plurality of insulating layers (131) and a plurality of conductive layers (133) can be protected from The stack (130) is damaged by the first etchant (113) when the second opening (126 or 226) is formed, or the stack (130) is prevented from being damaged by the etching process (211) when the trench (224) is formed. Even though the etch process (211) includes a highly selective dry etch, the stack (130) is still well protected by the spacers (260). Since the rate at which the first etchant (113) etches the buffer layer (120) may be much greater than the rate at which the buried layer (110) is etched, the buried layer (110) may have almost no recess and the overetching condition can be avoided. Since too many notches are not formed in the buried layer (110), the inversion gate (121 or 221) can have a good structure and thus have good controllability. In addition, by using the spacers (160 or 260) and the first etchant (113), a larger spacing can be provided to the memory layer and the channel material, and even if the stack is higher, the formation of the channels can be more continuous.

[0027]

In contrast, if spacers are not formed on the sidewalls of the stacked openings and a suitable etchant is not used to selectively etch the buffer layer, many recesses may be created in the buried layer, and the stack may be highly selective. The destruction of the etch and the reverse gate may have a sloped profile. In this case, the channel region between the respective inversion gates is less controllable, and the smaller interval of the inversion gate causes difficulty in filling the memory layer and the channel material, thereby causing the channel to form a non- continuous.

[0028]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Substrate

110‧‧‧ buried layer

120‧‧‧buffer layer

122‧‧‧ first opening

130‧‧‧Stacking

131‧‧‧Insulation

133‧‧‧ Conductive layer

140‧‧‧First hard mask layer

150‧‧‧Second hard mask layer

160‧‧‧ spacers

Claims (10)

[Item 1] A method of forming a semiconductor structure, comprising:
Forming a buffer layer stacked on a buried layer, the stack being composed of alternating plurality of conductive layers and a plurality of insulating layers;
Forming a first opening through the stack and a portion of the buffer layer; and forming a spacer on a sidewall of the first opening. [Item 2] The method for forming a semiconductor structure according to claim 1, further comprising:
Forming a first hard mask layer on the stack and forming a second hard mask layer on the first hard mask layer, wherein the first opening of the buffer layer is formed through the stack and a portion In the step, the first opening also passes through the first hard mask layer and the second hard mask layer. [Item 3] The method for forming a semiconductor structure according to claim 1, wherein after the step of forming the spacer on the sidewall of the first opening, the method further comprises:
Applying a first etchant to form a second opening that stops on the buried layer; and applying a second etchant to remove the spacer, wherein the first etchant has a separate layer for the buried layer and the buffer layer a first etch rate and a second etch rate, the second etch rate being greater than the first etch rate. [Item 4] The method for forming a semiconductor structure as described in claim 3, further comprising:
Before the step of applying the first etchant, an etching process is performed on the first opening, wherein the first etching process includes a dry etching. [Item 5] The method of forming a semiconductor structure according to claim 3, wherein the first etchant comprises ammonium (NH ₄ OH) or tetramethylammonium hydroxide (TMAH). [Item 6] The method of forming a semiconductor structure according to claim 1, wherein the buffer layer has a thickness ranging from 1500 Å to 2,000 Å. [Item 7] The method of forming a semiconductor structure according to claim 1, wherein the spacer has a thickness ranging from 300 Å to 400 Å. [Item 8] The method of forming a semiconductor structure according to claim 1, wherein the spacer has a thickness ranging from 100 Å to 200 Å. [Item 9] The method of forming a semiconductor structure according to claim 1, wherein the material of the spacer comprises tantalum nitride (SiN), germanium telluride (SiGe), or germanium (Ge). [Item 10] The method of forming a semiconductor structure according to claim 1, wherein the buffer layer comprises an N-type doped polysilicon.