KR102532496B1 - Three dimensional semiconductor device - Google Patents

Abstract

A three-dimensional semiconductor memory device is provided. A three-dimensional semiconductor memory device includes an oxidation inhibiting layer disposed in a substrate; laminated structures disposed on the oxidation suppression layer and including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; and a plurality of vertical structures passing through the stacked structures and connected to the substrate.

Description

Three dimensional semiconductor memory device {Three dimensional semiconductor device}

The present invention relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device with improved reliability and integration.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price demanded by consumers. In the case of a semiconductor device, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of a two-dimensional or planar semiconductor device, since the degree of integration is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for miniaturization of the pattern, although the degree of integration of the 2D semiconductor device is increasing, it is still limited. Accordingly, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed.

An object to be solved by the present invention is to provide a three-dimensional semiconductor memory device with improved reliability.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above object, a three-dimensional semiconductor memory device according to embodiments of the present invention includes an oxidation suppression layer disposed in a substrate; laminated structures disposed on the oxidation suppression layer and including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; and a plurality of vertical structures passing through the stacked structures and connected to the substrate.

According to embodiments, lower surfaces of the vertical structures may be positioned lower than lower surfaces of the oxidation inhibitor layer.

According to embodiments, the oxidation inhibitor layer may include carbon (C), nitrogen (N), or fluorine (F).

In example embodiments, the horizontal gate insulating layer may directly contact the oxidation inhibition layer.

According to embodiments, each of the vertical structures may include a lower semiconductor pattern connected to the substrate through a lower portion of the stacked structure and the oxidation suppression layer, and a lower semiconductor pattern passing through an upper portion of the stacked structure. It may include an upper semiconductor pattern connected to.

In example embodiments, a vertical gate insulating layer may be further included between the lower semiconductor pattern and the electrodes, and the horizontal and vertical gate insulating layers may be thermally oxidized.

In example embodiments, a distance between a sidewall of the lower semiconductor pattern and a sidewall of the electrode adjacent thereto may be substantially the same as a distance between a lower surface of the electrode and an upper surface of the oxidation suppression layer.

In example embodiments, the horizontal gate insulating layer may have a thickness smaller than a minimum thickness of the insulating layers.

In example embodiments, the oxidation suppression layer may have a thickness smaller than that of the horizontal gate insulating layer.

According to embodiments, the substrate includes impurities of a first conductivity type, and the device further includes common source regions disposed in the substrate between the stacked structures, wherein the common source regions have a second conductivity type. of impurities may be included.

According to embodiments, a data storage layer disposed between the vertical structures and the electrodes may be further included.

According to embodiments, the substrate includes a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region, wherein the stacked structures and the oxidation suppression layer are formed in the cell array region. It extends into the connection area, and in the connection area, the laminated structure may have a stepped structure descending toward the peripheral circuit area.

In example embodiments, the substrate may include a connection region between the cell array region and the peripheral circuit region, and the horizontal gate insulating layer may have substantially the same thickness in the cell array region and the connection region.

According to embodiments, a peripheral logic structure including peripheral logic circuits disposed on the substrate in the peripheral circuit area and a peripheral insulating pattern covering the peripheral logic circuits may be further included, wherein the oxidation suppression layer comprises the cell array It may extend from a region to a region between the stacked structures and the peripheral logic structure.

According to the embodiments, a buried insulating layer covering end portions of the electrodes positioned in the connection region and the peripheral logic structure may be further included, wherein the buried insulating layer may include the oxidation suppression layer between the stacked structures and the peripheral logic structure. can cover

In example embodiments, dummy vertical structures connected to the substrate through the stacked structures in the connection area may be further included.

In order to achieve the above object, a 3D semiconductor memory device according to example embodiments includes a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; laminated structures extending from the cell array region to the connection region, the laminated structures including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; and an oxidation inhibiting layer provided in the substrate and in contact with the horizontal gate insulating layer.

According to embodiments, the laminated structure in the connection area may have a stepped structure descending toward the peripheral circuit area.

In example embodiments, the horizontal gate insulating layer may have substantially the same thickness in the cell array region and the connection region.

In example embodiments, the cell array region may further include a plurality of vertical structures passing through the stacked structures and the oxidation inhibition layer and contacting the substrate.

According to embodiments, each of the vertical structures may include a lower semiconductor pattern connected to the substrate through a lower portion of the stacked structure and the oxidation suppression layer, and a lower semiconductor pattern passing through an upper portion of the stacked structure. It may include an upper semiconductor pattern connected to.

In example embodiments, a vertical gate insulating layer may be further included between the lower semiconductor pattern and the electrodes, and the horizontal and vertical gate insulating layers may be thermally oxidized.

According to embodiments, a data storage layer disposed between the vertical structures and the electrodes may be further included.

According to embodiments, a peripheral logic structure spaced apart from the stacked structures and disposed on the substrate in the peripheral circuit area may be further included, wherein the oxidation suppression layer is disposed on the substrate between the stacked structures and the peripheral logic structure. can be extended to

In example embodiments, the oxidation suppression layer may have a thickness smaller than that of the horizontal gate insulating layer.

According to embodiments, the oxidation inhibitor layer may include carbon (C), nitrogen (N), or fluorine (F).

Details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, the horizontal gate insulating layer extending from the cell array region to the connection region may have a substantially uniform thickness by forming the oxidation suppression layer in the substrate under the horizontal gate insulating layer. A threshold voltage distribution of ground selection transistors provided in the cell array region and the connection region may be reduced.

1 is a diagram for explaining a schematic arrangement structure of a 3D semiconductor memory device according to example embodiments.
2 is a block diagram of a 3D semiconductor memory device according to example embodiments.
3A and 3B are simplified circuit diagrams of a 3D semiconductor memory device according to example embodiments.
4 is a plan view of a 3D semiconductor memory device according to example embodiments.
5A to 14A are cross-sectional views illustrating a method of manufacturing a 3D semiconductor memory device according to example embodiments, and are cross-sectional views taken along the line II′ of FIG. 4 .
5B to 14B are cross-sectional views of a 3D semiconductor memory device according to example embodiments, taken along line II-II′ of FIG. 4 .
15A to 17A are enlarged views of portion A of FIGS. 11A to 13A, respectively.
15B to 17B are enlarged views of portion B of FIGS. 11B to 13B .
FIG. 18 is an enlarged view of portion C of FIG. 14B.
19A and 19B are views for explaining another example of a 3D semiconductor memory device according to embodiments of the present invention, and are enlarged views of portions A and B of FIGS. 13A and 13B , respectively.
20A to 20E are diagrams for explaining a structure of a data storage layer of a 3D semiconductor memory device according to example embodiments, and are enlarged views of portion D of FIG. 14B.
21 is a circuit diagram showing a part of a 3D semiconductor memory device according to embodiments of the present invention.
FIG. 22 is a cross-sectional view illustrating another example of a 3D semiconductor memory device according to embodiments of the present invention, taken along the line II′ of FIG. 4 .
23A and 23B are cross-sectional views illustrating another example of a 3D semiconductor memory device according to embodiments of the present invention, which are cross-sectional views taken along lines II' and II-II' of FIG. 4 , respectively.
24A and 24B are enlarged views of portions A and B of FIG. 23A, respectively, and FIG. 24C is an enlarged view of portion C of FIG. 23B.
25 is a schematic block diagram of a 3D semiconductor memory device according to example embodiments.
26 is a cross-sectional view of a 3D semiconductor memory device according to example embodiments.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and the common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numbers designate like elements throughout the specification.

Terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. As used herein, 'comprises' and/or 'comprising' means that a stated component, step, operation, and/or element is the presence of one or more other components, steps, operations, and/or elements. or do not rule out additions. Further, in this specification, when a film is referred to as being on another film or substrate, it means that it may be directly formed on the other film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described in this specification will be described with reference to cross-sectional views and/or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, the shape of the illustrative drawings may be modified due to manufacturing techniques and/or tolerances. Therefore, embodiments of the present invention are not limited to the specific shapes shown, but also include changes in shapes generated according to manufacturing processes. For example, an etched region shown at right angles may be round or have a predetermined curvature. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of a region of a device and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a diagram for explaining a schematic arrangement structure of a 3D semiconductor memory device according to example embodiments.

2 is a block diagram of a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 1 , a semiconductor memory device includes a cell array area (CAR) and a peripheral circuit area. The peripheral circuit area includes row decoder areas ROW DCR, a page buffer area PBR, and a column decoder area COL DCR. In addition, a connection region CNR may be disposed between the cell array region CAR and the row decoder regions ROW DCR.

Referring to FIGS. 1 and 2 , a memory cell array composed of a plurality of memory cells is disposed in the cell array area CAR. The memory cell array includes a plurality of memory cells and a plurality of word lines and bit lines electrically connected to the memory cells. The memory cell array may include a plurality of memory blocks BLK0 to BLKn as data erasing units. The memory cell array will be described in detail with reference to FIG. 3 .

A row decoder 2 for selecting word lines of a memory cell array is disposed in the row decoder region ROW DCR. A wiring structure electrically connecting the memory cell array and the row decoder 2 may be disposed in the connection region CNR. The row decoder 2 selects one of the memory blocks BLK0 to BLKn of the memory cell array and selects one of word lines of the selected memory block according to the address information. The row decoder 2 may provide a word line voltage generated from a voltage generator circuit (not shown) to selected word lines and non-selected word lines, respectively, in response to control of a control circuit (not shown).

A page buffer 3 for reading information stored in memory cells may be disposed in the page buffer area PBR. The page buffer 3 may temporarily store data to be stored in memory cells or detect data stored in memory cells according to an operation mode. The page buffer 3 may operate as a write driver circuit in the program operation mode and as a sense amplifier circuit in the read operation mode.

A column decoder 4 connected to the bit lines of the memory array is disposed in the column decoder region COL DCR. The column decoder 4 may provide a data transmission path between the page buffer 3 and an external device (eg, a memory controller).

3 are circuit diagrams illustrating a cell array of a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 3 , a cell array of a semiconductor memory device according to an example includes a common source line CSL, a plurality of bit lines BL, and disposed between the common source line CSL and the bit lines BL. It may include a plurality of cell strings (CSTR).

The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between a plurality of bit lines BL and one common source line CSL. According to one example, a plurality of common source lines CSL may be two-dimensionally arranged. Here, electrically the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be composed of a plurality of memory cell transistors MCT disposed between. Also, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected to sources of the ground select transistors GST in common. In addition, the ground select line GSL, the plurality of word lines WL0 to WL3, and the plurality of string select lines SSL disposed between the common source line CSL and the bit lines BL are connected to the ground. They may be used as gate electrodes of the selection transistor GST, memory cell transistors MCT, and string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a data storage element.

4 is a plan view of a 3D semiconductor memory device according to example embodiments. 5A to 14A and 5B to 14B are cross-sectional views illustrating a method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention, and FIGS. 5A to 14A are taken along line II' of FIG. 5b to 14b are cross-sections taken along the line II-II' of FIG. 4, respectively.

15A to 17A are enlarged views of portion A of FIGS. 11A to 13A, and FIGS. 15B to 17B are enlarged views of portion B of FIGS. 11B to 13B, respectively. 18 is an enlarged view of part C of FIG. 14B.

Referring to FIGS. 4 , 5A and 5B , the substrate 10 may include a cell array area CAR, a connection area CNR, and a peripheral circuit area PR. The connection region CNR may be positioned between the cell array region CAR and the peripheral circuit region PR.

The substrate 10 may be one of a material having semiconductor properties (eg, a silicon wafer), an insulating material (eg, glass), a semiconductor covered by an insulating material, or a conductor. For example, the substrate 10 may be a silicon wafer having a first conductivity type.

Peripheral logic circuits for writing and reading data to and from memory cells may be formed on the substrate 10 in the peripheral circuit area PR. As described with reference to FIG. 2, the peripheral logic circuits include row and column decoders (see 2 and 4 in FIG. 2), page buffers (see 3 in FIG. 2) and control circuits (see 5 in FIG. 2). can do. That is, the peripheral logic circuits may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the memory cells.

For example, a device isolation layer 21 defining the peripheral active region ACT may be formed on the substrate 10 of the peripheral circuit region PR. A peripheral gate insulating layer 22 may be formed between the peripheral gate electrode 23 crossing the peripheral active region ACT and between the peripheral gate electrode 23 and the substrate 10 . The peripheral gate electrode 23 may be formed of doped polysilicon, metal silicide, or a metal material, and the peripheral gate insulating layer 22 may be a silicon oxide layer formed by a thermal oxidation process. In addition, the source/drain regions 24 may be formed by doping impurities in the active region ACT on both sides of the peripheral gate electrode 23 .

After forming the peripheral logic circuits on the substrate 10 in the peripheral circuit region PR, a peripheral insulating layer 25 covering the entire surface of the substrate 10 may be formed. The peripheral insulating layer 25 may include a plurality of insulating layers, and may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a low-k dielectric layer.

4, 6A, and 6B, a peripheral insulating pattern 25P exposing the substrate 10 of the cell array region CAR and the connection region CNR is formed by patterning the peripheral insulating layer 25. can A peripheral logic structure PSTR may be formed on the substrate 10 in the peripheral circuit region PR by forming the peripheral insulating pattern 25P, and the peripheral logic structure PSTR includes the peripheral gate insulating layer 22 and the peripheral gate An electrode 23, source/drain regions 24, and a peripheral insulating pattern 25P may be included.

In detail, forming the peripheral insulating pattern 25P includes forming a mask pattern (not shown) covering the peripheral circuit region PR on the peripheral insulating layer 25 and using the mask pattern as an etch mask to form the peripheral insulating layer. (25).

In one example, the peripheral insulating layer 25 may be etched using an etching process using plasma. The etching process may be, for example, plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or ion beam etching (IBE, Ion Beam Etching) process.

For example, in the process of etching the peripheral insulating film 25, a fluorocarbon (CxFy)-based gas or a hydrofluorocarbon (CxHyFz)-based gas may be used as an etching gas. For example, etching gases such as CF ₄ , C ₃ F ₈ , C ₄ F ₈ , and CH ₂ F ₂ , and the like may be used.

According to example embodiments, after forming the peripheral insulating pattern 25P, the oxidation suppression layer 11 may be formed on the substrate 10 exposed by the peripheral insulating pattern 25P. The oxidation inhibitor layer 11 may be formed adjacent to the surface of the substrate 10 . For example, the oxidation inhibition layer 11 may include an oxidation inhibition material such as carbon (C), nitrogen (N), or fluorine (F). In addition, the oxidation inhibiting layer 11 may have a thickness of about 50 Å to about 150 Å.

According to an example, when the peripheral insulating layer 25 is plasma etched using an etching gas containing carbon and fluorine, carbon included in the etching gas may be ionized. In this case, carbon ions penetrate into the surface of the substrate 10 exposed by the peripheral insulating pattern 25P, and the oxidation suppression layer 11 may be formed on the surface of the substrate 10 . That is, the oxidation suppression layer 11 may be formed in-situ during an etching process of the peripheral insulating pattern 25P. When the oxidation inhibition layer 11 is formed in this way, the carbon concentration in the oxidation inhibition layer 11 may vary according to RF power during an etching process using plasma. For example, when RF power is increased during the plasma etching process, the amount of carbon penetrating into the surface of the substrate 10 exposed to the peripheral insulating pattern 25P may be increased.

According to another example, the oxidation suppression layer 11 may be formed by ion implanting an oxidation suppression material into the substrate 10 using the peripheral insulating pattern 25P as an ion implantation mask.

Furthermore, according to embodiments, after forming the peripheral insulating pattern 25P, a first conductive type well impurity layer 10P may be formed in the substrate 10 exposed by the peripheral insulating pattern 25P. . That is, the well impurity layer 10P may be formed in the substrate 10 in the cell array region CAR and the connection region CNR. The well impurity layer 10P may be formed by doping the substrate 10 with impurities of the first conductivity type. When the well impurity layer 10P is formed, the substrate 10 may include a second conductivity type semiconductor layer (not shown), and the well impurity layer 10P may be formed in the second conductivity type semiconductor layer. there is.

In another example, the oxidation suppression layer 11 may be formed by doping an oxidation suppression material together while forming the well impurity layer 10P on the substrate 10 .

Referring to FIGS. 4, 7A, and 7B , the mold structure 100 extending from the cell array area CAR to the connection area CNR may be formed on the substrate 10. . In the connection region CNR, the mold structure 100 may have a stepped structure in which a height decreases as it approaches the peripheral circuit region PR.

In detail, forming the mold structure 100 may include forming a thin film structure on the entire surface of the substrate 10 and performing a trimming process on the thin film structure.

In one example, the thin film structure may extend from the upper surface of the substrate 10 of the cell array area CAR to the upper surface of the peripheral logic structure PSTR. Also, the thin film structure may include a buffer insulating layer ILDa on the surface of the substrate 10 and sacrificial layers SL and insulating layers ILD alternately stacked on the buffer insulating layer ILDa. The buffer insulating layer ILDa may be a silicon oxide layer and may be formed using a thermal oxidation process or a deposition process. In embodiments, the buffer insulating layer ILDa may be formed on the oxidation inhibition layer 11 and may directly contact the oxidation inhibition layer 11 .

In the thin film structure, the sacrificial layers SL may be formed of a material that has etch selectivity with respect to the insulating layers ILD and can be etched. For example, the sacrificial layers SL and the insulating layers ILD may have a high etching selectivity in a wet etching process using a chemical solution and a low etching selectivity in a dry etching process using an etching gas. For example, the sacrificial layers SL and the insulating layers ILD may be formed of an insulating material and have etch selectivity to each other. That is, the sacrificial layers SL may be formed of an insulating material different from that of the insulating layers ILD. For example, the sacrificial layers SL may be at least one of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon germanium layer, a silicon oxynitride layer, and a silicon nitride layer. The insulating layers ILD may be at least one of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon oxynitride layer, and a silicon nitride layer, but may be made of a material different from that of the sacrificial layers SL. For example, the sacrificial layers SL may be formed of a silicon nitride layer, and the insulating layers ILD may be formed of a low-k dielectric layer. Alternatively, the sacrificial layers SL may be formed of a conductive material, and the insulating layers ILD may be made of an insulating material.

The sacrificial layers SL and the insulating layers ILD may be formed by thermal CVD, plasma enhanced CVD, physical CVD, or atomic layer deposition (ALD). It can be deposited using technology.

In the thin film structure, the sacrificial layers SL may have the same thickness. Unlike this, the lowermost and uppermost sacrificial layers SL among the sacrificial layers SL may be formed thicker than the sacrificial layers SL located therebetween. Also, the insulating layers ILD may have the same thickness, or some of the insulating layers ILD may have different thicknesses. In addition, the buffer insulating layer ILDa formed on the lowermost layer of the thin film structure may have a thickness smaller than that of the sacrificial layers SL and the insulating layers ILD formed thereon.

Subsequently, a trimming process of patterning the thin film structure to have a stepwise structure in the connection region CNR may be performed. In detail, the trimming process includes a process of forming a mask pattern (not shown) covering the thin film structure in the cell array region (CAR) and the connection region (CNR), a process of etching the thin film structure, and a process of reducing the horizontal area of the mask pattern. It may include alternately repeating the process, and the process of etching the thin film structure and the process of reducing the horizontal area of the mask pattern. As such a trimming process is performed, the mold structure 100 may be formed on the substrate 10 of the cell array region CAR and the connection region CNR. The mold structure 100 may be spaced apart from the peripheral logic structure PSTR, and the substrate 10 between the mold structure 100 and the peripheral logic structure PSTR may be exposed. Also, the mold structure 100 may have a stepped structure descending from the connection region CNR toward the peripheral circuit region PR. That is, ends of the insulating layers ILD and the sacrificial layers SL may be located in the connection region CNR, and the area of the insulating layers ILD and the sacrificial layers SL may be on the upper surface of the substrate 10 . may decrease as you move away from it. In other words, the height of the mold structure 100 may decrease from the connection region CNR to the peripheral circuit region PR.

Continuing to refer to FIGS. 7A and 7B , a filling insulating layer 120 covering the mold structure 100 and the peripheral logic structure PSTR may be formed on the entire surface of the substrate 10 . The filling insulating layer 120 may be formed of an insulating material having etch selectivity with respect to the sacrificial layers.

Forming the filling insulating film 120 may include depositing an insulating film on the entire surface of the substrate 10 to cover the mold structure 100 and the peripheral logic structure PSTR, and planarizing an upper surface of the insulating film. . That is, the filling insulating layer 120 is the part of the mold structure 100 in the connection region CNR. End portions of the sacrificial layers and the peripheral logic structure PSTR may be covered in the peripheral circuit region PR and may have a planarized top surface. Also, in one example, the filling insulating layer 120 may cover a portion of the oxidation suppression layer 11 exposed between the mold structures 100 and the peripheral logic structure PSTR.

The buried insulating film 120 may include, for example, a high density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O3-TEOS (O3-Tetra Ethyl Ortho Silicate), USG (Undoped Silicate Glass), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), Tonen SilaZene (TOSZ), or a combination thereof. Also, the filling insulating layer 120 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

Referring to FIGS. 4, 8A, and 8B , a plurality of vertical holes H and DH penetrating the mold structure 100 may be formed. In one example, the vertical holes H and DH may include cell vertical holes H formed in the cell array area CAR and dummy vertical holes DH formed in the connection area CNR.

According to embodiments, forming the vertical holes H and DH involves forming a mask pattern (not shown) on the mold structure 100 and using the mask pattern (not shown) as an etching mask to form the mold structure ( 100) may be formed by anisotropic etching. In the anisotropic etching process, the upper surface of the substrate 10 may be over-etched, and thus, the upper surface of the substrate 10 exposed to the vertical holes H and DH is recessed to a predetermined depth. It can be. In some embodiments, the vertical holes H and DH may pass through the oxidation suppression layer 11 to expose the well impurity layer 10P in the substrate 10 . Also, due to the anisotropic etching process, the lower widths of the vertical holes H and DH may be smaller than the upper widths of the vertical holes H and DH.

Furthermore, the cell vertical holes H may be arranged in one direction or in a zigzag form when viewed from a plan view. The dummy vertical holes DH may pass through ends of the filling insulating layer 120 and the sacrificial layers. As the dummy vertical holes HDH are formed in the connection region CNR, the closer the dummy vertical holes DH are to the peripheral circuit region PR, the more the sacrificial layers SL through which the dummy vertical holes DH pass through. number may decrease.

In one example, the dummy vertical holes DH may pass through ends of some of the sacrificial layers SL and may be spaced apart from each other by a predetermined distance. Meanwhile, the present invention is not limited thereto, and in another example, the dummy vertical holes DH may pass through end portions of each sacrificial layer SL. In another example, forming the dummy vertical holes DH may be omitted.

Subsequently, a lower semiconductor pattern LSP filling lower portions of the vertical holes H and DH may be formed.

According to example embodiments, the lower semiconductor pattern LSP may pass through the oxidation suppression layer 11 and contact the well impurity layer 10P, as shown in FIGS. 15A and 15B . That is, the bottom surface of the lower semiconductor pattern LSP may be positioned below the top surface of the substrate 10 , and furthermore, may be positioned below the bottom surface of the oxidation suppression layer 11 . In addition, the lower semiconductor pattern LSP may directly contact one sidewalls of the sacrificial layers SL and the insulating layers ILD positioned under the mold structure 100 . The lower semiconductor pattern LSP may cover sidewalls of at least one or more sacrificial layers SL. An upper surface of the lower semiconductor pattern LSP may be positioned between vertically adjacent sacrificial layers SL.

More specifically, the lower semiconductor pattern LSP is formed by a Selective Epitaxial Growth (SEG) process using the substrate 10 exposed to the vertical holes H and DH as a seed layer. can be formed by performing Accordingly, the lower semiconductor pattern LSP may be formed in a pillar shape filling lower portions of the vertical holes H and DH. In this case, the lower semiconductor pattern LSP may have a single-crystal structure or a poly-crystal structure having a larger grain size than the chemical vapor deposition technique. Meanwhile, a material for the lower semiconductor pattern LSP may be silicon, but is not limited thereto. For example, carbon nanostructures, organic semiconductor materials, and compound semiconductors may be used for the lower semiconductor pattern LSP. According to other examples, the lower semiconductor pattern LSP may be formed of a polycrystalline semiconductor material (eg, polycrystalline silicon).

In addition, the lower semiconductor pattern LSP may have the same conductivity type as the substrate 10 . During the selective epitaxial growth process, the lower semiconductor pattern LSP may be doped with impurities in-situ. Alternatively, after forming the lower semiconductor pattern LSP, impurities may be ion-implanted into the lower semiconductor pattern LSP.

Referring to FIGS. 4, 9A, and 9B , upper semiconductor patterns USP may be formed in the vertical holes H and DH in which the lower semiconductor patterns LSP are formed. Accordingly, vertical structures VS including the lower semiconductor pattern LSP and the upper semiconductor pattern USP may be formed in the cell vertical holes H, and the lower semiconductor pattern LSP may be formed in the dummy vertical holes DH. ) and upper semiconductor patterns USP, dummy vertical structures DVS may be formed.

In more detail, referring to FIGS. 15A and 15B , the upper semiconductor pattern USP may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The first semiconductor pattern SP1 may be connected to the lower semiconductor pattern LSP and may have a pipe shape or a macaroni shape with a lower end closed. The inside of the first semiconductor pattern SP1 of this type may be filled with the filling insulating pattern VI. Also, the first semiconductor pattern SP1 may contact the inner wall of the second semiconductor pattern SP2 and the upper surface of the lower semiconductor pattern LSP. That is, the first semiconductor pattern SP1 may electrically connect the second semiconductor pattern SP2 and the lower semiconductor pattern LSP. The second semiconductor pattern SP2 may have a pipe shape or a macaroni shape with upper and lower ends open. Also, the second semiconductor pattern SP2 may be spaced apart without contacting the lower semiconductor pattern LSP. The first and second semiconductor patterns SP1 and SP2 may be undoped or doped with impurities having the same conductivity as the substrate 10 . The first and second semiconductor patterns SP1 and SP2 may include silicon (Si), germanium (Ge), or a mixture thereof, and may be a semiconductor doped with impurities or an intrinsic semiconductor in an undoped state. semiconductor). Also, the first and second semiconductor patterns SP1 and SP2 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. For example, the first and second semiconductor patterns SP1 and SP2 may be a polycrystalline silicon layer formed using one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques.

Furthermore, a conductive pad PAD may be formed on top of each of the upper semiconductor patterns USP. The conductive pad PAD may be an impurity region doped with impurities or made of a conductive material.

In addition, according to an example, before forming the upper semiconductor pattern USP, vertical insulating patterns VP may be formed in the vertical holes H and DH as shown in FIGS. 15A and 15B . The vertical insulating pattern VP may be composed of one thin film or a plurality of thin films. In example embodiments, the vertical insulating pattern VP may be part of a data storage layer. For example, the vertical insulating pattern VP may include a charge storage layer used as a memory element of a flash memory device. For example, the charge storage layer may be a trap insulating layer or an insulating layer including conductive nano dots. Alternatively, the vertical insulating layer may include a thin film for a phase change memory or a thin film for a variable resistance memory.

Referring to FIGS. 4 , 10A and 10B , a capping insulating layer 125 covering upper surfaces of the vertical structures VS and DVS may be formed on the filling insulating layer 120 . Subsequently, trenches T exposing the substrate 10 may be formed by patterning the capping insulating layer 125 and the mold structure 100 . As the trenches T are formed, the mold structure 100 may have a line shape extending in one direction.

Specifically, forming the trenches T includes forming a mask pattern (not shown) defining the planar positions of the trenches T on the mold structure 100 and etching the mask pattern (not shown). Anisotropic etching of the mold structure 100 using it as a mask may be included.

The trenches T may be formed to be spaced apart from the vertical structures VS to expose sidewalls of the sacrificial layers SL and the insulating layers ILD. From a plan view, the trenches T may be formed in a line shape or a rectangle extending in the first direction D1, and at a vertical depth, the trenches T expose the upper surface of the substrate 10. may be formed. During formation of the trenches T, an upper surface of the substrate 10 exposed to the trenches T may be recessed to a predetermined depth by over-etching. Also, the trenches T may have inclined sidewalls by an anisotropic etching process.

As the trenches T are formed, the mold structure 100 may have a line shape extending in the first direction D1. Also, a plurality of vertical structures VS may pass through the mold structure 100 having a single line shape.

According to an example, after forming the trenches T, common source regions CSR may be formed in the substrate 10 exposed to the trenches T. The common source regions CSR may extend side by side in the first direction D1 and may be spaced apart from each other in the second direction D2. In other words, the common source regions CSR may be formed in the well impurity layer 10P between the mold structures 100 and may be adjacent to sidewalls of the mold structures 100 . The common source regions CSR may be formed by doping the substrate 10 with impurities of a different type from that of the substrate 10 . The common source regions CSR may include, for example, N-type impurities (eg, arsenic (As) or phosphorus (P)).

Referring to FIGS. 4, 11A, and 11B , gate regions GR may be formed between the insulating layers ILD by removing the sacrificial layers SL exposed in the trenches T.

The gate regions GR are isotropically formed on the sacrificial layers SL using an etching recipe having etch selectivity with respect to the buffer insulating layer ILDa, the insulating layers ILD, the vertical structures VS, and the substrate 10 . It can be formed by etching it away. Here, the sacrificial layers SL may be completely removed by an isotropic etching process. For example, when the sacrificial layers SL are silicon nitride and the insulating layers ILD are silicon oxide, an isotropic etching process may be performed using an etchant containing phosphoric acid. In addition, the vertical insulating pattern VP may be used as an etch stop layer during an isotropic etching process for forming the gate regions GR. The gate regions GR formed as described above may horizontally extend from the trench T to between the insulating layers ILD, and may cover portions of sidewalls of the vertical insulating pattern VP or portions of the sidewalls of the vertical structure VS. can be exposed. That is, the gate regions GR may be defined by vertically adjacent insulating layers ILD and one sidewall of the vertical insulating pattern VP.

According to embodiments, the lowermost gate region among the gate regions GR may expose a portion of the sidewall of the lower semiconductor pattern LSP, and the buffer insulating layer ILDa, as shown in FIGS. 15A and 15B . can expose. After forming the gate regions GR, the buffer insulating layer ILDa exposed in the gate regions GR may have a first thickness t1 as shown in FIGS. 15A and 15B . In one example, the first thickness t1 may be greater than or equal to the thickness of the oxidation inhibiting layer 11 .

4, 12A, and 12B, a vertical gate insulating layer 13 on the sidewall of the lower semiconductor pattern LSP exposed in the gate region GR and a horizontal layer on the surface of the oxidation suppression layer 11 A gate insulating layer ILDb may be formed.

In one example, the vertical gate insulating layer 13 and the horizontal gate insulating layer ILDb may be formed through a heat treatment process in a gas atmosphere containing oxygen atoms. In this case, the vertical gate insulating layer 13 and the horizontal gate insulating layer ILDb may be selectively formed only on a surface capable of providing a silicon element.

In more detail, referring to FIGS. 16A and 16B , the vertical gate insulating layer 13 may be formed by reacting oxygen atoms with silicon atoms of the lower semiconductor pattern LSP during a thermal oxidation process. That is, during the thermal oxidation process, silicon atoms of the lower semiconductor pattern LSP exposed in the gate region GR may be consumed. Accordingly, after forming the vertical gate insulating layer 13 , the width of the middle portion of the lower semiconductor pattern LSP exposed to the gate region GR may be smaller than the width of the upper portion contacting the insulating layer. Also, the vertical gate insulating layer 13 may have a rounded surface.

The horizontal gate insulating layer ILDb may be formed when oxygen atoms penetrate the thin buffer insulating layer ILDa and react with silicon atoms of the substrate 10 during a thermal oxidation process. Accordingly, while the silicon atoms of the substrate 10 are consumed under the buffer insulating layer ILDa, the thickness of the buffer insulating layer ILDa increases so that the horizontal gate insulating layer ILDb may be formed. That is, as shown in FIGS. 16A and 16B , the horizontal gate insulating layer ILDb has a second thickness t2 greater than the first thickness of the buffer insulating layer ILDa before the thermal oxidation process (see t1 in FIGS. 15A and 15B ). ) can have. For example, the second thickness t2 may be greater than the thickness of the oxidation suppression layer 11 . Also, the second thickness t2 may be smaller than the thickness of the insulating layers ILD constituting the mold structure 100 . Also, the second thickness t2 may be substantially the same as the thickness of the vertical gate insulating layer 13 . For example, the second thickness t2 of the horizontal gate insulating layer ILDb may be about 100 Å to about 150 Å.

In embodiments, during a thermal oxidation process for forming the vertical gate insulating layer 13, the buffer insulating layer ILDa is in contact with the oxidation suppression layer 11, so that the oxidation suppression material is used to consume silicon atoms of the substrate 10. can reduce Accordingly, it is possible to reduce a thickness deviation of the horizontal insulating film in the cell array region CAR and the connection region CNR.

More specifically, due to the structural difference of the mold structure 100 in the cell array region CAR and the connection region CNR, during the thermal oxidation process, the amount of oxygen atoms penetrating into the substrate 10 is the cell array region ( CAR) and linking region (CNR). For example, since the thickness of the mold structure 100 gradually decreases in the connection region CNR and the filling insulating film 120 is disposed on the connection region CNR, the substrate ( 10) may be reduced compared to the amount of oxygen atoms penetrating into the substrate 10 of the cell array region CAR. Accordingly, the thickness of the horizontal gate insulating layer ILDb in the cell array region CAR may be increased compared to the thickness of the horizontal gate insulating layer ILDb in the connection region CNR, but the cell array layer 11 may prevent oxidation. Since oxidation of the substrate 10 is suppressed in the region CAR and the connection region CNR, a thickness difference between the horizontal gate insulating layers ILDb in the cell array region CAR and the connection region CNR may be reduced. That is, according to an example, the horizontal gate insulating layer ILDb may have substantially the same thickness (ie, the second thickness t2) in the cell array region CAR and the connection region CNR. According to another example, The horizontal gate insulating layer ILDb may be thicker in the cell array region CAR than in the connection region CNR.

In addition, since oxygen atoms are provided to the gate region GR through the trenches T during the thermal oxidation process, the horizontal gate insulating film ( ILDb) may be formed with different thicknesses. In other words, although the thickness of the horizontal gate insulating layer ILDb may decrease from the trench T to the lower semiconductor pattern LSP, in the embodiments of the present invention, the oxidation suppression layer 11 is formed on the substrate during the thermal oxidation process. By reducing silicon consumption in (10), it is possible to reduce a thickness deviation of the horizontal gate insulating layer ILDb at a portion adjacent to the trench T and a portion adjacent to the lower semiconductor pattern LSP.

Furthermore, while forming the vertical gate insulating layer 13 and the horizontal gate insulating layer ILDb, since the gate regions GR adjacent to the upper semiconductor pattern USP expose the vertical insulating pattern VP, the upper semiconductor pattern USP ) and the adjacent gate regions GR, an oxide layer may not be substantially formed.

Referring to FIGS. 4, 13A, and 13B , horizontal insulating patterns HP conformally covering inner walls of the gate regions GR may be formed. Referring to FIGS. 17A, 17B, and 18 , the horizontal insulating pattern HP may be formed with a substantially uniform thickness on inner walls of the gate regions GR. The horizontal insulating pattern HP may be composed of one thin film or a plurality of thin films. In one example, the horizontal insulating pattern HP may be a part of a data storage layer of a charge trap type flash memory transistor.

Subsequently, electrodes EL may be formed in the gate regions GR on which the horizontal insulating pattern HP is formed. The electrodes EL may partially fill the gate regions GR or completely fill the gate regions GR.

Forming the electrodes EL includes forming a gate conductive layer filling the gate regions where the horizontal insulating pattern HP is formed, and removing a portion of the gate conductive layer formed in the trenches T to form electrodes in the gate regions. Each of the ELs may be locally formed. Here, each of the electrodes EL may include a barrier metal layer and a metal layer sequentially deposited. The barrier metal film may be formed of, for example, a metal nitride film such as TiN, TaN, or WN. Also, the metal layer may be formed of, for example, metal materials such as W, Al, Ti, Ta, Co, or Cu.

In this way, as the electrodes EL are formed in the gate regions, stacked structures ST including insulating films ILD and electrodes EL alternately and repeatedly stacked on the substrate 10 are formed. It can be. The stacked structures ST may extend in the first direction D1 , and sidewalls of the stacked structures ST may be exposed in the trench T. In addition, the substrate 10 may be exposed between the stacked structures ST adjacent to each other.

In such stacked structures ST, the lowermost electrode EL may be adjacent to the lower semiconductor patterns LSP of the vertical structures VS and DVS, as shown in FIG. 18 . Here, the distance Da between the sidewall of the lower semiconductor pattern LSP and the sidewall of the lowermost electrode EL adjacent thereto is the distance Db between the lower surface of the lowermost electrode EL and the upper surface of the oxidation suppression layer 11 may be substantially the same as

Next, referring to FIGS. 4, 14A, and 14B , insulating spacers SP covering sidewalls of the trenches T may be formed. Forming the insulating spacer SP may include depositing a spacer film having a uniform thickness on the substrate 10 on which the stacked structures ST are formed, and performing an etch-back process on the spacer film to form a common source region CSR. ) may include exposing. Here, the spacer layer may be formed of an insulating material and may be deposited on inner walls of the trenches T to a thickness of about 1/2 or less of the minimum width of the trenches T. For example, the spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A common source plug CSP may be formed in each trench T in which the insulating spacer SP is formed. According to an example, the common source plug CSP may be disposed between horizontally adjacent electrodes EL, and an insulating spacer SP is interposed between the electrodes EL and the common source plug CSP. It can be. That is, the insulating spacer SP may cover sidewalls of the common source plug CSP. Also, the common source plug CSP may extend parallel to the electrodes EL, and upper surfaces of the common source plug may be positioned above upper surfaces of the vertical structures.

Continuing to refer to FIGS. 4 , 14A and 14B , an upper insulating layer 130 covering an upper surface of the common source plug CSP may be formed on the capping insulating layer 125 . Next, bit line contact plugs BPLG may be formed through the capping insulating layer 125 and the upper insulating layer 130 and connected to each of the vertical structures VS. Subsequently, bit lines BL extending in the second direction D2 and connected to the bit line contact plugs BPLG may be formed on the upper insulating layer 130 .

Furthermore, contact plugs CPLG, PUPLG, and PPLG electrically connecting the electrodes EL and the peripheral logic circuits may be formed in the connection region CNR and the peripheral circuit region PR.

For example, the cell contact plugs CPLG may pass through the capping insulating layer 125 and the filling insulating layer 120 in the connection region CNR and be respectively connected to ends of the electrodes. The vertical lengths of the cell contact plugs CPLG may decrease as they are closer to the cell array region CAR. Also, upper surfaces of the cell contact plugs CPLG may be substantially coplanar. A pickup contact plug PUPLG may pass through the filling insulating layer 120 and be connected to the pickup regions 10PU. Here, the pick-up regions 10PU may include impurities of the first conductivity type and have an impurity concentration greater than that of the well impurity layer 10P. Top surfaces of the pickup contact plugs PUPLG may be substantially coplanar with top surfaces of the cell contact plugs CPLG. Also, the peripheral contact plugs PPLG may be electrically connected to the peripheral logic circuits in the peripheral circuit region PR by penetrating the buried insulating layer 120 and the peripheral insulating pattern 25P.

Connection wires CL connected to the cell contact plugs CPLG may be formed on the upper insulating layer 130 of the connection region CNR, and on the upper insulating layer 130 of the peripheral circuit region PR. Peripheral wires PCL connected to the contact plugs PPLG may be formed. In addition, a well conductive line PPL connected to the pickup contact plug PUPLG may be formed on the upper insulating layer 130 .

Hereinafter, a data storage layer according to various embodiments of the present disclosure will be described in detail with reference to FIGS. 20A to 20E .

According to embodiments, the 3D semiconductor memory device may be a NAND flash memory device. For example, the data storage layer DS interposed between the stacked structure ST and the vertical structure VS may include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BK. Data stored in the data storage layer DS may be changed using Fowler-Northernheim tunneling caused by a voltage difference between the data storage layer vertical structure VS including a semiconductor material and the electrodes EL. there is.

According to the embodiment shown in FIG. 20A , the tunnel insulating layer TIL, the charge storage layer CIL, and the blocking insulating layer BLK are interposed between the electrodes EL and the vertical structure VS. (VS) can be extended between. That is, the insulating layer ILD may directly contact the electrode.

According to the embodiment shown in FIG. 20B , the tunnel insulating layer TIL and the charge storage layer CIL may extend between the electrodes EL and the vertical structure VS and between the insulating layer ILD and the vertical structure VS. there is. Also, the blocking insulating layer BLK may extend to upper and lower surfaces of the electrodes EL between the electrodes EL and the vertical structure VS.

According to the embodiment shown in FIG. 20C , the tunnel insulating layer TIL may extend between the electrodes EL and the vertical structure VS and may extend between the insulating layer ILD and the vertical structure VS, and the charge storage layer CIL ) and the blocking insulating layer BLK may extend to upper and lower surfaces of the electrodes EL between the electrodes EL and the vertical structure VS.

According to the embodiment shown in FIG. 20D , the tunnel insulating layer TIL, the charge storage layer CIL, and the blocking insulating layer BLK are interposed between the electrodes EL and the vertical structure VS on the top surface of the electrodes EL. It may extend to the upper and lower surfaces.

According to the embodiment shown in FIG. 20E , the data storage layer DS may include first and second blocking insulating layers BLK1 and BLK2 made of different materials. The tunnel insulating layer TIL, the charge storage layer CIL, and the first blocking insulating layer BLK1 may extend vertically between the electrodes EL and the vertical structure VS between the insulating layer ILD and the vertical structure VS. can Also, the second blocking insulating layer BLK2 may extend horizontally between the electrodes EL and the first blocking insulating layer BLK1 to the upper and lower surfaces of the electrodes EL.

In the data storage layer shown in FIGS. 20A to 20E , the charge storage layer (CIL) may be one of insulating layers rich in trap sites and insulating layers including nanoparticles, and one of chemical vapor deposition or atomic layer deposition techniques. It can be formed using one. For example, the charge storage layer CIL may include one of a trap insulating layer, a floating gate electrode, and an insulating layer including conductive nano dots. As a more specific example, the charge storage layer (CIL) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, nanocrystalline Si, and a laminated trap layer. can include

The tunnel insulating layer (TIL) may be one of materials having a larger band gap than the charge storage layer (CIL), and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating layer TIL may be a silicon oxide layer formed using one of the deposition techniques described above. Alternatively, the tunnel insulating layer may be one of high dielectric layers such as an aluminum oxide layer and a hafnium oxide layer.

The blocking insulating layer BLK may be one of materials having a band gap smaller than that of the tunnel insulating layer TIL and larger than that of the charge storage layer CIL. The blocking insulating layer BLK may include high dielectric layers such as an aluminum oxide layer and a hafnium oxide layer. The blocking insulating layer BLK may be formed using one of chemical vapor deposition and atomic layer deposition techniques, and at least one of these may be formed through a wet oxidation process.

As shown in FIG. 20E, when the data storage layer DS includes first and second blocking insulating layers BLK1 and BLK2, for example, the first blocking insulating layer BLK1 may include an aluminum oxide layer, a hafnium oxide layer, and the like. It is one of the same high-k dielectric layers, and the second blocking insulating layer BLK2 may be made of a material having a smaller dielectric constant than the first blocking insulating layer BLK1. As another example, the second blocking insulating layer BLK2 is one of high-k dielectric layers, and the first blocking insulating layer BLK1 may be a material having a dielectric constant smaller than that of the second blocking insulating layer BLK2.

Data stored in the data storage layer DS described with reference to FIGS. 20A to 20E is Fowler-Northernheim tunneling caused by a voltage difference between the vertical structure VS including a semiconductor material and the electrodes EL. can be changed using Alternatively, the data storage layer DS may be a thin film capable of storing information based on a different operating principle (eg, a thin film for a phase change memory or a thin film for a variable resistance memory).

21 is a circuit diagram illustrating a part of a 3D semiconductor memory device according to example embodiments. As shown in FIG. 3 , a cell array of a 3D semiconductor memory device according to example embodiments may include memory cells arranged in a 3D manner. However, to avoid complexity in the drawing, FIG. 20 exemplarily shows a portion of a cell array. Also, for brevity of description, descriptions of the same technical features as the cell array of the 3D semiconductor memory device described above with reference to FIG. 3 may be omitted.

Referring to FIG. 21 , the string selection line SSL may be an electrode EL located on the uppermost layer in the stacked structures ST described with reference to FIGS. 14A and 14B . The uppermost electrode EL may form gate electrodes of string select transistors SST that control electrical connections between the bit line BL and the vertical structures VS.

The ground selection line GSL may be an electrode EL positioned at the lowest layer in the stacked structures ST described with reference to FIGS. 14A and 14B . The lowermost electrode EL may form gate electrodes of ground selection transistors GSTa and GSTb that control electrical connections between the common source region CSR and the vertical structures VS. In one example, each of the ground select transistors GSTa and GSTb may include two serially connected transistors, and gate electrodes of the two transistors may be connected to one ground select line. That is, one ground selection transistor includes a vertical transistor GSTa using the lower semiconductor pattern LSP of the vertical structure as a channel and a horizontal transistor GSTb using the substrate 10 adjacent to the lower semiconductor pattern LSP as a channel. ) may be included.

In addition, the word lines WL may be electrodes EL between the electrode EL of the uppermost layer and the electrode EL of the lowermost layer in the stacked structures ST described with reference to FIGS. 14A and 14B . . The electrodes EL between the electrode EL of the uppermost layer and the electrode EL of the lowermost layer may be combined with the vertical structures VS to form memory cells MCT.

In example embodiments, the word lines WL and the ground select line GSL may extend from the cell array area CAR to the connection area CNR. Also, as shown in FIGS. 14A and 14B , the dummy vertical structures DVS may penetrate the stacked structures ST in the connection region CNR. Accordingly, similarly to the cell strings CSTR of the cell array, the dummy strings DSTR may be disposed in the connection region CNR. In the connection region CNR, some of the word lines WL and the ground select line GSL are combined with the dummy vertical structures DVS described with reference to FIGS. 14A and 14B to form a dummy string DSTR. can be configured. Here, the dummy strings DSTR may be electrically floating with the bit line.

According to example embodiments, the horizontal transistor GSTb of the cell string CSTR and the horizontal transistor GSTb of the dummy string DSTR may be electrically connected in common to one ground select line GSL. A voltage of the ground selection line GSL may be an electrode of a lowermost layer of the stacked structures ST described with reference to FIGS. 14A and 14B . The lowermost electrode controls the potential of the substrate 10, and the threshold voltage of the horizontal transistors may vary according to the thickness of the horizontal gate insulating layer ILDb described with reference to FIGS. 14A and 14B. According to embodiments, the horizontal gate insulating layer ILDb is in contact with the oxidation suppression layer 11, and thus, the horizontal gate insulating layer ILDb is substantially uniform in the cell array region CAR and the connection region CNR. can have thickness. That is, a thickness deviation of the horizontal gate insulating layer ILDb in the cell array region CAR and the connection region CNR may be reduced. Therefore, threshold voltage distribution of ground select transistors connected to the common ground select line GSL in the cell array area CAR and the connection area CNR may be improved.

19A and 19B are views for explaining another example of a 3D semiconductor memory device according to embodiments of the present invention, and are enlarged views of portions A and B of FIGS. 13A and 13B , respectively. For brevity of description, descriptions of the same technical features as the manufacturing method of the 3D semiconductor memory device described above with reference to FIGS. 5A to 14A and 5B to 14B may be omitted.

Referring to FIGS. 19A and 19B , the substrate 10 may further include a channel impurity region 11P under the oxidation suppression layer 11 . In other words, the oxidation suppression layer 11 may be disposed between the horizontal gate insulating layer ILDb and the channel impurity region 11P. The channel impurity region 11P may include impurities of the same conductivity type as the well impurity layer 10P, and the impurity concentration of the channel impurity region 11P may be greater than that of the well impurity layer 10P. The channel impurity region 11P may be used as a channel of a ground select transistor using a lowermost electrode as a gate electrode. The threshold voltage of the ground select transistor using the lowermost electrode as a gate electrode may be controlled according to the impurity concentration of the channel impurity region 11P. In addition, the concentration of impurities of the first conductivity type in the channel impurity region 11P may be greater than the concentration of an oxidation suppression material (eg, carbon (C)) in the oxidation suppression layer 11 .

FIG. 22 is a cross-sectional view illustrating another example of a 3D semiconductor memory device according to embodiments of the present invention, taken along the line II′ of FIG. 4 . For brevity of description, descriptions of the same technical features as the manufacturing method of the 3D semiconductor memory device described above with reference to FIGS. 5A to 14A and 5B to 14B may be omitted.

Referring to FIG. 22 , the stacked structures ST include a horizontal gate insulating layer ILDb on the upper surface of the substrate 10 and electrodes and insulating layers alternately stacked on the horizontal gate insulating layer ILDb. The substrate 10 may include an oxidation suppression layer 11 including an oxidation suppression material such as carbon (C), nitrogen (N), or fluorine (F).

In one example, the oxidation suppression layer 11 may be formed in the substrate 10 of the cell array region CAR, and the horizontal gate insulating layer ILDb is in contact with the oxidation suppression layer 11 in the cell array region CAR. and may contact the well impurity layer 10P in the connection region CNR. In the cell array region CAR, the lower semiconductor patterns LSP of the vertical structure may pass through the oxidation suppression layer 11 and be connected to the well impurity layer 10P.

In one example, the oxidation inhibitor layer 11 may suppress an increase in the thickness of the horizontal gate insulating layer ILDb in the cell array region CAR during the thermal oxidation process described with reference to FIGS. 16A and 16B . Therefore, when the oxidation amount in the cell array region CAR is large in the connection region CNR, the thickness deviation of the horizontal gate insulating layer ILDb between the cell array region CAR and the connection region CNR may be reduced.

23A and 23B are cross-sectional views illustrating another example of a 3D semiconductor memory device according to embodiments of the present invention, which are cross-sectional views taken along lines II' and II-II' of FIG. 4 , respectively. 24A and 24B are enlarged views of portions A and B of FIG. 23A, respectively, and FIG. 24C is an enlarged view of portion C of FIG. 23B. For brevity of description, descriptions of the same technical features as the manufacturing method of the 3D semiconductor memory device described above with reference to FIGS. 5A to 14A and 5B to 14B may be omitted.

Referring to FIGS. 23A and 23B , an oxidation suppression layer 11 is included in the substrate 10 of the cell array region (CAR) and the connection region (CNR), and the oxidation suppression layer 11 extends in one direction. Stacked structures ST may be disposed.

Each of the stacked structures ST may include a horizontal gate insulating layer ILDb contacting the oxidation suppression layer 11 and electrodes and insulating layers alternately stacked on the horizontal gate insulating layer ILDb.

In the cell array region CAR, vertical structures may pass through the stacked structures ST and be connected to the well impurity layer 10P, and in the connection region CNR, the dummy vertical structures may pass through the stacked structures ST. It may penetrate and contact the well impurity layer 10P. In this embodiment, the lower semiconductor patterns LSPs of the vertical structures may be omitted.

That is, each of the vertical structures VS includes a first semiconductor pattern SP1 and a first semiconductor pattern SP1 contacting the well impurity layer 10P, as shown in FIGS. 24A, 24B, and 24C. and a second semiconductor pattern SP2 interposed between the data storage layer DS. The first semiconductor pattern SP1 may have a pipe-shaped or macaroni-shaped shape with a closed lower end, and the inside of the first semiconductor pattern SP1 is formed by the buried insulating pattern VI. can be filled The first semiconductor pattern SP1 may contact the inner wall of the second semiconductor pattern SP2 and the upper surface of the well impurity layer 10P. That is, the first semiconductor pattern SP1 may electrically connect the second semiconductor pattern SP2 and the well impurity layer 10P. Also, the bottom surface of the first semiconductor pattern SP1 may be positioned at a level lower than the top surface of the substrate 10 . In addition, the bottom surface of the first semiconductor pattern SP1 may be positioned at a lower level than the bottom surface of the oxidation suppression layer 11 . The second semiconductor pattern SP2 may have a pipe shape or a macaroni shape with open top and bottom ends. The first and second semiconductor patterns SP1 and SP2 may be undoped or doped with impurities having the same conductivity type as the horizontal semiconductor layer 100 . The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be in a polycrystalline state or a single crystal state.

25 is a schematic block diagram of a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 25 , a 3D semiconductor memory device according to example embodiments includes a peripheral logic structure PS and a cell array structure CS, and the cell array structure CS is stacked on the peripheral logic structure PS. It can be. That is, the peripheral logic structure PS and the cell array structure CS may overlap each other in a plan view.

In embodiments, the peripheral logic structure PS may include row and column decoders 2 and 4 , a page buffer 3 , and control circuits 5 described with reference to FIG. 1 . The cell array structure CS may include a plurality of memory blocks BLK0 to BLKn that are data erasing units. The memory blocks BLK1 to BLKn may include a structure stacked along a third direction D3 on a plane extending along the first and second directions D1 and D2. Each of the memory blocks BLK1 to BLKn includes a memory cell array having a 3D structure (or vertical structure). The memory cell array may include a plurality of three-dimensionally arranged memory cells described with reference to FIG. 2 and a plurality of word lines and bit lines electrically connected to the memory cells.

26 is a cross-sectional view of a 3D semiconductor memory device according to example embodiments described with reference to FIG. 25 . For brevity of description, descriptions of the same technical features as the manufacturing method of the 3D semiconductor memory device described above with reference to FIGS. 5A to 14A and 5B to 14B may be omitted.

Referring to FIG. 25 , a peripheral logic structure PS and a cell array structure CS may be sequentially stacked on the semiconductor substrate 10 . In other words, the peripheral logic structure PS may be disposed between the semiconductor substrate 10 and the cell array structure CS when viewed vertically. That is, the peripheral circuit area PR and the cell array area CAR may overlap each other in a plan view.

The semiconductor substrate 10 may be a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, or It may be a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

As described with reference to FIG. 1 , the peripheral logic structure PS may include row and column decoders (see 2 and 4 of FIG. 1 ), a page buffer (see 3 of FIG. 1 ), and control circuits. That is, the peripheral logic structure PS may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the cell array structure CS. These peripheral circuits may be formed on the entire surface of the semiconductor substrate 10 . In addition, the semiconductor substrate 10 may include an n-well region nw doped with n-type impurities and a p-well region pw doped with p-type impurities. Active regions ACT may be defined in the n-well region nw and the p-well region pw by the device isolation layer 11 .

The peripheral logic structure PS includes peripheral gate electrodes PG, source and drain impurity regions on both sides of the peripheral gate electrodes PG, peripheral circuit plugs CP, peripheral circuit lines ICL, and peripheral circuits. It may include a lower filling insulating film 90 covering them. More specifically, PMOS transistors may be formed on the n-well region nw, and NMOS transistors may be formed on the p-well region pw. The peripheral circuit wires ICL may be electrically connected to peripheral circuits through peripheral circuit plugs CP. For example, peripheral circuit plugs CP and peripheral circuit wires ICL may be connected to the NMOS and PMOS transistors.

The lower filling insulating layer 90 may cover peripheral circuits, peripheral circuit plugs CP, and peripheral circuit lines ICL. The lower filling insulating layer 90 may include insulating layers stacked in multiple layers.

The cell array structure CS is disposed on the lower filling insulating layer 90 and includes the horizontal semiconductor layer 100 , stacked structures ST, and vertical structures VS.

The horizontal semiconductor layer 100 may be formed on an upper surface of the lower buried insulating layer 90 covering peripheral circuits. That is, the lower surface of the horizontal semiconductor layer 100 may contact the lower buried insulating layer 90 . As described with reference to FIG. 4 , the horizontal semiconductor layer 100 may include a cell array region CAR and a connection region CNR disposed adjacent to the cell array region CAR.

The horizontal semiconductor layer 100 may be made of a semiconductor material, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or at least one of mixtures thereof. In addition, the horizontal semiconductor layer 100 may include a semiconductor doped with impurities of the first conductivity type and/or an intrinsic semiconductor in a state in which impurities are not doped. In addition, the horizontal semiconductor layer 100 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline.

In one example, the horizontal semiconductor layer 100 may include an oxidation suppression layer 11 , and stacked structures ST may be disposed on the oxidation suppression layer 11 .

As described with reference to FIG. 4 , the stacked structures ST may extend side by side in the first direction D1 on the horizontal semiconductor layer 100 and be spaced apart from each other in the second direction D2 . Each of the stacked structures ST includes electrodes EL vertically stacked on the horizontal semiconductor layer 100 and insulating films ILD interposed therebetween, and as described above, an oxidation suppression layer on the lowermost layer. (11) may include a horizontal gate insulating layer ILDb in contact with.

For electrical connection between the electrodes EL and the peripheral logic structure PS, the stacked structures ST may have a stepped structure in the connection region CNR, as described above. An upper filling insulating layer 120 covering ends of the electrodes EL having a stepped structure may be disposed on the horizontal semiconductor layer 100 . In addition, the capping insulating layer 125 may cover the plurality of stacked structures ST and the upper filling insulating layer 120 . Furthermore, bit lines BL extending in the second direction D2 across the stacked structures ST may be disposed on the capping insulating layer 125 . The bit lines BL may be electrically connected to the vertical structure VS through the bit line contact plug BPLG.

The vertical structures VS may be electrically connected to the horizontal semiconductor layer 100 through each of the stacked structures ST. In one example, each of the vertical structures may include a lower semiconductor pattern LSP and an upper semiconductor pattern USP. In contrast, each of the vertical structures is a first semiconductor pattern connected to the horizontal semiconductor layer through the stacked structures ST as described with reference to FIGS. 23A, 23B, 24A, 24B, and 24C . and a second semiconductor pattern interposed between the stacked structures ST and the first semiconductor pattern.

A data storage layer DS may be disposed between the stacked structures ST and the vertical structures VS.

The common source regions CSR may be disposed in the horizontal semiconductor layer 100 between adjacent stacked structures ST. The common source regions CSR may extend in the first direction D1 parallel to the stacked structures ST. The common source regions CSR may be formed by doping impurities of the second conductivity type into the horizontal semiconductor layer 100 .

The common source plug CSP may be connected to the common source region CSR. A sidewall insulation spacer SP may be interposed between the common source plug CSP and the stacked structures ST. For example, the common source plug CSP may extend in the first direction D1, and the sidewall insulation spacer SP may extend between the stacked structures ST and the common source plug CSP in the first direction D1. can be extended to As another example, the sidewall insulation spacer SP may fill between adjacent stacked structures ST, and the common source plug CSP penetrates the sidewall insulation spacer SP to form a common source region CSR and a local area. can be connected to.

The pick-up areas 10PU may be spaced apart from the stacked structures ST and disposed in the horizontal semiconductor layer 100 . The pickup regions 10PU may be formed by doping the first conductivity type impurities into the horizontal semiconductor layer 100 . The pickup regions 10PU may have the same conductivity type as the horizontal semiconductor layer 100 , and the impurity concentration in the pickup regions 10PU may be higher than that in the horizontal semiconductor layer 100 .

Wiring structures for electrically connecting the cell array structure CS and the peripheral logic structure PS may be disposed at ends of the stacked structures ST having a stepped structure. An upper filling insulating film 120 covering ends of the stacked structures ST may be disposed on the horizontal semiconductor layer 100, and the wiring structure penetrates the upper filling insulating film 120 to reach the ends of the electrodes EL. includes contact plugs PLG and connection lines CL connected to the contact plugs PLG on the upper filling insulating layer 120 . Vertical lengths of the contact plugs PLG may decrease as they are closer to the cell array region CAR.

In addition, pickup contact plugs PPLG may pass through the upper filling insulating layer 120 and be connected to the pickup regions 10PU. The pickup regions 10PU may be formed in the horizontal semiconductor layer 100 and may include impurities of the same conductivity type as the horizontal semiconductor layer 100 . Here, the impurity concentration of the pickup regions 10PU may be higher than that of the horizontal semiconductor layer 100 .

Top surfaces of the pickup contact plugs PPLG may be substantially coplanar with the top surfaces of the contact plugs PLG. The pickup contact plug PPLG may be connected to the peripheral logic structure PS through the well conductive line PCL and the connection plug CPLG.

The connection plug CPLG may electrically connect the cell array structure CS and the peripheral logic structure PS. The connection plug CPLG may pass through the upper filling insulating layer 120 and the horizontal semiconductor layer 100 and be connected to the peripheral circuit lines ICL of the peripheral logic structure PS.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

Board;
an impurity layer including impurities provided in the substrate and adjacent to an upper surface of the substrate;
stacked structures disposed on the impurity layer and including a horizontal gate insulating layer and insulating layers and electrodes vertically alternately stacked on the horizontal gate insulating layer; and
A three-dimensional semiconductor memory device including a plurality of vertical structures passing through the stacked structures and connected to the substrate. According to claim 1,
Lower surfaces of the vertical structures are positioned below lower surfaces of the impurity layer. According to claim 1,
The impurity layer includes carbon (C), nitrogen (N), or fluorine (F). According to claim 1,
Each of the vertical structures includes a lower semiconductor pattern connected to the substrate through a lower portion of the stack structure and the impurity layer, and an upper semiconductor pattern connected to the lower semiconductor pattern through an upper portion of the stack structure. A three-dimensional semiconductor memory device comprising: According to claim 4,
Further comprising a vertical gate insulating film between the lower semiconductor pattern and the electrodes,
The horizontal and vertical gate insulating films are thermally oxidized films. According to claim 4,
A distance between a sidewall of the lower semiconductor pattern and a sidewall of the electrode adjacent thereto is substantially equal to a distance between a lower surface of the electrode and an upper surface of the impurity layer. According to claim 1,
The horizontal gate insulating layer has a thickness smaller than the minimum thickness of the insulating layers. According to claim 1,
The substrate includes impurities of a first conductivity type,
the device further comprising common source regions disposed in the substrate between the stacked structures;
The common source regions include impurities of a second conductivity type. According to claim 1,
The 3D semiconductor memory device further comprising a data storage layer disposed between the vertical structures and the electrodes. According to claim 1,
The substrate includes a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region,
the stacked structures and the impurity layer extend from the cell array region to the connection region;
The three-dimensional semiconductor memory device of claim 1 , wherein the stacked structure in the connection region has a stepped structure descending toward the peripheral circuit region. According to claim 10,
The substrate includes a connection region between the cell array region and the peripheral circuit region, and the horizontal gate insulating layer has substantially the same thickness in the cell array region and the connection region. According to claim 10,
A peripheral logic structure including peripheral logic circuits disposed on the substrate in the peripheral circuit area and a peripheral insulating pattern covering the peripheral logic circuits;
The impurity layer extends from the cell array region to a region between the stacked structures and the peripheral logic structure. According to claim 12,
Further comprising a buried insulating film covering ends of the electrodes positioned in the connection area and the peripheral logic structure,
The buried insulating layer covers the impurity layer between the stacked structures and the peripheral logic structure. According to claim 10,
The 3D semiconductor memory device further comprises dummy vertical structures connected to the substrate by penetrating the stacked structures in the connection area. a substrate including a cell array area, a peripheral circuit area, and a connection area between the cell array area and the peripheral circuit area;
laminated structures extending from the cell array region to the connection region, the laminated structures including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; and
and an impurity layer contacting the horizontal gate insulating layer and including impurities provided in the substrate. According to claim 15,
The three-dimensional semiconductor memory device of claim 1 , wherein the stacked structure in the connection region has a stepped structure descending toward the peripheral circuit region. According to claim 15,
The horizontal gate insulating layer has substantially the same thickness in the cell array region and the connection region. According to claim 15,
and a plurality of vertical structures passing through the stacked structures and the impurity layer in the cell array region and contacting the substrate. According to claim 18,
Each of the vertical structures includes a lower semiconductor pattern connected to the substrate through a lower portion of the stack structure and the impurity layer, and an upper semiconductor pattern connected to the lower semiconductor pattern through an upper portion of the stack structure. A three-dimensional semiconductor memory device comprising: According to claim 19,
Further comprising a vertical gate insulating film between the lower semiconductor pattern and the electrodes,
The horizontal and vertical gate insulating films are thermally oxidized films.

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