KR20170042452A - Three dimensional semiconductor device - Google Patents

Abstract

Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes an oxidation inhibiting layer disposed in a substrate; stacking structures disposed on the oxidation inhibiting layer and including electrodes and insulating films to be vertically alternately stacked on a vertical gate insulating film and a horizontal gate insulating film; and a plurality of vertical structures connected to the substrate through the stacked structures.

Description

A three-dimensional semiconductor memory device

The present invention relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device with improved reliability and integration.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor devices, the degree of integration is an important factor in determining the price of the product, and therefore, an increased degree of integration is required in particular. In the case of a two-dimensional or planar semiconductor device, its degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of fine patterning technology. However, the integration of the two-dimensional semiconductor device is increasing, but is still limited, because of the high-cost equipment required to miniaturize the pattern. Accordingly, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed.

A third object of the present invention is to provide a three-dimensional semiconductor memory device with improved reliability.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a three-dimensional semiconductor memory device including: an oxidation suppressing layer disposed in a substrate; A plurality of stacked structures disposed on the oxidation-inhibiting layer and including insulating films and electrodes vertically stacked on the horizontal gate insulating film and the horizontal gate insulating film; And a plurality of vertical structures that are connected to the substrate through the stacked structures.

According to embodiments, the lower surfaces of the vertical structures may be located below the lower surface of the oxidation inhibiting layer.

According to embodiments, the antioxidant layer may comprise carbon (C), nitrogen (N), or fluorine (F).

According to embodiments, the horizontal gate insulating layer may be in direct contact with the oxidation inhibiting layer.

According to the embodiments, each of the vertical structures may include: a lower semiconductor pattern penetrating the lower portion of the laminated structure and the oxidation-inhibiting layer and connected to the substrate; and a lower semiconductor pattern penetrating the upper portion of the laminated structure, And an upper semiconductor pattern connected to the upper semiconductor pattern.

According to embodiments, the lower semiconductor pattern may further include a vertical gate insulating film between the electrodes, wherein the horizontal and vertical gate insulating films may be a thermal oxide film.

According to embodiments, the distance between the sidewall of the lower semiconductor pattern and the sidewall of the electrode adjacent thereto may be substantially the same as the distance between the lower surface of the electrode and the upper surface of the oxidation inhibiting layer.

According to embodiments, the horizontal gate insulating layer may have a thickness smaller than the minimum thickness of the insulating layers.

According to embodiments, the oxidation-inhibiting layer may have a thickness smaller than the thickness of the horizontal gate insulating film.

According to embodiments, the substrate includes impurities of a first conductivity type, and the device further includes common source regions disposed in the substrate between the stacked structures, wherein the common source regions are of a second conductivity type Lt; / RTI >

According to embodiments, the data structure may further include a data storage layer disposed between the vertical structures and the electrodes.

According to embodiments, the substrate includes a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region, wherein the stacked structures and the oxidation inhibition layer are formed in the cell array region And the stacked structure may extend in the connection region, and the stacked structure may have a stepwise structure in which the stacked structure moves down toward the peripheral circuit region.

According to embodiments, the substrate may include a connection region between the cell array region and the peripheral circuit region, and the horizontal gate insulation film may have substantially the same thickness at the cell array region and the connection region.

According to embodiments, the apparatus further comprises peripheral logic structures disposed on the substrate of the peripheral circuitry region, the peripheral logic structure including a peripheral insulation pattern covering the peripheral logic circuits, wherein the oxidation- Lt; RTI ID = 0.0 > region < / RTI > between the stacked structures and the peripheral logic structure.

According to embodiments, the method further includes a buried insulating layer covering the ends of the electrodes located in the connection region and the peripheral logic structure, wherein the buried insulating layer is formed between the stacked structures and the peripheral logic structure, .

According to embodiments, the connecting region may further include dummy vertical structures that are connected to the substrate through the stacking structures.

According to an aspect of the present invention, there is provided a three-dimensional semiconductor memory device including: a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region; The stacked structures extending from the cell array region to the connection region, wherein the stacked structures include stacked structures including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; And an oxidation inhibiting layer provided in the substrate in contact with the horizontal gate insulating film.

According to embodiments, the stacked structure may have a stepped structure in which the stacked structure is downward toward the peripheral circuit region in the connection region.

According to embodiments, the horizontal gate insulating layer may have substantially the same thickness in the cell array region and the connection region.

According to embodiments, the substrate may further include a plurality of vertical structures in contact with the substrate through the stacked structures and the oxidation-inhibiting layer in the cell array region.

According to the embodiments, each of the vertical structures may include: a lower semiconductor pattern penetrating the lower portion of the laminated structure and the oxidation-inhibiting layer and connected to the substrate; and a lower semiconductor pattern penetrating the upper portion of the laminated structure, And an upper semiconductor pattern connected to the upper semiconductor pattern.

According to embodiments, the lower semiconductor pattern may further include a vertical gate insulating film between the electrodes, wherein the horizontal and vertical gate insulating films may be a thermal oxide film.

According to embodiments, the data structure may further include a data storage layer disposed between the vertical structures and the electrodes.

According to embodiments, the semiconductor device further includes a peripheral logic structure spaced apart from the stacked structures and disposed on the substrate of the peripheral circuit region, wherein the oxidation inhibiting layer is disposed between the stacked structures and the peripheral logic structure, .

According to embodiments, the oxidation-inhibiting layer may have a thickness smaller than the thickness of the horizontal gate insulating film.

According to embodiments, the antioxidant layer may comprise carbon (C), nitrogen (N), or fluorine (F).

The details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, by forming the oxidation-suppressing layer in the substrate below the horizontal gate insulating film, the horizontal gate insulating film extending from the cell array region to the connecting region can have a substantially uniform thickness. The threshold voltage distribution of the ground selection transistors provided in the cell array region and the connection region can be reduced.

1 is a view for explaining a schematic arrangement structure of a three-dimensional semiconductor memory device according to embodiments of the present invention.
2 is a block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.
3A and 3B are simplified circuit diagrams of a three-dimensional semiconductor memory device according to embodiments of the present invention.
4 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIGS. 5A to 14A are cross-sectional views taken along line I-I 'of FIG. 4, illustrating a method for fabricating a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIGS. 5B to 14B are cross-sectional views of a three-dimensional semiconductor memory device according to embodiments of the present invention, taken along line II-II 'of FIG.
Figs. 15A to 17A are enlarged views of portions A in Figs. 11A to 13A, respectively.
Figs. 15B to 17B are enlarged views of portions B in Figs. 11B to 13B, respectively.
18 is an enlarged view of a portion C in Fig. 14B.
FIGS. 19A and 19B are views for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention, and enlarged portions A and B of FIGS. 13A and 13B, respectively.
FIGS. 20A to 20E are diagrams for explaining the data storage film structure of the three-dimensional semiconductor memory device according to the embodiments of the present invention, and enlarged part D of FIG. 14B.
21 is a circuit diagram showing a part of a three-dimensional semiconductor memory device according to the embodiments of the present invention.
22 is a sectional view for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention, taken along the line I-I 'in FIG.
23A and 23B are cross-sectional views taken along lines I-I 'and II-II' in FIG. 4, respectively, for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention.
24A and 24B are enlarged views of portions A and B of FIG. 23A, respectively, and FIG. 24C is an enlarged view of portion C of FIG. 23B.
25 is a schematic block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.
26 is a cross-sectional view of a three-dimensional semiconductor memory device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a view for explaining a schematic arrangement structure of a three-dimensional semiconductor memory device according to embodiments of the present invention.

2 is a block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a semiconductor memory device includes a cell array region CAR, and a peripheral circuit region. The peripheral circuit region includes row decoder regions (ROW DCR), a page buffer region (PBR), and a column decoder region (COL DCR). In addition, a connection area CNR may be disposed between the cell array area CAR and the row decoder areas ROW DCR.

Referring to FIGS. 1 and 2, a memory cell array composed of a plurality of memory cells is arranged in the cell array region CAR. The memory cell array includes a plurality of memory cells and a plurality of word lines and bit lines electrically coupled to the memory cells. The memory cell array may include a plurality of memory blocks BLK0 to BLKn, which are data erase units. The memory cell array will be described in detail with reference to Fig.

In the row decoder region (ROW DCR), a row decoder 2 for selecting the word lines of the memory cell array is disposed. A wiring structure for electrically connecting the memory cell array and the row decoder 2 may be disposed in the connection region CNR. The row decoder 2 selects one of the memory blocks BLK0 to BLKn of the memory cell array and selects one of the word lines of the selected memory block according to the address information. The row decoder 2 may provide a word line voltage generated from a voltage generating circuit (not shown) to selected word lines and unselected word lines, respectively, in response to control of a control circuit (not shown).

The page buffer area PBR may be provided with a page buffer 3 for reading information stored in the memory cells. The page buffer 3 may temporarily store data to be stored in the memory cells or sense data stored in the memory cells, depending on the operation mode. The page buffer 3 operates as a write driver circuit in a program operation mode and as a sense amplifier circuit in a read operation mode.

In the column decoder area (COL DCR), a column decoder (4) connected to the bit lines of the memory array is disposed. The column decoder 4 can provide a data transmission path between the page buffer 3 and an external device (for example, a memory controller).

3 is a circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.

3, a cell array of a semiconductor memory device according to an exemplary embodiment is disposed between a common source line CSL, a plurality of bit lines BL, and a common source line CSL and bit lines BL And may include a plurality of cell strings (CSTR).

The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL and one common source line CSL. According to an example, the common source lines CSL may be arranged two-dimensionally in plural. Here, electrically common voltages may be applied to the common source lines CSL, or each common source line CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and ground and string selection transistors GST and SST And a plurality of memory cell transistors MCT arranged between the plurality of memory cell transistors MCT. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, the ground selection line GSL, the plurality of word lines WL0-WL3 and the plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit lines BL, As the gate electrodes of the selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a data storage element.

4 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 5A to 14A and FIGS. 5B to 14B are cross-sectional views illustrating a method for fabricating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 5A to 14A are cross- And FIGS. 5B to 14B are cross-sectional views taken along line II-II 'of FIG. 4, respectively.

Figs. 15A to 17A are enlarged views of portions A of Figs. 11A to 13A, respectively, and Figs. 15B to 17B are enlarged views of portions B of Figs. 11B to 13B, respectively. 18 is an enlarged view of a portion C in Fig. 14B.

4, 5A, and 5B, the substrate 10 may include a cell array area CAR, a connection area CNR, and a peripheral circuit area PR. The connection region CNR may be located between the cell array region CAR and the peripheral circuit region PR.

The substrate 10 may be one of a semiconductor material having a semiconductor property (e.g., a silicon wafer), an insulating material (e.g., glass), or a semiconductor or a conductor covered with an insulating material. For example, the substrate 10 may be a silicon wafer having a first conductivity type.

Peripheral logic circuits for writing and reading data to and from the memory cells on the substrate 10 of the peripheral circuit region PR may be formed. Peripheral logic circuits include row and column decoders (see 2 and 4 in FIG. 2), page buffers (see 3 in FIG. 2), and control circuits (see 5 in FIG. 2) can do. That is, the peripheral logic circuits may include NMOS and PMOS transistors, resistors, and capacitors that are electrically coupled to the memory cells.

For example, the device isolation film 21 defining the peripheral active region ACT may be formed on the substrate 10 of the peripheral circuit region PR. A peripheral gate insulating film 22 may be formed between the peripheral gate electrode 23 and the peripheral gate electrode 23 across the peripheral active region ACT and the substrate 10. [ The peripheral gate electrode 23 may be formed of doped polysilicon, metal silicide, or a metal material, and the peripheral gate insulating film 22 may be a silicon oxide film formed by a thermal oxidation process. Further, the source / drain regions 24 may be formed by doping the active region ACT on both sides of the peripheral gate electrode 23 with an impurity.

After the peripheral logic circuits are formed on the substrate 10 of the peripheral circuit region PR, the peripheral insulating film 25 covering the entire surface of the substrate 10 may be formed. The peripheral insulating film 25 may include a plurality of insulating films, and may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low-k film.

Referring to FIGS. 4, 6A, and 6B, the peripheral insulating film 25 is patterned to form a peripheral insulating pattern 25P that exposes the substrate 10 of the cell array region CAR and the connecting region CNR . The peripheral logic structure PSTR may be formed on the substrate 10 of the peripheral circuit region PR by forming the peripheral insulating pattern 25P and the peripheral logic structure PSTR may be formed on the peripheral gate insulating film 22, Electrode 23, source / drain regions 24, and a peripheral insulation pattern 25P.

Specifically, the peripheral insulating pattern 25P is formed by forming a mask pattern (not shown) covering the peripheral circuit region PR on the peripheral insulating film 25 and forming the peripheral insulating film 25P by using the mask pattern as an etching mask. (25). ≪ / RTI >

In one example, the peripheral insulating film 25 may be etched using a plasma etching process. The etching process may be performed by, for example, plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or ion beam etching (IBE, Ion Beam Etching) process.

For example, fluorocarbon (CxFy) -based gas or hydrofluorocarbon (CxHyFz) -based gas may be used as the etching gas in the step of etching the peripheral insulating film 25. [ Etching gases such as, for example, CF ₄ , C ₃ F ₈ , C ₄ F ₈ , and CH ₂ F ₂ , etc. may be used.

According to the embodiments, after the peripheral insulating pattern 25P is formed, the oxidation inhibiting layer 11 may be formed on the substrate 10 exposed by the peripheral insulating pattern 25P. The oxidation-inhibiting layer 11 may be formed adjacent to the surface of the substrate 10. For example, the oxidation-inhibiting layer 11 may include an oxidation inhibiting substance such as carbon (C), nitrogen (N), or fluorine (F). In addition, the oxidation-inhibiting layer 11 may have a thickness of about 50 Å to about 150 Å.

According to one example, when the peripheral insulating film 25 is plasma-etched using the etching gas containing carbon and fluorine, the carbon contained in the etching gas can be ionized. At this time, the carbon ions penetrate into the surface of the substrate 10 exposed by the peripheral insulating pattern 25P, so that the oxidation inhibiting layer 11 can be formed on the surface of the substrate 10. That is, the oxidation-inhibiting layer 11 may be formed in situ during the etching process of the peripheral insulating pattern 25P. When the oxidation-inhibiting layer 11 is formed as described above, the carbon concentration in the oxidation-inhibiting layer 11 may vary depending on the RF power during the etching process using the plasma. For example, when the RF power is increased during the plasma etching process, the amount of carbon penetrating the surface of the substrate 10 exposed to the peripheral insulating pattern 25P may be increased.

According to another example, the oxidation-inhibiting layer 11 may be formed by ion implanting the oxidation inhibiting material into the substrate 10 using the peripheral insulating pattern 25P as an ion implantation mask.

Furthermore, according to the embodiments, after the peripheral insulating pattern 25P is formed, the well impurity layer 10P of the first conductivity type may be formed in the substrate 10 exposed by the peripheral insulating pattern 25P . That is, the well impurity layer 10P may be formed in the substrate 10 of the cell array region CAR and the connection region CNR. The well impurity layer 10P may be formed by doping an impurity of the first conductivity type into the substrate 10. [ When the well impurity layer 10P is formed, the substrate 10 may include a second conductive semiconductor layer (not shown), and the well impurity layer 10P may be formed in the second conductive semiconductor layer have.

In another example, the oxidation-inhibiting layer 11 may be formed by doping the oxidation inhibiting material with the substrate 10 while forming the well impurity layer 10P.

4, 7A, and 7B, the mold structure 100 may be formed on the substrate 10 with the mold structure 100 extending from the cell array area CAR to the connection area CNR . The mold structure 100 in the connection region CNR may have a stepped structure in which the height thereof decreases in the vicinity of the peripheral circuit region PR.

In detail, forming the mold structure 100 may include forming a thin film structure on the front surface of the substrate 10 and performing a trimming process on the thin film structure.

In one example, the thin film structure may extend from the top surface of the substrate 10 of the cell array region CAR to the top surface of the peripheral logic structure PSTR. The thin film structure may include the buffer insulating layer ILDa on the surface of the substrate 10 and the sacrificial layers SL and the insulating layers ILD alternately stacked on the buffer insulating layer ILDa. The buffer insulating film ILDa may be a silicon oxide film, and may be formed using a thermal oxidation process or a deposition process. In the embodiments, the buffer insulating film ILDa may be formed on the oxidation-inhibiting layer 11 and may be in direct contact with the oxidation-inhibiting layer 11.

In the thin film structure, the sacrificial films SL can be formed of a material which can be etched with etching selectivity to the insulating films ILD. For example, sacrificial films (SL) and insulating films (ILD) have a high etch selectivity in a wet etch process using a chemical solution and can have a low etch selectivity in a dry etch process using an etch gas. In one example, the sacrificial films SL and the insulating films ILD are formed of an insulating material, and may have etch selectivity with respect to each other. That is, the sacrificial films SL may be made of an insulating material different from the insulating films ILD. For example, the sacrificial films SL may be at least one of a silicon film, a silicon oxide film, a silicon carbide, a silicon germanium film, a silicon oxynitride film, and a silicon nitride film. The insulating films ILD are at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, and may be a material different from the sacrificial films SL. For example, the sacrificial films SL may be formed of a silicon nitride film, and the insulating films ILD may be formed of a low dielectric film. Alternatively, the sacrificial films SL may be formed of a conductive material, and the insulating films ILD may be formed of an insulating material.

The sacrificial layers SL and the insulating layers ILD may be formed by thermal CVD, plasma enhanced CVD, physical CVD, or atomic layer deposition (ALD) Technique. ≪ / RTI >

In the thin film structure, the sacrificial films SL may have the same thickness. Alternatively, the sacrificial films SL of the lowermost layer and the uppermost layer among the sacrificial films SL may be formed thicker than the sacrificial films SL located therebetween. Further, the insulating films ILD may have the same thickness, or some of the insulating films ILD may have different thicknesses. In addition, the buffer insulating film ILDa formed at the lowermost layer of the thin film structure may have a thickness thinner than the sacrificial films SL and the insulating films ILD formed thereon.

Then, a trimming process may be performed to pattern the thin film structure so as to have a stepwise structure in the connection region CNR. Specifically, the trimming process includes a process of forming a mask pattern (not shown) covering the thin film structure in the cell array region CAR and the connection region CNR, a process of etching the thin film structure, a process of reducing the horizontal area of the mask pattern And alternately repeating the step of etching the thin film structure and the step of reducing the horizontal area of the mask pattern. The mold structure 100 may be formed on the substrate 10 of the cell array area CAR and the connection area CNR by performing the trimming process. The mold structure 100 may be spaced apart from the peripheral logic structure PSTR and the substrate 10 between the mold structure 100 and the peripheral logic structure PSTR may be exposed. The mold structure 100 may have a stepped structure in which the mold structure 100 descends from the connection region CNR toward the peripheral circuit region PR. That is, the ends of the insulating films ILD and the sacrificial films SL may be located in the connection region CNR, and the areas of the insulating films ILD and the sacrificial films SL may be located on the upper surface Can be reduced. In other words, the height of the mold structure 100 may decrease from the connection region CNR to the peripheral circuit region PR.

7A and 7B, a buried insulating film 120 covering the mold structure 100 and the peripheral logic structure PSTR may be formed on the entire surface of the substrate 10. The buried insulating film 120 may be formed of an insulating material having etch selectivity to the sacrificial films.

The formation of the buried insulating film 120 may include depositing an insulating film over the entire surface of the substrate 10 to cover the mold structure 100 and the peripheral logic structure PSTR and planarizing the upper surface of the insulating film . That is, the buried insulating film 120 is formed on the surface of the mold structure 100 in the connection region CNR. The ends of the sacrificial films and the peripheral logic structure (PSTR) in the peripheral circuit region PR, and may have a planarized top surface. Further, in one example, the buried insulating film 120 may cover a portion of the oxidation inhibiting layer 11 exposed between the mold structures 100 and the surrounding logic structure PSTR.

The buried insulating film 120 may be formed of a high density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O3-TEOS (O3-Tetra Ethyl Ortho Silicate) A phosphosilicate glass (PSG), a borosilicate glass (BSG), a borophosphosilicate glass (BPSG), a fluoride silicate glass (FSG), a spin on glass (SOG), a toned silaZene or a combination thereof. In addition, the buried insulating film 120 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

Referring to FIGS. 4, 8A, and 8B, a plurality of vertical holes H and DH may be formed through the mold structure 100. In one example, the vertical holes H and DH may include cell vertical holes H formed in the cell array area CAR and dummy vertical holes DH formed in the connection area CNR.

According to the embodiments, forming the vertical holes H and DH may be performed by forming a mask pattern (not shown) on the mold structure 100 and etching the mold structure (not shown) using a mask pattern (not shown) 100). ≪ / RTI > The upper surface of the substrate 10 exposed to the vertical holes H and DH may be over-etched to the upper surface of the substrate 10 in the anisotropic etching process, . And, in the embodiments, the vertical holes H and DH can penetrate the oxidation inhibiting layer 11 to expose the well impurity layer 10P in the substrate 10. Further, the bottom width of the vertical holes H and DH may be smaller than the top width of the vertical holes H and DH by the anisotropic etching process.

Furthermore, the cell vertical holes H can be arranged in one direction or arranged in a zigzag form in plan view. The dummy vertical holes DH may penetrate the ends of the buried insulating film 120 and the sacrificial layers. The dummy vertical holes HDH are formed in the connection region CNR so that the distance between the dummy vertical holes DH and the peripheral circuit region PR becomes smaller as the dummy vertical holes DH pass through the sacrificial films SL The number can be reduced.

In one example, the dummy vertical holes DH may penetrate the end portions of some of the sacrificial films SL, and may be disposed at a certain distance from each other. However, the present invention is not limited to this, and in another example, the dummy vertical holes DH may pass through the end of each sacrificial layer SL. In another example, forming the dummy vertical holes DH may be omitted.

Subsequently, a lower semiconductor pattern LSP filling the lower portion of the vertical holes H, DH may be formed.

According to the embodiments, the lower semiconductor pattern LSP can contact the well impurity layer 10P through the oxidation-inhibiting layer 11, as shown in Figs. 15A and 15B. That is, the bottom surface of the lower semiconductor pattern LSP may be located below the upper surface of the substrate 10, and further below the bottom surface of the oxidation inhibiting layer 11. In addition, the lower semiconductor pattern LSP may directly contact the one side walls of the sacrificial layers SL and the insulating films ILD located under the mold structure 100. The lower semiconductor pattern LSP may cover the side walls of at least one or more sacrificial films SL. The upper surface of the lower semiconductor pattern LSP may be positioned between vertically adjacent sacrificial layers SL.

More specifically, the lower semiconductor pattern LSP is formed by a selective epitaxial growth (SEG) process using the substrate 10 exposed to the vertical holes H and DH as a seed layer As shown in FIG. Accordingly, the lower semiconductor pattern LSP can be formed in the form of a pillar filling the lower portions of the vertical holes H and DH. In this case, the lower semiconductor pattern LSP may have a single crystal structure or have a polycrystalline structure having an increased grain size than that of the chemical vapor deposition technique. On the other hand, the material for the lower semiconductor pattern LSP may be silicon, but is not limited thereto. For example, carbon nanostructures, organic semiconductor materials, and compound semiconductors can be used for the underlying semiconductor pattern (LSP). According to other examples, the lower semiconductor pattern LSP may be formed of a semiconductor material of polycrystalline structure (for example, polycrystalline silicon).

In addition, the lower semiconductor pattern LSP may have the same conductivity type as the substrate 10. The lower semiconductor pattern LSP may be doped in-situ with impurities during the selective epitaxial growth process. Alternatively, impurities may be implanted into the lower semiconductor pattern LSP after the lower semiconductor pattern LSP is formed.

Referring to FIGS. 4, 9A and 9B, upper semiconductor patterns USP may be formed in the vertical holes H and DH where the lower semiconductor pattern LSP is formed. The vertical structures VS including the lower semiconductor pattern LSP and the upper semiconductor pattern USP may be formed in the cell vertical holes H and the lower semiconductor patterns LSP ) And an upper semiconductor pattern USP may be formed on the dummy vertical structures DVS.

More specifically, referring to FIGS. 15A and 15B, the upper semiconductor pattern USP may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The first semiconductor pattern SP1 may be connected to the lower semiconductor pattern LSP, and the lower end may be in the form of a closed pipe or a macaroni. The inside of the first semiconductor pattern SP1 in this form can be filled with the buried insulating pattern VI. In addition, the first semiconductor pattern SP1 may be in contact with the inner wall of the second semiconductor pattern SP2 and the upper surface of the lower semiconductor pattern LSP. That is, the first semiconductor pattern SP1 can electrically connect the second semiconductor pattern SP2 and the lower semiconductor pattern LSP. The second semiconductor pattern SP2 may be an open pipe shape or a macaroni shape at the upper and lower ends. Then, the second semiconductor pattern SP2 can be separated without contacting the lower semiconductor pattern LSP. The first and second semiconductor patterns SP1 and SP2 may be in an unselected state or may be doped with an impurity having the same conductivity type as that of the substrate 10. [ The first and second semiconductor patterns SP1 and SP2 may include silicon (Si), germanium (Ge), or a mixture thereof, and may be an impurity-doped semiconductor or an intrinsic semiconductor semiconductor. In addition, the first and second semiconductor patterns SP1 and SP2 may have a crystal structure including at least one selected from the group consisting of single crystal, amorphous, and polycrystalline. In one example, the first and second semiconductor patterns SP1 and SP2 may be a polycrystalline silicon film formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques.

Furthermore, a conductive pad PAD may be formed on the top of each of the upper semiconductor patterns USP. The conductive pad PAD may be an impurity region doped with an impurity, or may be made of a conductive material.

In addition, according to one example, a vertical insulating pattern VP may be formed in the vertical holes H and DH, as shown in Figs. 15A and 15B, before the upper semiconductor pattern USP is formed. The vertical insulation pattern VP may be composed of one thin film or a plurality of thin films. In embodiments of the present invention, the vertical isolation pattern VP may be part of the data storage film. For example, the vertical isolation pattern VP may comprise a charge storage film used as a memory element of a flash memory device. For example, the charge storage film may be an insulating film including a trap insulating film or conductive nano dots. Alternatively, the vertical insulating film may comprise a thin film for a phase change memory or a thin film for a variable resistance memory.

Referring to FIGS. 4, 10A and 10B, a capping insulating film 125 covering upper surfaces of the vertical structures VS and DVS may be formed on the buried insulating film 120. The capping insulating layer 125 and the mold structure 100 may then be patterned to form trenches T exposing the substrate 10. As the trenches T are formed, the mold structure 100 may have a line shape extending in one direction.

Specifically, forming the trenches T includes forming a mask pattern (not shown) that defines the planar position of the trenches T on the mold structure 100, forming a mask pattern (not shown) And anisotropically etching the mold structure 100 using the mask as a mask.

The trenches T may be spaced from the vertical structures VS and formed to expose the sidewalls of the sacrificial films SL and the insulating films ILD. In plan view, the trenches T may be formed in a line shape or a rectangle extending in a first direction D1, and in a vertical depth, the trenches T expose the top surface of the substrate 10 . The top surface of the substrate 10 exposed to the trenches T by overetch may be recessed to a predetermined depth while forming the trenches T. [ Further, the trenches T may have inclined sidewalls by an anisotropic etching process.

As the trenches T are formed, the mold structure 100 may have a line shape extending in the first direction D1. A plurality of vertical structures VS may penetrate the mold structure 100 in the form of a single line.

According to one example, after forming the trenches T, common source regions CSR may be formed in the substrate 10 exposed to the trenches T. The common source regions CSR may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. In other words, common source regions (CSR) may be formed in the well impurity layer 10P between the mold structures 100 and adjacent to the sidewalls of the mold structures 100. The common source regions (CSR) may be formed by doping the substrate 10 and other types of impurities into the substrate 10. The common source regions CSR may include, for example, an N-type impurity (for example, arsenic (As) or phosphorus (P)).

Referring to FIGS. 4, 11A, and 11B, gate regions GR may be formed between the insulating films ILD by removing the sacrificial layers SL exposed to the trenches T. FIG.

The gate regions GR are formed by etching the sacrificial films SL using an etch recipe having etching selectivity to the buffer insulating film ILDa, the insulating films ILD, the vertical structures VS, And may be formed by etching. Here, the sacrificial films SL can be completely removed by an isotropic etching process. For example, when the sacrificial films SL are silicon nitride films and the insulating films ILD are silicon oxide films, the etching step may be performed using an etchant containing phosphoric acid. In addition, the vertical isolation pattern VP can be used as an etch stop film during an isotropic etching process to form the gate regions GR. The gate regions GR formed in this way can extend horizontally from the trench T to the insulating films ILD and can be formed as part of the sidewalls of the vertical insulation pattern VP or portions of the sidewalls of the vertical structure VS Can be exposed. That is, the gate regions GR can be defined by vertically adjacent insulating films ILD and one side wall of the vertical insulation pattern VP.

According to the embodiments, the lowermost gate region among the gate regions GR may expose a part of the side wall of the lower semiconductor pattern LSP, as shown in FIGS. 15A and 15B, and the buffer insulating film ILDa, . After forming the gate regions GR, the buffer insulating film ILDa exposed in the gate region GR may have a first thickness t1, as shown in Figs. 15A and 15B. In one example, the first thickness t1 may be greater than or equal to the thickness of the oxidation-inhibiting layer 11.

Referring to FIGS. 4, 12A and 12B, a vertical gate insulating film 13 is formed on the sidewall of the lower semiconductor pattern LSP exposed in the gate region GR, A gate insulating film ILDb may be formed.

In one example, the vertical gate insulating film 13 and the horizontal gate insulating film ILDb may be formed through a heat treatment process in a gas atmosphere containing oxygen atoms. In this case, the vertical gate insulating film 13 and the horizontal gate insulating film ILDb may be selectively formed only on the surface capable of providing the silicon element.

More specifically, referring to FIGS. 16A and 16B, the vertical gate insulating film 13 may be formed by reacting oxygen atoms with silicon atoms of a lower semiconductor pattern (LSP) in a thermal oxidation process. That is, the silicon atoms of the lower semiconductor pattern LSP exposed in the gate region GR during the thermal oxidation process may be consumed. Thus, after the vertical gate insulating film 13 is formed, the width at the middle portion of the lower semiconductor pattern LSP exposed in the gate region GR may be smaller than the width at the upper portion in contact with the insulating film. Further, the vertical gate insulating film 13 may have a rounded surface.

The horizontal gate insulating film ILDb may be formed by oxygen atoms penetrating the thin buffer insulating film ILDa during the thermal oxidation process and reacting with the silicon atoms of the substrate 10. [ Accordingly, as the silicon atoms of the substrate 10 are consumed under the buffer insulating film ILDa, the thickness of the buffer insulating film ILDa may be increased to form the horizontal gate insulating film ILDb. That is, as shown in FIGS. 16A and 16B, the horizontal gate insulating film ILDb has a second thickness t2 (t2) larger than a first thickness (see t1 in FIGS. 15A and 15B) of the buffer insulating film ILDa before the thermal oxidation process ). For example, the second thickness t2 may be greater than the thickness of the oxidation inhibiting layer 11. [ The second thickness t2 may be smaller than the thickness of the insulating films ILD constituting the mold structure 100. Further, the second thickness t2 may be substantially equal to the thickness of the vertical gate insulating film 13. For example, the second thickness t2 of the horizontal gate insulating film ILDb may be about 100 ANGSTROM to 150 ANGSTROM.

Since the buffer insulating film ILDa is in contact with the oxidation preventing layer 11 in the thermal oxidation process for forming the vertical gate insulating film 13, Can be reduced. Accordingly, variations in thickness of the horizontal insulating film in the cell array region CAR and the connection region CNR can be reduced.

More specifically, due to the structural difference of the mold structure 100 in the cell array region CAR and the connection region CNR, the amount of oxygen atoms infiltrating into the substrate 10 during the thermal oxidation process is larger than that in the cell array region CAR) and the connection area (CNR). For example, since the thickness of the mold structure 100 gradually decreases in the connection region CNR and the buried insulation film 120 is disposed on the connection region CNR, 10 can be reduced compared to the amount of oxygen atoms that penetrate into the substrate 10 of the cell array region CAR. The thickness of the horizontal gate insulating film ILDb in the cell array region CAR can be increased compared to the thickness of the horizontal gate insulating film ILDb in the connection region CNR, The oxidation of the substrate 10 is suppressed in the region CAR and the region CNR so that the thickness difference of the horizontal gate insulating film ILDb in the cell array region CAR and the connection region CNR can be reduced. That is, according to one example, the horizontal gate insulating film ILDb may have substantially the same thickness (i.e., the second thickness t2) at the connection region CNR with the cell array region CAR. According to another example, The horizontal gate insulating film ILDb may be thicker in the cell array region CAR than in the connection region CNR.

In addition, since the oxygen atoms are provided to the gate region GR through the trenches T during the thermal oxidation process, the portion adjacent to the trenches T and the portion adjacent to the sidewall of the lower semiconductor pattern LSP ILDb may have different thicknesses. In other words, although the thickness of the horizontal gate insulating film ILDb may decrease from the trench T to the lower semiconductor pattern LSP, in the embodiments of the present invention, the oxidation- The variation in the thickness of the horizontal gate insulating film ILDb can be reduced at portions adjacent to the trench T and adjacent portions of the lower semiconductor pattern LSP by reducing the silicon consumption of the gate insulating film 10.

Further, since the gate regions GR adjacent to the upper semiconductor pattern USP expose the vertical insulation pattern VP during the formation of the vertical gate insulation film 13 and the horizontal gate insulation film ILDb, the upper semiconductor pattern USP And the oxide film in the adjacent gate regions GR will not be substantially formed.

4, 13A, and 13B, a horizontal insulating pattern HP may be formed that conformally covers the inner walls of the gate regions GR. 17A, 17B and 18, the horizontal insulating pattern HP may be formed with a substantially uniform thickness on the inner walls of the gate regions GR. The horizontal insulation pattern HP may be composed of one thin film or a plurality of thin films. In one example, the horizontal isolation pattern HP may be part of the data storage film of the charge trapped flash memory transistor.

Subsequently, the electrodes EL may be formed in the gate regions GR formed with the horizontal insulation pattern HP. The electrodes EL can partially fill the gate regions GR or completely fill the gate regions GR.

The formation of the electrodes EL is performed by forming a gate conductive film filling the gate regions in which the horizontal insulation pattern HP is formed and removing a part of the gate conductive film formed in the trenches T, (EL), respectively, locally. Here, each of the electrodes EL may include a barrier metal film and a metal film which are sequentially deposited. The barrier metal film may be made of a metal nitride film, for example, TiN, TaN or WN. The metal film may be made of metal materials such as, for example, W, Al, Ti, Ta, Co or Cu.

As described above, by forming the electrodes EL in the gate regions, the stacked structures ST including the insulating films ILD and the electrodes EL repeatedly alternately stacked on the substrate 10 are formed . The stacked structures ST extend in the first direction D1 and the sidewalls of the stacked structures ST can be exposed to the trench T. [ Further, the substrate 10 can be exposed between the adjacent laminated structures ST.

In such stacked structures ST, the lowest electrode EL can be adjacent to the lower semiconductor patterns LSP of the vertical structures VS and DVS, as shown in Fig. The distance Da between the sidewall of the lower semiconductor pattern LSP and the sidewall of the lowest layer EL adjacent thereto is a distance Db between the lower surface of the lowest layer EL and the upper surface of the oxidation- . ≪ / RTI >

Referring now to Figs. 4, 14A and 14B, an insulating spacer SP covering the sidewalls of the trenches T may be formed. The formation of the insulating spacer SP is performed by depositing the spacer film to a uniform thickness on the substrate 10 on which the stacked structures ST are formed and performing an etchback process on the spacer film to form a common source region CSR ). ≪ / RTI > Here, the spacer film may be formed of an insulating material, and may be deposited on the inner wall of the trenches T with a thickness of about 1/2 of the minimum width of the trench T. [ For example, the spacer film may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A common source plug CSP may be formed in each of the trenches T in which the insulating spacers SP are formed. According to one example, the common source plug CSP may be disposed between horizontally adjacent electrodes EL, and an insulating spacer SP may be interposed between the electrodes EL and the common source plug CSP. . That is, the insulating spacer SP can cover the side walls of the common source plug CSP. Also, the common source plug CSP may extend alongside the electrodes EL, and the top surface of the common source plug may be located above the top surfaces of the vertical structures.

4, 14A, and 14B, an upper insulating layer 130 may be formed on the capping insulating layer 125 to cover the upper surface of the common source plug CSP. The bit line contact plugs BPLG connected to the vertical structures VS through the capping insulating layer 125 and the upper insulating layer 130 may be formed. Subsequently, on the upper insulating film 130, bit lines BL extending in the second direction D2 and connected to the bit line contact plugs BPLG may be formed.

Further, contact plugs (CPLG, PUPLG, PPLG) for electrically connecting the electrodes (EL) and peripheral logic circuits to the connection region (CNR) and the peripheral circuit region (PR) may be formed.

For example, the cell contact plugs CPLG may be connected to the ends of the electrodes through the capping insulating film 125 and the buried insulating film 120 in the connection region CNR, respectively. The vertical lengths of the cell contact plugs CPLG can be reduced as they approach the cell array area CAR. And, the upper surfaces of the cell contact plugs CPLG may be substantially coplanar. The pickup contact plug PUPLG can be connected to the pickup areas 10PU through the buried insulating film 120. [ Here, the pickup regions 10PU include impurities of the first conductivity type and may have an impurity concentration higher than the impurity concentration of the well impurity layer 10P. The upper surfaces of the pickup contact plugs PUPLG may be substantially coplanar with the upper surface of the cell contact plugs CPLG. The peripheral contact plugs PPLG may be electrically connected to the peripheral logic circuits through the buried insulating film 120 and the peripheral insulating pattern 25P in the peripheral circuit region PR.

The connection interconnections CL connected to the cell contact plugs CPLG may be formed on the upper insulating layer 130 of the connection region CNR and may be formed on the upper insulating layer 130 of the peripheral circuit region PR, The peripheral wirings PCL connected to the contact plugs PPLG can be formed. In addition, a well conductive line PPL connected to the pickup contact plug PUPLG may be formed on the upper insulating film 130.

Hereinafter, a data storage film according to various embodiments of the present invention will be described in detail with reference to FIGS. 20A to 20E. FIG.

According to embodiments, the three-dimensional semiconductor memory device may be a NAND flash memory device. For example, the data storage film DS interposed between the stacked structure ST and the vertical structure VS may include a tunnel insulating film TIL, a charge storage film CIL, and a blocking insulating film BK. The data stored in this data storage layer DS can be changed using Fowler-Nordheim tunneling caused by the voltage difference between the data storage layer vertical structure VS comprising the semiconductor material and the electrodes EL. have.

20A, a tunnel insulating film TIL, a charge storage film CIL, and a blocking insulating film BLK are formed between the electrodes EL and the vertical structure VS between the insulating film ILD and the vertical structure RTI ID = 0.0 > VS. ≪ / RTI > That is, the insulating film ILD can directly contact the electrode.

According to the embodiment shown in FIG. 20B, the tunnel insulating film TIL and the charge storage film CIL can extend between the electrodes EL and the vertical structure VS, and between the insulating film ILD and the vertical structure VS have. The blocking insulating film BLK may extend to upper and lower surfaces of the electrodes EL between the electrodes EL and the vertical structure VS.

20C, a tunnel insulating film TIL may extend between the electrodes EL and the vertical structure VS and between the insulating film ILD and the vertical structure VS, and the charge storage film CIL And the blocking insulating film BLK may extend to the upper and lower surfaces of the electrodes EL between the electrodes EL and the vertical structure VS.

20D, the tunnel insulating film TIL, the charge storage film CIL, and the blocking insulating film BLK are electrically connected to the upper surface of the electrodes EL between the electrodes EL and the vertical structure VS, And lower surfaces.

According to the embodiment shown in FIG. 20E, the data storage layer DS may include first and second blocking insulating layers BLK1 and BLK2 made of different materials. The tunnel insulating film TIL, the charge storage film CIL and the first blocking insulating film BLK1 extend vertically between the electrodes EL and the vertical structure VS between the insulating film ILD and the vertical structure VS . The second blocking insulating film BLK2 may extend horizontally between upper surfaces and lower surfaces of the electrodes EL between the electrodes EL and the first blocking insulating film BLK1.

In the data storage film shown in FIGS. 20A to 20E, the charge storage film (CIL) can be one of insulating films containing trapping sites and abundant insulating films and nanoparticles, and can be formed by chemical vapor deposition or atomic layer deposition techniques Or may be formed using one of these. For example, the charge storage film (CIL) may include one of a trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots. As a more specific example, the charge storage film (CIL) may comprise at least one of a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, a nanocrystalline silicon film and a laminated trap layer . ≪ / RTI >

The tunnel insulating film (TIL) may be one of materials having a larger bandgap than the charge storage film (CIL), and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating film TIL may be a silicon oxide film formed using one of the deposition techniques described above. Alternatively, the tunnel insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film.

The blocking insulating film BLK may be one of materials having a bandgap smaller than the tunnel insulating film TIL and larger than the charge storage film CIL. The blocking insulating film BLK may include a high dielectric film such as an aluminum oxide film and a hafnium oxide film. The blocking insulating film BLK may be formed using one of chemical vapor deposition or atomic layer deposition techniques, at least one of which may be formed through a wet oxidation process.

20E, when the data storage film DS includes the first and second blocking insulating films BLK1 and BLK2, for example, the first blocking insulating film BLK1 may be formed of an aluminum oxide film, a hafnium oxide film, And the second blocking insulating film BLK2 may be a material having a smaller dielectric constant than the first blocking insulating film BLK1. As another example, the second blocking insulating film BLK2 may be one of the high-k films, and the first blocking insulating film BLK1 may be a material having a smaller dielectric constant than the second blocking insulating film BLK2.

The data stored in the data storage film DS described with reference to FIGS. 20A to 20E includes the Fowler-Nordheim tunneling induced by the voltage difference between the vertical structure VS including the semiconductor material and the electrodes EL, As shown in FIG. Alternatively, the data storage layer DS may be a thin film (e.g., a thin film for a phase change memory or a thin film for a variable resistance memory) capable of storing information based on another operating principle.

21 is a circuit diagram showing a part of a three-dimensional semiconductor memory device according to the embodiments of the present invention. The cell array of the three-dimensional semiconductor memory device according to the embodiments of the present invention may include three-dimensionally arranged memory cells, as shown in FIG. However, in order to avoid the complexity in the figure, Fig. 20 exemplarily shows a part of the cell array. In addition, for simplicity of description, description of the same technical features as the cell array of the three-dimensional semiconductor memory device described above with reference to Fig. 3 can be omitted.

Referring to FIG. 21, the string selection line SSL may be an electrode EL located on the uppermost layer in the stacked structures ST described with reference to FIGS. 14A and 14B. The electrode EL of the uppermost layer can constitute the gate electrodes of the string selection transistors SST which control the electrical connection between the bit line BL and the vertical structures VS.

The ground selection line GSL may be an electrode EL positioned at the lowest layer in the laminated structures ST described with reference to Figs. 14A and 14B. The lowest electrode EL can constitute the gate electrodes of the ground selection transistors GSTa and GSTb controlling the electrical connection between the common source region CSR and the vertical structures VS. In one example, each of the ground select transistors GSTa and GSTb may be composed of two transistors connected in series, and the gate electrodes of the two transistors may be connected to one ground select line. That is, one ground selection transistor includes a vertical transistor GSTa using a lower semiconductor pattern LSP of a vertical structure and a horizontal transistor GSTb using a substrate 10 adjacent to the lower semiconductor pattern LSP as a channel. ).

The word lines WL may also be the electrodes EL between the uppermost electrode EL and the lowermost electrode EL in the stacked structures ST described with reference to Figures 14A and 14B . The electrodes EL between the uppermost electrode EL and the lowermost electrode EL can be combined with the vertical structures VS to constitute the memory cells MCT.

In embodiments, the word lines WL and the ground select line GSL may extend from the cell array area CAR to the connection area CNR. Further, as shown in FIGS. 14A and 14B, the dummy vertical structures DVS can penetrate the laminate structures ST in the connection region CNR. Thus, similar to the cell strings CSTR of the cell array, the dummy strings DSTR can be arranged in the connection area CNR. In the connection region CNR, a portion of the word lines WL and the ground select line GSL are coupled to the dummy vertical structures DVS described with reference to Figures 14A and 14B to form a dummy string DSTR Can be configured. Here, the dummy strings DSTR may be electrically floating with the bit line.

According to the embodiments, the horizontal transistor GSTb of the cell string CSTR and the horizontal transistor GSTb of the dummy string DSTR may be electrically connected in common to one ground selection line GSL. The voltage of the ground selection line GSL may be the lowest electrode of the stacked structures ST described with reference to Figs. 14A and 14B. The lowest electrode controls the potential of the substrate 10, and the threshold voltage of the horizontal transistors may be varied depending on the thickness of the horizontal gate insulating film ILDb described with reference to FIGS. 14A and 14B. The horizontal gate insulating film ILDb is in contact with the oxidation inhibiting layer 11 so that the horizontal gate insulating film ILDb in the cell array region CAR and the connection region CNR is substantially uniform Thickness. That is, the thickness variation of the horizontal gate insulating film ILDb in the cell array region CAR and the connection region CNR can be reduced. Therefore, the threshold voltage distribution of the ground selection transistors connected to the common ground selection line GSL in the cell array area CAR and the connection area CNR can be improved.

FIGS. 19A and 19B are views for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention, and enlarged portions A and B of FIGS. 13A and 13B, respectively. For simplicity of explanation, the description of the same technical features as the manufacturing method of the three-dimensional semiconductor memory device described above with reference to Figs. 5A to 14A and Figs. 5B to 14B can be omitted.

Referring to Figs. 19A and 19B, the substrate 10 may further include a channel impurity region 11P under the oxidation-inhibiting layer 11. In other words, the oxidation-inhibiting layer 11 may be disposed between the horizontal gate insulating film ILDb and the channel impurity region 11P. The channel impurity region 11P may include impurities of the same conductivity type as the well impurity layer 10P and the impurity concentration of the channel impurity region 11P may be larger than the impurity concentration of the well impurity layer 10P. The channel impurity region 11P can be used as a channel of the ground selection transistor using the lowest layer electrode as the gate electrode. The threshold voltage of the ground selection transistor using the lowest layer electrode as the gate electrode can be controlled in accordance with the impurity concentration of the channel impurity region 11P. The concentration of impurities of the first conductivity type in the channel impurity region 11P may be greater than the concentration of the oxidation inhibiting material (for example, carbon (C)) in the oxidation inhibiting layer 11.

22 is a sectional view for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention, taken along the line I-I 'in FIG. For simplicity of explanation, the description of the same technical features as the manufacturing method of the three-dimensional semiconductor memory device described above with reference to Figs. 5A to 14A and Figs. 5B to 14B can be omitted.

22, the stacked structures ST include electrodes alternately stacked on the horizontal gate insulating film ILDb and the horizontal gate insulating film ILDb on the upper surface of the substrate 10 and insulating films. The substrate 10 may include an oxidation inhibiting layer 11 comprising an oxidation inhibiting material such as carbon (C), nitrogen (N), or fluorine (F).

In one example, the oxidation inhibiting layer 11 may be formed in the substrate 10 of the cell array region CAR, and the horizontal gate insulating film ILDb may be formed in contact with the oxidation inhibiting layer 11 in the cell array region CAR. And can contact the well impurity layer 10P in the connection region CNR. In the cell array region CAR, the lower semiconductor patterns LSP of the vertical structure can be connected to the well impurity layer 10P through the oxidation-inhibiting layer 11. [

In one example, the oxidation inhibiting layer 11 can suppress the thickness of the horizontal gate insulating film ILDb from increasing in the cell array region CAR during the thermal oxidation process described with reference to Figs. 16A and 16B. Therefore, when the oxidation amount is large in the connection region CNR in the cell array region CAR, the thickness variation of the horizontal gate insulation film ILDb in the cell array region CAR and the connection region CNR can be reduced.

23A and 23B are cross-sectional views taken along lines I-I 'and II-II' in FIG. 4, respectively, for explaining another example of the three-dimensional semiconductor memory device according to the embodiments of the present invention. 24A and 24B are enlarged views of portions A and B of FIG. 23A, respectively, and FIG. 24C is an enlarged view of portion C of FIG. 23B. For simplicity of explanation, the description of the same technical features as the manufacturing method of the three-dimensional semiconductor memory device described above with reference to Figs. 5A to 14A and Figs. 5B to 14B can be omitted.

23A and 23B, an oxidation preventing layer 11 is formed in the substrate 10 of the cell array region CAR and the connecting region CNR and is formed on the oxidation preventing layer 11 in one direction The stacked structures ST may be disposed.

Each of the stacked structures ST may include electrodes and insulating films alternately stacked on the horizontal gate insulating film ILDb and the horizontal gate insulating film ILDb in contact with the oxidation inhibiting layer 11. [

In the cell array region CAR, the vertical structures can be connected to the well impurity layer 10P through the stacked structures ST and the dummy vertical structures can be connected to the stacked structures ST in the connection region CNR. And can be in contact with the well impurity layer 10P. In this embodiment, the vertical structures can omit the lower semiconductor patterns LSPs.

That is, each of the vertical structures VS includes a first semiconductor pattern SP1 and a first semiconductor pattern SP1 that are in contact with the well impurity layer 10P, as shown in Figs. 24A, 24B, And a second semiconductor pattern SP2 interposed between the data storage film DS and the data storage film DS. The bottom of the first semiconductor pattern SP1 may be a closed pipe-shaped or macaroni-shaped and the inside of the first semiconductor pattern SP1 may be formed by a buried insulating pattern VI Can be filled. The first semiconductor pattern SP1 may be in contact with the inner wall of the second semiconductor pattern SP2 and the upper surface of the well impurity layer 10P. That is, the first semiconductor pattern SP1 can electrically connect the second semiconductor pattern SP2 and the well impurity layer 10P. The bottom surface of the first semiconductor pattern SP1 may be located at a lower level than the top surface of the substrate 10. [ In addition, the bottom surface of the first semiconductor pattern SP1 may be located at a level lower than the bottom surface of the oxidation inhibiting layer 11. The second semiconductor pattern SP2 may be an open pipe shape or a macaroni shape at the upper and lower ends. The first and second semiconductor patterns SP1 and SP2 may be in an unselected state or may be doped with an impurity having the same conductivity type as that of the horizontal semiconductor layer 100. [ The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be in a polycrystalline state or a single crystal state.

25 is a schematic block diagram of a three-dimensional semiconductor memory device according to embodiments of the present invention.

25, a three-dimensional semiconductor memory device according to embodiments includes a peripheral logic structure (PS) and a cell array structure (CS), and a cell array structure (CS) is formed on a peripheral logic structure (PS) . That is, the peripheral logic structure PS and the cell array structure CS can overlap from a planar viewpoint.

In embodiments, the peripheral logic structure PS may include the row and column decoders 2, 4, page buffer 3, and control circuits 5 described with reference to FIG. The cell array structure CS may include a plurality of memory blocks BLK0 to BLKn, which are data erase units. The memory blocks BLK1 to BLKn may include a structure stacked along the third direction D3 on a plane extending along the first and second directions D1 and D2. Each of the memory blocks BLK1 to BLKn includes a memory cell array having a three-dimensional structure (or vertical structure). The memory cell array may include a plurality of three-dimensionally arranged memory cells described with reference to FIG. 2, a plurality of word lines and bit lines electrically coupled to the memory cells.

26 is a cross-sectional view of a three-dimensional semiconductor memory device according to embodiments of the present invention described with reference to FIG. For simplicity of explanation, the description of the same technical features as the manufacturing method of the three-dimensional semiconductor memory device described above with reference to Figs. 5A to 14A and Figs. 5B to 14B can be omitted.

Referring to FIG. 25, a peripheral logic structure PS and a cell array structure CS may be sequentially stacked on a semiconductor substrate 10. In other words, the peripheral logic structure PS can be disposed between the semiconductor substrate 10 and the cell array structure CS in a vertical view. That is, the peripheral circuit region PR and the cell array region CAR can overlap from a planar viewpoint.

The semiconductor substrate 10 may be a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, Or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

The peripheral logic structure PS may include row and column decoders (see 2 and 4 in FIG. 1), page buffers (see 3 in FIG. 1), and control circuits, as described with reference to FIG. That is, the peripheral logic structure PS may include NMOS and PMOS transistors, a resistor, and a capacitor, which are electrically connected to the cell array structure CS. These peripheral circuits may be formed on the front surface of the semiconductor substrate 10. In addition, the semiconductor substrate 10 may include an n-well region nw doped with an n-type impurity and a p-well region pw doped with a p-type impurity. Active regions (ACT) can be defined in the n-well region (nw) and the p-well region (pw)

The peripheral logic structure PS includes peripheral gate electrodes PG, source and drain impurity regions on both sides of the peripheral gate electrodes PG, peripheral circuit plugs CP, peripheral circuit wirings ICL, And a lower buried insulating film 90 covering the gate insulating film 90. [ More specifically, PMOS transistors may be formed on the n-well region nw, and NMOS transistors may be formed on the p-well region pw. The peripheral circuit wirings ICL can be electrically connected to the peripheral circuits via the peripheral circuit plugs CP. For example, peripheral circuit plugs CP and peripheral circuit wirings ICL may be connected to NMOS and PMOS transistors.

The lower buried insulating film 90 may cover the peripheral circuits, the peripheral circuit plugs CP, and the peripheral circuit wirings ICL. The lower buried insulating film 90 may include insulating films stacked in multiple layers.

The cell array structure CS is disposed on the lower buried insulating film 90 and includes a horizontal semiconductor layer 100, stacked structures ST, and vertical structures VS.

The horizontal semiconductor layer 100 may be formed on the upper surface of the lower buried insulating film 90 covering the peripheral circuits. That is, the lower surface of the horizontal semiconductor layer 100 may contact the lower buried insulating film 90. The horizontal semiconductor layer 100 may include a connection region CNR disposed adjacent to the cell array region CAR and the cell array region CAR as described with reference to FIG.

The horizontal semiconductor layer 100 may be made of a semiconductor material and may be formed of a material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs) (AlGaAs), or a mixture thereof. In addition, the horizontal semiconductor layer 100 may include intrinsic semiconductors doped with a first conductivity type impurity and / or an undoped state. In addition, the horizontal semiconductor layer 100 may have a crystal structure including at least one selected from the group consisting of single crystal, amorphous, and polycrystalline.

In one example, the horizontal semiconductor layer 100 may include an oxidation-inhibiting layer 11, and the stacking structures ST may be disposed on the oxidation-inhibiting layer 11.

The stacked structures ST may extend in the first direction D1 on the horizontal semiconductor layer 100 and may be arranged apart from each other in the second direction D2 as described with reference to Fig. Each of the stacked structures ST includes electrodes EL vertically stacked on the horizontal semiconductor layer 100 and insulating films ILD sandwiched therebetween. As described above, in the lowermost layer, And a horizontal gate insulating film (ILDb) in contact with the gate insulating film 11.

The stacked structures ST may have a stepped structure in the connection region CNR, as described above, for the electrical connection between the electrodes EL and the peripheral logic structure PS. An upper buried insulating film 120 covering the ends of the electrodes EL having a stepped structure may be disposed on the horizontal semiconductor layer 100. [ In addition, the capping insulating film 125 may cover the plurality of stacked structures ST and the upper buried insulating film 120. Further, the bit lines BL extending in the second direction D2 may be disposed on the capping insulating film 125 across the stacking structures ST. The bit lines BL may be electrically connected to the vertical structure VS via a bit line contact plug BPLG.

The vertical structures VS may be electrically connected to the horizontal semiconductor layer 100 through each of the stacked structures ST. In one example, each of the vertical structures may include a lower semiconductor pattern LSP and an upper semiconductor pattern USP. Alternatively, each of the vertical structures may include a first semiconductor pattern (not shown) connected to the horizontal semiconductor layer through the stacked structures ST as described with reference to FIGS. 23A, 23B, 24A, 24B, And a second semiconductor pattern interposed between the stacked structures ST and the first semiconductor pattern.

The data storage film DS may be disposed between the stacked structures ST and the vertical structures VS.

Common source regions CSR may be disposed in the horizontal semiconductor layer 100 between adjacent stacked structures ST. The common source regions CSR may extend in the first direction D1 in parallel with the stacking structures ST. The common source regions CSR may be formed by doping an impurity of the second conductivity type in the horizontal semiconductor layer 100. [

The common source plug CSP can be connected to the common source region CSR. A sidewall insulating spacer SP may be interposed between the common source plug CSP and the stacked structures ST. The common source plug CSP may extend in a first direction D1 and the sidewall insulating spacers SP may extend in a first direction D1 between the stacked structures ST and the common source plug CSP. / RTI > As another example, the sidewall insulating spacers SP may fill between the adjacent stacked structures ST, and a common source plug CSP may extend through the sidewall insulating spacers SP to form a common source region CSR and a local As shown in FIG.

Pickup regions 10PU may be disposed in the horizontal semiconductor layer 100 away from the stacked structures ST. The pickup regions 10PU may be formed by doping an impurity of the first conductivity type in the horizontal semiconductor layer 100. [ The pickup regions 10PU may have the same conductivity type as the horizontal semiconductor layer 100 and the impurity concentration in the pickup regions 10PU may be higher than the impurity concentration in the horizontal semiconductor layer 100. [

A wiring structure for electrically connecting the cell array structure CS and the peripheral logic structure PS to the ends of the stacked structures ST having a stepped structure may be disposed. An upper buried insulating film 120 covering the ends of the stacked structures ST may be disposed on the horizontal semiconductor layer 100. The wiring structure may pass through the upper buried insulating film 120 to form the ends of the electrodes EL, And contact lines PL connected to the contact plugs PLG on the upper buried insulating film 120. In this case, The vertical lengths of the contact plugs PLG can be reduced as they approach the cell array area CAR.

In addition, the pickup contact plugs PPLG can be connected to the pickup areas 10PU through the upper buried insulating film 120. [ The pickup regions 10PU may be formed in the horizontal semiconductor layer 100 and may include impurities of the same conductivity type as the horizontal semiconductor layer 100. [ Here, the impurity concentration of the pickup regions 10PU may be higher than the impurity concentration in the horizontal semiconductor layer 100. [

The upper surfaces of the pickup contact plugs PPLG may be substantially coplanar with the upper surface of the contact plugs PLG. The pick-up contact plug PPLG may be connected to the peripheral logic structure PS via a well conductive line PCL and a connection plug CPLG.

The connection plug CPLG can electrically connect the cell array structure CS and the peripheral logic structure PS. The connection plug CPLG may be connected to the peripheral circuit wirings ICL of the peripheral logic structure PS through the upper buried insulating film 120 and the horizontal semiconductor layer 100. [

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (20)

An oxidation inhibiting layer disposed in the substrate;
A plurality of stacked structures disposed on the oxidation-inhibiting layer and including insulating films and electrodes vertically stacked on the horizontal gate insulating film and the horizontal gate insulating film; And
And a plurality of vertical structures passing through the stacked structures and connected to the substrate. The method according to claim 1,
Wherein the lower surfaces of the vertical structures are located below the lower surface of the oxidation inhibiting layer. The method according to claim 1,
Wherein the oxidation inhibiting layer comprises carbon (C), nitrogen (N), or fluorine (F). The method according to claim 1,
Wherein each of the vertical structures includes a lower semiconductor pattern connected to the substrate through a lower portion of the laminated structure and the oxidation inhibiting layer and an upper semiconductor pattern connected to the lower semiconductor pattern through an upper portion of the laminated structure, And the third semiconductor memory device. 5. The method of claim 4,
And a vertical gate insulating film between the lower semiconductor pattern and the electrodes,
Wherein the horizontal and vertical gate insulating films are thermally-oxidized films. 5. The method of claim 4,
Wherein the distance between the sidewall of the lower semiconductor pattern and the sidewall of the electrode adjacent thereto is substantially the same as the distance between the lower surface of the electrode and the upper surface of the oxidation inhibiting layer. The method according to claim 1,
Wherein the horizontal gate insulating film has a thickness smaller than a minimum thickness of the insulating films. The method according to claim 1,
Wherein the substrate comprises impurities of a first conductivity type,
The apparatus further includes common source regions disposed in the substrate between the stacking structures,
Wherein the common source regions comprise impurities of a second conductivity type. The method according to claim 1,
And a data storage film disposed between the vertical structures and the electrodes. The method according to claim 1,
The substrate includes a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region,
Wherein the stacked structures and the oxidation inhibiting layer extend from the cell array region to the connection region,
Wherein the stacked structure in the connection region has a stepped structure in which the stacked structure moves down toward the peripheral circuit region. 11. The method of claim 10,
Wherein the substrate includes a connection region between the cell array region and the peripheral circuit region, and the horizontal gate insulation film has substantially the same thickness in the cell array region and the connection region. 11. The method of claim 10,
A peripheral logic structure including peripheral logic circuits disposed on the substrate of the peripheral circuit region, and a peripheral insulation pattern covering the peripheral logic circuits,
Wherein the oxidation-inhibiting layer extends in a region between the stacked structures and the peripheral logic structure in the cell array region. 13. The method of claim 12,
And a buried insulating layer covering the ends of the electrodes located in the connection region and the peripheral logic structure,
Wherein the buried insulating film covers the oxidation inhibiting layer between the stacked structures and the peripheral logic structure. 11. The method of claim 10,
Further comprising dummy vertical structures connected to the substrate through the stacked structures in the connection region. A substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region;
The stacked structures extending from the cell array region to the connection region, wherein the stacked structures include stacked structures including a horizontal gate insulating film and insulating films and electrodes vertically alternately stacked on the horizontal gate insulating film; And
And an oxidation inhibiting layer provided in the substrate in contact with the horizontal gate insulating film. 16. The method of claim 15,
Wherein the stacked structure in the connection region has a stepped structure in which the stacked structure moves down toward the peripheral circuit region. 16. The method of claim 15,
Wherein the horizontal gate insulating film has substantially the same thickness in the cell array region and the connection region. 16. The method of claim 15,
Further comprising a plurality of vertical structures in contact with the substrate through the stacked structures and the oxidation-inhibiting layer in the cell array region. 19. The method of claim 18,
Wherein each of the vertical structures includes a lower semiconductor pattern connected to the substrate through a lower portion of the laminated structure and the oxidation inhibiting layer and an upper semiconductor pattern connected to the lower semiconductor pattern through an upper portion of the laminated structure, And the third semiconductor memory device. 20. The method of claim 19,
And a vertical gate insulating film between the lower semiconductor pattern and the electrodes,
Wherein the horizontal and vertical gate insulating films are thermally-oxidized films.

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