CN114078701B

CN114078701B - Semiconductor structure and forming method thereof

Info

Publication number: CN114078701B
Application number: CN202010819904.2A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-08-14
Filing date: 2020-08-14
Publication date: 2024-05-17
Anticipated expiration: 2040-08-14
Also published as: CN114078701A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doped layer, an initial channel column and a semiconductor layer which are stacked from bottom to top in sequence; forming a dummy gate surrounding the initial channel pillar sidewall and exposing the semiconductor layer; forming a bottom dielectric layer which is filled between adjacent semiconductor laminated columns, surrounds the exposed semiconductor laminated column side walls of the dummy gate and covers the top surface of the dummy gate on the substrate, wherein the bottom dielectric layer exposes the side walls of the dummy gate away from the adjacent semiconductor laminated columns; removing the dummy gate to form a gate opening exposing the side wall of the initial channel column; thinning the exposed side wall of the initial channel column to form a channel column; a gate is formed in the gate opening surrounding the channel pillar sidewalls. The embodiment of the invention is beneficial to improving the performance of the VGAA transistor.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, the control capability of the gate to the channel is reduced, so that the subthreshold leakage (subthreshold leakage) phenomenon, that is, the so-called short channel effect (SCE-CHANNEL EFFECTS) is more likely to occur, and the channel leakage current of the transistor is increased.

Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. The fully-surrounding gate transistors include a lateral fully-surrounding gate (LATERAL GATE-all-around, LGAA) transistor and a vertical fully-surrounding gate (VERTICAL GATE-all-around, VGAA) transistor.

The channel of VGAA extends in the direction perpendicular to the surface of the substrate, which is beneficial to improving the area utilization efficiency of the semiconductor structure, and is beneficial to realizing further feature size reduction.

Disclosure of Invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which improves the performance of a vertical all-around gate (VGAA) transistor.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doped layer, an initial channel column and a semiconductor layer for forming a second doped layer, which are sequentially stacked from bottom to top; forming a dummy gate surrounding the initial channel pillar sidewall and exposing the semiconductor layer; forming a bottom dielectric layer which is filled between adjacent semiconductor laminated columns, surrounds the side walls of the semiconductor laminated columns exposed by the dummy gate and covers the top surface of the dummy gate on the substrate, wherein the bottom dielectric layer exposes the side walls of the dummy gate far away from the adjacent semiconductor laminated columns; removing the dummy gate, exposing the side wall of the initial channel column, and forming a gate opening in the bottom dielectric layer; thinning the side wall of the initial channel column exposed out of the gate opening, wherein the rest initial channel columns are used as channel columns; and filling the grid opening to form a grid surrounding the side wall of the channel column.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; the semiconductor laminated column protrudes out of the substrate and comprises a first doping layer, a channel column and a second doping layer which are stacked in sequence from bottom to top, and the side wall of the channel column is retracted relative to the side walls of the first doping layer and the second doping layer along the direction perpendicular to the side wall of the channel column; a gate surrounding a sidewall of the channel pillar, the gate being located adjacent to the sidewall of the semiconductor stack pillar with a space therebetween; and the dielectric layer is filled between the grid electrodes positioned on the side walls of the adjacent semiconductor laminated columns and covers the top surfaces of the grid electrodes.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

In the method for forming the semiconductor structure provided by the embodiment of the invention, a semiconductor laminated column is formed firstly, then a dummy gate surrounding the side wall of an initial channel column is formed, a bottom dielectric layer which is filled between adjacent semiconductor laminated columns and covers the top surface of the dummy gate is formed on the substrate, then the dummy gate is removed to form a gate opening, and then the side wall of the initial channel column is thinned through the gate opening to form the channel column; therefore, in the step of forming the semiconductor stacked column, the width of the initial channel column is larger than the target width of the channel column along the direction perpendicular to the side wall of the semiconductor stacked column, the semiconductor stacked column (including the first doped layer and the semiconductor layer) can have a larger width correspondingly, and the contact area between the semiconductor stacked column and the substrate is larger, so that the stability of the semiconductor stacked column erected on the substrate is improved, and the probability of occurrence of tilting or bending problems of the semiconductor stacked column in the formation process of the semiconductor structure is reduced correspondingly, for example: in the process of forming the isolation structure which is positioned on the substrate and surrounds the side wall of the first doped layer part, even if the stress of the semiconductor laminated column is uneven due to the non-uniform pattern density around the semiconductor laminated column, the probability of inclination or bending of the semiconductor laminated column is low, and the performance of a vertical fully-surrounded grid electrode (VGAA) transistor is further improved.

In the step of forming the dummy gate, a space is provided between the dummy gates located on the sidewalls of the adjacent semiconductor stacked columns, the sidewall of the dummy gate opposite to the adjacent semiconductor stacked columns is a first sidewall, and the sidewall of the dummy gate far away from the adjacent semiconductor stacked columns is a second sidewall, so that in the step of forming the bottom dielectric layer, the bottom dielectric layer can be filled between the first sidewalls of the adjacent dummy gate, surrounds the exposed sidewalls of the semiconductor stacked columns of the dummy gate and covers the top surface of the dummy gate, and in the process of forming the semiconductor structure (for example, the process of removing the dummy gate to form a gate opening and forming the gate in the gate opening), the bottom dielectric layer can play a role of supporting the semiconductor stacked columns, thereby reducing the probability of tilting or bending the semiconductor stacked columns and further improving the performance of the vertical fully-surrounding gate (VGAA) transistor.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure formed by a method;

FIGS. 2 through 10 are schematic views illustrating steps corresponding to the steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

Fig. 11 to 15 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, a vertical all-around (VGAA) transistor is advantageous for achieving further feature size reduction. Specifically, in the VGAA transistor, a semiconductor pillar protruding from the substrate is formed, the gate structure surrounds a portion of the sidewall of the semiconductor pillar, and a portion of the semiconductor pillar surrounded by the gate structure is a channel region, so that the channel of the VGAA transistor can extend in a direction perpendicular to the surface of the substrate.

However, the VGAA transistor formed at present still has the problem of poor performance. In particular, semiconductor pillars of VGAA transistors are prone to bending or tilting during formation of semiconductor structures, resulting in poor performance of VGAA transistors.

For example: the process of forming the VGAA transistor includes: as shown in fig. 1, an isolation structure 3 is formed on a substrate 1 where a semiconductor pillar 2 is exposed, the isolation structure 3 covering a portion of the side wall of the semiconductor pillar 2.

The pattern density varies at different locations on the substrate 1, resulting in a different pattern density around the periphery of each semiconductor pillar 2, for example: the substrate 1 includes a pattern dense region and a pattern sparse region, the number of semiconductor pillars 2 of the pattern dense region is greater than that of the pattern sparse region, or as shown in fig. 1, the pattern density is different on both sides of the semiconductor pillars 2 at the edge position. Due to the different pattern densities around the semiconductor pillars 2, the stress applied to the semiconductor pillars 2 is not uniform during the process of forming the isolation structure 3, especially, the stress applied to the semiconductor pillars 2 at the edge positions or the semiconductor pillars 2 at the junctions between the pattern dense regions and the pattern sparse regions is not uniform, so that the semiconductor pillars 2 are easy to bend or tilt (as shown by the dashed circles in fig. 1), and the performance of the formed VGAA transistor is poor.

In addition, the VGAA transistor forming process also comprises the processes of forming an interlayer dielectric layer (ILD), forming a grid electrode and the like. Along with the gradual reduction of the device size, the diameter or width of the semiconductor column 2 is smaller, the semiconductor column 2 is of an elongated vertical structure, the probability of the semiconductor column 2 tilting or bending in the forming process of the semiconductor structure is higher, and the influence on the performance of the VGAA transistor is not ignored.

In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the invention, a semiconductor laminated column is formed firstly, then a dummy gate surrounding the side wall of an initial channel column is formed, a bottom dielectric layer which is filled between adjacent semiconductor laminated columns and covers the top surface of the dummy gate is formed on the substrate, then the dummy gate is removed to form a gate opening, and then the side wall of the initial channel column is thinned through the gate opening to form the channel column; therefore, in the step of forming the semiconductor stacked column, the width of the initial channel column is larger than the target width of the channel column along the direction perpendicular to the side wall of the semiconductor stacked column, the semiconductor stacked column (including the first doped layer and the semiconductor layer) can have a larger width correspondingly, and the contact area between the semiconductor stacked column and the substrate is larger, so that the stability of the semiconductor stacked column erected on the substrate is improved, and the probability of occurrence of tilting or bending problems of the semiconductor stacked column in the formation process of the semiconductor structure is reduced correspondingly, for example: in the process of forming the isolation structure which is positioned on the substrate and surrounds the side wall of the first doped layer part, even if the stress of the semiconductor laminated column is uneven due to the non-uniform pattern density around the semiconductor laminated column, the probability of inclination or bending of the semiconductor laminated column is low, and the performance of a vertical fully-surrounded grid electrode (VGAA) transistor is further improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2 and 3, a substrate 100, and a semiconductor stack pillar 200 protruding from the substrate 100 are provided, the semiconductor stack pillar 200 including a first doped layer 10, an initial channel pillar 30, and a semiconductor layer 20 for forming a second doped layer, which are stacked in order from bottom to top.

The substrate 100 is used to provide a process platform for forming vertical fully-enclosed gate (VGAA) transistors.

The semiconductor stack pillar 200 is used to provide a process platform for the subsequent formation of a gate electrode surrounding the trench pillar sidewalls. The semiconductor stacked column 200 extends in a direction perpendicular to the substrate 100, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus is advantageous for achieving further feature size reduction.

The subsequent steps further comprise: thinning the side wall of the initial channel column 30 to form a channel column; therefore, in the step of forming the semiconductor stacked columns 30, the width of the initial channel columns 30 is larger than the target width of the channel columns in the direction perpendicular to the sidewalls of the semiconductor stacked columns 200, the semiconductor stacked columns 200 (including the first doping layer 10 and the semiconductor layer 20) can have a larger width dimension accordingly, and the contact area between the semiconductor stacked columns 200 and the substrate 100 is also larger, so that the stability of the semiconductor stacked columns 200 standing on the substrate 100 is improved, and the probability of the semiconductor stacked columns 200 tilting or bending in the subsequent process is reduced.

In this embodiment, the number of the semiconductor stacked columns 200 is plural, and the plural semiconductor stacked columns 200 are separated on the substrate 100. In this embodiment, the semiconductor stacked column 200 has a cylindrical structure.

In the step of providing the substrate 100 and the semiconductor stack pillar 200 in this embodiment, the first doped layer 10 is flush with the sidewalls of the initial channel pillar 30 and the semiconductor layer 20.

The first doped layer 10 is used as a source or drain region of a vertical fully-surrounding gate transistor. In this embodiment, the first doped layer 10 serves as the source region of the vertical fully-surrounding gate transistor.

In this embodiment, the width of the semiconductor stacked pillar 200 is larger along the direction perpendicular to the sidewall of the semiconductor stacked pillar 200, and the width dimension of the first doped layer 10 is also larger, that is, the volume of the first doped layer 10 is larger and the contact area between the first doped layer 10 and the substrate 100 is larger, so that the stability of the semiconductor stacked pillar 200 erected on the substrate 100 is advantageously improved, and the semiconductor stacked pillar 200 is not easy to bend, tilt or collapse. In addition, the width dimension of the first doped layer 10 is larger, and the volume of the first doped layer 10 is correspondingly larger, so that the stress on a channel region is improved, the mobility of carriers is improved, and the performance of the semiconductor structure is optimized correspondingly.

In the step of providing the substrate 100 and the semiconductor stacked pillar 200, the first doped layer 10 is different from the material of the initial channel pillar 30, and in the subsequent process of thinning the sidewall of the initial channel pillar 30, the initial channel pillar 30 and the first doped layer 10 have an etching selectivity ratio, which is favorable for reducing the damage probability of the first doped layer 10 and reducing the difficulty of thinning the sidewall of the initial channel pillar 30.

In this embodiment, the material of the first doped layer 10 may be SiGe doped with P-type ions, and the P-type ions may be B ions, ga ions or In ions. In other embodiments, when forming an NMOS transistor, the material of the first doped layer may be SiC or SiP doped with N-type ions, where the N-type ions may be P ions, as ions, or Sb ions.

The initial channel pillar 30 is used to form a channel pillar via a subsequent thinning process. The channel pillar has a target width in a direction perpendicular to the sidewalls of the semiconductor stack pillar 200. In this embodiment, the direction perpendicular to the sidewall of the semiconductor stacked column 200 is parallel to the substrate 100.

In the step of providing the substrate 100 and the semiconductor stack pillar 200, the width of the initial channel pillar 30 is greater than the target width. In this embodiment, the semiconductor stacked columns 200 have a cylindrical structure, and the width refers to the cross-sectional diameter of the channel column or the initial channel column 30.

In the step of providing the substrate 100 and the semiconductor stacked columns 200, the value of the width of the initial channel column 30 larger than the target width of the channel column in the direction perpendicular to the sidewalls of the semiconductor stacked columns 200 is preferably not too small or too large. If the value of the width of the initial channel pillar 30 larger than the target width of the channel pillar is too small, the effect of the increase in the width of the semiconductor stack pillar 200 is insignificant compared to the target width of the channel pillar, which tends to result in insignificant effect of the increase in the stability of the semiconductor stack pillar 200; if the width of the initial channel pillar 30 is larger than the target width of the channel pillar by too large a value, the width of the semiconductor stacked pillar 200 is too large, which easily results in too large an area of the substrate 100 occupied by the semiconductor stacked pillar 200, and thus easily reduces the wafer area utilization efficiency, and the thickness of the sidewall of the initial channel pillar 30 is also larger, and the time of the sidewall of the initial channel pillar 30 is too long, which easily increases the process risk and reduces the process controllability. For this reason, in the present embodiment, the width of the initial channel pillar 30 is 1.2 to 1.6 times the target width.

In this embodiment, the material of the initial channel pillar 30 includes Si.

The semiconductor layer 20 is used to form a second doped layer that is used as a source or drain region of the VGAA transistor. In this embodiment, the second doped layer is used as a drain region of the VGAA transistor.

In the step of providing the substrate 100 and the semiconductor stacked columns 200, the semiconductor layer 20 and the initial channel columns 30 are made of different materials, so that in the subsequent process of thinning the sidewalls of the initial channel columns 30, the initial channel columns 30 and the semiconductor layer 20 have an etching selection ratio, which is favorable for reducing the probability of causing false etching of the semiconductor layer 20 and reducing the difficulty of thinning the sidewalls of the initial channel columns 30.

In addition, in this embodiment, the width dimension of the semiconductor layer 20 is larger, and the volume of the semiconductor layer 20 is correspondingly larger, so that it is beneficial to improve the stress of the second doped layer on the channel region, further beneficial to improve the carrier mobility of the channel region, and correspondingly beneficial to optimize the performance of the semiconductor structure.

In this embodiment, the first doped layer 10 is used as a source region, the semiconductor layer 20 is used to form a second doped layer, and the second doped layer is used as a drain region. Therefore, the semiconductor layer 20 is the same material as the first doped layer 10.

In this embodiment, the PMOS transistor is formed, and the material of the semiconductor layer 20 is SiGe. In other embodiments, the material of the semiconductor layer may be SiC or SiP when forming the NMOS transistor.

In this embodiment, the semiconductor layer 20 is also doped with ions. The forming method further includes: a second doped layer is formed. In this embodiment, an epitaxial layer is subsequently formed on the semiconductor layer 20, and ions are self-doped in situ during the formation of the epitaxial layer, and the semiconductor layer 20 and the ion-doped epitaxial layer serve as the second doped layer. Thus, the doping ion type in the semiconductor layer 20 is the same as the doping ion type of the second doping layer.

In this embodiment, a PMOS transistor is formed, and the semiconductor layer 20 is doped with P-type ions, which may be B ions, ga ions, or In ions. In other embodiments, when forming the NMOS transistor, the semiconductor layer is doped with N-type ions, which may be P-ions, as-ions, or Sb-ions.

In other embodiments, the semiconductor layer may also be undoped with ions.

In the step of providing the substrate 100 and the semiconductor stack pillar 200, a doped layer side portion 110 connected to the bottom of the first doped layer 10, located on the substrate 100 and extending in a direction parallel to the substrate 100 is also formed.

The subsequent steps further comprise: a first source drain plug is formed in contact with the doped layer side 110. Therefore, by forming the doped layer side portion 110, the first doped layer 10 is electrically connected with the first source drain plug through the doped layer side portion 110, which is beneficial to reducing the difficulty of forming the first source drain plug, and by forming the doped layer side portion 110, the first doped layer 10 of the adjacent semiconductor stacked columns 200 can be contacted according to actual process requirements.

In this embodiment, the doped layer side portion 110 is the same as the material and doped ion type of the first doped layer 10.

In the present embodiment, the steps of providing the substrate 100 and the semiconductor stacked post 200 include:

As shown in fig. 2, a substrate 100, a first initially doped layer 101, a channel material layer 102 and an initial semiconductor layer 103 are provided, which are stacked in this order on the substrate 100 from bottom to top.

In this embodiment, the materials and ion doping types of the initial semiconductor layer 103 and the first initial doping layer 101 are the same, and the steps of forming the initial semiconductor layer 103 and the first initial doping layer 101 each include: an epitaxial layer is formed by adopting an epitaxial process, and ions are self-doped in situ in the process of forming the epitaxial layer.

The material formed by adopting the epitaxial process has high purity and few defects, which is beneficial to improving the formation quality of the initial semiconductor layer 103 and the first initial doping layer 101 and correspondingly improving the formation quality of the subsequent first doping layer and the semiconductor layer.

As shown in fig. 3, the initial semiconductor layer 103, the channel material layer 102, and a portion of the thickness of the first initial doped layer 101 are patterned to form the doped layer side 110, the first doped layer 10, the initial channel pillar 30, and the semiconductor layer 20.

Therefore, in this embodiment, the doped layer side portion 110 and the first doped layer 10 are formed as a single structure.

In this embodiment, the step of patterning the initial semiconductor layer 103, the channel material layer 102 and the first initial doped layer 101 with a partial thickness includes: forming a hard mask layer 104 on the initial semiconductor layer 103; the initial semiconductor layer 103, the channel material layer 102 and the first initial doped layer 101 having a partial thickness are patterned using the hard mask layer 104 as a mask.

The hard mask layer 104 is used as a mask for forming the semiconductor stack pillar 200. In this embodiment, the material of the hard mask layer 104 is silicon nitride.

In this embodiment, the hard mask layer 104 is used as a mask, and an anisotropic dry etching process is used to sequentially etch the initial semiconductor layer 103, the channel material layer 102, and a part of the thickness of the first initial doped layer 101.

In this embodiment, before forming the hard mask layer 104 on the initial semiconductor layer 103, the forming method further includes: a pad oxide layer 105 (shown in fig. 3) is formed on the initial semiconductor layer 103. The pad oxide layer 105 serves to reduce stress between the hard mask layer 104 and the initial semiconductor layer 103, thereby improving adhesion between the hard mask layer 104 and the initial semiconductor layer 103, and further improving accuracy of pattern transfer.

Therefore, a pad oxide layer 105 is further formed between the hard mask layer 104 and the semiconductor stacked pillar 200.

In this embodiment, after the semiconductor stacked column 200 is formed, the method for forming a semiconductor structure further includes: a dummy gate oxide layer 106 (shown in fig. 3) is formed on the sidewalls of the semiconductor stack pillar 200.

The dummy gate oxide layer 106 is used for protecting the sidewall of the semiconductor stack pillar 200, and the dummy gate oxide layer 106 is also used as a stop layer in the subsequent process of removing the dummy gate, so as to improve etching consistency and reduce damage to the semiconductor stack pillar 200. In this embodiment, the material of the dummy gate oxide layer 106 is silicon oxide.

Referring to fig. 4, a dummy gate 130 surrounding the sidewalls of the initial channel pillar 30 and exposing the semiconductor layer 20 is formed.

The dummy gate 130 is used to occupy space for the subsequent formation of a gate. Therefore, in this embodiment, the dummy gate 130 is also used to define the shape and position of the subsequent gate.

In this embodiment, there is a space S1 between the dummy gates 130 located on the sidewalls of the adjacent semiconductor stacked columns 200, the sidewalls of the dummy gates 130 opposite to the adjacent semiconductor stacked columns 200 are the first sidewalls 11, and the sidewalls of the dummy gates 130 away from the adjacent semiconductor stacked columns 200 are the second sidewalls 12.

In this embodiment, compared to the contact between the dummy gates on the sidewalls of the adjacent semiconductor stacked columns 200, the dummy gates 130 on the sidewalls of the adjacent semiconductor stacked columns 200 have a space S1 therebetween, and the bottom dielectric layer can be filled between the first sidewalls 11 of the adjacent dummy gates 130 during the process of forming a bottom dielectric layer on the substrate 100, which fills between the adjacent semiconductor stacked columns 200, surrounds the sidewalls of the exposed semiconductor stacked columns 200 of the dummy gates 130, and covers the top surfaces of the dummy gates 130, so that the bottom dielectric layer can serve as a support for the semiconductor stacked columns 200 during the formation of the semiconductor structure (e.g., during the process of removing the dummy gates 130 to form gate openings and forming gates in the gate openings).

Therefore, in the step of forming the dummy gate 130, the space S1 between the dummy gates 130 located on the side walls of the adjacent semiconductor stack pillars 200 is not preferably too small nor too large. If the space S1 is too small, the difficulty in filling the subsequent bottom dielectric layer between the dummy gates 130 on the sidewalls of the adjacent semiconductor stack columns 200 is easily increased, and the width of the bottom dielectric layer between the dummy gates 130 on the sidewalls of the adjacent semiconductor stack columns 200 is also easily too small in the direction perpendicular to the sidewalls of the semiconductor stack columns 200, so that the supporting effect of the bottom dielectric layer on the semiconductor stack columns 200 is easily reduced; if the spacing S1 is too large, the spacing between adjacent VGAA transistors is also easily increased, and thus the device density and wafer area utilization efficiency are easily reduced. For this reason, in the present embodiment, the space S1 between the dummy gates 130 located on the sidewalls of the adjacent semiconductor stack pillars 200 is 30% to 70% of the space S2 between the adjacent semiconductor stack pillars 200. As an example, the spacing S1 between the dummy gates 130 located on the sidewalls of the adjacent semiconductor stack pillars 200 is 50% of the spacing S2 between the adjacent semiconductor stack pillars 200.

The sidewall of the dummy gate 130 away from the adjacent semiconductor stack pillar 200 refers to a sidewall of the dummy gate 130 that is not opposite to the adjacent semiconductor stack pillar 200. For convenience of illustration and description, the second sidewall 12 shown in fig. 5 is a sidewall of the dummy gate 130 opposite to the adjacent semiconductor stack pillar 200, but in actual process, the second sidewall 12 may also be a sidewall of the dummy gate 130 facing other directions.

The dummy gate 130 may have a single-layer or stacked-layer structure. In this embodiment, the dummy gate 130 has a single-layer structure, and the material of the dummy gate 130 includes amorphous silicon, amorphous germanium, or HSQ (hydrogen silses-quioxane, hydrosilsesquioxane). The amorphous silicon and amorphous germanium are commonly used materials in the semiconductor process, which is favorable for improving the process compatibility, and the HSQ is a material with photosensitivity and high resolution, which is favorable for reducing the difficulty of the patterning process for forming the dummy gate 130 and improving the pattern precision of the dummy gate 130. As an example, the material of the dummy gate 130 is amorphous silicon.

In this embodiment, the dummy gate 130 surrounds the sidewalls of the initial channel pillar 30 and also extends around portions of the sidewalls of the semiconductor layer 20 and the first doped layer 10.

In this embodiment, the step of forming the dummy gate 130 includes: forming an initial dummy gate (not shown) on the substrate 100 to cover the semiconductor stack column 200; removing a part of the initial dummy gate to expose the semiconductor layer 20; the remaining initial dummy gate is patterned, leaving a portion of the initial dummy gate surrounding the sidewalls of the initial channel pillar 30 as the dummy gate 130.

An initial dummy gate is formed using a deposition process (e.g., a chemical vapor deposition process, etc.).

The step of removing a portion of the initial dummy gate thickness may include: flattening the initial dummy gate by taking the top surface of the hard mask layer 104 as a stop position; the remaining initial dummy gate of a partial thickness is etched back. Wherein, a Chemical Mechanical Polishing (CMP) process can be adopted for planarization treatment; the etch-back process may be a dry etch process.

In this embodiment, an anisotropic dry etching process is used to pattern the remaining initial dummy gate. The anisotropic dry etching process has high etching efficiency and etching precision, is beneficial to improving the appearance quality of the dummy gate 130, and is beneficial to enabling the dummy gate 130 on the side wall of the adjacent semiconductor laminated column 200 to meet the design requirement.

In this embodiment, after the substrate 100 and the semiconductor stack pillar 200 are provided and before the dummy gate 130 is formed, the method for forming a semiconductor structure further includes: an isolation structure 120 is formed on the substrate 100 surrounding a portion of the sidewall of the first doped layer 10.

The isolation structure 120 is used to isolate adjacent semiconductor stacked columns 200. In this embodiment, the isolation structure 120 is located on the doped layer side 110, and the isolation structure 120 is further used to isolate the doped layer side 110 from the subsequent gate.

In this embodiment, the width of the initial channel pillar 30 is greater than the target width of the channel pillar along the direction perpendicular to the sidewall of the semiconductor stacked pillar 200, the semiconductor stacked pillar 200 (including the first doped layer 10 and the semiconductor layer 20) can have a larger width, the contact area between the semiconductor stacked pillar 200 and the substrate 100 is larger, the stability of the semiconductor stacked pillar 200 standing on the substrate 100 is higher, and in the process of forming the isolation structure 120, even if the stress of the semiconductor stacked pillar 200 is uneven due to the inconsistent peripheral pattern density of the semiconductor stacked pillar 200, the probability of the semiconductor stacked pillar 200 tilting or bending is lower, thereby improving the semiconductor process yield and the performance of the vertical fully-enclosed gate transistor.

In this embodiment, the material of the isolation structure 120 is silicon nitride. In other embodiments, the material of the isolation structure can also be an insulating material such as silicon oxynitride, silicon oxide, or the like.

Accordingly, in the present embodiment, the dummy gate 130 is formed on the isolation structure 120.

Referring to fig. 5, a bottom dielectric layer 140 is formed on the substrate 100 to fill between adjacent semiconductor stack pillars 200, surround sidewalls of the semiconductor stack pillars 200 where the dummy gate 130 is exposed, and cover the top surface of the dummy gate 130, the bottom dielectric layer 140 exposing sidewalls of the dummy gate 130 remote from the adjacent semiconductor stack pillars 200.

The bottom dielectric layer 140 is used to isolate adjacent semiconductor stack pillars 120 or dummy gates 130 from each other. In this embodiment, the bottom dielectric layer 140 covers the first sidewall 11 of the dummy gate 130 and exposes the second sidewall 12 of the dummy gate 130.

In the embodiment of the present invention, in the process of forming the dummy gate 130, a space is provided between the dummy gates 130 located on the sidewalls of the adjacent semiconductor stacked columns 200, so that in the process of forming the bottom dielectric layer 140 on the substrate 100, which is filled between the adjacent semiconductor stacked columns 200 and covers the top surface of the dummy gate 130, the bottom dielectric layer 140 can be filled between the first sidewalls 11 of the adjacent dummy gates 130, and in the process of forming the semiconductor structures such as removing the dummy gate 130 to form the gate opening and forming the gate in the gate opening, the bottom dielectric layer 140 can play a role of supporting the semiconductor stacked columns 200, thereby reducing the probability of tilting or bending the semiconductor stacked columns 200; thereby improving the performance of the vertical fully-enclosed gate transistor.

In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide. In other embodiments, the material of the bottom dielectric layer may be an insulating material such as silicon oxynitride or silicon nitride.

In this embodiment, a bottom dielectric layer 140 is formed on the isolation structure 120.

The bottom dielectric layer 140 exposes sidewalls of the dummy gate 130 (i.e., the second sidewalls 12) that are remote from the adjacent semiconductor stack pillars 200 to facilitate subsequent removal of the dummy gate 130 through the exposed second sidewalls 12. Specifically, in the step of forming the bottom dielectric layer 140 in this embodiment, a via 145 exposing the second sidewall 12 is formed in the bottom dielectric layer 140.

In this embodiment, in the step of forming the bottom dielectric layer 140, the bottom dielectric layer 140 covers the top surface of the semiconductor stacked pillar 200. Specifically, the bottom dielectric layer 140 covers the top surface of the hard mask layer 104.

In this embodiment, the step of forming the bottom dielectric layer 140 includes: forming a dielectric material layer (not shown) covering the semiconductor stack pillar 200 and the dummy gate 130 on the substrate 100; and patterning the dielectric material layer, and reserving the dielectric material layer which is positioned between the adjacent semiconductor laminated columns 200, surrounds the side walls of the semiconductor laminated columns 200 exposed by the dummy gate 130 and covers the top surface of the dummy gate 130 as the bottom dielectric layer 140.

The dielectric material layer is formed using a deposition process (e.g., a chemical vapor deposition process or a high aspect ratio process). In this embodiment, a dry etching process is used to pattern the dielectric material layer.

Referring to fig. 6, dummy gate 130 is removed, exposing the sidewalls of initial channel pillar 30, and a gate opening 150 is formed in bottom dielectric layer 140. The gate opening 150 exposes sidewalls of the initial channel pillar 30 so that the sidewalls of the initial channel pillar 30 can be subsequently thinned. The gate opening 150 also provides room for a gate to be subsequently formed.

In this embodiment, after the dummy gate 130 is removed, the bottom dielectric layer 140 is further disposed on the isolation structure 120 between the adjacent gate openings 150, so that after the dummy gate 130 is removed, the bottom dielectric layer 140 can play a role in supporting the semiconductor stacked pillar 200, so that the semiconductor stacked pillar 200 is not easy to bend, tilt or collapse.

In this embodiment, the dummy gate 130 surrounds the sidewalls of the initial channel pillar 30 and also extends around a portion of the sidewalls of the semiconductor layer 20 and the first doped layer 10, so that the gate opening also exposes a portion of the sidewalls of the semiconductor layer 20 and the first doped layer 10 after the dummy gate 130 is removed.

In this embodiment, the gate opening 150 communicates with the via 145.

In this embodiment, the dummy gate oxide layer 106 is further formed between the dummy gate 130 and the semiconductor stack pillar 200, and thus, the step of forming the gate opening 150 includes: the dummy gate 130 and the dummy gate oxide 106 covered by the dummy gate 130 are removed.

In the process of removing the dummy gate 130, the dummy gate oxide layer 106 can be used as a stop layer, so that the etching consistency of removing the dummy gate 130 is improved, and the probability of causing false etching to other film layers (such as the first doped layer 10, the semiconductor layer 20 and the initial channel pillar 30) is reduced.

In this embodiment, the process of removing the dummy gate 130 includes a wet etching process. The wet etching process has an isotropic etching characteristic, so that the dummy gate 130 can be etched through the exposed second sidewall 12, thereby removing the dummy gate 130 cleanly. Specifically, in this embodiment, the material of the dummy gate 130 is amorphous silicon, and the etching solution of the wet etching process includes TMAH solution.

The process of removing the dummy gate oxide 106 covered by the dummy gate 130 includes a wet etching process. The etching solution of the wet etching process comprises hydrofluoric acid solution.

Referring to fig. 7, the sidewalls of the preliminary channel pillars 30 exposed by the gate openings 150 are thinned, and the remaining preliminary channel pillars 30 are used as the channel pillars 40. The channel pillars 40 are used to provide a conductive channel for the device to operate.

In the step of providing the semiconductor stacked columns 200, in order to improve the stability of the semiconductor stacked columns 200 on the substrate 200 and reduce the probability of bending, tilting or collapsing of the semiconductor stacked columns 200, the width of the initial channel columns 30 is larger than the target width of the channel columns 40, and therefore, the channel columns 40 meeting the target width are formed by thinning the sidewalls of the initial channel columns 30, and accordingly, the thickness of the conductive channels meets the design requirements.

After the sidewalls of the initial channel pillar 30 are thinned to form the channel pillar 40, the sidewalls of the channel pillar 40 are recessed with respect to the sidewalls of the first doped layer 10 or the semiconductor layer 20.

In this embodiment, the gate opening 150 also exposes a portion of the sidewalls of the semiconductor layer 20 and the first doped layer 10. The materials of the semiconductor layer 20 or the first doped layer 10 and the initial channel pillar 30 are different, so that in the process of thinning the initial channel pillar 30, an etching selection ratio is arranged between the initial channel pillar 30 and the semiconductor layer 20, and an etching selection ratio is arranged between the initial channel pillar 30 and the first doped layer 10, so that the semiconductor layer 20 or the first doped layer 10 is not easy to be mistakenly etched, and the thinning process difficulty is reduced.

In this embodiment, in the step of thinning the sidewall of the initial channel pillar 30, the etching selectivity ratio of the initial channel pillar 30 to the first doped layer 10 is at least 5:1; the etch selectivity of the initial channel pillar 30 to the semiconductor layer 20 is at least 5:1. The initial channel pillar 30 and the semiconductor layer 20, and the initial channel pillar 30 and the first doped layer 10 have a high etching selectivity, so that the difficulty of the thinning process and the probability of misetching the first doped layer 10 and the semiconductor layer 20 are significantly reduced.

In this embodiment, the process of thinning the sidewall of the initial trench pillar 30 includes a wet etching process. The wet etching process has the characteristic of isotropic etching, so that the side wall of the initial channel pillar 30 can be etched along the direction perpendicular to the side wall of the semiconductor laminated pillar 200, and further the thinning of the initial channel pillar 30 is realized, so that the channel pillar 40 meets the requirement of the target width. In this embodiment, the material of the initial channel pillar 30 is silicon, and the etching solution of the wet etching process includes TMAH solution.

Referring to fig. 8, the gate opening 150 is filled to form a gate 160 surrounding the sidewalls of the channel pillar 40.

The gate 160 acts as a device gate to control the opening or closing of the conduction channel when the device is in operation.

In this embodiment, in the process of forming the gate 160, the bottom dielectric layer 140 is still remained between the gate openings 150 on the sidewalls of the adjacent semiconductor stacked columns 200, so that the bottom dielectric layer 140 can play a supporting role, and the width dimension of the first doped layer 10 is larger, which is beneficial to ensuring that the semiconductor stacked columns 200 are not easy to incline, bend or collapse.

In this embodiment, the gate 160 is formed on the isolation structure 120.

In this embodiment, the gate opening 150 communicates with the via 145, and the gate 160 is also formed in part of the via 145. In this embodiment, the gate 160 also surrounds the top corner of the first doped layer 10 and the bottom corner of the semiconductor layer 20.

In this embodiment, the gate 160 is a metal gate, and the gate 160 includes: a high-k gate dielectric layer 61 surrounding the channel pillar 40 exposed by the gate opening 150, the first doped layer 10 exposed by the gate opening 150, the semiconductor layer 20, and the bottom dielectric layer 140; a work function layer 62 on the high-k gate dielectric layer 61; a gate electrode layer 63 is located on the work function layer 62 and fills the gate opening 150.

The high-k gate dielectric layer 61 is used to achieve electrical isolation between the gate 160 and the channel pillar 40 and also to achieve electrical isolation between the gate 160 and the first doped layer 10 or the semiconductor layer 20. The material of the high-k gate dielectric layer 61 is a high-k dielectric material. As an example, the material of the high-k gate dielectric layer 61 is HfO ₂.

The work function layer 62 is used to adjust the work function of the gate 160 and thus the threshold voltage of the transistor. In this embodiment, the PMOS transistor is formed, and the material of the work function layer 62 is a P-type work function material.

The gate electrode layer 63 serves as an electrode for making electrical connection between the gate electrode 160 and an external circuit or other interconnect structure. The material of the gate electrode layer 63 is a conductive material, for example: al, W, co, etc.

In this embodiment, the step of forming the gate 160 includes: forming an initial gate (not shown) in the gate opening 150 and the via 145; a portion of the initial gate located in the via 145 is removed and the remaining initial gate is used as the gate 160.

In this embodiment, the process of forming the initial gate electrode includes one or more of atomic layer deposition, physical vapor deposition, chemical vapor deposition, and electroplating. Specifically, the initial gate electrode includes an initial high-k gate dielectric layer, an initial work function layer on the initial high-k gate dielectric layer, and an initial gate electrode layer on the initial work function layer. In the embodiment, an atomic layer deposition process is adopted to form an initial high-k gate dielectric layer and an initial work function layer; and forming an initial gate electrode layer by adopting a physical vapor deposition process.

In this embodiment, a wet etching process is used to remove a portion of the initial gate electrode located in the via 145. Specifically, according to the material of the initial gate, the etching solution of the wet etching process is an acid solution capable of etching the material of the initial gate.

Referring to fig. 9 in combination, in this embodiment, after forming the gate 160, the method for forming a semiconductor structure further includes: and removing a part of the bottom dielectric layer 140 to expose the semiconductor layer 20.

The semiconductor layer 20 is exposed so that an epitaxial layer can be subsequently formed on the semiconductor layer 20.

In this embodiment, in the step of removing the bottom dielectric layer 140 with a partial thickness, the hard mask layer 104 on the semiconductor layer 20 is also removed.

With continued reference to fig. 9, the method of forming a semiconductor structure further includes: a second doped layer (not shown) is formed on top of the channel pillars 30. In this embodiment, the step of forming the second doped layer includes: an epitaxial layer 50 is formed on the semiconductor layer 20, and ions are self-doped in situ during the formation of the epitaxial layer 50, the semiconductor layer 20 and the ion-doped epitaxial layer 50 serving as the second doped layer.

The second doped layer is used as a source region or a drain region of the VGAA transistor. Specifically, in this embodiment, the first doped layer 10 is used as a source region, and the second doped layer is correspondingly used as a drain region.

By forming the epitaxial layer 50 doped with ions on the semiconductor layer 20, the volume of the second doped layer is advantageously increased, and the stress of the second doped layer on the channel region is advantageously further increased during operation of the device, thereby increasing the mobility of carriers. Meanwhile, by forming the epitaxial layer 50, the volume of the second doped layer is increased, the contact area between the subsequent second source-drain plug and the second doped layer is correspondingly increased, the second doped layer is larger in area along the direction parallel to the substrate 100, the requirement on the alignment precision of the photoetching process for forming the second source-drain plug is reduced, the process difficulty for forming the second source-drain plug is further reduced, and the contact performance between the second source-drain plug and the second doped layer is improved.

The material and doping ion type of the epitaxial layer 50 are the same as those of the semiconductor layer 20, and will not be described here again.

It should be noted that the above step of forming the second doped layer is merely an example, and the step of forming the second doped layer of the present invention is not limited thereto. For example, in the step of providing the substrate and the semiconductor stacked pillar, the semiconductor layer is doped with ions, and the semiconductor layer doped with ions is used as the second doped layer. Or in some embodiments, after forming the gate, the method of forming the semiconductor structure further comprises: removing part of the thickness of the bottom dielectric layer to expose the semiconductor layer; the step of forming the second doped layer includes: and carrying out ion doping on the semiconductor layer, wherein the semiconductor layer doped with ions is used as the second doping layer.

Referring to fig. 10 in combination, in this embodiment, after forming the gate 160 and the second doped layer, the forming method further includes: forming a first source drain plug 170 in contact with the doped layer side 110; forming a second source drain plug 180 in contact with the second doped layer; a gate plug 190 is formed in contact with the gate 160.

The first source-drain plug 170 is used as a source plug, and contacts the doped layer side 110 to electrically connect with the first doped layer 10, so that the first doped layer 10 is electrically connected with an external circuit or other interconnection structure.

The second source drain plug 180 acts as a drain plug for making electrical connection between the second doped layer and an external circuit or other interconnect structure. In this embodiment, the second source drain plug 180 is in contact with the epitaxial layer 50.

The gate plug 190 is used to make electrical connection between the gate 160 and an external circuit or other interconnect structure.

In this embodiment, the materials of the first source drain plug 170, the second source drain plug 180 and the gate plug 190 are the same, and are conductive materials, for example: w, co, ni, cu, etc.

In this embodiment, before forming the first source drain plug 170, the second source drain plug 180 and the gate plug 190, the method for forming the semiconductor structure further includes: an interlayer dielectric layer 165 is formed on the bottom dielectric layer 140, covering the gate 160 and the second doped layer.

Thus, the first source-drain plug 170 penetrates the isolation structure 120, the bottom dielectric layer 140 and the interlayer dielectric layer 165 above the doped layer side 110; the second source drain plug 180 penetrates the interlayer dielectric layer 165 above the second doped layer; the gate plug 190 penetrates the interlayer dielectric layer 165 over the gate 160.

The interlayer dielectric layer 165 is used to electrically isolate the first source drain plug 170, the second source drain plug 180, and the gate plug 190. The interlayer dielectric layer 165 is made of a dielectric material, for example: low-k dielectric materials, ultra-low k dielectric materials, silicon oxide, silicon nitride or silicon oxynitride, and the like.

Fig. 11 to 15 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention. The points of the present embodiment that are the same as those of the foregoing embodiment are not described in detail here, and the difference between the present embodiment and the foregoing embodiment is that: the initial channel pillars are used as initial bottom channel pillars 30a; the semiconductor layer is used as the second doping layer 20a; the dummy gate is used as a bottom dummy gate; the gate opening is used as a bottom gate opening; the channel pillars are used as bottom channel pillars 40a; the gate is used as the bottom gate 160a.

Referring to fig. 11, a substrate 100a, and a semiconductor stack pillar 200a protruding from the substrate 100a are provided, the semiconductor stack pillar 200a including a first doped layer 10a, an initial bottom channel pillar 30a, and a semiconductor layer for forming a second doped layer 20a, which are stacked in order from bottom to top.

In this embodiment, in the step of providing the semiconductor stacked pillar 200a, the semiconductor layer is used as the second doped layer 20a, and the semiconductor stacked pillar 200a further includes a buffer layer 310, a third doped layer 320, an initial top channel pillar 330, and a top semiconductor layer for forming the fourth doped layer 340, which are stacked on the second doped layer 20a in order from bottom to top.

By having the semiconductor stack pillar 200a further include a third doped layer 320, an initial top channel pillar 330, and a top semiconductor layer for forming a fourth doped layer 340, provision is made for subsequently forming another VGAA transistor over the second doped layer 20 a.

In this embodiment, the sidewalls of the first doped layer 10a, the initial bottom channel pillar 30a, the second doped layer 20a, the buffer layer 310, the third doped layer 320, the initial top channel pillar 330, and the top semiconductor layer are flush. In this embodiment, the semiconductor stacked column 200a has a cylindrical structure.

The buffer layer 310 serves to prevent defects such as dislocation caused by a large stress generated directly on the second doped layer 20a by the third doped layer 320. In this embodiment, the material of the buffer layer 310 is silicon.

The third doped layer 320 is used to form a source or drain region of another VGAA transistor. The fourth doped layer 340 is used to form a source or drain region of another VGAA transistor. In this embodiment, the third doped layer 320 is used as a source region and the fourth doped layer is used as a drain region.

In this embodiment, the first doped layer 10a and the second doped layer 20a are doped with first type ions; the third doped layer 320 and the fourth doped layer 340 are doped with ions of a second type, which is different from the first type. Therefore, the first doped layer 10a, the second doped layer 20a, the bottom channel pillar 40a and the corresponding bottom gate 160a are used to form a first type transistor, the third doped layer 320, the fourth doped layer 340 and the corresponding top channel pillar, and the subsequent top gate are used to form a second type transistor, and the doping types of the second type transistor and the first type transistor are different, so that two different types of devices can be formed on the same semiconductor stacked pillar 200a, which is beneficial to meeting the requirements of different devices and reducing the complexity of the process.

In this embodiment, the second type transistor is an NMOS transistor, and thus, N-type ions are doped in the third doped layer 320 and the fourth doped layer 340. The material of the third doped layer 320 and the top semiconductor layer is SiC or SiP.

The initial top channel pillars 330 are used to form top channel pillars via a subsequent thinning process.

In this embodiment, the material of the initial top channel pillars 330 is silicon.

In this embodiment, the top semiconductor layer is doped with ions, and the doping type of the ions in the top semiconductor layer is the same as that of the third doped layer 320, and the top semiconductor layer 340 doped with ions is used as the fourth doped layer 340.

For a detailed description of the third doped layer 320, the top semiconductor layer, the fourth doped layer 340 and the initial top channel pillar 330, please refer to the previous embodiments for a detailed description of the first doped layer, the channel pillar, the semiconductor layer and the second doped layer, which will not be repeated herein.

Referring to fig. 12, a bottom dummy gate (not shown) surrounding the sidewalls of the initial bottom channel pillar 30a and exposing the second doped layer 20a is formed; forming a bottom dielectric layer 140a on the substrate 100a, wherein the bottom dielectric layer is filled between adjacent semiconductor laminated columns 200a, surrounds the side walls of the semiconductor laminated columns 200a exposed by the bottom dummy gate, and covers the top surface of the bottom dummy gate; removing the bottom dummy gate to expose sidewalls of the initial bottom channel pillar 30a, forming a bottom gate opening (not shown) in the bottom dielectric layer 140a; thinning the side wall of the initial bottom channel pillar 30a exposed by the bottom gate opening, and using the rest of the initial bottom channel pillar 30a as a bottom channel pillar 40a; the bottom gate opening is filled to form a bottom gate 160a surrounding the sidewalls of the bottom channel pillar 40 a.

The steps of forming the bottom dummy gate, the bottom dielectric layer 140a and the bottom gate opening, thinning the sidewalls of the initial bottom channel pillar 30a, and forming the bottom gate 160a are referred to in the corresponding description of the foregoing embodiments, and are not repeated herein.

Referring to fig. 13, after forming the bottom gate 160a, the method for forming the semiconductor structure further includes: a portion of the bottom dielectric layer 140a is removed to expose the initial top channel pillars 330.

In this embodiment, the method for forming a semiconductor structure further includes: after forming the bottom gate 160a, a common source-drain interconnect layer 345 is formed that covers sidewalls of the buffer layer 310 and also extends over portions of the sidewalls of the second and third doped layers 20a and 320 before forming the top dummy gate.

The common source-drain interconnection layer 345 covers part of the sidewalls of the second doped layer 20a and the third doped layer 320, thereby electrically connecting the second doped layer 20a and the third doped layer 320, which is beneficial to reducing the complexity of the process for electrically extracting the second doped layer 20a or the third doped layer 320. Specifically, the common source-drain interconnection layer 345 surrounds the sidewall of the buffer layer 310 and extends to surround a portion of the sidewalls of the third doped layer 320 and the second doped layer 20a, which is advantageous in increasing the contact area of the common interconnection layer 345 with the third doped layer 320 or the second doped layer 20 a. A common source-drain interconnect layer 345 is formed on the bottom dielectric layer 140 a.

Referring to fig. 14, a top dummy gate 350 is formed surrounding the initial top channel pillar 330; a top dielectric layer 360 is formed on the bottom dielectric layer 140, and fills the space between adjacent semiconductor stacked columns 200a, surrounds the sidewalls of the semiconductor stacked columns 200a exposed by the top dummy gate 350, and covers the top surface of the top dummy gate 350, and the top dielectric layer 360 exposes the sidewalls of the top dummy gate 350 away from the adjacent semiconductor stacked columns 200 a.

In this embodiment, the top dummy gate 350 is located on the sidewall of the adjacent semiconductor stacked column 200a, so that in the process of forming the top dielectric layer 360, the top dielectric layer 360 can cover the sidewall of the top dummy gate 350 opposite to the adjacent semiconductor stacked column 200a, so that the top dielectric layer 360 can support the semiconductor stacked column 200a, and the semiconductor stacked column 200a is not suitable to bend or tilt.

In this embodiment, after forming the common source-drain interconnection layer 345 and before forming the top dummy gate 350, the forming method further includes: a spacer layer 355 is formed on the common source-drain interconnection layer 345 surrounding a portion of the sidewall of the third doped layer 320. Spacer layer 355 is used to achieve spacing between common source-drain interconnect layer 345 and top dummy gate 350, and correspondingly to achieve electrical isolation between common source-drain interconnect layer 345 and top gate 350. The material of the spacer layer 355 is an insulating material. Thus, a top dummy gate 350 is formed on spacer 355.

For the description of the top dummy gate 350 and the top dielectric layer 360, reference may be made to the corresponding descriptions of the dummy gate and the bottom dielectric layer in the foregoing embodiments, and thus, the description is not repeated here.

Referring to fig. 15, top dummy gate 350 is removed to form a top gate opening (not shown); thinning the sidewalls of the initial top channel pillars 330 exposed by the top gate openings to form top channel pillars 370; a top gate 380 is formed in the top gate opening surrounding the top channel pillar 370.

The top channel pillars 370 are used to provide conductive channels for the second type transistors.

The top gate 380 is used to control the turning on or off of the conduction channel of the second transistor.

For a detailed description of removing the top dummy gate 350, thinning the sidewalls of the initial top channel pillar 330, and forming the top gate 380, reference may be made to the corresponding description of the previous embodiments, which are not repeated here.

With continued reference to fig. 15, the forming method further includes: a top source drain plug 390 is formed overlying the fourth doped layer 340 and in contact with the fourth doped layer 340. The top source drain plug 390 is used to make electrical connection between the fourth doped layer 340 and an external circuit or other interconnect structure.

For a specific description of the method for forming a semiconductor structure according to this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 10, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a semiconductor stacked column 200 protruding from the substrate 100, wherein the semiconductor stacked column 200 includes a first doped layer 10, a channel column 40, and a second doped layer (not labeled) stacked in this order from bottom to top, and the sidewalls of the channel column 40 are recessed with respect to the sidewalls of the first doped layer 10 and the second doped layer along a direction perpendicular to the sidewalls of the channel column 40; a gate electrode 160 surrounding the sidewall of the channel pillar 40, the gate electrode 160 being located on the sidewall of the adjacent semiconductor stack pillar 200 with a space therebetween; dielectric layer 140 fills between gates 160 located on sidewalls of adjacent semiconductor stack pillars 200 and covers the top surface of gates 160, dielectric layer 140 covering the sidewalls of gates 160 opposite adjacent semiconductor stack pillars 200.

In this embodiment, the dielectric layer 140 is used as the bottom dielectric layer 140.

The channel pillar 40 has a target width in a direction perpendicular to the sidewall of the channel pillar 40. Along the direction perpendicular to the sidewall of the channel pillar 40, the sidewall of the channel pillar 40 is recessed with respect to the sidewalls of the first doped layer 10 and the second doped layer, that is, the widths of the first doped layer 10 and the second doped layer are greater than the target width of the channel pillar 40, and the widths of the first doped layer 10 and the second doped layer are greater, which is advantageous for improving the stability of the semiconductor stack pillar 200 standing on the substrate 100.

Furthermore, a space is provided between the gates 160 located on the sidewalls of the adjacent semiconductor stacked columns 200, a bottom dielectric layer 140 is filled between the adjacent semiconductor stacked columns 200 to cover the sidewalls of the gates 160 opposite to the adjacent semiconductor stacked columns 200, and the bottom dielectric layer 140 can play a role in supporting the semiconductor stacked columns 200 during the formation of the semiconductor structure; both aspects are beneficial to reducing the probability of the semiconductor stacked pillar 200 having a tilt or bend problem during the formation of a semiconductor structure, and improving the performance of a vertical all-around-gate (VGAA) transistor.

The substrate 100 is used to provide a process platform for forming VGAA transistors.

The semiconductor stacked columns 200 extend in a direction perpendicular to the substrate 100, and can improve the area utilization efficiency of the semiconductor structure. In this embodiment, the semiconductor stacked column 200 has a cylindrical structure. In the present embodiment, the number of semiconductor stacked columns 200 is plural, and the plural semiconductor stacked columns 200 are separated on the substrate 100.

In this embodiment, the first doped layer 10 serves as the source region of the vertical fully-surrounding gate transistor.

In this embodiment, along the direction perpendicular to the sidewall of the semiconductor stacked pillar 200, the width of the semiconductor stacked pillar 200 is larger, and the width dimension of the first doped layer 10 is also larger, so that the volume of the first doped layer 10 is larger and the contact area between the first doped layer 10 and the substrate 100 is larger, which is beneficial to improving the stability of the semiconductor stacked pillar 200 erected on the substrate 100, so that the semiconductor stacked pillar 200 is not easy to bend, tilt or collapse. In addition, the width dimension of the first doped layer 10 is larger, and the volume of the first doped layer 10 is correspondingly larger, so that the stress on the channel region is improved, the carrier mobility of the channel region is improved, and the performance of the semiconductor structure is optimized.

In this embodiment, the first doped layer 10 is different from the material of the channel pillar 40, and the channel pillar 40 is formed by thinning the sidewall of the initial channel pillar, so that the etching selectivity between the initial channel pillar and the first doped layer 10 is beneficial to reducing the probability of damage of the first doped layer 10 during the process of thinning the sidewall of the initial channel pillar to form the channel pillar 40.

In this embodiment, the material of the first doped layer 10 may be SiGe doped with P-type ions to form a PMOS transistor. In other embodiments, when forming an NMOS transistor, the material of the first doped layer may be SiC or SiP doped with N-type ions.

In this embodiment, the direction perpendicular to the sidewall of the semiconductor stacked column 200 is parallel to the substrate 100.

In this embodiment, the semiconductor stacked column 200 has a cylindrical structure, and the width refers to the cross-sectional diameter of the channel column 40. In this embodiment, the material of the channel pillar 40 includes Si.

The channel pillar 40 has a target width in a direction perpendicular to the sidewall of the channel pillar 40; the dimensions of the setback of the single side wall of the channel pillar 40 with respect to the sidewall of the first doped layer 10 are setback widths, which are 10% to 30% of the target width.

In this embodiment, the second doped layer is used as a drain region of the VGAA transistor. In this embodiment, the second doped layer includes a semiconductor layer 20 and an epitaxial layer 50 on the semiconductor layer 20 and doped with ions.

By including the semiconductor layer 20 and the epitaxial layer 50 in the second doped layer, the volume of the second doped layer is advantageously increased, and the stress of the second doped layer on the channel region is advantageously increased during operation of the device, thereby increasing the mobility of carriers. Meanwhile, by arranging the epitaxial layer 50, the volume of the second doped layer is increased, the contact area between the second source and drain plug and the second doped layer is correspondingly increased, the area of the second doped layer along the direction parallel to the substrate 100 is larger, the requirement on the alignment precision of the photoetching process for forming the second source and drain plug is reduced, the forming difficulty of the second source and drain plug is further reduced, and the forming quality of the second source and drain plug and the contact performance of the second source and drain plug and the second doped layer are correspondingly improved.

In this embodiment, the semiconductor layer 20 is made of a different material from the channel pillar 40. Specifically, the semiconductor layer 20 is the same material as the first doped layer 10. In this embodiment, the PMOS transistor is formed, and the material of the semiconductor layer 20 is SiGe. In other embodiments, the material of the semiconductor layer may be SiC or SiP when forming the NMOS transistor.

In this embodiment, the semiconductor layer 20 is further doped with ions, and the doping ion type in the semiconductor layer 20 is the same as the doping ion type of the first doping layer 10. The material and doping ion type of the epitaxial layer 50 are the same as those of the semiconductor layer 20, and will not be described here again.

In this embodiment, the semiconductor structure further includes: the doped layer side portion 110 is connected to the bottom of the first doped layer 10, is located on the substrate 100, and extends in a direction parallel to the substrate 100.

The semiconductor structure typically further comprises: the first source drain plug 170 is in contact with the doped layer side 110.

By arranging the doped layer side portion 110, the first doped layer 10 is electrically connected with the first source drain plug 170 through the doped layer side portion 110, the doped layer side portion 110 has a larger area along the direction parallel to the substrate 100, the difficulty in forming the first source drain plug 170 is reduced, and by arranging the doped layer side portion 110, the first doped layers 10 of the adjacent semiconductor laminated columns 200 can be contacted according to actual process requirements, so that the first doped layers 10 of the adjacent semiconductor laminated columns 200 are electrically connected.

In this embodiment, the semiconductor structure further includes: an isolation structure 120 is located on the substrate 100 and surrounds a portion of the sidewall of the first doped layer 10.

The isolation structure 120 is used to isolate adjacent semiconductor stacked columns 200. In this embodiment, the isolation structure 120 is located on the doped layer side 110, and the isolation structure 120 is further used to isolate the doped layer side 110 from the gate 160. In this embodiment, the material of the isolation structure 120 is silicon nitride.

In this embodiment, the gate 160 also surrounds the top corner of the first doped layer 10 and the bottom corner of the semiconductor layer 20.

In this embodiment, a gate opening (not shown) exposing the sidewall of the channel pillar 40 and a via (not shown) in the bottom dielectric layer 140 on a side of the semiconductor stack pillar 200 away from the adjacent semiconductor stack pillar 200 are formed in the bottom dielectric layer 140, and the gate opening is in communication with the via.

In this embodiment, the gate 160 is located in the gate opening and in a portion of the via.

In this embodiment, the gate 160 is a metal gate, and the gate 160 includes: a high-k gate dielectric layer 61 surrounding the sidewall of the channel pillar 40, the first doped layer 10 exposed by the gate opening, the semiconductor layer 20, and the bottom dielectric layer 140; a work function layer 62 on the high-k gate dielectric layer 61; a gate electrode layer 63 is located on the work function layer 62 and fills the gate opening.

The bottom dielectric layer 140 is used to isolate adjacent semiconductor stack pillars 120 or gates 160 from each other. In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide. A bottom dielectric layer 140 is located on the isolation structures 120.

The space is provided between the gates 160 on the sidewalls of the adjacent semiconductor stacked columns 200, the bottom dielectric layer 140 is further filled between the gates 160 on the sidewalls of the adjacent semiconductor stacked columns 200, and the bottom dielectric layer 140 can play a role in supporting the semiconductor stacked columns 200 during the formation of the semiconductor structure, so as to reduce the probability of tilting or bending the semiconductor stacked columns 200, thereby being beneficial to improving the process yield and the performance of the VGAA transistor. In this embodiment, the spacing between the gates 160 on the sidewalls of the adjacent semiconductor stacked columns 200 is 30% to 70% of the spacing between the adjacent semiconductor stacked columns 200, for example: 50%.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 165 on the bottom dielectric layer 140, covering the gate 160 and the second doped layer; a first source drain plug 170 penetrating the isolation structure 120, the bottom dielectric layer 140 and the interlayer dielectric layer 165 above the doped layer side 110 and contacting the doped layer side 110; a second source drain plug 180 penetrating the interlayer dielectric layer 165 above the second doped layer and contacting the second doped layer; a gate plug 190 penetrates the interlayer dielectric layer 140 above the gate 160 and contacts the gate 160.

The interlayer dielectric layer 165 is used to electrically isolate the first source drain plug 170, the second source drain plug 180, and the gate plug 190. The interlayer dielectric layer 165 is made of a dielectric material.

The first source-drain plug 170 is used as a source plug, and contacts the doped layer side 110 to electrically connect with the first doped layer 10, so that the first doped layer 10 is electrically connected with an external circuit or other interconnection structure. The second source drain plug 180 acts as a drain plug for making electrical connection between the second doped layer and an external circuit or other interconnect structure. In this embodiment, the second source drain plug 180 is in contact with the epitaxial layer 50.

The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 15, a schematic structural diagram of another embodiment of the semiconductor structure of the present invention is shown.

The points of the present embodiment that are the same as those of the foregoing embodiment are not described in detail here, and the difference between the present embodiment and the foregoing embodiment is that:

The channel pillars are used as bottom channel pillars 40a; the gate is used as a bottom gate 160a; the semiconductor stacked column 200a further includes: the buffer layer 310, the third doped layer 320, the top channel pillar 370 and the fourth doped layer 340 sequentially stacked on the second doped layer 20a, wherein the sidewall of the top channel pillar 370 is retracted with respect to the sidewall of the third doped layer 320 or the fourth doped layer 340; the semiconductor structure further includes: a top gate 380 surrounding sidewalls of the top channel pillar 370.

By having the semiconductor stack pillar 200a further include the third doped layer 320, the top channel pillar 370, and the fourth doped layer 340, another VGAA transistor can be formed over the second doped layer 20 a.

The third doped layer 320 is used to form a source or drain region of another VGAA transistor. The fourth doped layer 340 is used to form a source or drain region of another VGAA transistor. In this embodiment, the third doped layer 320 is used as a source region and the fourth doped layer 340 is used as a drain region.

In this embodiment, the first doped layer 10a and the second doped layer 20a are doped with first type ions; the third doped layer 320 and the fourth doped layer 340 are doped with ions of a second type, which is different from the first type. Therefore, the first doped layer 10a, the second doped layer 20a, the bottom channel pillar 40a and the corresponding bottom gate 160a are used to form a first type transistor, the third doped layer 320, the fourth doped layer 340 and the corresponding top channel pillar 370 and the corresponding top gate 380 are used to form a second type transistor, and the doping types of the second type transistor and the first type transistor are different, so that two different types of devices can be formed on the same semiconductor stack pillar 200a, which is beneficial to meeting the requirements of different devices and reducing the complexity of the process.

In this embodiment, the second type transistor is an NMOS transistor, and thus, N-type ions are doped in the third doped layer 320 and the fourth doped layer. The material of the third doped layer 320 and the fourth doped layer 340 is SiC or SiP. In this embodiment, the material of the top channel pillars 370 is silicon.

In this embodiment, the semiconductor structure further includes: a common source-drain interconnection layer 345 covers the sidewalls of the buffer layer 310 and extends to cover portions of the sidewalls of the third doped layer 320 and the second doped layer 20 a.

The common source-drain interconnection layer 345 covers part of the sidewalls of the second and third doped layers 20a and 320, thereby realizing electrical connection between the second and third doped layers 20a and 320, which is advantageous in reducing process complexity of electrically extracting the second and third doped layers 20a and 320. Specifically, the common source-drain interconnection layer 345 surrounds the sidewall of the buffer layer 310 and extends to surround a portion of the sidewalls of the third doped layer 320 and the second doped layer 20a, which is advantageous in increasing the contact area of the common interconnection layer 345 with the third doped layer 320 or the second doped layer 20 a. A common source-drain interconnect layer 345 is located on the bottom dielectric layer 140 a.

In this embodiment, the semiconductor structure further includes: spacer layer 355, located between top gate 380 and common source drain interconnect layer 345, surrounds a portion of the sidewalls of third doped layer 320. Spacer layer 355 is used to achieve spacing between common source-drain interconnect layer 345 and top gate 380, and correspondingly to achieve electrical isolation between common source-drain interconnect layer 345 and subsequent top gate 380. The material of the spacer layer 355 is an insulating material.

Thus, top gate 380 is located on spacer 355.

In this embodiment, the semiconductor structure further includes: and a top dielectric layer 360 filled between adjacent semiconductor stacked columns 200a, surrounding the sidewalls of the semiconductor stacked columns 200a exposed by the top gate 380, and covering the top surface of the top gate 380.

The top dielectric layer 360 is used to support the semiconductor stack column 200 a.

In this embodiment, the semiconductor structure further includes: a top source drain plug 390 is located on the fourth doped layer 340 and contacts the fourth doped layer 340. The top source drain plug 390 is used to make electrical connection between the fourth doped layer 340 and an external circuit or other interconnect structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

Providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doped layer, an initial channel column and a semiconductor layer for forming a second doped layer, which are sequentially stacked from bottom to top;

forming a dummy gate surrounding the initial channel pillar sidewall and exposing the semiconductor layer;

Forming a bottom dielectric layer which is filled between adjacent semiconductor laminated columns, surrounds and covers the side walls and the top surfaces of the semiconductor laminated columns exposed by the dummy gate and covers the top surfaces of the dummy gate on the substrate, wherein the bottom dielectric layer exposes the side walls of the dummy gate far away from the adjacent semiconductor laminated columns;

Removing the dummy gate, exposing the side wall of the initial channel column, and forming a gate opening in the bottom dielectric layer;

Thinning the side wall of the initial channel column exposed out of the gate opening, wherein the rest initial channel columns are used as channel columns;

and filling the grid opening to form a grid surrounding the side wall of the channel column.

2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the dummy gate, there is a space between the dummy gates located on the sidewalls of the adjacent semiconductor stack pillars, the sidewalls of the dummy gates opposite to the adjacent semiconductor stack pillars are first sidewalls, and the sidewalls of the dummy gates away from the adjacent semiconductor stack pillars are second sidewalls;

In the step of forming the bottom dielectric layer, the bottom dielectric layer covers the first side wall of the dummy gate and exposes the second side wall of the dummy gate.

3. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate and a semiconductor stack pillar, sidewalls of the first doped layer are flush with sidewalls of the initial channel pillar and sidewalls of the semiconductor layer.

4. The method of forming a semiconductor structure of claim 1, wherein the process of thinning the initial trench pillar sidewalls comprises a wet etch process.

5. The method of forming a semiconductor structure of claim 4, wherein the etching solution of the wet etching process comprises a TMAH solution.

6. The method of forming a semiconductor structure of claim 1, wherein in the step of thinning the initial trench pillar sidewall, an etch selectivity of the initial trench pillar to the first doped layer is at least 5:1, and an etch selectivity of the initial trench pillar to the semiconductor layer is at least 5:1.

7. The method of forming a semiconductor structure of claim 1, wherein the channel pillar has a target width in a direction perpendicular to sidewalls of the semiconductor stack pillar;

In the step of providing a substrate and a semiconductor stacked pillar, a width of the initial channel pillar is 1.2 times to 1.6 times the target width in a direction perpendicular to a sidewall of the semiconductor stacked pillar.

8. The method of forming a semiconductor structure of claim 1, wherein after providing a substrate and a semiconductor stack pillar, and before forming the dummy gate, the method of forming a semiconductor structure further comprises: and forming an isolation structure on the substrate to surround part of the side wall of the first doping layer.

9. The method of forming a semiconductor structure of claim 2, wherein a spacing between dummy gates located on sidewalls of adjacent ones of said semiconductor stacked columns is between 30% and 70% of a spacing between adjacent ones of said semiconductor stacked columns.

10. The method of forming a semiconductor structure of claim 1 or 2, wherein the step of forming the dummy gate comprises: forming an initial dummy gate covering the semiconductor stack column on the substrate;

removing part of the initial dummy gate with the thickness to enable the rest initial dummy gate to expose the semiconductor layer;

And patterning the rest initial dummy gate, and reserving part of the initial dummy gate surrounding the side wall of the initial channel column as the dummy gate.

11. The method of forming a semiconductor structure according to claim 1 or 2, wherein in the step of forming the bottom dielectric layer, the bottom dielectric layer covers top surfaces of the semiconductor stack pillars;

The step of forming the bottom dielectric layer comprises the following steps: forming a dielectric material layer covering the semiconductor laminated column and the dummy gate on the substrate;

and patterning the dielectric material layer, and reserving the dielectric material layer which is positioned between adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the dummy gate and covers the top surface of the dummy gate as a bottom dielectric layer.

12. The method of forming a semiconductor structure of claim 1, wherein the process of forming the gate electrode comprises one or more of atomic layer deposition, physical vapor deposition, chemical vapor deposition, and electroplating.

13. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate and a semiconductor stack column, a doped layer side portion connected to a bottom portion of the first doped layer, located on the substrate and extending in a direction parallel to the substrate is further formed;

after forming the gate, the method for forming the semiconductor structure further comprises: and forming a first source drain plug which is contacted with the side part of the doped layer.

14. The method of forming a semiconductor structure of claim 13, wherein the step of providing a substrate and a semiconductor stack pillar comprises: providing a substrate, and sequentially stacking a first initial doping layer, a channel material layer and an initial semiconductor layer on the substrate from bottom to top;

And patterning the initial semiconductor layer, the channel material layer and a part of the first initial doping layer to form the side part of the doping layer, the first doping layer, the initial channel column and the semiconductor layer.

15. The method of forming a semiconductor structure of claim 1, wherein the initial channel pillar is configured to act as an initial bottom channel pillar; the semiconductor layer is used as a second doping layer; the dummy gate is used as a bottom dummy gate; the gate opening is used as a bottom gate opening; the channel column is used as a bottom channel column; the grid is used as a bottom grid;

In the step of providing a semiconductor stacked pillar, the semiconductor stacked pillar further includes a buffer layer, a third doped layer, an initial top channel pillar, and a top semiconductor layer for forming a fourth doped layer stacked in this order from bottom to top on the second doped layer;

After forming the bottom gate, the method for forming the semiconductor structure further comprises: removing a part of the thickness of the bottom dielectric layer to expose the initial top channel column; forming a top dummy gate surrounding the initial top channel pillar; forming a top dielectric layer which is filled between adjacent semiconductor laminated columns, surrounds the side walls of the semiconductor laminated columns exposed by the top dummy gate and covers the top surface of the top dummy gate on the bottom dielectric layer, wherein the top dielectric layer exposes the side walls of the top dummy gate far away from the adjacent semiconductor laminated columns; removing the top dummy gate to form a top gate opening; thinning the side wall of the initial top channel column exposed out of the top gate opening to form a top channel column; a top gate is formed in the top gate opening surrounding the top channel pillar.

16. A semiconductor structure, comprising:

a substrate;

The semiconductor laminated column protrudes out of the substrate and comprises a first doping layer, a channel column and a second doping layer which are sequentially stacked from bottom to top, and the side wall of the channel column is retracted relative to the side walls of the first doping layer and the second doping layer along the direction perpendicular to the side wall of the channel column;

A gate surrounding a sidewall of the channel pillar, the gate being located adjacent to the sidewall of the semiconductor stack pillar with a space therebetween;

And the dielectric layer is filled between the grid electrodes positioned on the side walls of the adjacent semiconductor laminated columns and covers the top surface of the grid electrode and the side walls of the semiconductor laminated columns exposed by the grid electrode.

17. The semiconductor structure of claim 16, wherein the material of the channel pillar comprises Si; the materials of the first doped layer and the second doped layer comprise SiGe, siP or SiC.

18. The semiconductor structure of claim 16, wherein the channel pillar has a target width in a direction perpendicular to the channel pillar sidewalls;

The dimension of the single-side sidewall of the channel column, which is retracted relative to the sidewall of the first doped layer, is an retraction width, and the retraction width is 10% to 30% of the target width.

19. The semiconductor structure of claim 16, wherein the channel pillar is configured to function as a bottom channel pillar; the grid is used as a bottom grid;

the semiconductor stacked column further includes: the buffer layer, the third doping layer, the top channel column and the fourth doping layer are sequentially stacked on the second doping layer from bottom to top, and the side wall of the top channel column is retracted relative to the side wall of the third doping layer or the side wall of the fourth doping layer;

the semiconductor structure further includes: a top gate surrounding the top channel pillar sidewall.

20. The semiconductor structure of claim 19, wherein the first doped layer and the second doped layer are doped with a first type of ion; the third doped layer and the fourth doped layer are doped with second type ions, and the second type ions are different from the first type ions.