CN109962105B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN109962105B
CN109962105B CN201711338301.5A CN201711338301A CN109962105B CN 109962105 B CN109962105 B CN 109962105B CN 201711338301 A CN201711338301 A CN 201711338301A CN 109962105 B CN109962105 B CN 109962105B
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forming
layer
side wall
fin
sacrificial layer
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CN109962105A (en
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李勇
洪中山
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a side wall covering the side walls of the channel region and the top region of the fin part column; forming a first conductive structure on the surface of the side wall of the bottom area by taking the side wall as a mask; after the first conductive structure is formed, removing the side wall; after the side walls are removed, a grid electrode structure is formed at the top of the first conductive structure, and the grid electrode structure is located on the surface of the fin column channel region; and after the gate structure is formed, forming a second conductive structure on the top of the gate structure, wherein the second conductive structure is positioned on the surface of the top area of the fin column. The forming method can improve the integration level of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the element density and integration of semiconductor devices increase, the size of transistors also becomes smaller, and the reduction in the size of transistors makes short-channel effects more and more significant.
To reduce short channel effects, finfets operate. The grid electrode of the fin field effect transistor is in a fork-shaped 3D structure similar to a fish fin. The grid electrode of the fin field effect transistor can be switched on and off in the multi-side control circuit of the fin part, so that the short channel effect of the transistor can be well inhibited.
The integration of either planar or finfet devices is still low. In order to improve the integration of a semiconductor structure, a vertical nanowire transistor is proposed.
However, the performance of the existing vertical nanowire transistor is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a fin pillar thereon, the fin pillar comprising: a bottom region, a channel region on the bottom region and a top region on the channel region; forming a side wall covering the side walls of the channel region and the top region of the fin part column; forming a first conductive structure on the surface of the side wall of the bottom area by taking the side wall as a mask; after the first conductive structure is formed, removing the side wall; after the side walls are removed, a grid electrode structure is formed at the top of the first conductive structure, and the grid electrode structure is located on the surface of the fin column channel region; and after the gate structure is formed, forming a second conductive structure on the top of the gate structure, wherein the second conductive structure is positioned on the surface of the top area of the fin column.
Optionally, the fin column is made of silicon, germanium, silicon carbide or a monocrystal composed of III-V group elements.
Optionally, the step of forming the side wall includes: forming a sacrificial layer on the substrate, wherein the surface of the sacrificial layer is flush with the surface of the top of the bottom area of the fin column; forming a side wall layer covering the surface of the sacrificial layer and the side walls of the channel region and the top region of the fin part column, wherein the side wall layer is made of different materials from the sacrificial layer; and removing the sacrificial layer and the side wall layer covering the sacrificial layer to form the side wall.
Optionally, the material of the sacrificial layer is silicon oxide or an organic dielectric material.
Optionally, the step of forming the sacrificial layer includes: forming an initial sacrificial layer on the substrate, wherein the surface of the initial sacrificial layer is higher than the top surface of the bottom area of the fin column; and etching the initial sacrificial layer to form a sacrificial layer, wherein the surface of the sacrificial layer is flush with the top surface of the bottom area.
Optionally, the initial sacrificial layer is made of silicon oxide, and the process for forming the initial sacrificial layer includes a fluid chemical vapor deposition process; or, the initial sacrificial layer is made of an organic dielectric material, and the process for forming the initial sacrificial layer comprises a spin coating process.
Optionally, the process for etching the initial sacrificial layer includes one or two of dry etching and wet etching.
Optionally, the step of removing the sacrificial layer and the sidewall layer covering the sacrificial layer includes: performing anisotropic etching on the side wall layer, and removing the side wall layer covering the sacrificial layer to form a side wall; and removing the sacrificial layer after the anisotropic etching.
Optionally, the material of the sidewall layer is silicon nitride or silicon oxynitride.
Optionally, the process of forming the sidewall layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the thickness of the side wall is 2nm to 20 nm; the height of the side wall is 6 nm-70 nm.
Optionally, before forming the gate structure, the method further includes: forming a first isolation layer on top of the first conductive structure; before forming the second conductive structure, the method further comprises: and forming a second isolation layer on the top of the gate structure.
Optionally, the first isolation layer is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material; the second isolation layer is made of silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric material.
Optionally, after removing the sacrificial layer and before removing the sidewall, the method further includes: forming a first doping area in the bottom area of the fin column, wherein the first doping area is provided with first doping ions; the first conductive structure is positioned on the surface of the first doped region; after the gate structure is formed and before the second conductive structure is formed, the method further includes: forming a second doping area in the fin portion column top area, wherein second doping ions are arranged in the second doping area; the second doping ions have a conductivity type opposite to or the same as that of the first doping ions.
Optionally, the gate structure surrounds the fin pillar channel region; the first conductive structure surrounds the fin column bottom region, and the second conductive structure surrounds the fin column top region.
Optionally, the first conductive structure includes: a first metallization on the surface of the bottom region of the fin pillar; the step of forming the first conductive structure comprises: forming a first metal layer on the surface of the bottom area of the fin column and the surface of the side wall; and carrying out first annealing treatment on the first metal layer to enable the first metal layer to react with the bottom area of the fin portion column to form a first metallization.
Optionally, the first conductive structure further includes: a first plug covering a sidewall surface of the first metallization; the step of forming the first conductive structure further comprises: forming an initial plug covering the first metallization and the side wall; and carrying out back etching on the initial plug, and removing part of the initial plug to form a plug, wherein the top surface of the plug is lower than or flush with the top surface of the bottom area.
Optionally, after the first annealing treatment, the step of forming the first conductive structure further includes: removing the first metal layer on the surface of the side wall; removing the first metal layer on the surface of the side wall before forming the initial plug; or after the first conductive structure is formed, removing the first metal layer on the surface of the side wall.
Optionally, the step of forming the first conductive structure includes: forming a first conducting layer covering the side wall of the bottom area of the fin part column and the side wall; and etching back the first conductive layer by taking the side wall as a mask, removing part of the first conductive layer to form a first conductive structure, wherein the top surface of the first conductive structure is lower than or level to the top surface of the channel region.
The technical scheme of the invention also provides a semiconductor structure formed by the forming method.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the arrangement directions of the bottom region, the channel region and the top region are vertical to the surface of the substrate, and the bottom region and the top region are respectively used for forming the source region and the drain region of the formed semiconductor structure, so that the arrangement directions of the source region, the drain region and the grid electrode of the formed semiconductor structure are vertical to the surface of the substrate, the area of the surface of the substrate occupied by the formed semiconductor structure is smaller, and the integration level of the formed semiconductor structure is higher. In addition, before the first conductive structure is formed, side walls are formed on the surfaces of the channel region and the top region of the fin column, and the side walls can prevent a first conductive structure material from being formed on the surface of the channel region of the fin column in the process of forming the first conductive structure, so that the performance of the formed semiconductor structure is influenced.
Further, when the conductivity types of the first doped ions and the second doped ions are opposite, the formed semiconductor structure is a tunneling field effect transistor. The gate structure surrounds the fin column channel region, and the gate structure can control electric field distribution in the fin column from each side surface of the fin column channel region, so that the probability that electrons in the channel region penetrate through a potential barrier between the channel region and the bottom region or the top region can be increased, the subthreshold slope of the tunneling field effect transistor can be reduced, and the performance of the formed semiconductor structure can be improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of the steps of an embodiment of a method of forming a vertical nanowire transistor;
fig. 3 to 17 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The prior art semiconductor structure has many problems, such as: the performance of the semiconductor structure is poor and the integration level is low.
The reason why the integration level of the conventional semiconductor structure is low is now analyzed in combination with a semiconductor structure:
the conventional planar transistor occupies a large substrate surface, so that the integration degree of the semiconductor structure is low. In order to improve the integration of the formed semiconductor structure, a vertical nanowire transistor is proposed.
Fig. 1 and 2 are schematic structural diagrams of steps of a method of forming a vertical nanowire transistor.
Referring to fig. 1, a substrate 130 is provided, the surface of the substrate 130 has a fin pillar 131, and the fin pillar 131 includes a bottom region I, a channel region II on the bottom region I, and a top region III on the channel region II.
With continued reference to fig. 1, a first metal silicide 141 is formed to connect the bottom region I of the fin pillar 131; a second metal silicide 142 is formed on the top surface of the fin pillar 131.
Referring to fig. 2, a first isolation layer 150 is formed on the substrate 130, wherein the first isolation layer 150 covers sidewalls of the bottom region I of the fin pillar 131 and sidewalls of the first metallization 141; forming a gate structure 151 on top of the first isolation layer 150, wherein the gate structure 151 is located on the surface of the sidewall of the channel region II; a second isolation layer 152 is formed on top of the gate structure 151, and the second isolation layer 152 covers the sidewall of the top region III and exposes the second metal silicide 142.
Subsequently forming a first plug connecting the first metal silicide 141; a second plug is formed connecting the second metal silicide 142.
Wherein the forming steps of the first metal silicide 141 and the second metal silicide 142 comprise: forming an oxide layer on the sidewall surface of the fin pillar 131; forming metal layers on the top and the sidewall surfaces of the fin portion pillar 131 and the surface of the oxide layer; and annealing the metal layer, wherein a part of the metal layer reacts with the substrate 130 to form a first metal silicide 141, and a part of the metal layer reacts with the top of the fin column 131 to form a second metal silicide 142.
Since the oxide layer covers the surface of the sidewall of the fin portion pillar 131, the metal layer does not contact the sidewall of the fin portion pillar 131, and the metal layer does not react with the sidewall of the fin portion pillar 131 during the annealing process. Therefore, the first metallization 141 is only located on the surface of the substrate 130, and the contact area between the first metallization 141 and the bottom region I of the fin column 131 is small, which results in high contact resistance between the first metallization 141 and the bottom region I of the fin column 131, and thus the performance of the formed vertical nanowire transistor is poor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a side wall covering the side walls of the channel region and the top region of the fin part column; forming a first conductive structure on the surface of the side wall of the bottom area by taking the side wall as a mask; and after the first conductive structure is formed, removing the side wall. The forming method can improve the integration level of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 17 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
It should be noted that, because the tunnel field effect transistor uses the gate structure to control the electric field in the transistor channel, thereby controlling the energy band structure of the channel region, when the valence band bottom of the channel region is lower than the conduction band top of the source region, electrons on the valence band of the source region can pass through the potential barrier between the source region and the channel region by the band-to-band tunneling effect, thereby turning on the tunnel field effect transistor. Therefore, the control of the transistor channel by the gate structure is critical for tunneling field effect transistors. Meanwhile, the doping ions of the source region and the drain region of the tunneling field effect transistor are different, and the first doping region and the second doping region of the transistor are formed through different technological processes, so that the doping ions of the source region and the drain region of the tunneling field effect transistor are different, and the process complexity is not easy to increase. Therefore, in the present embodiment, the formed semiconductor structure is a tunneling field effect transistor. In other embodiments, the forming method of the invention can also be used for forming a MOS transistor.
Referring to fig. 3, a substrate 200 is provided, the substrate 200 having a fin pillar 201 thereon, the fin pillar 201 comprising: a bottom region C, a channel region B located on the bottom region C, and a top region A located on the channel region B.
In this embodiment, the substrate 200 and the fin pillar 201 are made of silicon, germanium, silicon germanium, or silicon carbide. In other embodiments, the substrate and the fin pillar are made of a single crystal formed of a III-V element.
The fin pillar 201 is shaped as a cylinder. Specifically, the fin portion pillar 201 is a cylinder or a square column.
The steps of forming the substrate 200 and the fin pillars 201 include: providing an initial substrate; forming a patterned mask layer 203 on the initial substrate; and etching the initial substrate by taking the mask layer 203 as a mask to form a substrate 200 and a fin column 201 positioned on the substrate 200.
Before forming the mask layer 203, the method further includes: an adhesion layer 202 is formed on the initial substrate.
The adhesion layer 202 is used to improve the adhesion of the interface between the mask layer 203 and the initial substrate.
In this embodiment, the starting substrate is made of silicon, germanium, silicon germanium or a single crystal of a group III-V element. The mask layer 203 is made of silicon nitride or silicon oxynitride. The material of the adhesion layer 202 is silicon oxide.
The process of etching the initial substrate comprises a dry etching process. The dry etching process has a good line width control effect, the size of the fin portion pillar 201 is easy to control, and the formed fin portion pillar 201 has good verticality with the surface of the substrate 200. In other embodiments, the process of etching the initial substrate comprises wet etching.
In this embodiment, the bottom region C of the fin pillar 201 is used to form a drain region or a source region of the tunneling field effect transistor; the channel region B is used for forming a channel of the tunneling field effect transistor; the top region A is used for forming a source region or a drain region of the tunneling field effect transistor. In other embodiments, the semiconductor structure formed is a MOS transistor. The bottom region is used for forming a source region or a drain region of the MOS transistor; the channel region is used for forming a channel of the MOS transistor. The top region is used for forming a source region or a drain region of the MOS transistor.
In this embodiment, the number of the fin pillars 201 is two. In other embodiments, the number of the fin pillars may be one or more than two.
If the height of the fin pillar 201 is too small, it is easy to cause the dimension of the first doped region, the second doped region or the gate structure formed subsequently to be too small along the direction perpendicular to the surface of the substrate 200, thereby affecting the performance of the formed semiconductor structure; if the height of the fin portion 201 is too large, the process difficulty is increased. Specifically, in this embodiment, the height of the fin pillar 201 is 6nm to 65 nm.
And forming a side wall covering the side walls of the channel region B and the top region A of the fin portion column 201.
In this embodiment, the step of forming the sidewall is shown in fig. 4 to 6.
Referring to fig. 4, a sacrificial layer 250 is formed on the substrate 200, wherein the surface of the sacrificial layer 250 is flush with the top surface of the bottom region C.
The sacrificial layer 250 is used to prevent a sidewall layer from being formed on the bottom region C surface, so that the bottom region C sidewall surface has no sidewall layer after the sacrificial layer 250 is removed.
In this embodiment, the material of the sacrificial layer 250 is silicon oxide. In other embodiments, the material of the sacrificial layer is silicon nitride or silicon oxynitride.
In this embodiment, the step of forming the sacrificial layer 250 includes: forming an initial sacrificial layer on the substrate 200, wherein the surface of the initial sacrificial layer is higher than or flush with the top surface of the bottom region C of the fin column 201; and etching the initial sacrificial layer to form a sacrificial layer 250, wherein the surface of the sacrificial layer 250 is flush with the top surface of the bottom area C.
In this embodiment, the initial sacrificial layer is made of silicon oxide, and the process of forming the initial sacrificial layer includes a fluid chemical vapor deposition process. The initial sacrificial layer formed by the fluid chemical vapor deposition process has good gap filling capability and can fully fill the gap between adjacent fin pillars 201.
In other embodiments, the material of the initial sacrificial layer is an organic dielectric material, and the process of forming the initial sacrificial layer includes a spin coating process.
The step of forming the semiconductor structure further comprises: an isolation structure 204 is formed in the substrate between adjacent fin pillars 201, the top of the isolation structure 204 being higher than or flush with the top surface of the bottom region C.
The isolation structure 204 is used for subsequently isolating the first conductive structures on the sidewall surfaces of the adjacent fin pillars 201, so that electrical isolation between the first conductive structures of the transistors formed by the adjacent fin pillars 201 is realized, the first conductive structures of the transistors formed by the adjacent fin pillars 201 can be connected with different potentials, and different functions are realized.
In this embodiment, the isolation structure 204 is formed before the sacrificial layer 250 is formed.
The step of forming the isolation structure 204 comprises: forming an isolation groove in the substrate between the adjacent fin portion columns; isolation structures 204 are formed in the isolation grooves.
The step of forming isolation structures 204 in the recesses comprises: forming an initial isolation structure in the isolation groove and on the substrate; the initial isolation structure surface is higher than or flush with the bottom region C top surface; and etching the initial isolation structure to remove the initial isolation structure on the surface of the substrate.
The isolation structure 204 is made of silicon oxide.
Referring to fig. 5, a sidewall layer 210 covering the surface of the sacrificial layer 250 and sidewalls of the channel region B and the top region a of the fin pillar 201 is formed, and the sidewall layer 210 and the sacrificial layer 250 are made of different materials.
In this embodiment, the sidewall layer 210 is used for forming a sidewall subsequently.
The side wall layer 210 and the sacrificial layer 250 are made of different materials, so that the side wall is prevented from being removed in the subsequent process of removing the sacrificial layer 250.
In this embodiment, the sacrificial layer 250 is made of silicon oxide, and the sidewall layer 210 is made of silicon nitride. In other embodiments, the material of the sacrificial layer is silicon nitride, and the material of the sidewall layer is silicon oxide or silicon oxynitride. The process of forming the sidewall layer 210 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The sidewall layer 210 is also located on the mask layer 203.
Referring to fig. 6, the sacrificial layer 250 (see fig. 5) and the sidewall layer 210 (see fig. 5) covering the sacrificial layer 250 are removed to form a sidewall 211.
The side wall 211 is used for isolating the first metal layer from the channel region B of the fin portion pillar 201 in the subsequent process of forming the first metallization, so that the first metal layer is prevented from reacting with the channel region B, and the performance of the formed semiconductor structure is improved.
In this embodiment, the step of removing the sacrificial layer 250 and the sidewall layer 210 covering the sacrificial layer 250 includes: forming an opening in the sidewall layer 210 covering the sacrificial layer 250; after the opening is formed, the sacrificial layer 250 is stripped through wet etching, and the sacrificial layer 250 and the sidewall layer 210 covering the sacrificial layer 250 are removed.
The step of forming an opening in the sidewall layer 210 covering the sacrificial layer includes: forming a pattern layer covering the top and the sidewalls of the fin pillar 131, wherein the pattern layer exposes a part of the sidewall layer 210 covering the sacrificial layer 250; and etching the side wall layer 210 by using the pattern layer as a mask, and forming an opening in the side wall layer 210.
The material of the graphic layer is photoresist or an anti-reflection coating.
In this embodiment, the process of etching the sidewall layer 210 includes: and (5) wet etching process. In other embodiments, the process of etching the sidewall layer includes a dry etching process.
The process parameters for etching the sidewall layer 210 include: the etching liquid comprises phosphoric acid, and the etching temperature is 700-900 ℃.
Specifically, in this embodiment, the process of stripping the sacrificial layer 250 includes a wet etching process. The wet etching has a good selectivity, so that the sidewall layer 210 of the channel region B and the top region a of the fin pillar 201 is not easily damaged.
The technological parameters of the wet etching comprise: the etching liquid is a mixed solution of hydrofluoric acid and ammonium fluoride, wherein the volume ratio of the ammonium fluoride to the hydrofluoric acid is 5-7.
After the sacrificial layer 250 is stripped, the sidewall layer 210 covering the sacrificial layer 250 is also removed.
In this embodiment, the pattern layer is formed before the sidewall layer 210 is etched to form the opening, and the pattern layer can protect the sidewall of the fin pillar 201 and the sidewall layer 210 at the top, so that the loss of the sidewall of the fin pillar 201 and the sidewall layer 210 at the top is reduced.
In other embodiments, the step of removing the sacrificial layer and the sidewall layer on the sacrificial layer includes: performing anisotropic etching on the side wall layer, and removing the side wall layer on the sacrificial layer to form a side wall; and removing the sacrificial layer after the anisotropic etching. The anisotropic etching process comprises an anisotropic dry etching process. The process for removing the sacrificial layer comprises one or two of a wet etching process and a dry etching process.
If the height of the sidewall 211 is too large, the dimension of the first doped region 261 formed subsequently along the direction perpendicular to the surface of the substrate 200 is too small, so that the performance of the semiconductor structure is easily affected; if the height of the sidewall 211 is too small, the dimension of the subsequently formed gate structure or the second doped region along the direction perpendicular to the surface of the substrate 200 is too small, so that the performance of the formed semiconductor structure is easily affected. Specifically, in this embodiment, the height of the sidewall 211 is 6nm to 70 nm.
If the thickness of the sidewall 211 is too small, it is not favorable for subsequently isolating the first metal layer 220 from the channel region B of the fin portion pillar 201, so that atoms of the first metal layer 220 easily penetrate through the sidewall 211 to react with the first metal layer 220, and a first metallization 221 is formed on the surface of the channel region B, which is not favorable for improving the performance of the formed semiconductor structure; if the thickness of the sidewall 211 is too large, the difficulty of the subsequent process for removing the sidewall 211 is easily increased. Specifically, in this embodiment, the thickness of the sidewall 211 is 2nm to 20 nm.
Referring to fig. 7, after the sidewalls 211 are formed, a first doped region 261 is formed in the bottom region C of the fin pillar 201, where the first doped region 261 has first doped ions therein.
The first doped region 261 serves as a source or drain region for the transistor being formed.
In this embodiment, first doping ions are implanted into the bottom region C of the fin pillar 201 by first ion implantation to form a first doping region 261.
In this embodiment, the first doping ions are N-type ions, such as phosphorous ions or arsenic ions. In other embodiments, the first dopant ion may also be a P-type ion, such as boron ion or BF 2 +Ions. The process parameters of the first ion implantation comprise: the injection angle is 0-5 degrees; the injection energy is 1 KeV-10 KeV; the implantation dose is 1E14atoms/cm2～5E15atoms/cm2。
And forming a first conductive structure on the surface of the sidewall of the bottom region C of the substrate 200 by using the sidewall spacers 211 as masks.
In this embodiment, the first conductive structure includes: a first metallization on the surface of the bottom region C of the fin pillar 201; a first plug on the substrate 200 covering the first metallization sidewall surface. In other embodiments, the first conductive structure may not include the first plug.
Specifically, in this embodiment, the steps of forming the first conductive structure are as shown in fig. 8 to 10.
Referring to fig. 8, a first metallization 221 is formed on the surface of the bottom region C of the fin pillar 201.
Specifically, in the present embodiment, the first metallization 221 is located on the surface of the first doped region 261. The first metallization 221 surrounds the fin pillar 201 bottom region C.
In this embodiment, the step of forming the first metallization 221 includes: forming a first metal layer 220 on the bottom region C of the fin pillar 201 and the surface of the sidewall 211; the first metal layer 220 is subjected to a first annealing treatment, so that the first metal layer 220 reacts with the bottom region C of the fin pillar 201 to form a first metallization 221.
The first metal layer 220 is used for subsequent reaction with the first doped region 261 to form a first metallization 221.
The material of the first metal layer 220 is nickel, cobalt or titanium. The process of forming the first metal layer 220 includes an electroplating process or a physical vapor deposition process.
In this embodiment, before the first annealing process, the first metal layer 220 is also located on the surface of the substrate 200 and the mask layer 203.
Since the bottom region C of the fin pillar 201 and the substrate 200 can react with the first metal layer 220 in the first annealing process, the first metallization 221 is located on the surface of the substrate 200 and the bottom region C of the fin pillar 201. The side wall 211 and the mask layer 203 do not react with the first metal layer 220, so that the first metal layer 220 is still on the side wall 211 and the mask layer 203 after the first annealing treatment.
In other embodiments, after the first annealing process and before the subsequent formation of the initial plug, the step of forming the first conductive structure further comprises: and removing the residual metal layer.
Referring to fig. 9, an initial plug 230 is formed to cover the first metallization 221 and the sidewall spacers 211.
The initial plug 230 is used to electrically connect the first metallization 221 to an external circuit.
Specifically, in this embodiment, the initial plug 230 is located on the surface of the first metallization 221 and the surface of the first metal layer 220. Before forming the initial plug, the step of forming the first conductive structure further includes removing the first metal layer, and the initial plug is located on the first metallization and the surface of the sidewall.
In this embodiment, the material of the initial plug 230 is tungsten. The process of forming the initial plug 230 includes an organic metal chemical vapor deposition process or an electroplating process.
The first conductive structure surrounds the fin pillar 201 bottom region C. In other embodiments, the first conductive structure may be located on a portion of the bottom region C surface of the fin pillar 201.
Referring to fig. 10, the initial plug is etched to form a first plug 231, and the surface of the first plug 231 is lower than or flush with the top surface of the channel region B.
The first conductive structure is used to electrically connect the first doped region 261 to an external circuit.
In this embodiment, after the etching the initial plug 230 to form the first plug 231, the step of forming the first conductive structure further includes: the remaining first metal layer 220 is removed (as shown in fig. 9).
In this embodiment, after the etching of the initial plug 230, the remaining first metal layer 220 is removed. In other embodiments, the remaining first metal layer is removed after the first annealing process and before the initial plug is formed.
In this embodiment, the process of removing the first metal layer 220 includes a wet etching process. The process of etching the initial plug 230 includes a dry etching process or a wet etching process.
In other embodiments, the step of etching the initial plug and removing the remaining first metal layer comprises: and etching the initial plug and the first metal layer until the surface of the initial plug is lower than or flush with the top surface of the channel region.
In this embodiment, the first plug 221 surrounds the bottom region C of the fin pillar 201. In other embodiments, the first plug may cover a surface of a bottom region of the fin portion pillar.
It should be noted that, in other embodiments, the step of forming the first conductive structure includes: forming a first conducting layer covering the side wall of the bottom area of the fin part column and the side wall; and etching back the first conductive layer by taking the side wall as a mask, removing part of the first conductive layer to form a first conductive structure, wherein the top surface of the first conductive structure is lower than or level to the top surface of the channel region. The first conductive structure is made of aluminum or tungsten.
In the process of performing back etching on the first conductive layer, the side wall can protect the channel region and the top region of the fin column, and the loss of the fin column is reduced.
Referring to fig. 11, after the first conductive structure is formed, the sidewall spacers 211 are removed (as shown in fig. 10).
And removing the side wall 211 to expose the channel region B of the fin portion 201, so that the subsequently formed gate structure is in contact with the surface of the channel region B of the fin portion 201.
In this embodiment, the process of removing the sidewall 211 includes a wet etching process. In other embodiments, the process of removing the sidewall spacers comprises an isotropic dry etching process.
The process parameters for removing the side wall 211 include: the etching liquid comprises phosphoric acid; the etching temperature is 720-880 ℃.
Referring to fig. 12, a first isolation layer 222 is formed on the first conductive structure.
The first isolation layer 222 is used to electrically isolate the first conductive structure from a subsequently formed gate structure.
In this embodiment, the first isolation layer 222 is made of silicon oxide. Silicon oxide has good insulating properties. In other embodiments, the material of the first isolation layer may also be silicon nitride, silicon oxynitride, or a low-k (k less than 3.9) dielectric material, and the low-k dielectric material is a porous material.
The step of forming the first isolation layer 222 includes: forming a first initial isolation layer on the first conductive structure, wherein the surface of the first initial isolation layer is higher than the top surface of the fin pillar 201; and etching the first initial isolation layer to form a first isolation layer 222, wherein the surface of the first isolation layer 222 is lower than the top surface of the channel region B.
The process of forming the first initial isolation layer comprises a fluid chemical vapor deposition process. The gap filling capability of the first initial isolation layer formed by the fluid chemical vapor deposition process is better.
The thickness of the first isolation layer 222 is a dimension of the first isolation layer 222 in a direction perpendicular to the surface of the substrate 200.
If the thickness of the first isolation layer 222 is too small, it is not favorable to achieve electrical isolation between the first conductive structure and the subsequently formed gate structure; if the thickness of the first isolation layer 222 is too large, the size of the subsequently formed gate structure or the second doped region is easily too small, thereby affecting the performance of the formed semiconductor structure. Specifically, in this embodiment, the thickness of the first isolation layer 222 is 2nm to 5 nm.
And after the side walls 211 are removed subsequently, a gate structure is formed at the top of the first conductive structure, and the gate structure is located on the surface of the channel region B of the fin column 201.
In this embodiment, the steps of forming the gate structure are shown in fig. 13 and 14.
Referring to fig. 13, an initial gate structure is formed on top of the first conductive structure, and the surface of the initial gate structure is higher than the surface of the top of the channel region B.
The initial gate structure is used for subsequently forming a gate structure.
The initial gate structure is located on top of the first isolation layer. The initial gate structure includes: an initial gate dielectric layer located on the surfaces of the channel region B and the top region a of the fin pillar 201, and on the top of the first isolation layer 222; and the initial grid electrode covers the initial grid dielectric layer.
In this embodiment, the step of forming the initial gate structure includes: forming an initial gate dielectric layer on the surfaces of the channel region B and the top region a of the fin column 201 and on the first isolation layer 222; and forming an initial gate 242 covering the initial gate dielectric layer.
In this embodiment, the initial gate dielectric layer includes: an initial oxide layer 240 on top of the first isolation layer 222 and the fin pillar 201 channel region B and top region a; an initial high-k dielectric layer 241 covering the initial oxide layer 240. In other embodiments, the initial gate dielectric layer may comprise only an initial high-k dielectric layer.
The initial oxide layer 240 is used to improve an interface state between the initial high-k dielectric layer 241 and the bottom region C of the fin pillar 201.
The first stageThe material of the initial oxide layer 240 is silicon oxide. The initial high-k dielectric layer 241 is made of a high-k (k is greater than 3.9) dielectric material, for example: HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4. The material of the initial gate 242 is metal, such as: l, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Referring to fig. 14, the initial gate structure is etched to form a gate structure, and the surface of the gate structure is lower than or flush with the top surface of the channel region B.
The gate structure is used for controlling an electric field in the fin column 201, so that the probability that electrons in the channel region B pass through a potential barrier between the first doping region 261 and the channel region B or between a subsequently formed second doping region and the channel region B is controlled, and the on and off of the formed transistor are controlled.
The process for etching the initial gate structure comprises the following steps: etching the initial gate 242 to form a gate 245; etching the initial high-k dielectric layer 241 to form a high-k dielectric layer 244; the initial oxide layer 240 is etched to form an oxide layer 243.
The thickness of the gate structure is the dimension of the gate structure in a direction perpendicular to the surface of the substrate 200.
If the thickness of the gate structure is too large, the dimension of the second doping layer formed subsequently along the direction perpendicular to the surface of the substrate 200 is too small, which affects the performance of the formed semiconductor structure; if the thickness of the gate structure is too small, it is not favorable to increase the contact area between the gate structure and the fin pillar 201, and it is not favorable to increase the control effect of the gate structure on the electric field in the channel region B. Specifically, in this embodiment, the thickness of the gate structure is 10nm to 25 nm.
In this embodiment, the process of etching the initial gate structure includes a dry etching process.
It should be noted that the initial gate structure surrounds the channel region B of the fin pillar 201, and the gate structure surrounds the channel region B of the fin pillar 201. The gate structure surrounds the channel region B of the fin portion column 201, the gate structure is in contact with each side face of the channel of the fin portion column 201, and the gate structure can control an electric field in the fin portion column 201 from each side face of the channel region B of the fin portion column 201, so that the control effect of the gate structure on electrons in the fin portion column 201 can be increased, and the performance of a formed semiconductor structure is improved.
Referring to fig. 15, a second isolation layer 251 is formed on top of the gate structure.
The second isolation layer 251 is used to electrically isolate the gate structure from a subsequently formed second conductive structure.
The material of the second isolation layer 251 is silicon oxide. Silicon oxide has good insulating properties. In other embodiments, the material of the second isolation layer may also be silicon nitride, silicon oxynitride, or a low-k (k less than 3.9) dielectric material, and the low-k dielectric material is a porous material.
The step of forming the second isolation layer 251 includes: forming a second initial isolation layer on the top of the gate structure, wherein the surface of the second initial isolation layer is higher than the surface of the top of the fin column 201; and etching the second initial isolation layer to form a second isolation layer 251, wherein the surface of the second isolation layer 251 is lower than the top surface of the top area A.
The process of forming the second initial isolation layer comprises a fluid chemical vapor deposition process. The gap filling capability of the second initial isolation layer formed by the fluid chemical vapor deposition process is good.
The thickness of the second isolation layer 251 is a dimension of the second isolation layer 251 in a direction perpendicular to the surface of the substrate 200. If the thickness of the second isolation layer 251 is too small, it is not favorable for realizing the electrical isolation between the subsequently formed second conductive structure and the gate structure; if the thickness of the second isolation layer 251 is too large, the size of the second conductive structure to be formed later is too small, which may affect the performance of the semiconductor structure to be formed. Specifically, in this embodiment, the thickness of the second isolation layer 251 is 2nm to 5 nm.
Referring to fig. 16, a second doped region 262 is formed in the top region a of the fin pillar 201.
When the first doped region 261 serves as a source region of a formed transistor, the second doped region 262 serves as a drain region of the formed transistor; the second doped region 262 serves as a source region for the formed transistor when the first doped region 261 serves as a drain region for the formed transistor.
In this embodiment, second doped ions are implanted into the top region a of the fin pillar 201 by second ion implantation to form a second doped region 262.
In this embodiment, the formed semiconductor structure is a tunneling field effect transistor, and the conductivity types of the second doped ions are opposite to the conductivity types of the first doped ions. In particular, the second dopant ion is a P-type ion, such as boron ion or BF2 +Ions. In other embodiments, the second dopant ion may also be an N-type ion, such as a phosphorous ion or an arsenic ion.
In other embodiments, the semiconductor structure is a MOS transistor, and the conductivity type of the second doped ions is the same as that of the first doped ions.
In this embodiment, the process parameters of the second ion implantation include: 0 degree to 5 degrees; the injection energy is 1 KeV-10 KeV; the implantation dose is 1E14atoms/cm 2～5E15atoms/cm2。
Referring to fig. 17, a second conductive structure is formed on the gate structure, and the second conductive structure is located on the surface of the top region a of the fin pillar 201.
Specifically, the second conductive structure is located on the top of the second isolation layer 251, and the second conductive structure is located on the surface of the second doped region 262.
The second conductive structure surrounds the fin pillar 202 top region a.
The second conductive structure includes: a second metallization 270 on the surface of the top region a of the fin pillar 201; a second plug 271 covering the second metallization 270. Specifically, the second metallization 270 is located on the sidewall surface of the second doped layer 262.
In this embodiment, the step of forming the second conductive structure includes: forming a second metallization 270 on the surface of the top region a of the fin pillar 201; a second plug 271 is formed on the second isolation layer 251, and the second plug 271 covers the second metallization 270.
The step of forming the second metallization 270 comprises: forming a second metal layer on the surface of the top region a of the fin portion pillar 201 and the second isolation layer 251; and performing second annealing treatment on the second metal layer to enable the second metal layer to react with the top area A of the fin portion column 201 to form a second metallization 270.
In this embodiment, before forming the second plug 271 and after the second annealing, the step of forming the second conductive structure further includes: and removing the residual second metal layer. Removing the second metal layer can reduce the influence of the second metal layer on the isolation performance of the second isolation layer 251. In other embodiments, the remaining second metal layer may not be removed.
In this embodiment, the second metallization 270 is located on the sidewall surface of the top region a of the fin pillar 201.
In this embodiment, in the process of forming the second metal layer, the top of the fin pillar 201 has a mask layer 203, and the second metal layer is located on the surface of the sidewall of the top region a of the fin pillar 201 and on the mask layer 203. In the second annealing process, the second metal layer does not react with the mask layer 203 and the second isolation layer 251, so that the second isolation layer 251 and the mask layer 203 still have the second metal layer thereon after the second annealing process.
The step of removing the second metal layer comprises: and removing the second metal layer on the second isolation layer 251 and the mask layer 203.
In other embodiments, before forming the second metal layer, the forming method further includes: and removing the mask layer and the adhesion layer, wherein the second metal layer is positioned on the top and the side wall surface of the fin portion column and on the surface of the second isolation layer, and the second metal layer is further reacted on the top of the fin portion column in the second annealing treatment process to form a second metallization. Therefore, the mask layer and the adhesion layer are removed before the second metal layer is formed, and the second metallization can be located on the top surface of the fin portion column, so that the contact area between the second metallization and the fin portion column can be increased, the contact resistance between the second metallization and the fin portion column is reduced, and the performance of the semiconductor structure is improved.
The second metal layer is made of nickel or cobalt. The process for forming the second metal layer includes an electroplating process or a physical vapor deposition process. The material of the second plug 271 is tungsten. The process of forming the second plug 271 includes: an electroplating process or an organometallic chemical vapor deposition process.
With continued reference to fig. 17, the present invention further provides a semiconductor structure, including: a substrate 200; a fin pillar 201 on the substrate 200, the fin pillar 201 comprising: a bottom region C, a channel region B located on the bottom region C, and a top region A located on the channel region B; a first conductive structure located on the surface of the bottom region C of the fin pillar 201; the grid electrode structure is positioned at the top of the first conductive structure and positioned on the surface of the channel region B of the fin portion column 201; and the second conductive structure is positioned at the top of the gate structure and positioned on the surface of the region A at the top of the fin column 201.
The semiconductor structure further includes: a first doped region 261 located in a bottom region C of the fin pillar 201, the first doped region 261 having first doped ions therein; a second doped region 262 located in the top region a of the fin pillar 201, the second doped region 262 having a second doped ion therein, the second doped ion having a same or opposite conductivity type as the first doped ion.
The semiconductor structure in this embodiment is formed by the forming method of the previous embodiment.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part column, and the fin part column comprises a bottom region, a channel region positioned on the bottom region and a top region positioned on the channel region;
forming a side wall covering the side walls of the channel region and the top region of the fin part column;
forming a first conductive structure on the surface of the side wall of the bottom area by taking the side wall as a mask;
after the first conductive structure is formed, removing the side wall;
after the side walls are removed, a grid electrode structure is formed at the top of the first conductive structure, and the grid electrode structure is located on the surface of the fin column channel region;
after the grid electrode structure is formed, forming a second conductive structure on the top of the grid electrode structure, wherein the second conductive structure is positioned on the surface of the top area of the fin column;
The thickness of the side wall is 2 nm-20 nm; the height of the side wall is 6 nm-70 nm.
2. The method of claim 1, wherein the fin pillar is formed of a single crystal of silicon, germanium, silicon carbide, or a group III-V element.
3. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the side walls comprises: forming a sacrificial layer on the substrate, wherein the surface of the sacrificial layer is flush with the surface of the top of the bottom area of the fin column; forming a side wall layer covering the surface of the sacrificial layer, the side wall layer of the fin part column channel region and the side wall of the top region, wherein the side wall layer is made of different materials from the sacrificial layer; and removing the sacrificial layer and the side wall layer covering the sacrificial layer to form the side wall.
4. The method of claim 3, wherein the sacrificial layer is made of silicon oxide or an organic dielectric material.
5. The method of forming a semiconductor structure of claim 3, wherein the step of forming the sacrificial layer comprises: forming an initial sacrificial layer on the substrate, wherein the surface of the initial sacrificial layer is higher than the top surface of the bottom area of the fin column; and etching the initial sacrificial layer to form a sacrificial layer, wherein the surface of the sacrificial layer is flush with the top surface of the bottom area.
6. The method of claim 5, wherein the initial sacrificial layer is formed of silicon oxide, and the process of forming the initial sacrificial layer comprises a fluid chemical vapor deposition process; or, the initial sacrificial layer is made of an organic dielectric material, and the process for forming the initial sacrificial layer comprises a spin coating process.
7. The method of claim 5, wherein the etching of the initial sacrificial layer comprises one or a combination of dry etching and wet etching.
8. The method of forming a semiconductor structure of claim 3, wherein removing the sacrificial layer and the sidewall layer covering the sacrificial layer comprises: performing anisotropic etching on the side wall layer, and removing the side wall layer covering the sacrificial layer to form a side wall; and removing the sacrificial layer after the anisotropic etching.
9. The method of claim 3, wherein the sidewall layer is formed of silicon nitride or silicon oxynitride.
10. The method of claim 3, wherein the sidewall layer is formed by a process comprising a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
11. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: forming a first isolation layer on top of the first conductive structure;
before forming the second conductive structure, the method further comprises: and forming a second isolation layer on the top of the gate structure.
12. The method of forming a semiconductor structure of claim 11, wherein the first spacer layer is formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials; the second isolation layer is made of silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric material.
13. The method for forming a semiconductor structure according to claim 3, wherein after removing the sacrificial layer and before removing the side walls, the method further comprises: forming a first doping area in the bottom area of the fin column, wherein the first doping area is provided with first doping ions; the first conductive structure is positioned on the surface of the first doped region; after the gate structure is formed and before the second conductive structure is formed, the method further includes: forming a second doping area in the fin portion column top area, wherein second doping ions are arranged in the second doping area; the second doping ions have a conductivity type opposite to or the same as that of the first doping ions.
14. The method of claim 1 or 13, wherein the gate structure surrounds the fin pillar channel region; the first conductive structure surrounds the fin column bottom region, and the second conductive structure surrounds the fin column top region.
15. The method of forming a semiconductor structure of claim 1, wherein the first conductive structure comprises: a first metallization on the surface of the bottom region of the fin pillar;
the step of forming the first conductive structure comprises: forming a first metal layer on the surface of the bottom area of the fin part column and the surface of the side wall; and carrying out first annealing treatment on the first metal layer to enable the first metal layer to react with the bottom area of the fin column to form a first metallization.
16. The method of forming a semiconductor structure of claim 15, wherein the first conductive structure further comprises: a first plug covering a sidewall surface of the first metallization;
the step of forming the first conductive structure further comprises: forming an initial plug covering the first metallization and the side wall; and carrying out back etching on the initial plug, and removing part of the initial plug to form a plug, wherein the top surface of the plug is lower than or flush with the top surface of the bottom area.
17. The method of forming a semiconductor structure of claim 16, wherein after the first annealing, forming a first conductive structure further comprises: removing the first metal layer on the surface of the side wall;
removing the first metal layer on the surface of the side wall before forming the initial plug; or after the first conductive structure is formed, removing the first metal layer on the surface of the side wall.
18. The method of forming a semiconductor structure of claim 1, wherein forming the first conductive structure comprises: forming a first conductive layer covering the side wall of the fin part column bottom area and the side wall; and etching back the first conductive layer by taking the side wall as a mask, removing part of the first conductive layer to form a first conductive structure, wherein the top surface of the first conductive structure is lower than or level to the top surface of the channel region.
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