CN114078701A

CN114078701A - Semiconductor structure and forming method thereof

Info

Publication number: CN114078701A
Application number: CN202010819904.2A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-08-14
Filing date: 2020-08-14
Publication date: 2022-02-22
Anticipated expiration: 2040-08-14
Also published as: CN114078701B

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doping layer, an initial channel column and a semiconductor layer which are sequentially stacked from bottom to top; forming a dummy gate surrounding the sidewall of the initial channel pillar and exposing the semiconductor layer; forming a bottom dielectric layer which is filled between adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the pseudo gate and covers the top surface of the pseudo gate on the substrate, wherein the bottom dielectric layer is exposed out of the side wall of the pseudo gate far away from the adjacent semiconductor laminated column; removing the dummy gate to form a gate opening exposing the side wall of the initial channel column; thinning the exposed side wall of the initial channel column to form a channel column; a gate is formed in the gate opening surrounding the sidewalls of the channel pillar. The embodiment of the invention is beneficial to improving the performance of the VGAA transistor.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be shortened in order to accommodate the reduction of process nodes.

The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, and the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (short-channel leakage) is more likely to occur, and the channel leakage current of the transistor is increased.

Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect. The fully-wrapped-Gate transistor includes a Lateral Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor.

The channel of VGAA extends in a direction perpendicular to the substrate surface, which is beneficial to improving the area utilization efficiency of the semiconductor structure, thereby facilitating the realization of further feature size reduction.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of a vertical fully-enclosed gate (VGAA) transistor.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doping layer, an initial channel column and a semiconductor layer for forming a second doping layer, which are sequentially stacked from bottom to top; forming a dummy gate surrounding the sidewall of the initial channel pillar and exposing the semiconductor layer; forming a bottom dielectric layer which is filled between the adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the pseudo gate and covers the top surface of the pseudo gate on the substrate, wherein the bottom dielectric layer is exposed out of the side wall of the pseudo gate far away from the adjacent semiconductor laminated column; removing the pseudo gate, exposing the side wall of the initial channel column, and forming a gate opening in the bottom dielectric layer; thinning the side wall of the initial channel column exposed by the gate opening, wherein the rest initial channel column is used as a channel column; and filling the gate opening to form a gate surrounding the side wall of the channel column.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the semiconductor laminated column protrudes out of the substrate and comprises a first doping layer, a channel column and a second doping layer which are sequentially stacked from bottom to top, and the side wall of the channel column is retracted relative to the side walls of the first doping layer and the second doping layer along the direction perpendicular to the side wall of the channel column; a gate surrounding sidewalls of the channel pillar with a space between gates on sidewalls of adjacent semiconductor stack pillars; and the dielectric layer is filled between the gates positioned on the side walls of the adjacent semiconductor laminated columns and covers the top surfaces of the gates.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, the semiconductor laminated columns are formed firstly, then the pseudo gates surrounding the side walls of the initial channel columns are formed, the bottom dielectric layers which are filled between the adjacent semiconductor laminated columns and cover the top surfaces of the pseudo gates are formed on the substrate, then the pseudo gates are removed to form the gate openings, and then the side walls of the initial channel columns are thinned through the gate openings to form the channel columns; therefore, in the step of forming the semiconductor laminated pillar, the width of the initial channel pillar is greater than the target width of the channel pillar in the direction perpendicular to the sidewall of the semiconductor laminated pillar, the semiconductor laminated pillar (including the first doped layer and the semiconductor layer) can also have a larger width dimension, and the contact area of the semiconductor laminated pillar and the substrate is larger, so as to improve the stability of the semiconductor laminated pillar standing on the substrate, which is beneficial to reducing the probability of the semiconductor laminated pillar tilting or bending problems during the formation of the semiconductor structure, for example: in the process of forming the isolation structure which is positioned on the substrate and surrounds the side wall of the first doped layer part, even if the stress on the semiconductor laminated column is uneven due to the fact that the density of the peripheral graph of the semiconductor laminated column is not uniform, the probability of inclination or bending of the semiconductor laminated column is low, and therefore the performance of a vertical all-around gate (VGAA) transistor is improved.

In the alternative, in the step of forming the dummy gates, the dummy gates on the sidewalls of the adjacent semiconductor stacked pillars have a space therebetween, the side wall of the dummy gate opposite to the adjacent semiconductor laminated column is a first side wall, and the side wall of the dummy gate far away from the adjacent semiconductor laminated column is a second side wall, so that in the step of forming the bottom dielectric layer, the bottom dielectric layer can be filled between the first side walls of the adjacent dummy gates, surrounds the side walls of the semiconductor laminated column exposed by the dummy gates and covers the top surfaces of the dummy gates, during the formation of the semiconductor structure (e.g., during the removal of the dummy gate to form the gate opening and the formation of the gate in the gate opening), the bottom dielectric layer can act as a support for the semiconductor stack pillar, thereby reducing the probability of the semiconductor stacked pillar tilting or bending and further improving the performance of a vertical fully-enclosed gate (VGAA) transistor.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure formed by a method;

FIGS. 2 to 10 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 11 to 15 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, Vertical Gate-all-around (VGAA) transistors are advantageous for achieving further feature size reduction. Specifically, in the VGAA transistor, a semiconductor pillar protruding from the substrate is formed, the gate structure surrounds a part of the sidewall of the semiconductor pillar, and a part of the semiconductor pillar surrounded by the gate structure is a channel region, so that the channel of the VGAA transistor can extend in a direction perpendicular to the surface of the substrate.

However, the currently formed VGAA transistor still has a problem of poor performance. In particular, the semiconductor pillar of the VGAA transistor is easily bent or tilted during the formation of the semiconductor structure, resulting in poor performance of the VGAA transistor.

For example: the process of forming the VGAA transistor includes: as shown in fig. 1, an isolation structure 3 is formed on a substrate 1 where a semiconductor pillar 2 is exposed, and the isolation structure 3 covers a part of a sidewall of the semiconductor pillar 2.

The pattern density at different positions on the substrate 1 differs, resulting in different pattern densities around the semiconductor pillars 2, for example: the substrate 1 includes a pattern dense region and a pattern sparse region, the number of semiconductor pillars 2 of the pattern dense region is greater than the number of semiconductor pillars 2 of the pattern sparse region, or, as shown in fig. 1, the pattern densities of both sides of the semiconductor pillars 2 located at the edge positions are different. Due to the different pattern densities around the semiconductor pillars 2, in the process of forming the isolation structure 3, the stresses applied to the semiconductor pillars 2 are not uniform, and particularly, the stresses applied to the semiconductor pillars 2 located at the edge positions or the semiconductor pillars 2 located at the junctions of the pattern dense areas and the pattern sparse areas are not uniform, so that the semiconductor pillars 2 are easily bent or inclined (as shown by dotted circles in fig. 1), and the performance of the formed VGAA transistor is poor.

In addition, the forming process of the VGAA transistor further comprises processes of forming an interlayer dielectric layer (ILD), forming a grid electrode and the like. With the gradual reduction of the device size, the diameter or the width of the semiconductor pillar 2 is also smaller, the semiconductor pillar 2 is a slender vertical structure, the probability of the semiconductor pillar 2 tilting or bending in the formation process of the semiconductor structure is higher, and the influence on the performance of the VGAA transistor is not negligible.

In order to solve the technical problem, in the method for forming the semiconductor structure provided by the embodiment of the invention, the semiconductor laminated columns are formed firstly, then the dummy gates surrounding the side walls of the initial channel columns are formed, the bottom dielectric layers which are filled between the adjacent semiconductor laminated columns and cover the top surfaces of the dummy gates are formed on the substrate, then the dummy gates are removed to form the gate openings, and then the side walls of the initial channel columns are thinned through the gate openings to form the channel columns; therefore, in the step of forming the semiconductor laminated pillar, the width of the initial channel pillar is greater than the target width of the channel pillar in the direction perpendicular to the sidewall of the semiconductor laminated pillar, the semiconductor laminated pillar (including the first doped layer and the semiconductor layer) can also have a larger width dimension, and the contact area of the semiconductor laminated pillar and the substrate is larger, so as to improve the stability of the semiconductor laminated pillar standing on the substrate, which is beneficial to reducing the probability of the semiconductor laminated pillar tilting or bending problems during the formation of the semiconductor structure, for example: in the process of forming the isolation structure which is positioned on the substrate and surrounds the side wall of the first doped layer part, even if the stress on the semiconductor laminated column is uneven due to the fact that the density of the peripheral graph of the semiconductor laminated column is not uniform, the probability of inclination or bending of the semiconductor laminated column is low, and therefore the performance of a vertical all-around gate (VGAA) transistor is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2 and 3, a substrate 100 and a semiconductor stacked pillar 200 protruding from the substrate 100 are provided, wherein the semiconductor stacked pillar 200 includes a first doped layer 10, an initial channel pillar 30, and a semiconductor layer 20 for forming a second doped layer, which are sequentially stacked from bottom to top.

The substrate 100 is used to provide a process platform for forming vertical fully-enclosed gate (VGAA) transistors.

The semiconductor stack pillar 200 is used to provide a process platform for the subsequent formation of a gate surrounding the sidewalls of the channel pillar. The semiconductor stacked pillar 200 extends in a direction perpendicular to the substrate 100, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus is advantageous for realizing further feature size reduction.

The subsequent steps further comprise: thinning the side wall of the initial channel column 30 to form a channel column; therefore, in the step of forming the semiconductor laminated pillar 30, the width of the initial channel pillar 30 is greater than the target width of the channel pillar in the direction perpendicular to the sidewall of the semiconductor laminated pillar 200, the semiconductor laminated pillar 200 (including the first doped layer 10 and the semiconductor layer 20) can have a relatively large width dimension, and the contact area between the semiconductor laminated pillar 200 and the substrate 100 is also large, so that the stability of the semiconductor laminated pillar 200 standing on the substrate 100 is improved, and the probability of the semiconductor laminated pillar 200 tilting or bending in the subsequent process is reduced.

In this embodiment, the number of the semiconductor stacked pillars 200 is plural, and the plural semiconductor stacked pillars 200 are separated from the substrate 100. In the present embodiment, the semiconductor stacked pillar 200 is a cylinder structure.

In this embodiment, in the step of providing the substrate 100 and the semiconductor stacked pillar 200, the first doped layer 10 is flush with the sidewalls of the initial channel pillar 30 and the semiconductor layer 20.

The first doped layer 10 is used as a source region or a drain region of a vertical all-around gate transistor. In this embodiment, the first doped layer 10 serves as a source region of the vertically all-around gate transistor.

In this embodiment, along a direction perpendicular to the sidewall of the semiconductor stacked pillar 200, the width of the semiconductor stacked pillar 200 is larger, and the width of the first doped layer 10 is also larger, that is, the volume of the first doped layer 10 is larger and the contact area between the first doped layer 10 and the substrate 100 is larger, so as to improve the stability of the semiconductor stacked pillar 200 standing on the substrate 100, and prevent the semiconductor stacked pillar 200 from bending, tilting or collapsing. In addition, the width of the first doped layer 10 is large, and the volume of the first doped layer 10 is correspondingly large, so that the stress on a channel region is favorably improved, the mobility of carriers is favorably improved, and the performance of a semiconductor structure is favorably optimized correspondingly.

In the step of providing the substrate 100 and the semiconductor laminated pillar 200 in this embodiment, the materials of the first doping layer 10 and the initial channel pillar 30 are different, and in the subsequent process of thinning the sidewall of the initial channel pillar 30, an etching selection ratio is provided between the initial channel pillar 30 and the first doping layer 10, which is beneficial to reducing the probability of damage to the first doping layer 10, and can also reduce the process difficulty of thinning the sidewall of the initial channel pillar 30.

In this embodiment, a PMOS transistor is formed, the material of the first doping layer 10 may be SiGe doped with P-type ions, and the P-type ions may be B ions, Ga ions, or In ions. In other embodiments, when forming an NMOS transistor, the material of the first doped layer may be SiC or SiP doped with N-type ions, wherein the N-type ions may be P ions, As ions, or Sb ions.

The initial channel post 30 is used to form a channel post via a subsequent thinning process. The channel pillar has a target width in a direction perpendicular to sidewalls of the semiconductor stacked pillar 200. In this embodiment, the direction perpendicular to the sidewalls of the semiconductor stacked pillar 200 is parallel to the substrate 100.

In the step of providing the substrate 100 and the semiconductor stack pillar 200, the width of the initial channel pillar 30 is greater than the target width. In this embodiment, the semiconductor stacked pillar 200 has a cylindrical structure, and the width refers to the cross-sectional diameter of the channel pillar or initial channel pillar 30.

It should be noted that, in the step of providing the substrate 100 and the semiconductor stacked pillar 200, the width of the initial channel pillar 30 is not too small or too large in the direction perpendicular to the sidewall of the semiconductor stacked pillar 200, which is larger than the target width of the channel pillar. If the value that the width of the initial channel column 30 is larger than the target width of the channel column is too small, the effect of increasing the width of the semiconductor laminated column 200 is not obvious as compared with the target width of the channel column, easily resulting in an insignificant effect of improving the stability of the semiconductor laminated column 200; if the width of the initial trench pillar 30 is larger than the target width of the trench pillar, the width of the semiconductor stacked pillar 200 is too large, which easily causes the area of the substrate 100 occupied by the semiconductor stacked pillar 200 to be too large, and further easily reduces the utilization efficiency of the wafer area, and the thickness of the sidewall of the initial trench pillar 30 to be thinned is also large subsequently, the time for thinning the sidewall of the initial trench pillar 30 is too long, thereby easily increasing the process risk and reducing the process controllability. For this reason, in the present embodiment, the width of the initial channel column 30 is 1.2 times to 1.6 times the target width.

In the present embodiment, the material of the initial channel pillar 30 includes Si.

The semiconductor layer 20 is used to form a second doped layer, which is used as a source or drain region of the VGAA transistor. In this embodiment, the second doped layer is used as a drain region of the VGAA transistor.

In the step of providing the substrate 100 and the semiconductor laminated pillar 200, the semiconductor layer 20 and the initial trench pillar 30 are made of different materials, so that in the subsequent process of thinning the sidewall of the initial trench pillar 30, the initial trench pillar 30 and the semiconductor layer 20 have an etching selection ratio, which is beneficial to reducing the probability of causing false etching to the semiconductor layer 20 and reducing the process difficulty of thinning the sidewall of the initial trench pillar 30.

In addition, in this embodiment, the width of the semiconductor layer 20 is relatively large, and the volume of the semiconductor layer 20 is relatively large, so that the stress of the second doped layer on the channel region is favorably improved, the carrier mobility of the channel region is favorably improved, and the performance of the semiconductor structure is favorably optimized.

In this embodiment, the first doped layer 10 is used as a source region, the semiconductor layer 20 is used to form a second doped layer, and the second doped layer is used as a drain region. Accordingly, the semiconductor layer 20 is the same material as the first doping layer 10.

In this embodiment, a PMOS transistor is formed, and the material of the semiconductor layer 20 is SiGe. In other embodiments, when forming an NMOS transistor, the material of the semiconductor layer may be SiC or SiP.

In this embodiment, the semiconductor layer 20 is also doped with ions. In addition, the forming method further includes: a second doped layer is formed. In this embodiment, an epitaxial layer is formed on the semiconductor layer 20, and ions are self-doped in situ during the process of forming the epitaxial layer, and the semiconductor layer 20 and the epitaxial layer doped with ions are used as the second doping layer. Therefore, the type of doping ions in the semiconductor layer 20 is the same as that of the second doping layer.

In this embodiment, a PMOS transistor is formed, and the semiconductor layer 20 is doped with P-type ions, which may be B ions, Ga ions, or In ions. In other embodiments, when forming the NMOS transistor, the semiconductor layer is doped with N-type ions, which may be P ions, As ions, or Sb ions.

In other embodiments, the semiconductor layer may be further not doped with ions.

In the step of providing the substrate 100 and the semiconductor stacked pillar 200, a doped layer side portion 110 connected to the bottom of the first doped layer 10, located on the substrate 100, and extending in a direction parallel to the substrate 100 is also formed.

The subsequent steps further comprise: a first source drain plug is formed in contact with the doped layer side 110. Therefore, by forming the doped layer side portion 110, the first doped layer 10 is electrically connected to the first source/drain plug through the doped layer side portion 110, which is beneficial to reducing the difficulty of forming the first source/drain plug, and by forming the doped layer side portion 110, the first doped layers 10 of adjacent semiconductor stacked pillars 200 can be contacted according to the actual process requirements.

In this embodiment, the doped layer side 110 is made of the same material and doped ion type as the first doped layer 10.

In the present embodiment, the step of providing the substrate 100 and the semiconductor stacked pillar 200 includes:

as shown in fig. 2, a substrate 100, a first initial doping layer 101, a channel material layer 102 and an initial semiconductor layer 103 are provided, which are sequentially stacked from bottom to top on the substrate 100.

In this embodiment, the material and the ion doping type of the initial semiconductor layer 103 and the first initial doping layer 101 are the same, and the steps of forming the initial semiconductor layer 103 and the first initial doping layer 101 each include: and forming an epitaxial layer by adopting an epitaxial process, and self-doping ions in situ in the process of forming the epitaxial layer.

The material formed by the epitaxial process has high purity and few defects, and is beneficial to improving the forming quality of the initial semiconductor layer 103 and the first initial doping layer 101, and correspondingly improving the forming quality of the subsequent first doping layer and the semiconductor layer.

As shown in fig. 3, the preliminary semiconductor layer 103, the channel material layer 102, and the partial thickness of the first preliminary doping layer 101 are patterned to form the doping layer side 110, the first doping layer 10, the preliminary channel column 30, and the semiconductor layer 20.

Therefore, in this embodiment, the doped layer side portion 110 and the first doped layer 10 are an integral structure.

In this embodiment, the step of patterning the initial semiconductor layer 103, the channel material layer 102 and the partial thickness of the first initial doping layer 101 includes: forming a hard mask layer 104 on the initial semiconductor layer 103; and patterning the initial semiconductor layer 103, the channel material layer 102 and the first initial doping layer 101 with a partial thickness by using the hard mask layer 104 as a mask.

The hard mask layer 104 is used as a mask for forming the semiconductor stacked pillar 200. In this embodiment, the hard mask layer 104 is made of silicon nitride.

In this embodiment, the hard mask layer 104 is used as a mask, and an anisotropic dry etching process is used to sequentially etch the initial semiconductor layer 103, the channel material layer 102, and the first initial doping layer 101 with a partial thickness.

In this embodiment, before forming the hard mask layer 104 on the initial semiconductor layer 103, the forming method further includes: a pad oxide layer 105 is formed on the initial semiconductor layer 103 (as shown in fig. 3). The pad oxide layer 105 serves to reduce stress between the hard mask layer 104 and the initial semiconductor layer 103, thereby improving adhesion between the hard mask layer 104 and the initial semiconductor layer 103, and thus improving the accuracy of pattern transfer.

Therefore, a pad oxide layer 105 is also formed between the hard mask layer 104 and the semiconductor stacked pillar 200.

In this embodiment, after forming the semiconductor stacked pillar 200, the method for forming the semiconductor structure further includes: a dummy gate oxide layer 106 is formed on the sidewalls of the semiconductor stack pillars 200 (as shown in fig. 3).

The dummy gate oxide layer 106 is used for protecting the side wall of the semiconductor stacked pillar 200, and the dummy gate oxide layer 106 is also used as a stop layer in the subsequent process of removing the dummy gate, so that the etching consistency is improved, and the damage to the semiconductor stacked pillar 200 is reduced. In this embodiment, the material of the dummy gate oxide layer 106 is silicon oxide.

Referring to fig. 4, a dummy gate 130 surrounding sidewalls of the preliminary channel pillar 30 and exposing the semiconductor layer 20 is formed.

The dummy gate 130 is used to occupy space for the subsequent formation of a gate. Therefore, in this embodiment, the dummy gate 130 is also used to define the shape and position of the subsequent gate.

In this embodiment, a space S1 is formed between the dummy gates 130 located on the sidewalls of the adjacent stacked semiconductor pillars 200, the sidewall of the dummy gate 130 opposite to the adjacent stacked semiconductor pillars 200 is a first sidewall 11, and the sidewall of the dummy gate 130 away from the adjacent stacked semiconductor pillars 200 is a second sidewall 12.

Compared with the dummy gate contact on the side wall of the adjacent semiconductor stack pillar, in the embodiment, the space S1 is provided between the dummy gates 130 on the side walls of the adjacent semiconductor stack pillars 200, and in the subsequent process of forming a bottom dielectric layer on the substrate 100, the bottom dielectric layer is filled between the first side walls 11 of the adjacent dummy gates 130, surrounds the side walls of the semiconductor stack pillars 200 exposed by the dummy gates 130, and covers the top surfaces of the dummy gates 130, so that in the formation process of the semiconductor structure (for example, in the subsequent process of removing the dummy gates 130 to form gate openings and forming gates in the gate openings), the bottom dielectric layer can support the semiconductor stack pillars 200.

Therefore, in the step of forming the dummy gates 130, the spacing S1 between the dummy gates 130 on the sidewalls of the adjacent semiconductor stacked pillars 200 is not necessarily too small or too large. If the spacing S1 is too small, the difficulty in filling the subsequent bottom dielectric layer between the dummy gates 130 on the sidewalls of the adjacent semiconductor stacked pillars 200 is easily increased, and the width of the bottom dielectric layer between the dummy gates 130 on the sidewalls of the adjacent semiconductor stacked pillars 200 is also easily decreased in a direction perpendicular to the sidewalls of the semiconductor stacked pillars 200, so that the supporting effect of the bottom dielectric layer on the semiconductor stacked pillars 200 is easily reduced; if the spacing S1 is too large, it is also easy to cause the spacing between adjacent VGAA transistors to be too large, thereby easily reducing the device density and the wafer area utilization efficiency. For this reason, in the present embodiment, the interval S1 between the dummy gates 130 positioned on the sidewalls of the adjacent semiconductor stacked pillar 200 is 30% to 70% of the interval S2 between the adjacent semiconductor stacked pillars 200. As an example, the spacing S1 between the dummy gates 130 on the sidewalls of the adjacent semiconductor stacked pillars 200 is 50% of the spacing S2 between the adjacent semiconductor stacked pillars 200.

The dummy gate 130 is far from the sidewall of the adjacent semiconductor stack pillar 200, which means that the dummy gate 130 is not opposite to the sidewall of the adjacent semiconductor stack pillar 200. For convenience of illustration and explanation, the second sidewall 12 shown in fig. 5 is a sidewall of the dummy gate 130 opposite to the adjacent semiconductor stacked pillar 200, but in an actual process, the second sidewall 12 may also be a sidewall of the dummy gate 130 facing other directions.

The dummy gate 130 may have a single layer or a stacked structure. In the embodiment, the dummy gate 130 has a single-layer structure, and the material of the dummy gate 130 includes amorphous silicon, amorphous germanium or HSQ (hydrogen silsesquioxanes). The amorphous silicon and the amorphous germanium are commonly used materials in a semiconductor process, and are favorable for improving process compatibility, and the HSQ is a material with photosensitivity and high resolution, and is favorable for reducing the difficulty of a patterning process for forming the dummy gate 130 and improving the pattern precision of the dummy gate 130. As an example, the material of the dummy gate 130 is amorphous silicon.

In this embodiment, the dummy gate 130 surrounds the sidewall of the initial channel pillar 30 and also extends to surround the semiconductor layer 20 and a portion of the sidewall of the first doped layer 10.

In this embodiment, the step of forming the dummy gate 130 includes: forming an initial dummy gate (not shown) on the substrate 100 to cover the semiconductor stack pillar 200; removing a part of the thickness of the initial dummy gate to expose the semiconductor layer 20; the remaining initial dummy gate is patterned, leaving a portion of the initial dummy gate surrounding the sidewalls of the initial channel pillar 30 to serve as the dummy gate 130.

The initial dummy gate is formed using a deposition process (e.g., a chemical vapor deposition process, etc.).

The step of removing the partial thickness of the initial dummy gate may include: taking the top surface of the hard mask layer 104 as a stop position, and carrying out planarization treatment on the initial pseudo gate; and etching back the residual initial pseudo gate with partial thickness. Wherein, Chemical Mechanical Polishing (CMP) process can be adopted for planarization treatment; the etch-back process may be a dry etch process.

In this embodiment, the remaining initial dummy gate is patterned by using an anisotropic dry etching process. The anisotropic dry etching process has high etching efficiency and high etching precision, is favorable for improving the appearance quality of the dummy gate 130, and is also favorable for enabling the dummy gate 130 on the side wall of the adjacent semiconductor laminated column 200 to meet the design requirement.

In this embodiment, after providing the substrate 100 and the semiconductor stacked pillar 200, and before forming the dummy gate 130, the method for forming the semiconductor structure further includes: an isolation structure 120 is formed on the substrate 100, surrounding a portion of the sidewall of the first doped layer 10.

The isolation structure 120 is used to isolate adjacent semiconductor stack pillars 200. In this embodiment, the isolation structure 120 is located on the doped layer side portion 110, and the isolation structure 120 is further used for isolating the doped layer side portion 110 from a subsequent gate.

In this embodiment, along a direction perpendicular to the sidewall of the semiconductor stacked pillar 200, the width of the initial channel pillar 30 is greater than a target width of the channel pillar, and the semiconductor stacked pillar 200 (including the first doped layer 10 and the semiconductor layer 20) can have a relatively large width, the contact area between the semiconductor stacked pillar 200 and the substrate 100 is relatively large, the semiconductor stacked pillar 200 stands on the substrate 100 with relatively high stability, and during the formation of the isolation structure 120, even if the semiconductor stacked pillar 200 is subjected to uneven stress due to non-uniform pattern density around the semiconductor stacked pillar 200, the probability of the semiconductor stacked pillar 200 being tilted or bent is relatively low, thereby improving the yield of semiconductor processes and the performance of the vertical fully-wrapped-around gate transistor.

In this embodiment, the isolation structure 120 is made of silicon nitride. In other embodiments, the material of the isolation structure can also be an insulating material such as silicon oxynitride, silicon oxide, or the like.

Accordingly, in the present embodiment, the dummy gate 130 is formed on the isolation structure 120.

Referring to fig. 5, a bottom dielectric layer 140 is formed on the substrate 100, and the bottom dielectric layer 140 is filled between the adjacent semiconductor stacked pillars 200, surrounds the exposed sidewalls of the semiconductor stacked pillars 200 of the dummy gate 130, and covers the top surface of the dummy gate 130, and exposes the sidewalls of the dummy gate 130 far away from the adjacent semiconductor stacked pillars 200 from the bottom dielectric layer 140.

The bottom dielectric layer 140 is used to isolate the adjacent semiconductor stacked pillars 120 or dummy gates 130. In this embodiment, the bottom dielectric layer 140 covers the first sidewall 11 of the dummy gate 130 and exposes the second sidewall 12 of the dummy gate 130.

In the embodiment of the present invention, in the process of forming the dummy gates 130, there is a space between the dummy gates 130 located on the sidewalls of the adjacent semiconductor stacked pillars 200, so that, in the process of forming the bottom dielectric layer 140 on the substrate 100, which is filled between the adjacent semiconductor stacked pillars 200 and covers the top surfaces of the dummy gates 130, the bottom dielectric layer 140 can be filled between the first sidewalls 11 of the adjacent dummy gates 130, and in the subsequent forming process of removing the dummy gates 130 to form gate openings and forming semiconductor structures such as gates in the gate openings, the bottom dielectric layer 140 can support the semiconductor stacked pillars 200, thereby reducing the probability of the semiconductor stacked pillars 200 being inclined or bent; thereby improving the performance of the vertical all-around gate transistor.

In this embodiment, the bottom dielectric layer 140 is made of silicon oxide. In other embodiments, the material of the bottom dielectric layer may also be an insulating material such as silicon oxynitride, silicon nitride, or the like.

In this embodiment, the bottom dielectric layer 140 is formed on the isolation structure 120.

The bottom dielectric layer 140 exposes sidewalls (i.e., the second sidewalls 12) of the dummy gates 130 away from the adjacent semiconductor stack pillars 200, so as to facilitate subsequent removal of the dummy gates 130 through the exposed second sidewalls 12. Specifically, in the step of forming the bottom dielectric layer 140, a through hole 145 exposing the second sidewall 12 is formed in the bottom dielectric layer 140.

In this embodiment, in the step of forming the bottom dielectric layer 140, the bottom dielectric layer 140 covers the top surface of the semiconductor stacked pillar 200. Specifically, the bottom dielectric layer 140 covers the top surface of the hard mask layer 104.

In this embodiment, the step of forming the bottom dielectric layer 140 includes: forming a dielectric material layer (not shown) covering the semiconductor stacked pillar 200 and the dummy gate 130 on the substrate 100; and patterning the dielectric material layer, wherein the dielectric material layer which is positioned between the adjacent semiconductor laminated columns 200, surrounds the side wall of the semiconductor laminated column 200 exposed by the dummy gate 130 and covers the top surface of the dummy gate 130 is reserved as the bottom dielectric layer 140.

The dielectric material layer is formed by a deposition process (e.g., a chemical vapor deposition process or a high aspect ratio process). In this embodiment, a dry etching process is used to pattern the dielectric material layer.

Referring to fig. 6, the dummy gate 130 is removed to expose sidewalls of the initial trench pillar 30, and a gate opening 150 is formed in the bottom dielectric layer 140. The gate opening 150 exposes the sidewalls of the initial channel pillar 30 so that the sidewalls of the initial channel pillar 30 can be subsequently thinned. The gate opening 150 also allows room for subsequent gate formation.

In this embodiment, after the dummy gate 130 is removed, the bottom dielectric layer 140 is further disposed on the isolation structure 120 between the adjacent gate openings 150, so that after the dummy gate 130 is removed, the bottom dielectric layer 140 can support the semiconductor stacked pillar 200, and the semiconductor stacked pillar 200 is not easily bent, inclined, or collapsed.

In this embodiment, the dummy gate 130 surrounds the sidewall of the initial channel pillar 30 and also extends to surround the semiconductor layer 20 and a portion of the sidewall of the first doped layer 10, so that after the dummy gate 130 is removed, the gate opening also exposes the semiconductor layer 20 and a portion of the sidewall of the first doped layer 10.

In this embodiment, the gate opening 150 is in communication with the via 145.

In this embodiment, a dummy gate oxide layer 106 is further formed between the dummy gate 130 and the semiconductor stacked pillar 200, and therefore, the step of forming the gate opening 150 includes: and removing the dummy gate 130 and the dummy gate oxide layer 106 covered by the dummy gate 130.

In the process of removing the dummy gate 130, the dummy gate oxide layer 106 can be used as a stop layer, so that the etching consistency for removing the dummy gate 130 is improved, and the probability of causing false etching to other film layers (such as the first doping layer 10, the semiconductor layer 20 and the initial channel column 30) is reduced.

In this embodiment, the process of removing the dummy gate 130 includes a wet etching process. The wet etching process has an isotropic etching characteristic, so that the dummy gate 130 can be etched through the exposed second sidewall 12, and the dummy gate 130 can be removed. Specifically, in this embodiment, the material of the dummy gate 130 is amorphous silicon, and the etching solution of the wet etching process includes a TMAH solution.

The process of removing the dummy gate oxide layer 106 covered by the dummy gate 130 includes a wet etching process. The etching solution of the wet etching process comprises a hydrofluoric acid solution.

Referring to fig. 7, the exposed sidewalls of the initial channel pillar 30 of the gate opening 150 are thinned, and the remaining initial channel pillar 30 is used as the channel pillar 40. Channel pillars 40 are used to provide a conductive channel for the device in operation.

In the step of providing the semiconductor stacked pillar 200, in order to improve the stability of the semiconductor stacked pillar 200 on the substrate 200 to reduce the probability of the semiconductor stacked pillar 200 being bent, inclined or collapsed, the width of the initial channel pillar 30 is greater than the target width of the channel pillar 40, and therefore, by thinning the sidewall of the initial channel pillar 30, the channel pillar 40 satisfying the target width is formed, and accordingly, the thickness degree of the conductive channel satisfies the design requirement.

After the sidewalls of the initial channel pillar 30 are thinned to form the channel pillar 40, the sidewalls of the channel pillar 40 are recessed with respect to the sidewalls of the first doped layer 10 or the semiconductor layer 20.

In this embodiment, the gate opening 150 also exposes the semiconductor layer 20 and a portion of the sidewall of the first doped layer 10. The material of the semiconductor layer 20 or the first doping layer 10 is different from that of the initial channel column 30, so that in the process of thinning the initial channel column 30, the etching selection ratio is formed between the initial channel column 30 and the semiconductor layer 20, and the etching selection ratio is formed between the initial channel column 30 and the first doping layer 10, so that the semiconductor layer 20 or the first doping layer 10 is not easily etched by mistake, and the thinning process difficulty is favorably reduced.

In this embodiment, in the step of thinning the sidewall of the initial channel pillar 30, the etching selection ratio of the initial channel pillar 30 to the first doping layer 10 is at least 5: 1; the etch selectivity of the initial channel pillar 30 to the semiconductor layer 20 is at least 5: 1. The initial channel column 30 and the semiconductor layer 20, and the initial channel column 30 and the first doping layer 10 have higher etching selection ratios, so that the difficulty of the thinning process and the probability of causing false etching to the first doping layer 10 and the semiconductor layer 20 are remarkably reduced.

In this embodiment, the process of thinning the sidewall of the initial trench pillar 30 includes a wet etching process. The wet etching process has the characteristic of isotropic etching, so that the side wall of the initial trench pillar 30 can be etched along the direction perpendicular to the side wall of the semiconductor laminated pillar 200, the initial trench pillar 30 can be thinned, and the trench pillar 40 can meet the requirement of the target width. In this embodiment, the initial trench pillar 30 is made of silicon, and the etching solution of the wet etching process includes a TMAH solution.

Referring to fig. 8, the gate opening 150 is filled to form a gate 160 surrounding the sidewalls of the channel pillar 40.

The gate 160 serves as a device gate for controlling the conduction channel to be turned on or off when the device is in operation.

In the embodiment, in the process of forming the gate 160, the bottom dielectric layer 140 is further remained between the gate openings 150 on the sidewalls of the adjacent semiconductor stacked pillars 200, so that the bottom dielectric layer 140 can play a role of supporting, and the width of the first doped layer 10 is larger, which is beneficial to ensuring that the semiconductor stacked pillars 200 are not prone to tilt, bend or collapse.

In this embodiment, the gate 160 is formed on the isolation structure 120.

In this embodiment, the gate opening 150 communicates with the through hole 145, and the gate 160 is further formed in a portion of the through hole 145. In this embodiment, the gate 160 also surrounds the top corner of the first doped layer 10 and the bottom corner of the semiconductor layer 20.

In this embodiment, the gate 160 is a metal gate, and the gate 160 includes: a high-k gate dielectric layer 61 surrounding the channel pillar 40 exposed by the gate opening 150, the first doped layer 10 covering the gate opening 150, the semiconductor layer 20, and the bottom dielectric layer 140; a work function layer 62 on the high-k gate dielectric layer 61; and a gate electrode layer 63 on the work function layer 62 and filling the gate opening 150.

The high-k gate dielectric layer 61 serves to achieve electrical isolation between the gate electrode 160 and the channel pillar 40, and also serves to achieve electrical isolation between the gate electrode 160 and the first doped layer 10 or the semiconductor layer 20. The material of the high-k gate dielectric layer 61 is a high-k dielectric material. As an example, the material of the high-k gate dielectric layer 61 is HfO₂。

The work function layer 62 is used to adjust the work function of the gate 160 and thus the threshold voltage of the transistor. In this embodiment, a PMOS transistor is formed, and the work function layer 62 is made of a P-type work function material.

The gate electrode layer 63 serves as an electrode for making electrical connection between the gate electrode 160 and an external circuit or other interconnection structure. The material of the gate electrode layer 63 is a conductive material, for example: al, W, Co, etc.

In this embodiment, the step of forming the gate 160 includes: forming an initial gate (not shown) in the gate opening 150 and the via 145; a portion of the preliminary gate located in the via 145 is removed, and the remaining preliminary gate is used as the gate 160.

In this embodiment, the process of forming the initial gate includes one or more of atomic layer deposition, physical vapor deposition, chemical vapor deposition, and electroplating. Specifically, the initial gate includes an initial high-k gate dielectric layer, an initial work function layer on the initial high-k gate dielectric layer, and an initial gate electrode layer on the initial work function layer. In the embodiment, an atomic layer deposition process is adopted to form an initial high-k gate dielectric layer and an initial work function layer; and forming an initial gate electrode layer by adopting a physical vapor deposition process.

In this embodiment, a wet etching process is used to remove a portion of the initial gate in the via 145. Specifically, according to the material of the initial gate, the etching solution of the wet etching process is an acid solution capable of etching the material of the initial gate.

With reference to fig. 9, in this embodiment, after forming the gate 160, the method for forming the semiconductor structure further includes: and removing part of the thickness of the bottom dielectric layer 140 to expose the semiconductor layer 20.

The semiconductor layer 20 is exposed so that an epitaxial layer can be subsequently formed on the semiconductor layer 20.

In this embodiment, in the step of removing a part of the thickness of the bottom dielectric layer 140, the hard mask layer 104 on the semiconductor layer 20 is also removed.

With continued reference to fig. 9, the method of forming the semiconductor structure further includes: a second doped layer (not labeled) is formed on top of the channel pillar 30. In this embodiment, the step of forming the second doping layer includes: an epitaxial layer 50 is formed on the semiconductor layer 20, and ions are self-doped in situ during the process of forming the epitaxial layer 50, and the semiconductor layer 20 and the epitaxial layer 50 doped with ions are used as the second doping layer.

The second doped layer is used as a source region or a drain region of the VGAA transistor. Specifically, in the present embodiment, the first doped layer 10 is used as a source region, and the second doped layer is correspondingly used as a drain region.

By forming the epitaxial layer 50 doped with ions on the semiconductor layer 20, the volume of the second doped layer is increased, and when the device works, the stress of the second doped layer on the channel region is further increased, so that the mobility of carriers is increased. Meanwhile, by forming the epitaxial layer 50, the volume of the second doping layer is increased, which is beneficial to increase the contact area between the subsequent second source drain plug and the second doping layer, and the area of the second doping layer in the direction parallel to the substrate 100 is larger, which is beneficial to reducing the requirement on the alignment precision of the photoetching process for forming the second source drain plug, thereby reducing the process difficulty for forming the second source drain plug, and both the two aspects are beneficial to improving the contact performance between the second source drain plug and the second doping layer.

The material and the type of the dopant ions of the epitaxial layer 50 are the same as those of the semiconductor layer 20, and are not described herein again.

It should be noted that the above step of forming the second doping layer is only an example, and the step of forming the second doping layer according to the present invention is not limited thereto. For example, in the step of providing the substrate and the semiconductor laminated pillar, the semiconductor layer is doped with ions, and the semiconductor layer doped with ions is used as the second doping layer. Alternatively, in some embodiments, after forming the gate electrode, the method for forming the semiconductor structure further includes: removing part of the bottom dielectric layer to expose the semiconductor layer; the step of forming the second doped layer includes: and carrying out ion doping on the semiconductor layer, wherein the semiconductor layer doped with ions is used as the second doping layer.

Referring to fig. 10 in combination, in this embodiment, after the gate 160 and the second doped layer are formed, the forming method further includes: forming a first source drain plug 170 in contact with the doped layer side 110; forming a second source drain plug 180 in contact with the second doped layer; a gate plug 190 is formed in contact with the gate 160.

The first source drain plug 170 is used as a source plug to electrically connect with the first doped layer 10 by contacting with the doped layer side 110, so as to electrically connect the first doped layer 10 with an external circuit or other interconnection structure.

The second source drain plug 180 serves as a drain plug for electrically connecting the second doped layer to an external circuit or other interconnect structure. In this embodiment, the second source/drain plug 180 is in contact with the epitaxial layer 50.

The gate plug 190 is used to electrically connect the gate 160 to external circuitry or other interconnect structures.

In this embodiment, the first source-drain plug 170, the second source-drain plug 180, and the gate plug 190 are made of the same material, and are made of conductive materials, for example: w, Co, Ni, Cu, or the like.

In this embodiment, before forming the first source-drain plug 170, the second source-drain plug 180, and the gate plug 190, the method for forming the semiconductor structure further includes: an interlayer dielectric layer 165 is formed on the bottom dielectric layer 140 to cover the gate 160 and the second doped layer.

Therefore, the first source-drain plug 170 penetrates through the isolation structure 120, the bottom dielectric layer 140 and the interlayer dielectric layer 165 above the doped layer side portion 110; the second source drain plug 180 penetrates through the interlayer dielectric layer 165 above the second doped layer; the gate plug 190 penetrates the interlayer dielectric layer 165 above the gate 160.

The interlayer dielectric layer 165 is used for realizing electrical isolation among the first source-drain plug 170, the second source-drain plug 180 and the gate plug 190. The interlayer dielectric layer 165 is made of a dielectric material, for example: low-k dielectric materials, ultra-low-k dielectric materials, silicon oxide, silicon nitride, or silicon oxynitride.

Fig. 11 to 15 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention. The same parts of this embodiment as those of the previous embodiments are not described herein again, and the differences between this embodiment and the previous embodiments are: the initial channel pillar is used as an initial bottom channel pillar 30 a; the semiconductor layer is used as a second doping layer 20 a; the dummy gate is used as a bottom dummy gate; the gate opening is used as a bottom gate opening; the channel pillar is used as a bottom channel pillar 40 a; the gate is used as a bottom gate 160 a.

Referring to fig. 11, a substrate 100a and a semiconductor stacked pillar 200a protruding from the substrate 100a are provided, wherein the semiconductor stacked pillar 200a includes a first doped layer 10a, an initial bottom channel pillar 30a, and a semiconductor layer for forming a second doped layer 20a, which are sequentially stacked from bottom to top.

In this embodiment, in the step of providing the semiconductor laminated pillar 200a, the semiconductor layer is used as the second doped layer 20a, and the semiconductor laminated pillar 200a further includes a buffer layer 310, a third doped layer 320, an initial top channel pillar 330, and a top semiconductor layer for forming a fourth doped layer 340, which are sequentially stacked from bottom to top on the second doped layer 20 a.

By providing the semiconductor stack pillar 200a further including the third doped layer 320, the initial top channel pillar 330 and the top semiconductor layer for forming the fourth doped layer 340, provision is made for a subsequent formation of another VGAA transistor above the second doped layer 20 a.

In this embodiment, the sidewalls of the first doped layer 10a, the preliminary bottom channel pillar 30a, the second doped layer 20a, the buffer layer 310, the third doped layer 320, the preliminary top channel pillar 330, and the top semiconductor layer are flush. In this embodiment, the semiconductor stacked pillar 200a has a cylindrical structure.

The buffer layer 310 is used to prevent the third doped layer 320 from being directly formed on the second doped layer 20a to generate a large stress, which may cause defects such as dislocations. In this embodiment, the buffer layer 310 is made of silicon.

The third doped layer 320 is used to form a source or drain region of another VGAA transistor. The fourth doped layer 340 is used to form a source region or a drain region of another VGAA transistor. In this embodiment, the third doped layer 320 is used as a source region and the fourth doped layer is used as a drain region.

In this embodiment, the first doped layer 10a and the second doped layer 20a are doped with first type ions; the third doped layer 320 and the fourth doped layer 340 are doped with ions of a second type, which is different from the first type. Therefore, the first doping layer 10a and the second doping layer 20a, and the bottom channel pillar 40a and the corresponding bottom gate 160a are used to form a first-type transistor, the third doping layer 320 and the fourth doping layer 340 and the corresponding top channel pillar, and the subsequent top gate are used to form a second-type transistor, and the doping types of the second-type transistor and the first-type transistor are different, so that two different types of devices can be formed on the same semiconductor laminated pillar 200a, which is beneficial to meeting the requirements of different devices and simultaneously reducing the process complexity.

In this embodiment, the second type transistor is an NMOS transistor, and therefore, the third doped layer 320 and the fourth doped layer 340 are doped with N-type ions. The material of the third doped layer 320 and the top semiconductor layer is SiC or SiP.

The initial top channel pillar 330 is used to form a top channel pillar via a subsequent thinning process.

In this embodiment, the material of the initial top channel pillar 330 is silicon.

In this embodiment, the top semiconductor layer is doped with ions, the doping type of the ions in the top semiconductor layer is the same as that of the third doping layer 320, and the top semiconductor layer 340 doped with ions is used as the fourth doping layer 340.

For a detailed description of the third doped layer 320, the top semiconductor layer, the fourth doped layer 340 and the initial top channel pillar 330, please refer to the related description of the first doped layer, the channel pillar, the semiconductor layer and the second doped layer in the foregoing embodiments, which is not repeated herein.

Referring to fig. 12, a bottom dummy gate (not shown) surrounding sidewalls of the preliminary bottom channel pillar 30a and exposing the second doping layer 20a is formed; forming a bottom dielectric layer 140a on the substrate 100a, wherein the bottom dielectric layer is filled between adjacent semiconductor stacked pillars 200a, surrounds the exposed sidewalls of the semiconductor stacked pillars 200a of the bottom dummy gate, and covers the top surface of the bottom dummy gate; removing the bottom dummy gate to expose the sidewall of the initial bottom channel pillar 30a, and forming a bottom gate opening (not shown) in the bottom dielectric layer 140 a; thinning the sidewall of the initial bottom channel column 30a exposed from the bottom gate opening, and using the remaining initial bottom channel column 30a as a bottom channel column 40 a; the bottom gate opening is filled to form a bottom gate 160a surrounding the sidewalls of the bottom channel pillar 40 a.

The steps of forming the bottom dummy gate, the bottom dielectric layer 140a and the bottom gate opening, thinning the sidewall of the initial bottom channel pillar 30a, and forming the bottom gate 160a refer to the corresponding description of the previous embodiments, and are not repeated herein.

Referring to fig. 13, after forming the bottom gate 160a, the method for forming the semiconductor structure further includes: a portion of the thickness of the bottom dielectric layer 140a is removed to expose the initial top trench pillars 330.

In this embodiment, the method for forming the semiconductor structure further includes: after the bottom gate 160a is formed and before the top dummy gate is formed, a common source/drain interconnection layer 345 covering the sidewall of the buffer layer 310 and also extending to cover the sidewalls of the second doped layer 20a and the third doped layer 320 is formed.

The common source-drain interconnection layer 345 covers part of the sidewalls of the second doped layer 20a and the third doped layer 320, so that the second doped layer 20a and the third doped layer 320 are electrically connected, and the process complexity of electrically leading out the second doped layer 20a or the third doped layer 320 is favorably reduced. Specifically, the common source-drain interconnection layer 345 surrounds the sidewall of the buffer layer 310 and extends to surround the third doped layer 320 and a part of the sidewall of the second doped layer 20a, which is beneficial to increase the contact area between the common interconnection layer 345 and the third doped layer 320 or the second doped layer 20 a. A common source drain interconnect layer 345 is formed on the bottom dielectric layer 140 a.

Referring to fig. 14, a top dummy gate 350 surrounding the preliminary top channel pillar 330 is formed; a top dielectric layer 360 is formed on the bottom dielectric layer 140, and the top dielectric layer 360 is filled between the adjacent semiconductor stacked pillars 200a, surrounds the exposed sidewalls of the semiconductor stacked pillars 200a of the top dummy gate 350, and covers the top surface of the top dummy gate 350, and exposes the sidewalls of the top dummy gate 350 far away from the adjacent semiconductor stacked pillars 200 a.

In this embodiment, the top dummy gates 350 on the sidewalls of the adjacent semiconductor stacked pillars 200a are spaced apart from each other, so that in the process of forming the top dielectric layer 360, the top dielectric layer 360 can cover the sidewalls of the top dummy gates 350 opposite to the adjacent semiconductor stacked pillars 200a, and further the top dielectric layer 360 can support the semiconductor stacked pillars 200a, so that the semiconductor stacked pillars 200a are not bent or inclined.

In this embodiment, after the common source-drain interconnection layer 345 is formed and before the top dummy gate 350 is formed, the forming method further includes: a spacer 355 is formed on the common source drain interconnect layer 345, surrounding a portion of the sidewalls of the third doped layer 320. The spacer layer 355 serves to realize a spacing between the common source drain interconnect layer 345 and the top dummy gate 350, and accordingly, to realize electrical isolation between the common source drain interconnect layer 345 and the top gate 350. The material of the spacer layer 355 is an insulating material. Thus, a top dummy gate 350 is formed on the spacer 355.

For the related description of the top dummy gate 350 and the top dielectric layer 360, reference may be made to the corresponding description of the dummy gate and the bottom dielectric layer in the foregoing embodiments, and further description is omitted here.

Referring to fig. 15, the top dummy gate 350 is removed to form a top gate opening (not shown); thinning the sidewall of the initial top channel pillar 330 exposed by the top gate opening to form a top channel pillar 370; a top gate 380 is formed in the top gate opening surrounding the top channel pillar 370.

The top channel pillar 370 is used to provide the conduction channel of the second type transistor.

The top gate 380 is used to control the conduction channel of the second type transistor to be turned on or off.

For a detailed description of removing the top dummy gate 350, thinning the sidewall of the initial top channel pillar 330, and forming the top gate 380, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here.

With continued reference to fig. 15, the method of forming further includes: top source drain plugs 390 are formed on the fourth doped layer 340 and in contact with the fourth doped layer 340. Top source drain plugs 390 are used to make electrical connections between fourth doped layer 340 and external circuitry or other interconnect structures.

For a detailed description of the method for forming the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 10, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a semiconductor stacked pillar 200 protruding from the substrate 100, wherein the semiconductor stacked pillar 200 includes a first doped layer 10, a channel pillar 40, and a second doped layer (not labeled) stacked in sequence from bottom to top, and a sidewall of the channel pillar 40 is recessed with respect to sidewalls of the first doped layer 10 and the second doped layer along a direction perpendicular to a sidewall of the channel pillar 40; a gate 160 surrounding sidewalls of the channel pillar 40 with a space between the gates 160 on sidewalls of adjacent semiconductor stack pillars 200; a dielectric layer 140 filled between the gates 160 located on the sidewalls of the adjacent semiconductor stacked pillars 200 and covering the top surfaces of the gates 160, wherein the dielectric layer 140 covers the sidewalls of the gates 160 opposite to the adjacent semiconductor stacked pillars 200.

In this embodiment, the dielectric layer 140 is used as the bottom dielectric layer 140.

The channel pillar 40 has a target width in a direction perpendicular to the sidewalls of the channel pillar 40. In a direction perpendicular to the sidewall of the channel pillar 40, the sidewall of the channel pillar 40 is recessed with respect to the sidewalls of the first doped layer 10 and the second doped layer, that is, the widths of the first doped layer 10 and the second doped layer are greater than the target width of the channel pillar 40, and the widths of the first doped layer 10 and the second doped layer are greater, which is beneficial to improving the stability of the semiconductor stacked pillar 200 standing on the substrate 100.

Moreover, there is a space between the gates 160 located on the sidewalls of the adjacent semiconductor stacked pillars 200, and the bottom dielectric layer 140 is filled between the adjacent semiconductor stacked pillars 200, covering the sidewalls of the gates 160 opposite to the adjacent semiconductor stacked pillars 200, where the bottom dielectric layer 140 can support the semiconductor stacked pillars 200 during the formation of the semiconductor structure; both of the above aspects are beneficial to reducing the probability of the semiconductor stacked pillar 200 tilting or bending in the formation process of the semiconductor structure, and improving the performance of the vertical fully-enclosed gate (VGAA) transistor.

The substrate 100 is used to provide a process platform for forming VGAA transistors.

The semiconductor laminated pillar 200 extends in a direction perpendicular to the substrate 100, and the area utilization efficiency of the semiconductor structure can be improved. In this embodiment, the semiconductor stacked pillar 200 has a cylindrical structure. In this embodiment, the number of the semiconductor stacked pillars 200 is plural, and the plural semiconductor stacked pillars 200 are separated from the substrate 100.

In this embodiment, the first doped layer 10 serves as a source region of the vertically all-around gate transistor.

In this embodiment, along a direction perpendicular to the sidewall of the semiconductor laminated pillar 200, the width of the semiconductor laminated pillar 200 is larger, and the width of the first doped layer 10 is also larger, so that the volume of the first doped layer 10 is larger and the contact area between the first doped layer 10 and the substrate 100 is larger, which is beneficial to improving the stability of the semiconductor laminated pillar 200 standing on the substrate 100, and makes the semiconductor laminated pillar 200 less prone to bending, tilting or collapsing. In addition, the width of the first doped layer 10 is relatively large, and the volume of the first doped layer 10 is relatively large, which is beneficial to improving the stress on the channel region, further beneficial to improving the carrier mobility of the channel region, and correspondingly beneficial to optimizing the performance of the semiconductor structure.

In this embodiment, the first doping layer 10 and the channel pillar 40 are made of different materials, and the channel pillar 40 is formed by thinning a sidewall of an initial channel pillar, so that an etching selectivity ratio is provided between the initial channel pillar and the first doping layer 10, which is beneficial to reducing the probability of damage to the first doping layer 10 in the process of thinning the sidewall of the initial channel pillar to form the channel pillar 40.

In this embodiment, a PMOS transistor is formed, and the material of the first doped layer 10 may be SiGe doped with P-type ions. In other embodiments, when forming an NMOS transistor, the material of the first doped layer may be SiC or SiP doped with N-type ions.

In this embodiment, the direction perpendicular to the sidewalls of the semiconductor stacked pillar 200 is parallel to the substrate 100.

In this embodiment, the semiconductor stacked pillar 200 has a cylindrical structure, and the width refers to the cross-sectional diameter of the channel pillar 40. In the present embodiment, the material of the channel pillar 40 includes Si.

The channel pillar 40 has a target width in a direction perpendicular to sidewalls of the channel pillar 40; the recess dimension of the sidewall of the channel pillar 40 on one side with respect to the sidewall of the first doped layer 10 is a recess width, and the recess width is 10% to 30% of the target width.

In this embodiment, the second doped layer is used as a drain region of the VGAA transistor. In this embodiment, the second doped layer includes a semiconductor layer 20 and an epitaxial layer 50 located on the semiconductor layer 20 and doped with ions.

By making the second doped layer include the semiconductor layer 20 and the epitaxial layer 50, the volume of the second doped layer is increased, and when the device is in operation, the stress of the second doped layer on the channel region is increased, so that the mobility of carriers is increased. Meanwhile, by arranging the epitaxial layer 50, the volume of the second doping layer is increased, the contact area between the second source drain plug and the second doping layer is increased correspondingly, the area of the second doping layer in the direction parallel to the substrate 100 is larger, the requirement on the alignment precision of the photoetching process for forming the second source drain plug is reduced, the forming difficulty of the second source drain plug is reduced, and the forming quality of the second source drain plug and the contact performance between the second source drain plug and the second doping layer are improved correspondingly.

In this embodiment, the semiconductor layer 20 and the channel pillar 40 are made of different materials. Specifically, the semiconductor layer 20 is the same material as the first doped layer 10. In this embodiment, a PMOS transistor is formed, and the material of the semiconductor layer 20 is SiGe. In other embodiments, when forming an NMOS transistor, the material of the semiconductor layer may be SiC or SiP.

In this embodiment, the semiconductor layer 20 is further doped with ions, and the type of the doped ions in the semiconductor layer 20 is the same as that of the doped ions in the first doped layer 10. The material and the type of the dopant ions of the epitaxial layer 50 are the same as those of the semiconductor layer 20, and are not described herein again.

In this embodiment, the semiconductor structure further includes: and a doped layer side portion 110 connected to the bottom of the first doped layer 10, located on the substrate 100, and extending in a direction parallel to the substrate 100.

The semiconductor structure typically further comprises: and a first source drain plug 170 contacting the doped layer side 110.

Through setting up doping layer lateral part 110 to make first doping layer 10 realize the electricity through between doping layer lateral part 110 and the first source leakage plug 170 and be connected, doping layer lateral part 110 is great along the area that is on a parallel with substrate 100 direction, is favorable to reducing the degree of difficulty that forms first source leakage plug 170, moreover, through setting up doping layer lateral part 110, can also make the first doping layer 10 of adjacent semiconductor lamination post 200 contact according to actual technology demand, and then make the first doping layer 10 of adjacent semiconductor lamination post 200 realize the electricity and connect.

In this embodiment, the semiconductor structure further includes: an isolation structure 120 located on the substrate 100 and surrounding a portion of the sidewall of the first doped layer 10.

The isolation structure 120 is used to isolate adjacent semiconductor stack pillars 200. In this embodiment, the isolation structure 120 is located on the doped layer side 110, and the isolation structure 120 is further used for isolating the doped layer side 110 from the gate 160. In this embodiment, the isolation structure 120 is made of silicon nitride.

In this embodiment, the gate 160 also surrounds the top corner of the first doped layer 10 and the bottom corner of the semiconductor layer 20.

In this embodiment, a gate opening (not labeled) exposing the sidewall of the channel pillar 40 and a through hole (not labeled) in the bottom dielectric layer 140 located on a side of the semiconductor stacked pillar 200 far away from the adjacent semiconductor stacked pillar 200 are formed in the bottom dielectric layer 140, and the gate opening is communicated with the through hole.

In this embodiment, the gate 160 is located in the gate opening and part of the via.

In this embodiment, the gate 160 is a metal gate, and the gate 160 includes: a high-k gate dielectric layer 61 surrounding the sidewall of the channel pillar 40, the first doped layer 10 covering the exposed gate opening, the semiconductor layer 20, and the bottom dielectric layer 140; a work function layer 62 on the high-k gate dielectric layer 61; and a gate electrode layer 63 on the work function layer 62 and filling the gate opening.

The bottom dielectric layer 140 is used to isolate adjacent semiconductor stack pillars 120 or gates 160. In this embodiment, the bottom dielectric layer 140 is made of silicon oxide. A bottom dielectric layer 140 is located on the isolation structure 120.

The bottom dielectric layer 140 can support the semiconductor stacked pillar 200 in the formation process of the semiconductor structure, thereby reducing the probability of the semiconductor stacked pillar 200 being inclined or bent, and further being beneficial to improving the process yield and the performance of the VGAA transistor. In the present embodiment, the spacing between the gates 160 on the sidewalls of the adjacent semiconductor stacked pillars 200 is 30% to 70% of the spacing between the adjacent semiconductor stacked pillars 200, for example: 50 percent.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 165 on the bottom dielectric layer 140 covering the gate 160 and the second doped layer; a first source-drain plug 170 penetrating through the isolation structure 120, the bottom dielectric layer 140 and the interlayer dielectric layer 165 above the doped layer side 110 and contacting the doped layer side 110; the second source-drain plug 180 penetrates through the interlayer dielectric layer 165 above the second doped layer and is in contact with the second doped layer; and a gate plug 190 penetrating through the interlayer dielectric layer 140 above the gate 160 and contacting the gate 160.

The interlayer dielectric layer 165 is used for realizing electrical isolation among the first source-drain plug 170, the second source-drain plug 180 and the gate plug 190. The interlayer dielectric layer 165 is made of a dielectric material.

The first source drain plug 170 is used as a source plug to electrically connect with the first doped layer 10 by contacting with the doped layer side 110, so as to electrically connect the first doped layer 10 with an external circuit or other interconnection structure. The second source drain plug 180 serves as a drain plug for electrically connecting the second doped layer to an external circuit or other interconnect structure. In this embodiment, the second source/drain plug 180 is in contact with the epitaxial layer 50.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 15, a schematic structural diagram of another embodiment of a semiconductor structure of the present invention is shown.

The same parts of this embodiment as those of the previous embodiments are not described herein again, and the differences between this embodiment and the previous embodiments are:

the channel pillar is used as a bottom channel pillar 40 a; the gate is used as a bottom gate 160 a; the semiconductor stacked pillar 200a further includes: a buffer layer 310, a third doped layer 320, a top channel pillar 370 and a fourth doped layer 340 sequentially stacked on the second doped layer 20a, wherein a sidewall of the top channel pillar 370 is recessed with respect to a sidewall of the third doped layer 320 or the fourth doped layer 340; the semiconductor structure further includes: a top gate 380 surrounding sidewalls of the top channel pillar 370.

Another VGAA transistor can be formed above the second doped layer 20a by making the semiconductor stacked pillar 200a further include a third doped layer 320, a top channel pillar 370, and a fourth doped layer 340.

The third doped layer 320 is used to form a source or drain region of another VGAA transistor. The fourth doped layer 340 is used to form a source region or a drain region of another VGAA transistor. In this embodiment, third doped layer 320 is used as a source region and fourth doped layer 340 is used as a drain region.

In this embodiment, the first doped layer 10a and the second doped layer 20a are doped with first type ions; the third doped layer 320 and the fourth doped layer 340 are doped with ions of a second type, which is different from the first type. Therefore, the first doping layer 10a and the second doping layer 20a, and the bottom channel pillar 40a and the corresponding bottom gate 160a are used to form a first-type transistor, the third doping layer 320 and the fourth doping layer 340 and the corresponding top channel pillar 370 and the corresponding top gate 380 are used to form a second-type transistor, and the doping types of the second-type transistor and the first-type transistor are different, so that two different types of devices can be formed on the same semiconductor laminated pillar 200a, which is beneficial to meeting the requirements of different devices and simultaneously reducing the process complexity.

In this embodiment, the second type transistor is an NMOS transistor, and therefore, the third doped layer 320 and the fourth doped layer are doped with N-type ions. The material of the third doped layer 320 and the fourth doped layer 340 is SiC or SiP. In this embodiment, the material of the top channel pillar 370 is silicon.

In this embodiment, the semiconductor structure further includes: and a common source-drain interconnection layer 345 covering the sidewall of the buffer layer 310 and extending to cover the third doped layer 320 and a part of the sidewall of the second doped layer 20 a.

The common source-drain interconnection layer 345 covers part of the sidewalls of the second doped layer 20a and the third doped layer 320, so that the second doped layer 20a and the third doped layer 320 are electrically connected, and the process complexity of electrically leading out the second doped layer 20a and the third doped layer 320 is reduced. Specifically, the common source-drain interconnection layer 345 surrounds the sidewall of the buffer layer 310 and extends to surround the third doped layer 320 and a part of the sidewall of the second doped layer 20a, which is beneficial to increase the contact area between the common interconnection layer 345 and the third doped layer 320 or the second doped layer 20 a. A common source drain interconnect layer 345 is located on the bottom dielectric layer 140 a.

In this embodiment, the semiconductor structure further includes: a spacer layer 355 between the top gate 380 and the common source drain interconnect layer 345 surrounds a portion of the sidewalls of the third doped layer 320. The spacer layer 355 serves to achieve a separation between the common source drain interconnect layer 345 and the top gate 380, and accordingly, electrical isolation between the common source drain interconnect layer 345 and the subsequent top gate 380. The material of the spacer layer 355 is an insulating material.

Thus, top gate 380 is located over spacer 355.

In this embodiment, the semiconductor structure further includes: and a top dielectric layer 360 filled between adjacent semiconductor stacked pillars 200a, surrounding sidewalls of the semiconductor stacked pillars 200a exposed by the top gate 380, and covering a top surface of the top gate 380.

The top dielectric layer 360 serves to support the semiconductor stack pillar 200 a.

In this embodiment, the semiconductor structure further includes: and a top source drain plug 390 located on the fourth doped layer 340 and contacting the fourth doped layer 340. Top source drain plugs 390 are used to make electrical connections between fourth doped layer 340 and external circuitry or other interconnect structures.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate and a semiconductor laminated column protruding out of the substrate, wherein the semiconductor laminated column comprises a first doping layer, an initial channel column and a semiconductor layer for forming a second doping layer, which are sequentially stacked from bottom to top;

forming a dummy gate surrounding the sidewall of the initial channel pillar and exposing the semiconductor layer;

forming a bottom dielectric layer which is filled between the adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the pseudo gate and covers the top surface of the pseudo gate on the substrate, wherein the bottom dielectric layer is exposed out of the side wall of the pseudo gate far away from the adjacent semiconductor laminated column;

removing the pseudo gate, exposing the side wall of the initial channel column, and forming a gate opening in the bottom dielectric layer;

thinning the side wall of the initial channel column exposed by the gate opening, wherein the rest initial channel column is used as a channel column;

and filling the gate opening to form a gate surrounding the side wall of the channel column.

2. The method of claim 1, wherein in the step of forming the dummy gates, the dummy gates on the sidewalls of the adjacent stacked semiconductor pillars have a space therebetween, the sidewall of the dummy gate opposite to the adjacent stacked semiconductor pillar is a first sidewall, and the sidewall of the dummy gate away from the adjacent stacked semiconductor pillar is a second sidewall;

in the step of forming the bottom dielectric layer, the bottom dielectric layer covers the first side wall of the dummy gate and exposes the second side wall of the dummy gate.

3. The method of claim 1, wherein in the step of providing a substrate and a semiconductor stack, the sidewalls of the first doped layer are flush with the sidewalls of the initial channel pillar and the sidewalls of the semiconductor layer.

4. The method of forming a semiconductor structure of claim 1, wherein the process of thinning the initial trench pillar sidewalls comprises a wet etch process.

5. The method of claim 4, wherein the etching solution of the wet etching process comprises a TMAH solution.

6. The method of claim 1, wherein in the step of thinning the sidewalls of the initial trench pillar, an etch selectivity of the initial trench pillar to the first doped layer is at least 5:1, and an etch selectivity of the initial trench pillar to the semiconductor layer is at least 5: 1.

7. The method of forming a semiconductor structure of claim 1, wherein the channel pillar has a target width in a direction perpendicular to sidewalls of the semiconductor stack pillar;

in the step of providing the substrate and the semiconductor stacked pillar, a width of the initial channel pillar is 1.2 times to 1.6 times the target width in a direction perpendicular to a sidewall of the semiconductor stacked pillar.

8. The method of forming a semiconductor structure of claim 1, wherein after providing the substrate and the semiconductor stack pillar, and before forming the dummy gate, the method of forming a semiconductor structure further comprises: and forming an isolation structure on the substrate, wherein the isolation structure surrounds part of the side wall of the first doped layer.

9. The method of forming a semiconductor structure of claim 2, wherein a spacing between dummy gates located on sidewalls of adjacent semiconductor stacked pillars is 30% to 70% of a spacing between adjacent semiconductor stacked pillars.

10. The method of forming a semiconductor structure according to claim 1 or 2, wherein the step of forming the dummy gate includes: forming an initial dummy gate on the substrate to cover the semiconductor stacked pillar;

removing part of the initial pseudo gate to expose the semiconductor layer;

and patterning the rest initial pseudo gate, and reserving a part of the initial pseudo gate surrounding the side wall of the initial channel pillar to be used as the pseudo gate.

11. The method of forming a semiconductor structure according to claim 1 or 2, wherein in the step of forming the bottom dielectric layer, the bottom dielectric layer covers a top surface of the semiconductor stacked pillar;

the step of forming the bottom dielectric layer comprises: forming a dielectric material layer covering the semiconductor laminated column and the dummy gate on the substrate;

and patterning the dielectric material layer, and keeping the dielectric material layer which is positioned between the adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the pseudo gate and covers the top surface of the pseudo gate as a bottom dielectric layer.

12. The method of claim 1, wherein the process of forming the gate comprises one or more of atomic layer deposition, physical vapor deposition, chemical vapor deposition, and electroplating.

13. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing the substrate and the semiconductor stacked pillar, a side portion of the doped layer connected to a bottom portion of the first doped layer, located on the substrate, and extending in a direction parallel to the substrate is further formed;

after the gate electrode is formed, the method for forming the semiconductor structure further comprises the following steps: and forming a first source drain plug which is in contact with the side part of the doped layer.

14. The method of forming a semiconductor structure of claim 13, wherein the step of providing a substrate and a semiconductor stack pillar comprises: providing a substrate, and a first initial doping layer, a channel material layer and an initial semiconductor layer which are sequentially stacked on the substrate from bottom to top;

and patterning the initial semiconductor layer, the channel material layer and the first initial doping layer with partial thickness to form the doping layer side part, the first doping layer, the initial channel column and the semiconductor layer.

15. The method of forming a semiconductor structure of claim 1, wherein the initial channel pillar is to serve as an initial bottom channel pillar; the semiconductor layer is used as a second doping layer; the dummy gate is used as a bottom dummy gate; the gate opening is used as a bottom gate opening; the channel column is used as a bottom channel column; the grid is used as a bottom grid;

in the step of providing the semiconductor laminated pillar, the semiconductor laminated pillar further includes a buffer layer, a third doping layer, an initial top channel pillar, and a top semiconductor layer for forming a fourth doping layer, which are sequentially stacked from bottom to top on the second doping layer;

after the forming the bottom gate, the forming method of the semiconductor structure further comprises: removing part of the bottom dielectric layer to expose the initial top channel column; forming a top dummy gate surrounding the initial top channel pillar; forming a top dielectric layer which is filled between the adjacent semiconductor laminated columns, surrounds the side wall of the semiconductor laminated column exposed by the top pseudo gate and covers the top surface of the top pseudo gate on the bottom dielectric layer, wherein the top dielectric layer is exposed out of the side wall of the top pseudo gate far away from the adjacent semiconductor laminated column; removing the top dummy gate to form a top gate opening; thinning the side wall of the initial top channel column exposed by the top gate opening to form a top channel column; a top gate surrounding the top channel pillar is formed in the top gate opening.

16. A semiconductor structure, comprising:

a substrate;

the semiconductor laminated column protrudes out of the substrate and comprises a first doping layer, a channel column and a second doping layer which are sequentially stacked from bottom to top, and the side wall of the channel column is retracted relative to the side walls of the first doping layer and the second doping layer along the direction perpendicular to the side wall of the channel column;

a gate surrounding sidewalls of the channel pillar with a space between gates on sidewalls of adjacent semiconductor stack pillars;

and the dielectric layer is filled between the gates positioned on the side walls of the adjacent semiconductor laminated columns and covers the top surfaces of the gates.

17. The semiconductor structure of claim 16, wherein the material of the channel pillar comprises Si; the material of the first and second doped layers comprises SiGe, SiP or SiC.

18. The semiconductor structure of claim 16, wherein the channel pillar has a target width in a direction perpendicular to the channel pillar sidewalls;

the recess width is 10-30% of the target width and is a recess width of the sidewall of the channel pillar on one side with respect to the sidewall of the first doped layer.

19. The semiconductor structure of claim 16, wherein the channel pillar is to act as a bottom channel pillar; the grid is used as a bottom grid;

the semiconductor stack pillar further includes: the buffer layer, the third doping layer, the top channel column and the fourth doping layer are sequentially stacked from bottom to top on the second doping layer, and the side wall of the top channel column is retracted relative to the side wall of the third doping layer or the fourth doping layer;

the semiconductor structure further includes: a top gate surrounding the top channel pillar sidewall.

20. The semiconductor structure of claim 19, wherein the first and second doped layers are doped with ions of a first type; and the third doping layer and the fourth doping layer are doped with second type ions, and the doping types of the second type and the first type are different.