CN114267674A

CN114267674A - Semiconductor structure and forming method thereof

Info

Publication number: CN114267674A
Application number: CN202010975880.XA
Authority: CN
Inventors: 郑二虎; 纪世良; 张冬平
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2022-04-01

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a substrate comprising a first isolation region; forming a plurality of grid structures and an intermediate layer on the substrate, wherein the intermediate layer is also positioned on the side wall surface of the grid structures, and at least 2 grid structures cross the first isolation region; etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures, forming a first opening penetrating through the plurality of grid structures on the first isolation region in the intermediate layer, and etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures in the process, wherein the etching selection ratio of the grid structure and the intermediate layer is within a preset range. Thus, the performance and reliability of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In the conventional semiconductor field, the size of a transistor is continuously reduced along with the increase of the integration degree of a semiconductor device, and the size of a gate structure is also required to be reduced along with the reduction of the size of the transistor. In order to further reduce the size of the gate structure, form a small-sized gate structure and achieve electrical isolation between different gates, a gate structure cutting process (gate cut) is usually performed on the gate structure to divide the gate structure into a plurality of gate structures.

However, in the prior art, the performance and reliability of the semiconductor structure still need to be improved.

Disclosure of Invention

The invention solves the technical problem of a semiconductor structure and a forming method thereof, and aims to improve the performance and the reliability of the semiconductor structure.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate comprising a first isolation region; a plurality of gate structures on the substrate, at least 2 gate structures crossing the first isolation region, and each of more than 2 gate structures crossing the first isolation region having a first isolation groove penetrating the gate structure on the first isolation region; and the second dielectric structure is positioned on the surface of the first isolation region, and is also positioned on the side wall surfaces of the plurality of gate structures and in the first isolation groove.

Optionally, the substrate further includes a second isolation region, 1 of the plurality of gate structures crosses over the second isolation region, and on the second isolation region, a second opening penetrating through the gate structure is provided in the gate structure crossing over the second isolation region, and the second dielectric structure is further located in the second opening.

Optionally, the method further includes: a number of interconnect structures within said second dielectric structure, at least 1 of said interconnect structures spanning said first isolation region.

Optionally, the method further includes: and the etching stop layer is positioned between the substrate outside the first isolation region and the second dielectric structure and is also positioned on the side wall surface of the gate structure.

Optionally, the base includes a substrate and a plurality of fin structures located on the substrate and separated from each other, and the plurality of gate structures cross the plurality of fin structures.

The technical solution of the present invention also provides a semiconductor structure, including: a substrate comprising a first isolation region; the gate structure comprises a plurality of gate structures and an intermediate layer, wherein the intermediate layer is positioned on the side wall surface of each gate structure, and at least 2 gate structures cross the first isolation region; a first opening in the middle layer and through the plurality of gate structures on the first isolation region.

Optionally, the material of the intermediate layer comprises a non-dielectric material or a semiconductor material.

Optionally, the material of the intermediate layer includes: a metal compound, silicon carbide, silicon germanium, or a group III-V element.

Optionally, the material of the intermediate layer comprises a dielectric material.

Optionally, the method further includes: an isolation structure located within the first opening.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate comprising a first isolation region; forming a plurality of grid structures and an intermediate layer on the substrate, wherein the intermediate layer is also positioned on the side wall surface of the grid structures, and at least 2 grid structures cross the first isolation region; etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures, forming a first opening penetrating through the plurality of grid structures on the first isolation region in the intermediate layer, and etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures in the process, wherein the etching selection ratio of the grid structure and the intermediate layer is within a preset range.

Optionally, the preset range is 4:5 to 6: 5.

Optionally, the method for forming the intermediate layer includes: forming a plurality of pseudo gate structures on the substrate; after the pseudo gate structure is formed, forming an intermediate layer covering the side wall surface of the pseudo gate structure on the surface of the substrate; and after the intermediate layer is formed, removing the pseudo gate structure.

Optionally, the method for forming the gate structure includes: and forming the gate structure in the gate opening after the intermediate layer is formed.

Optionally, the method for forming the gate structure includes: forming a first dielectric structure on the surface of the substrate before forming the intermediate layer, wherein the first dielectric structure is provided with a plurality of gate openings, and at least 2 gate openings cross the first isolation region; and forming a gate structure in the gate opening.

Optionally, the method for forming the intermediate layer includes: after the gate structure is formed, removing the first dielectric structure; and after removing the first medium structure, forming the intermediate layer on the surface of the substrate.

Optionally, the method for forming the first dielectric structure and the gate opening includes: forming a plurality of pseudo gate structures on the substrate; after the pseudo gate structure is formed, forming a first medium structure covering the side wall surface of the pseudo gate structure on the surface of the substrate; and after the first medium structure is formed, removing the pseudo gate structure.

Optionally, the material of the intermediate layer includes: a metal compound, silicon germanium, or a group III-V element.

Optionally, in the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the adopted gas includes: cl₂、BCl₃HCl and SiCl₄At least one of (1).

Optionally, the method further includes: removing the intermediate layer after forming the first opening; and after removing the intermediate layer, forming a second dielectric structure on the surface of the substrate, wherein the second dielectric structure is also positioned on the side wall surface of the gate structure.

Optionally, in the etching process for removing the intermediate layer, the etching selection ratio of the intermediate layer to the gate structure is more than 5: 1.

Optionally, the material of the second dielectric structure includes at least one of silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon hydroxide.

Optionally, the method further includes: and forming a plurality of interconnection structures in the second dielectric structure, wherein at least 1 interconnection structure spans the first isolation region.

Optionally, the material of the intermediate layer is a dielectric material; the method for forming the semiconductor structure further comprises the following steps: and forming an isolation structure in the first opening.

Optionally, the method further includes: and etching the isolation structures and the middle layer, and forming a plurality of interconnection structures in the middle layer, wherein at least 1 interconnection structure spans the first isolation region.

Optionally, the method further includes: and forming an etching stop layer between the substrate and the intermediate layer, wherein the etching stop layer is also positioned on the side wall surface of the gate structure.

Optionally, the method further includes: and etching the etching stop layer on the first isolation region while etching the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures.

Optionally, the method for forming the first opening includes: forming an isolation mask structure on the surface of the gate structure and the surface of the intermediate layer, wherein the isolation mask structure is internally provided with a first isolation opening which exposes the gate structure on the first isolation region and the surface of the intermediate layer between the adjacent gate structures; and etching the gate structure and the intermediate layer between the adjacent gate structures by taking the isolation mask structure as a mask until the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures are removed.

Optionally, the substrate further includes a second isolation region, and 1 of the plurality of gate structures crosses the second isolation region; the method for forming the semiconductor structure further comprises the following steps: and removing the gate structure on the second isolation region while removing the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures.

Optionally, the base includes a substrate and a plurality of fin structures located on the substrate and separated from each other, and the gate structure spans the plurality of fin structures.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

according to the forming method of the semiconductor structure provided by the technical scheme of the invention, a plurality of grid structures and the intermediate layer positioned on the side wall surface of the grid structures are formed on the substrate, and in the etching process for forming the first opening, the etching selection ratio of the grid structures and the intermediate layer is within a preset range, so that the rate of etching the grid structures and the rate of etching the intermediate layer can be close to or the same when the first opening is formed, and therefore, the residual intermediate layer material between adjacent grid structures on the first isolation region and the residual grid structures on the side wall surface of the intermediate layer and the surrounding substrate surface are reduced, and the performance and the reliability of the semiconductor structure are improved.

Further, since the intermediate layer is removed after the first opening is formed, the intermediate layer material remaining at the bottom of the first opening can be further reduced by the intermediate layer removing process. Meanwhile, after the intermediate layer is removed, the second dielectric structure located on the side wall surface of the gate structure is formed on the surface of the substrate, so that the space for forming the second dielectric structure is large, the process difficulty for forming the small-size electric insulation structure on the first isolation region is reduced, the influence of the process for forming the small-size electric insulation structure on the gate structure is avoided, and the performance and the reliability of the semiconductor structure are improved.

Drawings

FIGS. 1-3 are schematic cross-sectional views illustrating a process for forming a semiconductor structure;

fig. 4 to 10 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 11 to 14 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, the performance and reliability of semiconductor structures in the prior art still need to be improved. The reason why the performance and reliability of the semiconductor structure still remain to be improved is described in detail below with reference to the accompanying drawings.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 3 are schematic cross-sectional views illustrating a process of forming a semiconductor structure.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view of a semiconductor structure, and fig. 2 is a schematic cross-sectional view taken along a direction a-a1 in fig. 1, providing a substrate 100, wherein the substrate 100 includes an isolation region I; forming a first dielectric structure 110 on the substrate 100, wherein the first dielectric structure 110 has a plurality of gate openings (not shown) therein, and 2 gate openings of the plurality of gate openings cross over the isolation region I; a gate structure 120 is formed within the gate opening.

Referring to fig. 3, fig. 3 is the same as the view direction of fig. 2, a mask structure 130 is formed on the surfaces of the first dielectric structure 110 and the gate structure 120, a mask opening 131 is formed in the mask structure 130, and the mask opening 131 exposes 2 surfaces of the gate structure 120 and the first dielectric structure 110 on the isolation region I; taking the mask structure 130 as a mask, etching the gate structure 120 until 2 gate structures 120 on the isolation region I are removed, and forming an isolation opening 140 penetrating through the 2 gate structures 120 on the isolation region I; isolation structures are formed within the isolation openings 140.

In the above embodiment, since the integration of the semiconductor structure is high, and the distance between the adjacent 2 gate structures 120 is small, when the 2 gate structures 120 on the isolation region I need to be cut, under the limitation of the exposure process limit, usually, the mask opening 131 that exposes the 2 gate structures 120 on the isolation region I at the same time will be formed in the mask structure 130, and meanwhile, in order to increase the process window of the etching process for etching the 2 gate structures 120 on the isolation region I, usually, not only the 2 gate structures 120 on the isolation region I are etched, but also the first dielectric structure 110 between the 2 gate structures 120 on the isolation region I is etched and removed, that is, the isolation opening 140 also penetrates through the first dielectric structure 110 between the 2 gate structures 120 on the isolation region I.

However, due to the etching process for etching 2 gate structures 120 on the isolation region I, the etching selectivity for etching the gate structures 120 and the first dielectric structures 110 is relatively large, and therefore, the first dielectric structure material 111 (as shown in fig. 3) is easily remained on the isolation region I, so that the gate structure material 121 is easily remained on the sidewall surface of the remaining first dielectric structure material 111 and the surrounding surface of the substrate 100. On one hand, the residual gate structure material 121 is likely to cause short circuit between the gate structures 120 on both sides of the isolation region I, and the parasitic capacitance and parasitic resistance of the semiconductor structure are affected, so that the performance and reliability of the semiconductor structure are poor. On the other hand, when the isolation structure is etched later to form the interconnect opening, the remaining first dielectric structure material 111 easily blocks the bottom of the interconnect opening, which results in a large contact resistance between the interconnect structure in the interconnect opening and the substrate 100, or results in an open circuit between the interconnect structure and the circuit of the substrate 100, so that the performance and reliability of the semiconductor structure are poor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which an intermediate layer is formed on a substrate, then, a gate structure on a first isolation region and the intermediate layer between adjacent gate structures are etched, first openings penetrating through a plurality of gate structures on the first isolation region are formed in the intermediate layer, and in a process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, an etching selection ratio of the gate structure and the intermediate layer is within a preset range. Thus, the performance and reliability of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 4 and 5, fig. 4 is a schematic top view along a direction X3 in fig. 5, and fig. 5 is a schematic cross-sectional view along a direction X1-X2 in fig. 4, which provides a substrate 200, wherein the substrate 200 includes a first isolation region I.

In the present embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) located on the substrate and separated from each other, and the gate opening 211 crosses over the plurality of fin structures.

In other embodiments, the substrate is a planar substrate.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, the substrate 200 further includes a second isolation region II.

In other embodiments, the substrate does not include the second isolation region II.

Next, a plurality of gate structures and an intermediate layer are formed on the substrate 200, and the intermediate layer is also located on the sidewall surface of the gate structures. Of the plurality of gate openings, 1 spans the second isolation region II and at least 2 spans the first isolation region I. For a process of forming the gate structure and the intermediate layer, please refer to fig. 4 to fig. 7.

With continued reference to fig. 4 and fig. 5, a first dielectric structure 210 is formed on the surface of the substrate 200, the first dielectric structure 210 has a plurality of gate openings 211 therein, and 1 of the plurality of gate openings 211 in the first dielectric structure 210 crosses over the second isolation region II and at least 2 of the plurality of gate openings 211 crosses over the first isolation region I.

The gate opening 211 also spans several of the fin structures.

The method of forming the first dielectric structure 210 and the gate opening 211 comprises: forming a plurality of dummy gate structures (not shown) crossing the fin structure and gate side walls (not shown) on the side wall surfaces of the dummy gate structures on the substrate 200; after the dummy gate structure is formed, forming a first dielectric structure 210 covering the side wall surface of the dummy gate structure on the surface of the substrate 200; after the first dielectric structure 210 is formed, the dummy gate structure is removed.

Specifically, in this embodiment, the method for forming the first dielectric structure 210 covering the sidewall surface of the dummy gate structure includes: forming a first dielectric structure material layer (not shown) covering the surface of the pseudo gate structure on the substrate 200; and planarizing the first dielectric structure material layer until the top surface of the pseudo gate structure is exposed to form the first dielectric structure 210, wherein the top surface of the pseudo gate structure is exposed to the first dielectric structure 210.

The first dielectric structure 210 provides support for the subsequent formation of a gate structure.

In this embodiment, the method for forming the dummy gate structure includes: forming a pseudo-gate material film covering the surface of the fin structure on the substrate 200; and patterning the pseudo-gate material film until the surface of the substrate 200 is exposed, and forming a pseudo-gate structure crossing the fin structure on the substrate 200, wherein the top surface of the pseudo-gate structure is higher than that of the fin structure.

In this embodiment, the method for forming a semiconductor structure further includes: before the pseudo-gate structure is formed, a base dielectric layer 201 is formed on the surface of the substrate, and the base dielectric layer 201 is also positioned on part of the side wall surface of the fin portion structure; after the dummy gate structure and the gate sidewall are formed and before the first dielectric structure 210 is formed, source-drain doped layers (not shown in the figure) are formed in the fin structures on the two sides of the dummy gate structure; after the source-drain doping layer is formed, before the first dielectric structure 210 is formed, an etching stop layer 212 is formed on the side wall surface of the dummy gate structure and the surface of the substrate 200.

The forming method of the source-drain doping layer comprises the following steps: forming source and drain openings (not shown in the figure) in the fin part structures on two sides of the pseudo gate structure; and forming a source-drain doped layer in the source-drain opening by adopting an epitaxial process.

The base dielectric layer 201 functions as: and electrically insulating the adjacent fin structures and the semiconductor device from the substrate.

The etch stop layer 212 functions to: when the dummy gate structure is exposed, the problem of oxidation of the side wall surface and the gate side wall of the dummy gate structure is solved, and meanwhile, the first dielectric structure 210 and the middle layer are etched subsequently to serve as an etching stop layer to protect the gate structure, the substrate 200 and the substrate dielectric layer 201, so that damage to the gate structure, the substrate 200 and the substrate dielectric layer 201 in the etching process is reduced. Thus, the performance and reliability of the semiconductor structure is improved.

In this embodiment, the material of the gate sidewall spacer includes a low-k dielectric material (k is less than 3.9).

In the present embodiment, the material of the first dielectric structure 210 includes silicon oxide.

Referring to fig. 6, a plurality of gate structures 220 are formed on the substrate 200, wherein 1 of the gate structures 220 crosses the second isolation region II, and at least 2 of the gate structures 220 cross the first isolation region I.

Specifically, in the present embodiment, a gate structure 220 is formed in the gate opening 211, and the gate structure 220 further spans over a plurality of fin structures.

The gate structure 220 includes: a gate dielectric layer (not shown) on the sidewall surface and the bottom surface of the gate opening 211, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.

The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.

The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.

The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.

The method of forming the gate structure 220 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric structure 210 and in the gate opening 211; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer fills the gate opening 211; and planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric structure 210 is exposed, so as to form the gate structure 220.

The process for forming the gate dielectric material layer includes an oxidation process, a deposition process, and the like, and the deposition process is, for example, a chemical vapor deposition process (CVD), a physical vapor deposition Process (PVD), an atomic layer deposition process (ALD), and the like.

The process of forming the work function material layer includes a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The process of forming the gate electrode material layer includes a metal plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The process for planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer includes an etch back process or a Chemical Mechanical Polishing (CMP) process.

Referring to fig. 7, after the gate structure 220 is formed, the first dielectric structure 210 is removed; after removing the first dielectric structure 210, an intermediate layer 230 is formed on the surface of the substrate 200, where the intermediate layer 230 is also located on the sidewall surface of the gate structure 220.

In this embodiment, the etch stop layer 212 is located between the substrate 200 and the intermediate layer 230.

In this embodiment, the process of removing the first dielectric structure 210 includes at least one of a dry etching process or a wet etching process.

In this embodiment, the method of forming the intermediate layer 230 includes: forming an intermediate material layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 220; the intermediate material layer is planarized until the top surface of the gate structure 220 is exposed.

In this embodiment, the process of planarizing the intermediate material layer includes an etch-back process or a chemical mechanical polishing process.

In yet another embodiment, the first dielectric structure is not formed. The method of forming the intermediate layer includes: forming a plurality of pseudo gate structures crossing the fin part structures and etching stop layers positioned on the side wall surfaces of the pseudo gate structures and the surface of the substrate on the substrate; after the pseudo gate structure is formed, forming an intermediate layer covering the side wall surface of the pseudo gate structure on the surface of the substrate; and after the intermediate layer is formed, removing the pseudo gate structure, and forming a plurality of gate openings in the intermediate layer. In a plurality of the gate openings, 1 spans the second isolation region II and at least 2 spans the first isolation region I.

In yet another embodiment, a method of forming a plurality of the gate structures includes: and forming the gate structure in the gate opening after the intermediate layer is formed.

The material of the intermediate layer 230 includes a non-dielectric material or a semiconductor material, such as a metal compound, silicon germanium, or a multi-element semiconductor material composed of iii-v elements, etc.

In this embodiment, the material of the intermediate layer 230 is silicon.

Referring to fig. 8, the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 are etched, first openings 231 penetrating through the gate structures 220 on the first isolation region I are formed in the intermediate layer 230, and in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220, the etching selection ratio of the gate structure 220 and the intermediate layer 230 is within a predetermined range.

Because a plurality of gate structures 220 and the intermediate layer 230 located on the sidewall surface of the gate structures 220 are formed on the substrate 200, and the etching selection ratio of the gate structures 220 and the intermediate layer 230 in the etching process for forming the first opening 231 is within a preset range, the rate of etching the gate structures 220 and the rate of etching the intermediate layer can be close to or the same as each other when forming the first opening 231, and thus, the residual material of the intermediate layer 230 between adjacent gate structures 220 on the first isolation region I, and the residual material of the gate structures 220 on the sidewall surface of the intermediate layer 230 and the surrounding substrate 200 surface are reduced, and the performance and reliability of the semiconductor structure are improved.

Specifically, by reducing the residue of the intermediate layer 230 and the residue of the gate structures 220, on one hand, the risk of short circuit between the gate structures 220 that need to be spaced is reduced, and the reliability of the semiconductor structure is improved; on the other hand, the influence of the residue of the intermediate layer 230 and the residue of the gate structure 220 on the magnitude of the parasitic capacitance and the parasitic resistance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved. Furthermore, when an interconnect structure electrically interconnected with the circuit of the substrate 200 is formed subsequently, the risk of contact between the interconnect structure and the residual portions of the intermediate layer 230 and the gate structure 220 can be reduced, thereby reducing the contact resistance between the interconnect structure and the substrate 200 and improving the performance of the semiconductor structure; meanwhile, the blocking of the residual parts of the intermediate layer 230 and the gate structure 220 to the etching of the interconnect opening providing a space for the interconnect structure can be reduced, and the risk that the interconnect opening cannot expose the surface of the substrate 200 is reduced, so that the risk of open circuit between the interconnect structure and the substrate 200 is reduced, and the reliability of the semiconductor structure is improved.

In this embodiment, the predetermined range is 4:5 to 6: 5.

By setting the predetermined range to be 4:5 to 6:5, the material of the intermediate layer 230 remaining between the adjacent gate structures 220 and the remaining material of the gate structures 220 remaining on the sidewall surface of the intermediate layer 230 and the surrounding surface of the substrate 200 can be better improved during the formation of the first opening 231, so as to better improve the performance and reliability of the semiconductor structure.

Specifically, in the present embodiment, a method of forming the first opening 231 includes: forming an isolation mask structure 240 on the surface of the gate structure 220 and the surface of the intermediate layer 230, wherein the isolation mask structure 240 has a first isolation opening 241 therein, and the first isolation opening 241 exposes the gate structure 220 on the first isolation region I and the surface of the intermediate layer 230 between the adjacent gate structures 220; and etching the gate structure 220 and the intermediate layer 230 between the adjacent gate structures 220 by using the isolation mask structure 240 as a mask until the gate structure 220 on the first isolation region I and the intermediate layer 230 between the adjacent gate structures 220 are removed.

In the present embodiment, the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between the adjacent gate structures 220 includes a dry etching process.

In this embodiment, in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220, the gases used include: cl₂、BCl₃HCl and SiCl₄At least one of (1). Since the Cl-containing gas can form an etching by-product with better volatility in the etching process, by using the gas, the etching selection ratio of the gate structure 220 and the intermediate layer 230 in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 can be within a preset range.

In this embodiment, the gate structure 220 on the first isolation region I and the intermediate layer 230 between the adjacent gate structures 220 are removed, and at the same time, the gate structure 220 on the second isolation region II is removed, and a second opening 232 penetrating through 1 gate structure 220 is formed in the intermediate layer 230.

In the present embodiment, the etching stop layer 212 on the first isolation region I and the second isolation region II is etched while the gate structure 220 on the first isolation region I and the intermediate layer 230 between the adjacent gate structures 220 are etched.

In the present embodiment, after the first opening 231 is formed, the isolation mask structure 240 is removed.

Referring to fig. 9, after the first opening 231 is formed, the intermediate layer 230 is removed; after removing the intermediate layer 230, a second dielectric structure 250 is formed on the surface of the substrate 200, where the second dielectric structure 250 is also located on the sidewall surface of the gate structure 220.

By removing the intermediate layer 230 and forming the second dielectric structure 250, on one hand, electrical insulation between adjacent gate structures 220 is achieved, and electrical insulation reliability between the gate structures 220 and the substrate 200 is enhanced, and on the other hand, the second dielectric structure 250 provides support for subsequently forming interconnection structures, and electrical insulation between the interconnection structures and other semiconductor devices is achieved.

Since the intermediate layer 230 is removed after the first opening 231 is formed, the material of the intermediate layer 230 remaining at the bottom of the first opening 231 can be further reduced by the process of removing the intermediate layer 230. Meanwhile, after the intermediate layer 230 is removed, the second dielectric structure 250 located on the sidewall surface of the gate structure 220 is formed on the surface of the substrate 200, so that the space for forming the second dielectric structure 250 is large, the process difficulty for forming a small-size electrical insulation structure on the first isolation region I is reduced, the influence of the process for forming the small-size electrical insulation structure on the gate structure 220 is avoided, and the performance and reliability of the semiconductor structure are improved.

Specifically, when the space where the dielectric structure is formed is small, that is, when the dielectric structure is formed in a small space, in order to reduce defects inside the dielectric structure, it is necessary to fill the small space with a material having high fluidity. Since the material with high fluidity needs to be cured by high temperature annealing after filling the small space, the material of the gate structure may be affected due to the high temperature annealing, which may affect the electrical performance of the semiconductor device. In this embodiment, since the space for forming the second dielectric structure 250 is large, when the second dielectric structure 250 is formed, a high-fluidity material is not required, and a high-temperature annealing step is not required, so that the process difficulty of forming a small-sized electrical insulation structure on the first isolation region I can be reduced, the influence of the process for forming the small-sized electrical insulation structure on the gate structure 220 is avoided, and the performance and reliability of the semiconductor structure are improved.

Furthermore, after the first opening 231 is formed, the intermediate layer 230 is removed, and after the intermediate layer 230 is removed, a second dielectric structure 250 is formed on the surface of the substrate 200. Therefore, when the second dielectric structure 250 is simultaneously located on the first isolation region I and the substrate 200 outside the first isolation region I, and an interconnect structure electrically interconnected with the substrate 200 or the gate structure 220 is formed subsequently, an interconnect opening for providing a space for the interconnect structure can be formed in the dielectric structure (the second dielectric structure 250) with the same material, so that the etching rate can be easily the same or close in the etching process for forming the interconnect opening, and further, the depths of the interconnect opening on the first isolation region I and the interconnect opening on the substrate outside the first isolation region I are close. Because the depths of the interconnection opening on the first isolation region I and the interconnection openings on the substrate except the first isolation region I and the second isolation region II are close, the risk of over-etching or insufficient etching during the formation of the interconnection openings is reduced, and therefore the risk of disconnection of the interconnection structure on the first isolation region I and the interconnection opening structure on the substrate except the first isolation region I or the risk of damaging other semiconductor devices during the formation of the interconnection openings is reduced, and the reliability of the semiconductor structure is improved. Similarly, the same effect is obtained when the interconnection structures are formed on the second isolation region II and the substrate 200 except the second isolation region II at the same time, and the details are not repeated here.

In this embodiment, the etching process for removing the intermediate layer 230 has an etching selection ratio of the intermediate layer 230 to the gate structure 220 of more than 5: 1. Therefore, through a larger etching selection ratio, the etching process for removing the intermediate layer 230 is reduced, the damage to the gate structure 220 is reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the etching process for removing the intermediate layer 230 has an etching selection ratio of the intermediate layer 230 to the etch stop layer 212 of more than 5: 1. Therefore, through a larger etching selection ratio, in the etching process of removing the intermediate layer 230, the gate structure 220 and the substrate 200 can be better protected by the etching stop layer 212, so that the damage of the etching process of removing the intermediate layer 230 to the gate structure 220 and the substrate 200 is reduced, and the performance of the semiconductor structure is improved.

In the present embodiment, the material of the second dielectric structure 250 includes at least one of silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon hydroxide.

Referring to fig. 10, a plurality of interconnect structures 260 are formed in the second dielectric structure 250, and at least 1 interconnect structure 260 spans the first isolation region I.

In other embodiments, at least 1 interconnect structure also spans the second isolation region.

In this embodiment, the method for forming the interconnect structure 260 includes: forming a third dielectric structure 270 on the surfaces of the second dielectric structure 250 and the gate structure 220; forming an interconnection mask structure (not shown) on the surface of the third dielectric structure 270, wherein the interconnection mask structure has a plurality of interconnection mask openings therein, and each interconnection mask opening exposes a portion of the surface of the third dielectric structure 270; etching the third dielectric structure 270, the second dielectric structure 250 and the etch stop layer 212 by using the interconnect mask opening as a mask until the surface of the substrate 200 is exposed, and forming an interconnect opening (not shown) in the third dielectric structure 270 and the second dielectric structure 250; forming a layer of interconnect structure material within the interconnect opening and on a surface of the third dielectric structure 270; planarizing the interconnect structure material layer until the third dielectric structure 270 surface is exposed.

The third media construction 270 functions to: the surface flatness of the semiconductor structure is improved, the process difficulty of forming the interconnection mask structure is reduced, the pattern precision of the interconnection mask structure is improved, meanwhile, in the etching process of forming the interconnection structure, the top surface of the grid structure 220 is protected, the damage to the top surface of the grid structure 220 in the etching process is reduced, and therefore the performance and the reliability of the semiconductor structure are improved.

In other embodiments, the third dielectric structure is not formed.

In the present embodiment, exposing the surface of the substrate 200 refers to exposing the surface of the fin structure. In other embodiments, exposing the substrate may also refer to exposing a surface of the substrate other than the fin structure.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 8, including: a substrate 200, the substrate 200 comprising a first isolation region I; a plurality of gate structures 220 and an interlayer 230 on the substrate 200, wherein the interlayer 230 is also located on the sidewall of the gate structures 220, and at least 2 gate structures 220 cross over the first isolation region I; located within the intermediate layer 230 and extending through the first openings 231 of the plurality of gate structures 220 on the first isolation region I.

In other embodiments, the substrate is a planar substrate.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator or germanium-on-insulator, and the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, the substrate 200 further includes a second isolation region II, 1 of the gate structures 220 crosses over the second isolation region II, and on the second isolation region II, the intermediate layer 230 further has a second opening 232 therein, and the second opening 232 penetrates through the gate structure 220 crossing over the second isolation region II.

In this embodiment, the semiconductor structure further includes: a base dielectric layer 201 located between the intermediate layer 230 and the surface of the substrate 200, wherein the base dielectric layer 201 is also located on a part of a sidewall surface of the fin structure, and the base dielectric layer 201 functions as: and electrically insulating the adjacent fin structures and the semiconductor device from the substrate.

In this embodiment, the semiconductor structure further includes: an etch stop layer 212 located between the intermediate layer 230 and the surface of the substrate 200, wherein the etch stop layer 212 is also located on a sidewall surface of the gate structure 220.

In this embodiment, the semiconductor structure further includes: gate spacers (not shown) located between the sidewall surfaces of the gate structure 220 and the etch stop layer 212.

In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) on the sidewall surface and the bottom surface of the gate opening 211, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.

In the present embodiment, the material of the intermediate layer 230 includes a non-dielectric material or a semiconductor material, such as a metal compound, silicon germanium, or a multi-element semiconductor material composed of iii-v elements.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 10, including: a substrate 200, the substrate 200 comprising a first isolation region I; a plurality of gate structures 220 located on the substrate 200, at least 2 gate structures 220 crossing the first isolation region I, and, on the first isolation region I, each gate structure 220 of more than 2 gate structures 220 crossing the first isolation region I has a first isolation groove penetrating the gate structure 220 respectively; and a second dielectric structure 250 located on the surface of the first isolation region I, wherein the second dielectric structure 250 is also located on the sidewall surface of the plurality of gate structures 220 and in the first isolation trench.

Note that, the first isolation trench refers to an opening portion of the first opening 231 (as shown in fig. 8) that exposes a sidewall surface of the gate structure 200.

In other embodiments, the substrate is a planar substrate.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

In this embodiment, the substrate 200 further includes a second isolation region II, 1 of the plurality of gate structures 220 crosses over the second isolation region II, and on the second isolation region II, the gate structure 220 crossing over the second isolation region II has a second opening 232 (as shown in fig. 8) penetrating through the gate structure 220, and the second dielectric structure 250 is further located in the second opening 232.

In this embodiment, the semiconductor structure further includes: and the etching stop layer 212 is positioned between the substrate 200 and the second dielectric structure 250 outside the first isolation region I and the second isolation region II, and the etching stop layer 212 is also positioned on the side wall surface of the gate structure 220.

In this embodiment, the semiconductor structure further includes: a plurality of interconnect structures 260 disposed within said second dielectric structure 250, at least 1 of said interconnect structures 260 spanning said first isolation region I.

In this embodiment, the semiconductor structure further includes: a third dielectric structure 270 on top of the second dielectric structure 250 and the gate structure 220, the interconnect structure 260 further being located within the third dielectric structure 270.

Fig. 11 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to another embodiment of the present invention, and the main difference between this embodiment and the embodiment shown in fig. 4 to 10 is that the material of the intermediate layer is different.

Referring to fig. 11 on the basis of fig. 6, after the gate structure 220 is formed, the first dielectric structure 210 is removed; after removing the first dielectric structure 210, an intermediate layer 330 is formed on the surface of the substrate 200, where the intermediate layer 330 is also located on the sidewall surface of the gate structure 220.

In this embodiment, the etch stop layer 212 is located between the substrate 200 and the intermediate layer 330.

In this embodiment, the method of forming the intermediate layer 330 includes: forming an intermediate material layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 220; the intermediate material layer is planarized until the top surface of the gate structure 220 is exposed.

The material of the intermediate layer 330 is a dielectric material. Thus, electrical isolation between adjacent gate structures 220 can be achieved directly by the intermediate layer 330.

Referring to fig. 12, the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 are etched, first openings 331 penetrating through the plurality of gate structures 220 on the first isolation region I are formed in the intermediate layer 330, and in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220, the etching selection ratio of the gate structures 220 and the intermediate layer 330 is within a predetermined range.

Because a plurality of gate structures 220 and the intermediate layer 330 located on the sidewall surface of the gate structures 220 are formed on the substrate 200, and the etching selection ratio of the gate structures 220 and the intermediate layer 330 in the etching process for forming the first opening 331 is within a preset range, the rate of etching the gate structures 220 and the rate of etching the intermediate layer can be close to or the same as each other when forming the first opening 331, and thus, the residual material of the intermediate layer 330 between adjacent gate structures 220 on the first isolation region I, and the residual material of the gate structures 220 on the sidewall surface of the intermediate layer 330 and the surrounding substrate 200 surface are reduced, and the performance and reliability of the semiconductor structure are improved.

Specifically, by reducing the residue of the intermediate layer 330 and the residue of the gate structures 220, on one hand, the risk of short circuit between the gate structures 220 that need to be spaced is reduced, and the reliability of the semiconductor structure is improved; on the other hand, the influence of the residue of the intermediate layer 330 and the residue of the gate structure 220 on the parasitic capacitance and the parasitic resistance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved. Furthermore, when an interconnect structure electrically interconnected with the circuit of the substrate 200 is formed subsequently, the risk of contact between the interconnect structure and the residual portions of the intermediate layer 330 and the gate structure 220 can be reduced, thereby reducing the contact resistance between the interconnect structure and the substrate 200 and improving the performance of the semiconductor structure; meanwhile, the blocking of the residual parts of the intermediate layer 330 and the gate structure 220 to the etching of the interconnect opening providing a space for the interconnect structure can be reduced, and the risk that the interconnect opening cannot expose the surface of the substrate 200 is reduced, so that the risk of open circuit between the interconnect structure and the substrate 200 is reduced, and the reliability of the semiconductor structure is improved.

In this embodiment, the predetermined range is 4:5 to 6: 5.

By the predetermined range of 4:5 to 6:5, the material of the intermediate layer 330 remaining between the adjacent gate structures 220, and the remaining material of the gate structures 220 remaining on the sidewall surface of the intermediate layer 330 and the surrounding surface of the substrate 200 can be better improved when the first opening 331 is formed, so as to better improve the performance and reliability of the semiconductor structure.

Specifically, in the present embodiment, the method of forming the first opening 331 includes: forming an isolation mask structure 240 on the surface of the gate structure 220 and the surface of the intermediate layer 330, wherein the isolation mask structure 340 has a first isolation opening 341 therein, and the first isolation opening 341 exposes the gate structure 220 on the first isolation region I and the surface of the intermediate layer 330 between the adjacent gate structures 220; and etching the gate structure 220 and the intermediate layer 330 between the adjacent gate structures 220 by using the isolation mask structure 340 as a mask until the gate structure 220 on the first isolation region I and the intermediate layer 330 between the adjacent gate structures 220 are removed.

In the present embodiment, the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 330 between the adjacent gate structures 220 includes a dry etching process.

In this embodiment, the gate structure 220 on the first isolation region I and the intermediate layer 330 between the adjacent gate structures 220 are removed, and at the same time, the gate structure 220 on the second isolation region II is removed, and a second opening 332 penetrating through 1 gate structure 220 is formed in the intermediate layer 330.

In the present embodiment, the etching stop layer 212 on the first isolation region I and the second isolation region II is etched while the gate structure 220 on the first isolation region I and the interlayer 330 between the adjacent gate structures 220 are etched.

In the present embodiment, after the first opening 331 is formed, the isolation mask structure 340 is removed.

Referring to fig. 13, an isolation structure 351 is formed in the first opening 331.

In the present embodiment, an isolation structure 352 is formed in the second opening 332 at the same time as the isolation structure 351 is formed.

The method of forming the

isolation structures

351 and 352 comprises: forming a layer of isolating material (not shown) in the first and

second openings

331 and 332 and on the surface of the intermediate layer 330; the spacer material layer is planarized until the surface of the intermediate layer 330 is exposed.

The process for planarizing the isolation material layer comprises a back etching process or a chemical mechanical polishing process.

The material of

isolation structures

351 and 352 comprises a dielectric material.

In this embodiment, the process of forming the isolation material layer includes: filling the first opening 331 and the second opening 332 with a high-fluidity material to form an initial isolation material layer (not shown); and carrying out a high-temperature annealing process on the initial isolation material layer, and curing the initial isolation material layer to form the isolation material layer.

Referring to fig. 14, the isolation structures 351 and the intermediate layer 330 are etched, and a plurality of interconnect structures 360 are formed in the intermediate layer 330, wherein at least 1 interconnect structure 360 spans the first isolation region I.

In this embodiment, the method for forming the interconnect structure 360 includes: forming a third dielectric structure 370 on the surface of the intermediate layer 330, the surface of the isolation structure 351, the surface of the isolation structure 352 and the surface of the gate structure 220; forming an interconnect mask structure (not shown) on the surface of the third dielectric structure 370, wherein the interconnect mask structure has a plurality of interconnect mask openings therein, and each interconnect mask opening exposes a portion of the surface of the third dielectric structure 370; etching the third dielectric structure 370, the intermediate layer 330, the isolation structure 351 and the etch stop layer 212 by using the interconnect mask opening as a mask until the surface of the substrate 200 is exposed, and forming an interconnect opening (not shown) in the third dielectric structure 370 and the intermediate layer 330; forming a layer of interconnect structure material within the interconnect opening and on a surface of the third dielectric structure 370; planarizing the interconnect structure material layer until the third dielectric structure 370 surface is exposed.

The third dielectric structure 370 functions to: the surface flatness of the semiconductor structure is improved, the process difficulty of forming the interconnection mask structure is reduced, the pattern precision of the interconnection mask structure is improved, meanwhile, in the etching process of forming the interconnection structure, the top surface of the grid structure 220 is protected, the damage to the top surface of the grid structure 220 in the etching process is reduced, and therefore the performance and the reliability of the semiconductor structure are improved.

In other embodiments, the third dielectric structure is not formed.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please refer to fig. 14, which includes a substrate 200, wherein the substrate 200 includes a first isolation region I; a plurality of gate structures 220 and an interlayer 330 on the substrate 200, wherein the interlayer 330 is also located on the sidewall of the gate structures 220, and at least 2 gate structures 220 cross over the first isolation region I; located within the intermediate layer 330 and extending through the first openings 331 of the plurality of gate structures 220 over the first isolation region I.

In other embodiments, the substrate is a planar substrate.

The material of the substrate comprises a semiconductor material.

In this embodiment, the substrate is made of silicon.

In this embodiment, the substrate 200 further includes a second isolation region II, 1 of the gate structures 220 crosses over the second isolation region II, and on the second isolation region II, the intermediate layer 330 further has a second opening 332 therein, and the second opening 332 penetrates through the gate structure 220 crossing over the second isolation region II.

In this embodiment, the semiconductor structure further includes: the base dielectric layer 201 is located between the middle layer 330 and the surface of the substrate 200, the base dielectric layer 201 is also located on a part of the side wall surface of the fin portion structure, and the base dielectric layer 201 has the following functions: and electrically insulating the adjacent fin structures and the semiconductor device from the substrate.

In this embodiment, the semiconductor structure further includes: an etch stop layer 212 located between the intermediate layer 330 and the surface of the substrate 200, wherein the etch stop layer 212 is also located on a sidewall surface of the gate structure 220.

In this embodiment, the material of the intermediate layer 330 includes a dielectric material.

In this embodiment, the semiconductor structure further includes: an isolation structure 351 located within the first opening 331.

In this embodiment, the semiconductor structure further includes: an isolation structure 352 within the second opening 332.

In this embodiment, the semiconductor structure further includes: a plurality of interconnect structures 360 disposed within the intermediate layer 330, at least 1 of the interconnect structures 360 spanning the first isolation region I.

In this embodiment, the semiconductor structure further includes: a third dielectric structure 370 on top of the interlayer 330 and the gate structure 220, the interconnect structure 360 further being located within the third dielectric structure 370.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first isolation region;

a plurality of gate structures on the substrate, at least 2 gate structures crossing the first isolation region, and each of more than 2 gate structures crossing the first isolation region having a first isolation groove penetrating the gate structure on the first isolation region;

and the second dielectric structure is positioned on the surface of the first isolation region, and is also positioned on the side wall surfaces of the plurality of gate structures and in the first isolation groove.

2. The semiconductor structure of claim 1, wherein the substrate further comprises a second isolation region, wherein 1 of the plurality of gate structures crosses the second isolation region, and wherein on the second isolation region, the gate structure crossing the second isolation region has a second opening therethrough, the second dielectric structure being further located within the second opening.

3. The semiconductor structure of claim 1, further comprising: a number of interconnect structures within said second dielectric structure, at least 1 of said interconnect structures spanning said first isolation region.

4. The semiconductor structure of claim 1, further comprising: and the etching stop layer is positioned between the substrate outside the first isolation region and the second dielectric structure and is also positioned on the side wall surface of the gate structure.

5. The semiconductor structure of claim 1, wherein the base comprises a substrate and a plurality of fin structures located on the substrate and separated from each other, and wherein a plurality of the gate structures span the plurality of fin structures.

6. A semiconductor structure, comprising:

a substrate comprising a first isolation region;

the gate structure comprises a plurality of gate structures and an intermediate layer, wherein the intermediate layer is positioned on the side wall surface of each gate structure, and at least 2 gate structures cross the first isolation region;

a first opening in the middle layer and through the plurality of gate structures on the first isolation region.

7. The semiconductor structure of claim 6, in which a material of the intermediate layer comprises a non-dielectric material or a semiconductor material.

8. The method of forming a semiconductor structure of claim 8, wherein the material of the intermediate layer comprises: a metal compound, silicon carbide, silicon germanium, or a group III-V element.

9. The semiconductor structure of claim 6, in which a material of the intermediate layer comprises a dielectric material.

10. The semiconductor structure of claim 6, further comprising: an isolation structure located within the first opening.

11. The semiconductor structure of claim 6, wherein the base comprises a substrate and a plurality of fin structures located on the substrate and separated from each other, and wherein a plurality of the gate structures span the plurality of fin structures.

12. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a first isolation region;

forming a plurality of grid structures and an intermediate layer on the substrate, wherein the intermediate layer is also positioned on the side wall surface of the grid structures, and at least 2 grid structures cross the first isolation region;

etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures, forming a first opening penetrating through the plurality of grid structures on the first isolation region in the intermediate layer, and etching the grid structure on the first isolation region and the intermediate layer between the adjacent grid structures in the process, wherein the etching selection ratio of the grid structure and the intermediate layer is within a preset range.

13. The method of claim 12, wherein the predetermined range is 4:5 to 6: 5.

14. The method of forming a semiconductor structure of claim 12, wherein the method of forming the intermediate layer comprises: forming a plurality of pseudo gate structures on the substrate; after the pseudo gate structure is formed, forming an intermediate layer covering the side wall surface of the pseudo gate structure on the surface of the substrate; and after the intermediate layer is formed, removing the pseudo gate structure.

15. The method of forming a semiconductor structure of claim 14, wherein forming the gate structure comprises: and forming the gate structure in the gate opening after the intermediate layer is formed.

16. The method of forming a semiconductor structure of claim 12, wherein forming the gate structure comprises: forming a first dielectric structure on the surface of the substrate before forming the intermediate layer, wherein the first dielectric structure is provided with a plurality of gate openings, and at least 2 gate openings cross the first isolation region; and forming a gate structure in the gate opening.

17. The method of forming a semiconductor structure of claim 16, wherein the method of forming the intermediate layer comprises: after the gate structure is formed, removing the first dielectric structure; and after removing the first medium structure, forming the intermediate layer on the surface of the substrate.

18. The method of forming a semiconductor structure of claim 16, wherein forming the first dielectric structure and gate opening comprises: forming a plurality of pseudo gate structures on the substrate; after the pseudo gate structure is formed, forming a first medium structure covering the side wall surface of the pseudo gate structure on the surface of the substrate; and after the first medium structure is formed, removing the pseudo gate structure.

19. The method of forming a semiconductor structure of claim 12, wherein a material of the intermediate layer comprises a non-dielectric material or a semiconductor material.

20. The method of forming a semiconductor structure of claim 19, wherein the material of the intermediate layer comprises: a metal compound, silicon germanium, or a group III-V element.

21. The method of claim 19, wherein the etching of the gate structure over the first isolation region and the intermediate layer between adjacent gate structures is performed using a gas comprising: cl₂、BCl₃HCl and SiCl₄At least one of (1).

22. The method of forming a semiconductor structure of claim 19, further comprising: removing the intermediate layer after forming the first opening; and after removing the intermediate layer, forming a second dielectric structure on the surface of the substrate, wherein the second dielectric structure is also positioned on the side wall surface of the gate structure.

23. The method of claim 22, wherein the etching process to remove the intermediate layer has an etch selectivity of the intermediate layer to the gate structure of greater than 5: 1.

24. The method of forming a semiconductor structure of claim 22, wherein the material of the second dielectric structure comprises at least one of silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon hydroxide.

25. The method of forming a semiconductor structure of claim 24, further comprising: and forming a plurality of interconnection structures in the second dielectric structure, wherein at least 1 interconnection structure spans the first isolation region.

26. The method of forming a semiconductor structure of claim 12, wherein the material of the intermediate layer is a dielectric material; the method for forming the semiconductor structure further comprises the following steps: and forming an isolation structure in the first opening.

27. The method of forming a semiconductor structure of claim 26, further comprising: and etching the isolation structures and the middle layer, and forming a plurality of interconnection structures in the middle layer, wherein at least 1 interconnection structure spans the first isolation region.

28. The method of forming a semiconductor structure of claim 12, further comprising: and forming an etching stop layer between the substrate and the intermediate layer, wherein the etching stop layer is also positioned on the side wall surface of the gate structure.

29. The method of forming a semiconductor structure of claim 28, further comprising: and etching the etching stop layer on the first isolation region while etching the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures.

30. The method of forming a semiconductor structure of claim 12, wherein the method of forming the first opening comprises: forming an isolation mask structure on the surface of the gate structure and the surface of the intermediate layer, wherein the isolation mask structure is internally provided with a first isolation opening which exposes the gate structure on the first isolation region and the surface of the intermediate layer between the adjacent gate structures; and etching the gate structure and the intermediate layer between the adjacent gate structures by taking the isolation mask structure as a mask until the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures are removed.

31. The method of forming a semiconductor structure of claim 12, wherein the substrate further comprises a second isolation region, and wherein 1 of the plurality of gate structures crosses the second isolation region; the method for forming the semiconductor structure further comprises the following steps: and removing the gate structure on the second isolation region while removing the gate structure on the first isolation region and the intermediate layer between the adjacent gate structures.

32. The method of claim 12, wherein the base comprises a substrate and a plurality of fin structures located on the substrate and separated from each other, and the gate structure spans the plurality of fin structures.