CN113871394A - Memory structure - Google Patents

Memory structure Download PDF

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Publication number
CN113871394A
CN113871394A CN202111063721.3A CN202111063721A CN113871394A CN 113871394 A CN113871394 A CN 113871394A CN 202111063721 A CN202111063721 A CN 202111063721A CN 113871394 A CN113871394 A CN 113871394A
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Prior art keywords
layer
channel
dielectric layer
memory structure
channel hole
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CN202111063721.3A
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Inventor
向银松
刘隆冬
任连娟
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111063721.3A priority Critical patent/CN113871394A/en
Publication of CN113871394A publication Critical patent/CN113871394A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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  • Semiconductor Memories (AREA)

Abstract

The invention relates to a memory structure, comprising: the semiconductor device comprises a substrate, wherein a stacked structure is formed on the surface of the substrate and comprises control gates and insulating layers which are alternately stacked along the direction vertical to the surface of the substrate; a trench hole structure penetrating the stacked structure; the width of the control grid electrode is smaller than that of the insulating layers, so that a groove is formed between the adjacent insulating layers; and the gate dielectric layer at least covers the surface of the inner wall of the groove. The memory structure is low in forming difficulty and performance of the memory structure is improved.

Description

Memory structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory structure.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In a 3D NAND flash memory structure, a memory array structure is included, the memory array structure including a pair of multi-layer stack structures. With the increasing number of layers of the composite dielectric thin film with the stacked structure, the formation of functional sidewalls in the trench holes becomes more difficult under the background of the Critical Dimension (CD) of the (CH) of the very high aspect ratio trench in the small trench holes. In addition, because the conventional gate-last method needs to deposit a TiN film and a high-K dielectric film and then fill the metal gate W after removing the dummy gate SiN by a phosphoric acid wet method, the space for filling the metal gate is reduced to a certain extent, and the difficulty of the process for forming the metal gate is increased.
Disclosure of Invention
The invention aims to provide a memory structure, which can improve the performance of the formed memory structure.
The present invention provides a memory structure comprising: the semiconductor device comprises a substrate, wherein a stacked structure is formed on the surface of the substrate and comprises control gates and insulating layers which are alternately stacked along the direction vertical to the surface of the substrate; a trench hole structure penetrating the stacked structure; the width of the control grid electrode is smaller than that of the insulating layers, so that a groove is formed between the adjacent insulating layers; and the gate dielectric layer at least covers the surface of the inner wall of the groove.
Optionally, the trench hole structure is formed in the trench hole, and the gate dielectric layer further covers the inner wall surface of the trench hole.
Optionally, the stacked structure includes a core region and a step region surrounding the core region, and in the step region, the substrate surface has a dielectric layer covering the surface of the control gate.
Optionally, the memory cell further comprises a contact portion penetrating through the dielectric layer and electrically connected with the control gate.
Optionally, a portion of the channel hole structure is located within the recess.
Optionally, the trench hole structure comprises: the charge blocking layer is at least partially positioned in the groove, the charge capturing layer covers the side wall of the channel hole and the surface of the charge blocking layer, the tunneling layer covers the charge capturing layer, the channel layer covers the tunneling layer, and the channel medium layer is positioned on the surface of the channel layer and is filled in the channel hole.
Optionally, the depth of the groove is the sum of the thicknesses of the gate dielectric layer and the charge blocking layer.
Optionally, the depth of the groove is less than the sum of the thicknesses of the gate dielectric layer and the charge blocking layer.
Optionally, the device further includes an epitaxial semiconductor layer located at the bottom of the channel hole, the epitaxial semiconductor layer being connected to the channel layer.
In the memory structure, the groove is arranged between the adjacent insulating layers to provide space for a diffusion barrier layer for subsequently forming a channel hole structure, and the diffusion barrier layer does not occupy the space in the channel hole, so that the difficulty of forming the channel hole structure in the channel hole can be reduced, and the quality of the formed channel structure is improved; the size of the channel hole may also be reduced to further increase the integration of the memory structure.
Furthermore, only the gate dielectric layer is formed on the surface of the inner wall of the groove, and the forming space of the control gate formed subsequently is not occupied, so that the difficulty of forming the control gate between adjacent insulating layers is reduced, the quality of the control gate is improved, and the performance of the memory is improved.
Drawings
FIGS. 1 to 8 are schematic structural diagrams illustrating a process of forming a memory structure according to an embodiment of the invention;
FIGS. 9-11 are schematic diagrams illustrating a process of forming a memory structure according to an embodiment of the invention;
FIG. 12 is a diagram illustrating a memory structure according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the memory structure provided by the present invention with reference to the drawings.
In the forming process of the existing memory structure, after a stacked structure is formed on the surface of a substrate, the stacked structure needs to be etched to form a channel hole, then a functional material layer is formed on the surface of the inner wall of the channel hole, and then the functional material layer is etched to expose the substrate at the bottom of the channel hole.
The inventors have found that, as the integration of the memory device is higher, the critical dimension of the channel hole is too small, which results in the functional material layer formed at the bottom of the channel hole not being opened.
And after a channel hole structure is formed in the channel hole, the sacrificial layer is removed, an opening is formed between the insulating layers of the stacked structure, a gate dielectric layer is formed on the surface of the inner wall of the opening, and then a control gate filling the opening is formed. The inventor further finds that only a part of the gate dielectric layer between the end face of the control gate and the trench structure can function, which means that the rest of the gate dielectric layer is an extra part, which occupies the space in the opening and brings difficulty to the filling of the control gate.
And, since the gate dielectric layer is deposited after the sacrificial layer is removed, the surface of the control gate in the step region of the memory structure is also covered with the gate dielectric layer. When the contact hole on the step area is formed subsequently, the etching of the contact hole needs to penetrate through the gate dielectric layer and stop on the surface of the control gate, so that the difficulty of the etching selection ratio of the contact hole is increased.
In view of the above problems, the inventor proposes a method for forming a new memory structure, and please refer to fig. 1 to 8 for structural schematic diagrams of a forming process of a memory structure according to an embodiment.
Referring to fig. 1, a substrate 100 is provided, a stacked structure 110 is formed on a surface of the substrate 100, and the stacked structure 110 includes a sacrificial layer 112 and an insulating layer 111 alternately stacked along a direction perpendicular to the surface of the substrate 100; a channel hole 130 is formed through the stacked structure 110.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used.
In other embodiments, the top of the stacked structure 110 may further have a cap layer (not shown) for protecting the stacked structure 110, and also may be used as a mask layer for etching the stacked structure 110 to form the channel hole 130.
The stack structure 110 is etched to the surface of the substrate 100 by a dry etching process to form a trench hole 130. In this embodiment, the channel hole 130 has vertical sidewalls. In other embodiments, the channel hole 130 may also have sloped sidewalls. The inclination of the sidewall of the channel hole 130 may be adjusted by adjusting the parameters of the etching process or by using a high aspect ratio etching process, etc.
In this embodiment, after forming the channel hole 130, the method further includes: an epitaxial semiconductor layer (not shown) is formed on the surface of the substrate 100 at the bottom of the channel hole 130. In other embodiments, an epitaxial semiconductor layer at the bottom of the channel hole 130 may be formed in a subsequent step.
Referring to fig. 2, which is an enlarged schematic view of the partial structure 20 in fig. 1, a subsequent process will be described on the basis of fig. 2.
Referring to fig. 3, the sacrificial layer 112 is etched back along the sidewall of the channel hole 130 to form a groove 301 between adjacent insulating layers 111.
The sacrificial layer 112 may be etched back by a dry etching process, and an etching gas having a higher etching selectivity for the sacrificial layer 112 is selected to be etched in a high-pressure environment. In one embodiment, the etching gas used in the dry etching process comprises CH3F and CH2F2The flow rate of the etching gas is 80 sccm-120 sccm, the pressure is 25 mtorr-35 mtorr, and the bias voltage is 800V-1500V.
By controlling the process parameters of the etching process, the depth of the groove 301 can be accurately controlled. In this embodiment, the depth of the groove 201 is the sum of the thicknesses of a gate dielectric layer to be formed later and a charge blocking layer in a trench hole structure.
Referring to fig. 4, a gate dielectric layer 401 is formed to cover the channel hole 130 and the inner wall surface of the groove 301.
Since the depth of the channel hole 130 is large, in order to improve the step coverage performance of the gate dielectric layer 401, in this embodiment, an atomic layer deposition process is used to form the gate dielectric layer 401. In addition, the thickness of the formed gate dielectric layer 401 can be accurately controlled by adopting an atomic layer deposition process.
The gate dielectric layer 401 may be made of insulating materials such as silicon oxide and silicon oxynitride. Preferably, the material of the gate dielectric layer 401 may be at least one of high-K dielectric materials such as hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide. In this embodiment, the gate dielectric layer 401 covers not only the inner wall surfaces of the channel holes 130, but also the inner wall surfaces of the grooves 301 between the insulating layers 111.
In another specific embodiment, the gate dielectric layers on the sidewall and the bottom surface of the channel hole 130 may be further removed by an etching process, and only the gate dielectric layer 401 on the inner wall surface of the groove 301 is remained, so as to prevent the gate dielectric layer 401 from occupying the space in the channel hole 130.
Referring to fig. 5, a charge blocking material layer 501 is formed to cover the inner wall surface of the channel hole 130 and fill the groove 301.
The charge blocking material layer 501 may be formed using an atomic layer deposition process in order to accurately control the thickness of the blocking material layer 501. In other embodiments, the charge blocking material layer 501 may also be formed by chemical vapor deposition or other processes.
In this embodiment, the material of the charge blocking material layer 501 is silicon oxide. The charge blocking material layer 501 covers the gate dielectric layer 401 and fills the recess 301 (see fig. 4).
Referring to fig. 6, the charge blocking material layer 501 (see fig. 5) on the inner wall surface of the channel hole 130 is removed, and the blocking material layer in the recess 301 (see fig. 4) is retained as a charge blocking layer 601.
Removing the charge blocking material layer on the sidewall and bottom surface of the channel hole 130 can prevent the charge blocking material layer from occupying the space inside the channel hole 130. Under the condition that the feature size of the channel hole 130 is fixed, the charge blocking layer 601 is formed in the groove 301 between the insulating layers 111, and does not occupy the space in the channel hole 130, thereby reducing the difficulty of forming other material layers in the channel hole 130 and performing an etching process.
The charge blocking material layer 501 may be etched by a dry etching process, and the dry etching has isotropy by controlling etching process parameters, for example, by using a low bias power, so that the charge blocking material layer on the sidewall and the bottom surface of the channel hole 130 can be removed at the same time, and the charge blocking layer 601 is retained in the groove 301. In this embodiment, the etching gas used for etching the charge blocking material layer 501 includes C4F8And CO, wherein the flow rate of the etching gas is 60-120 sccm, the pressure is 35-45 mtorr, and the bias voltage is 800-1500V.
In other embodiments, the charge blocking material layer 501 may also be etched by a wet etching process.
In other embodiments, the charge blocking material layer 501 on the inner wall surface of the channel hole 130 may be retained, and the process steps shown in fig. 6 are not performed, so as to reduce the number of process steps.
Referring to fig. 7, a charge trapping layer 602 covering the sidewall of the channel hole and the surface of the charge blocking layer 601, a tunneling layer 603 covering the charge trapping layer 602, and a channel layer 604 covering the tunneling layer 603 are sequentially formed in the channel hole 130; a channel dielectric layer 605 filling the channel hole is formed on the surface of the channel layer 604.
In this embodiment, after the charge blocking layer 601 is formed, an epitaxial semiconductor layer may be first formed on the substrate surface at the bottom of the channel hole 130, and then the charge trapping layer 602, the tunneling layer 603, the channel layer 604, and the channel medium layer 605 may be formed.
The method for forming the charge trapping layer 602, the tunneling layer 603 and the channel layer 604 includes: after a charge trapping material layer, a tunneling material layer and a channel material layer are sequentially formed on the surface of the inner wall of the channel hole, the charge trapping material layer, the tunneling material layer and the channel material layer which are positioned at the bottom of the channel hole are etched, and the surface of the epitaxial semiconductor layer at the bottom of the channel hole is exposed; then, forming a channel material layer covering the surface of the epitaxial semiconductor layer so that the channel layer is connected with the epitaxial semiconductor layer 131; and then a trench dielectric layer 605 is formed to fill the trench hole 130.
In other specific embodiments, the method for forming the charge trapping layer 602, the tunneling layer 603, and the channel layer 604 may further include: sequentially forming a charge trapping material layer and a tunneling material layer on the surface of the side wall of the channel hole, etching the charge trapping material layer and the tunneling material layer at the bottom of the channel hole to expose the epitaxial semiconductor layer, forming a charge trapping layer 602 and a tunneling layer 603 on the surface of the side wall of the channel hole, and then forming a channel layer 604 covering the tunneling layer 603 and the surface of the epitaxial semiconductor layer 131; and then a trench dielectric layer 605 is formed to fill the trench hole 130.
In this embodiment, the trench hole structure of the memory structure includes: a charge blocking layer 601, a charge trapping layer 602, a tunneling layer 603, a channel layer 604, and a channel dielectric layer 605.
Since the charge blocking layer 601 is located in the groove between the insulating layers 111 and does not occupy the inner space of the channel hole 130, the difficulty of the deposition step and the etching step in forming the charge trapping layer 602, the tunneling layer 603, and the channel layer 604 can be reduced, which is beneficial to improving the performance of the formed channel hole structure.
Referring to fig. 8, the sacrificial layer 112 is removed to form an opening between adjacent insulating layers 111; a control gate 800 is formed filling the opening.
In one embodiment, a gate line isolation trench is first formed through the stacked structure; then, a wet etching process is used to remove the sacrificial layer 112 along the gate line spacer sidewalls (see fig. 7).
The control gate 800 includes a diffusion barrier layer 801 covering the inner wall surface of the opening and a gate 802 located on the surface of the diffusion barrier layer 801 and filling the opening. In other embodiments, the control gate 800 may include only the gate 802.
The diffusion barrier layer 801 is made of at least one of TiN, TaN, Ti or TiW, and can block the out-diffusion of the gate 802 material. The diffusion barrier layer 801 may be formed by an atomic layer deposition process in order to precisely control the thickness of the diffusion barrier layer 801 and to allow the diffusion barrier layer 801 to have high step coverage.
The material of the gate 802 is at least one of polysilicon, aluminum, copper or tungsten. The gate electrode 802 may be formed using an atomic layer deposition process, a chemical vapor deposition process, or the like.
In this embodiment, the diffusion barrier layer 801 is made of TiN, and the diffusion barrier layer 801 is formed by an atomic layer deposition process; the gate 802 is made of W, and the gate 802 is formed by a chemical vapor deposition process.
In this embodiment, after the opening is formed by removing the sacrificial layer 112, a gate dielectric layer is not required to be formed in the opening, so that the diffusion barrier layer 801 and the gate electrode 802 can occupy the whole opening space; therefore, difficulty in forming the diffusion barrier layer 801 and the gate electrode 802 can be reduced.
The gate dielectric layer 401 is located between the control gate 800 and the channel hole structure, and serves as a gate dielectric layer of the memory cell.
Referring to fig. 12, in another embodiment of the present invention, after the recess 301 (see fig. 3) is formed, the charge blocking layer 601 may be directly formed in the recess 301 without forming the gate dielectric layer 401; after the sacrificial layer 112 is removed and the opening between the adjacent insulating layers 111 is formed, a gate dielectric layer 401 'is formed on the inner wall surface of the opening, and then a control gate 800 filling the opening is formed on the surface of the gate dielectric layer 401'. In this embodiment, the forming process and the forming step of the gate dielectric layer 401' do not need to be changed, the process is easy to implement, and the space for forming the channel hole structure in the channel hole 130 can be further increased.
According to the forming method of the memory structure, after the channel hole is formed, the sacrificial layer on the side wall of the channel hole is etched back to form the groove, the gate dielectric layer is formed on the surface of the inner wall of the groove, then the channel hole structure is formed, and the gate dielectric layer does not need to be formed in the opening formed by removing the sacrificial layer, so that the space for forming the control grid in the opening can be increased, and the difficulty in forming the control grid is reduced.
Furthermore, a charge blocking layer of the channel hole structure can be formed in the groove, so that the charge blocking layer does not occupy the space of the channel hole, the space for forming other material layers of the channel hole structure is increased, and the difficulty for forming the channel hole structure is reduced.
In the formation process of the memory structure, the stacked structure includes a core region and a step region surrounding the core region, and fig. 1 to 8 described above each show only the structure at the core region of the stacked structure.
Please refer to fig. 9 to fig. 11, which are schematic structural diagrams illustrating a process of forming a memory structure according to another embodiment of the present invention.
Please refer to fig. 9, which is a schematic structural diagram of a step region of the stacked structure. The step regions expose the end portions of each of the sacrificial layers 212; a dielectric layer 900 covering the step region is also formed on the surface of the substrate 100.
Referring to fig. 10, after removing the sacrificial layer 112 and forming the control gate 800, a contact hole 901 is formed through the dielectric layer 900 to the end surface of the control gate 800.
In this embodiment, the control gate 800 includes a gate 802 and a diffusion barrier 801 covering the gate 802. Since the surface of the control gate 800 is only covered with the dielectric layer 900, only the dielectric layer 900 needs to be etched in the process of forming the contact hole 901, and therefore, only an etching process with a high selection ratio between the dielectric layer 900 and the control gate 800 needs to be selected, so that the difficulty in etching the contact hole 901 can be reduced.
Referring to fig. 11, a contact portion 902 is formed in the contact hole 901.
And filling a metal material in the contact hole 901 to form a contact portion 902, wherein the contact portion 902 is electrically connected with the diffusion barrier layer 801 and the gate 802.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (9)

1. A memory structure, comprising:
the semiconductor device comprises a substrate, wherein a stacked structure is formed on the surface of the substrate and comprises control gates and insulating layers which are alternately stacked along the direction vertical to the surface of the substrate;
a trench hole structure penetrating the stacked structure;
the width of the control grid electrode is smaller than that of the insulating layers, so that a groove is formed between the adjacent insulating layers;
and the gate dielectric layer at least covers the surface of the inner wall of the groove.
2. The memory structure of claim 1, wherein the trench hole structure is formed in a trench hole, and the gate dielectric layer further covers an inner wall surface of the trench hole.
3. The memory structure of claim 1, wherein the stack structure comprises a core region and a step region surrounding the core region, wherein the substrate surface has a dielectric layer in the step region, and wherein the dielectric layer covers the control gate surface.
4. The memory structure of claim 3, further comprising a contact extending through said dielectric layer and electrically connected to said control gate.
5. The memory structure of claim 1, wherein a portion of the channel hole structure is located within the recess.
6. The memory structure of claim 5, wherein the channel hole structure comprises: the charge blocking layer is at least partially positioned in the groove, the charge capturing layer covers the side wall of the channel hole and the surface of the charge blocking layer, the tunneling layer covers the charge capturing layer, the channel layer covers the tunneling layer, and the channel medium layer is positioned on the surface of the channel layer and is filled in the channel hole.
7. The memory structure of claim 6, wherein the depth of the recess is the sum of the thicknesses of the gate dielectric layer and the charge blocking layer.
8. The memory structure of claim 6, wherein a depth of the recess is less than a sum of thicknesses of the gate dielectric layer and the charge blocking layer.
9. The memory structure of claim 6, further comprising an epitaxial semiconductor layer at a bottom of the channel hole, the epitaxial semiconductor layer being connected to the channel layer.
CN202111063721.3A 2018-09-19 2018-09-19 Memory structure Pending CN113871394A (en)

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