CN108831889A - Three-dimensional storage - Google Patents
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- CN108831889A CN108831889A CN201811092868.3A CN201811092868A CN108831889A CN 108831889 A CN108831889 A CN 108831889A CN 201811092868 A CN201811092868 A CN 201811092868A CN 108831889 A CN108831889 A CN 108831889A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention relates to a kind of three-dimensional storage, the three-dimensional storage includes：Substrate is provided, the substrate surface is formed with stacked structure, and the stacked structure includes the sacrificial layer and insulating layer being alternately stacked along vertical substrates surface direction；Form the channel hole for running through the stacked structure；The sacrificial layer is etched back along channel hole side wall, forms the groove between adjacent insulating layer；Form the gate dielectric layer at least filling the groove；Channel pore structure is formed in the channel hole.The above method can reduce the formation difficulty of three-dimensional storage, improve the performance of the three-dimensional storage of formation.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of three-dimensional storages.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
In 3D NAND flash memory structure, including memory array structure, the memory array structure include to multiple-level stack knot
Structure.With being continuously increased for the stacked structure composite dielectric film number of plies, (CH) of the high depth-to-width ratio channel in small channel hole
It is more difficult that function side wall is formed under critical size (CD) background, in channel hole.Further, since traditional rear grid method is needed in phosphorus
After sour wet process removes false grid SiN, first depositing TiN thin film and high K dielectric film fill out metal gates W again, this can to a certain extent
The space of filling metal gates is cut down, the technology difficulty for forming metal gates is increased.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of three-dimensional storages, improve the performance of three-dimensional storage.
Technical solution of the present invention provides a kind of three-dimensional storage, including：Storage stack structure, the storage stack structure
Including the control grid being alternately stacked and insulating layer；Channel pore structure runs through the storage stack structure；The control grid
Width is less than the width of insulating layer so that have between adjacent insulating layer positioned at the control gate terminal portion and channel pore structure it
Between groove；Gate dielectric layer is at least filled in the groove.
Optionally, the gate dielectric layer is only filled in the end sidewalls in the groove, covering the control grid.
Optionally, the gate dielectric layer fills the full groove, and covers the side wall of the insulating layer around channel pore structure.
Optionally, the material of the gate dielectric layer is high-k dielectric material.
Optionally, the channel pore structure is formed in channel hole, including：Cover channel hole side wall and gate dielectric layer
Electric charge barrier layer；Cover the electric charge capture layer of the charge barrier layer surface, the covering electric charge capture layer tunnel layer with
And the channel layer of the covering tunnel layer；Channel dielectric layer positioned at the channel layer surface and the full channel hole of filling.
Optionally, the control grid include grid and be located at the grid and insulating layer, grid and gate dielectric layer it
Between diffusion barrier layer.
Optionally, the storage stack structure includes nucleus and the stepped area around the nucleus, described
Stepped area exposes the end of each layer of control grid；Dielectric layer is covered in the stepped area.
It optionally, further include the contact portion that gate terminal portion surface is controlled through the dielectric layer to each layer.
It optionally, further include the array common source for running through the storage stack structure.
Optionally, the three-dimensional storage is 3D nand memory.
Between the adjacent insulating layer of three-dimensional storage of the invention have be located at control gate terminal portion and channel pore structure it
Between groove, gate dielectric layer is formed in the groove, the formation space of control grid is not take up, to reduce in adjacent insulation
The difficulty that control grid is formed between layer improves the quality of control grid, and then improves the performance of memory.
Detailed description of the invention
Fig. 1 to Fig. 7 is the structural schematic diagram of the forming process of the three-dimensional storage of the embodiment of the invention；
Fig. 8 to Figure 10 is the structural schematic diagram of the forming process of the three-dimensional storage of the embodiment of the invention.
Specific embodiment
The specific embodiment of three-dimensional storage provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
In the forming process of existing three-dimensional storage, after substrate surface forms stacked structure, need to etch described
Stacked structure forms channel hole, then forms function material layer in channel hole inner wall surface and forms channel pore structure.Channel
Pore structure is formed and then removal sacrificial layer, opening is formed between the insulating layer of stacked structure, and first in opening inner wall surface
Gate dielectric layer is formed, the control grid of filling opening is then re-formed.Inventor is it has furthermore been found that the gate dielectric layer only has position
Part gate dielectric layer between control gate terminal face and channel pore structure can play a role, it is meant that the grid at remaining position are situated between
Matter layer is extra part, can occupy the space in opening, is come to the filling tape of control grid difficult.
Also, since gate dielectric layer deposits after removal of the sacrificial layer, then the control of the stepped area in storage organization
Gate surface can also be covered with gate dielectric layer.In the contact hole being subsequently formed in stepped area, since the etching of contact hole needs
Control gate surface is stopped at through gate dielectric layer, will increase the difficulty of the etching selection ratio of contact hole in this way.
In view of the above-mentioned problems, inventor proposes a kind of forming method of new three-dimensional storage, Fig. 1 is specifically please referred to figure
7 be the structural schematic diagram of the forming process of the three-dimensional storage of a specific embodiment.
Referring to FIG. 1, providing substrate 100,100 surface of substrate is formed with stacked structure 110, the stacked structure
110 include the sacrificial layer 112 and insulating layer 111 being alternately stacked along 100 surface direction of vertical substrates；It is formed and runs through the stacking
The channel hole 130 of structure 110.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device
Demand can choose suitable semiconductor material as the substrate 100, be not limited thereto.In the specific embodiment, institute
Stating substrate 100 is monocrystalline silicon wafer crystal.
The stacked structure 110 includes the insulating layer 111 and sacrificial layer being stacked with along 100 surface direction of vertical substrates
112.In a specific embodiment, the material of the insulating layer 111 is silica, and the material of the sacrificial layer 112 is nitrogen
SiClx；In other specific embodiments, the insulating layer 111 and sacrificial layer 112 can also use other suitable materials.
In other specific embodiments, there can also be cap layer (not shown) at the top of the stacked structure 110,
For protecting the stacked structure 110, the mask layer that etching stacked structure 110 forms channel hole 130 can also be used as.
The stacked structure 110 is etched to 100 surface of substrate by dry etch process, forms channel hole 130.The tool
In body embodiment, the channel hole 130 has vertical sidewall.In other specific embodiments, the channel hole 130 can also
With sloped sidewall.The ditch can be adjusted by adjusting etch process parameters or using high aspect ratio technique etc.
The gradient of 130 side wall of road hole.
In the specific embodiment, after forming the channel hole 130, further include：In 130 bottom of channel hole
100 surface of substrate formed epitaxial semiconductor layer (not shown).It, can also be in subsequent step in other specific embodiments
In rapid, the epitaxial semiconductor layer for being located at 130 bottom of channel hole is formed.
Referring to FIG. 2, for the enlarged diagram of partial structurtes 20 in Fig. 1, follow-up process will continue on the basis of Fig. 2 into
Row description.
Referring to FIG. 3, being etched back along 130 side wall of channel hole to the sacrificial layer 112, formed positioned at adjacent exhausted
Groove 301 between edge layer 111.
The sacrificial layer 112 can be etched back using dry etch process, under hyperbaric environment, be selected to described
There is sacrificial layer 112 etching gas compared with high etch selectivity to perform etching.In a specific embodiment, the dry method is carved
The etching gas that etching technique uses includes CH3F and CH2F2, etching gas flow is 80sccm~120sccm, and pressure is
25mtorr~35mtorr, bias voltage are 800V~1500V.
By controlling the technological parameter of etching process, the depth of the groove 301 can accurately be controlled.In the tool
In body embodiment, the depth of the groove 301 is the thickness of subsequent gate dielectric layer to be formed.
Referring to FIG. 4, forming the gate medium filled the full groove 301 and cover 130 inner wall surface of channel hole
Material layer 401.
Since the depth in the channel hole 130 is larger, in order to improve the step coverage of the gate dielectric material layer 401
Can, in the specific embodiment, the gate dielectric material layer 401 is formed using atom layer deposition process.Also, use atom
Layer depositing operation can accurately control the thickness for the gate dielectric material layer 401 to be formed.
The material of the gate dielectric material layer 401 can be the insulating materials such as silica, silicon oxynitride.Preferably, described
The material of gate dielectric material layer 401 can in the high-k dielectric materials such as hafnium oxide, aluminium oxide, zirconium oxide and lanthana extremely
Few one kind.In the specific embodiment, the gate dielectric material layer 401 not only covers the inner wall surface in the channel hole 130,
Also fill up the completely described groove 301.
Referring to FIG. 5, removal is located at the gate dielectric material layer 401 (please referring to Fig. 4) of 130 inner wall surface of channel hole,
Retain the gate dielectric material layer in groove as gate dielectric layer 402.
The gate dielectric material layer 401 can be performed etching using dry etch process, pass through control etching technics ginseng
Number, so that dry etching has isotropism, is located at described for example, by using lower bias power etc. so as to removal simultaneously
The gate dielectric material layer 401 of 130 side wall of channel hole and bottom surface retains gate dielectric layer 402 in groove 301.This is specific
In embodiment, etching the etching gas that the gate dielectric material layer 401 uses includes C4F8And CO, etching gas flow are
60sccm~120sccm, pressure are 35mtorr~45mtorr, and bias voltage is 800V~1500V.In other specific implementations
In mode, the gate dielectric material layer 401 can also be performed etching by wet-etching technology.
The part gate dielectric material layer 401 for removing channel hole sidewall surfaces, can account for avoid the gate dielectric material layer 401
According to the space in the channel hole 130, the subsequent formation channel pore structure in channel hole 130 is influenced.
In another specific embodiment, the gate dielectric material layer 401 can not also be performed etching, retain and be located at ditch
The gate dielectric material layer 401 of 130 sidewall surfaces of road hole, to save the process step.In this case, in order to avoid influence channel hole
The formation of structure can suitably increase the characteristic size in the channel hole 130.
Referring to FIG. 6, forming channel pore structure in the channel hole 130.
Electric charge barrier layer 601, the covering electricity of covering channel hole side wall are sequentially formed in the channel hole 130
The electric charge capture layer 602 on lotus barrier layer 601, the tunnel layer 603 of the covering electric charge capture layer 602 and the covering tunnelling
The channel layer 604 of layer 603；The channel dielectric layer 605 for filling the full channel hole is formed on 604 surface of channel layer.The tool
In body embodiment, the material of the electric charge barrier layer 601 be silica, electric charge capture layer 602 material be silicon nitride, tunnelling
The material of layer 603 be silica, channel layer 604 material be the material of polysilicon and the channel dielectric layer 605 be oxidation
Silicon.
In a specific embodiment, before forming the electric charge barrier layer 601, first in the channel hole 130
The substrate surface of bottom forms epitaxial semiconductor layer, then re-forms the electric charge barrier layer 601, electric charge capture layer 602, tunnelling
Layer 603, channel layer 604 and channel dielectric layer 605.
Specifically, the formation of the electric charge barrier layer 601, electric charge capture layer 602, tunnel layer 603 and channel layer 604
Method includes：In the channel hole, inner wall surface sequentially forms charge blocking material layer, charge-trapping material layer, tunneling material layer
And after channel material, etching is located at charge blocking material layer, charge-trapping material layer, the tunnelling material of channel hole bottom
The bed of material and layer of channel material expose the epitaxial semiconductor layer surface of channel hole bottom；Then it re-forms described in covering
The layer of channel material of epitaxial semiconductor layer surface, so that the channel layer is connect with the epitaxial semiconductor layer 131；It re-forms and fills out
Channel dielectric layer 605 full of the channel hole 130.
In other specific embodiments, the electric charge barrier layer 601, electric charge capture layer 602, tunnel layer 603 and ditch
The forming method of channel layer 604 may include：In the channel hole, sidewall surfaces sequentially form charge blocking material layer, charge-trapping
Material layer, tunneling material layer etch charge blocking material layer, charge-trapping material layer and the tunnelling material of channel hole bottom
The bed of material exposes epitaxial semiconductor layer, forms electric charge barrier layer 601,602 and of electric charge capture layer for being located at channel hole sidewall surfaces
Tunnel layer 603；Then the channel layer 604 for covering the tunnel layer 603 and epitaxial semiconductor layer surface is formed；It is full to re-form filling
The channel dielectric layer 605 in the channel hole 130.
The charge blocking material layer, charge-trapping material layer, tunneling material can be formed using atom layer deposition process
Layer and layer of channel material, to accurately control the electric charge barrier layer 601, electric charge capture layer 602, tunnel layer 603 and ditch
The thickness of channel layer 604.
Referring to FIG. 7, removing the sacrificial layer 112 (please referring to Fig. 6), opening between adjacent insulating layer 111 is formed
Mouthful；Form the control grid 800 for filling the opening.
In a specific embodiment, it is initially formed the grid line separate slot (not shown) through the stacked structure；
Then along the grid line separate slot side wall, the sacrificial layer 112 (please referring to Fig. 7) is removed using wet-etching technology.
The control grid 800 includes covering the diffusion barrier layer 801 of the opening inner wall surface and being located at the expansion
Dissipate the grid 802 that the full opening is filled on 801 surface of barrier layer.It is a in other specific embodiments, the control grid 800
It can also only include the grid 802.
The material of the diffusion barrier layer 801 is at least one of TiN, TaN, Ti or TiW, can stop the grid
802 material is to external diffusion.The diffusion barrier layer 801 can be formed, by atom layer deposition process accurately to control institute
The thickness of diffusion barrier layer 801 is stated, and makes the diffusion barrier layer 801 step coverage with higher.
The material of the grid 802 is at least one of polysilicon, aluminium, copper or tungsten.Atomic layer deposition work can be used
Skill or chemical vapor deposition process etc. form the grid 802.
In the specific embodiment, the material of the diffusion barrier layer 801 is TiN, is formed using atom layer deposition process
The diffusion barrier layer 801；The material of the grid 802 is W, forms the grid 802 using chemical vapor deposition process.
Due in the specific embodiment, removal sacrificial layer 112 formed the opening between adjacent insulating layer 111 it
Afterwards, it no longer needs to form gate dielectric layer in the opening, therefore the diffusion barrier layer 801 and grid 802 can occupy entirely
Open space, so as to reduce the difficulty to form the diffusion barrier layer 801 and grid 802.
The gate dielectric layer 402 is located between the end and channel pore structure of the control grid 800, as storage unit
Gate dielectric layer.
Above-mentioned three-dimensional storage forming method is etched back the sacrificial layer of channel hole side wall after forming channel hole
Groove is formed, then forms gate dielectric layer on groove inner wall surface, then re-forms channel pore structure, it is subsequent without being sacrificed in removal
Gate dielectric layer is re-formed in the opening that layer is formed, so as to improve the space for forming control grid in the opening, is reduced
Form the difficulty of the control grid.
In the forming process of above-mentioned three-dimensional storage, the stacked structure includes nucleus and around the core space
The stepped area in domain, above-mentioned Fig. 1 to Fig. 7 illustrate only the partial structurtes at the nucleus of the stacked structure.
The structure for please referring to the forming process for the three-dimensional storage that Fig. 8 to Figure 10 is another specific embodiment of the present invention is shown
It is intended to.
Referring to FIG. 8, for the partial structural diagram at the stepped area of the stacked structure.The stepped area exposure
The end of each layer of sacrificial layer 112 out；100 surface of substrate is also formed with the dielectric layer 900 for covering the stepped area.
Referring to FIG. 9, removing the sacrificial layer 112 and being formed after control grid 800, is formed and run through the dielectric layer
900 to control 800 end surface of grid contact hole 901.
In the specific embodiment, controlled grid 800 includes the diffusion resistance of grid 802 and the covering grid 802
Barrier 801.Since 800 surface of control grid is just coated with the dielectric layer 900, the contact hole 901 is formed
In the process, it is only necessary to the dielectric layer 900 is etched, thus, it is only required to select to have the dielectric layer 900 with control grid 800
There is the etching technics compared with high selectivity ratio, the difficulty for etching the contact hole 901 can be reduced.
Referring to FIG. 10, forming contact portion 902 in the contact hole 901.
Metal material is filled in the contact hole 901, forms contact portion 902, and the contact portion 902 is hindered with the diffusion
Barrier 801, grid 802 form electrical connection.
In a specific embodiment of the invention, a kind of three-dimensional storage is also provided.
Referring to FIG. 7, the partial structural diagram of the three-dimensional storage for the embodiment of the invention.
The three-dimensional storage, including：Storage stack structure, the storage stack structure include the control gate being alternately stacked
Pole 800 and insulating layer 111；Channel pore structure runs through the storage stack structure；The width of the control grid 800 is less than exhausted
The width of edge layer 111, so that having between the control gate terminal portion 800 and channel pore structure between adjacent insulating layer
Groove；Gate dielectric layer 402 is at least filled in the groove.
The partial schematic diagram of the storage stack structure of three-dimensional storage is illustrated only in Fig. 7.Actual three-dimensional storage packet
The control grid 800 and insulating layer 111 that multilayer is alternately stacked are included, such as can be 28 layers, 64 layers or 128 layers etc., the storage
Stacked structure is formed in a substrate surface.In Fig. 8, the substrate is not shown.
The control grid 800 includes：Grid 802 and it is located at the grid 802 and insulating layer 111, gate dielectric layer
Diffusion barrier layer 801 between 402.
The material of the diffusion barrier layer 801 is at least one of TiN, TaN, Ti or TiW, can stop the grid
802 material is to external diffusion.The material of the grid 802 is at least one of polysilicon, aluminium, copper or tungsten.
The insulating layer 111 can be silicon oxide layer or silicon nitride layer as the separation layer between adjacent control gates pole 800
Equal insulating dielectric materials layer.
The material of the gate dielectric layer 402 includes the insulating materials such as silica, silicon oxynitride；Preferably, the gate medium
The material of layer 402 can be at least one of high-k dielectric materials such as hafnium oxide, aluminium oxide, zirconium oxide and lanthana.
In the specific embodiment, the gate dielectric layer 402 be only filled in the control grid 800 and channel pore structure it
Between groove in, avoid occupying the space in channel hole.The gate dielectric layer 402 be located at it is described control grid 800 end face and
Gate dielectric layer between channel pore structure, as storage unit.Due to non-shape between the control grid 800 and insulating layer 111
At gate dielectric layer, it is thus possible to improve forming the space of control grid between adjacent insulating layer 111, three-dimensional storage is also improved
Integrated level.
In another specific embodiment, the gate dielectric layer 402 be not only filled with completely described 800 end of control grid with
Groove between channel pore structure, also sidewall surfaces of the covering around the insulating layer 111 of the channel pore structure.
The channel pore structure is formed in channel hole, including：Electric charge barrier layer 601, electric charge capture layer 602, tunnel layer
603, channel layer 604 and the channel dielectric layer 605 in the full channel hole of filling.In the specific embodiment, the electric charge barrier layer
601 covering channel hole side walls and gate dielectric layer 402, the electric charge capture layer 602 cover the electric charge barrier layer 601, the tunnel
It wears layer 603 and covers the electric charge capture layer 602, the channel layer 604 covers the tunnel layer 603；The electric charge barrier layer
601, electric charge capture layer 602, tunnel layer 603, channel layer 604 cover the side wall in channel hole, expose the substrate of channel hole bottom
Surface；The channel dielectric layer 605 is located at 604 surface of channel layer and fills the full channel hole.
Referring to FIG. 10, the structural schematic diagram of the three-dimensional storage for another specific embodiment of the present invention.
In the specific embodiment, the stacked structure of the three-dimensional storage includes nucleus and around the core space
The stepped area in domain.The partial structural diagram of the stepped area of the three-dimensional storage is shown in above-mentioned Figure 10.
The storage stack structure is formed in 100 surface of substrate, and the stepped area exposes each layer of control grid 800
End；The storage stack body structure surface has the dielectric layer 900 for covering the stepped area, and the dielectric layer 900 is located at
The end surface of the control grid 800.
900 have the contact portion through the dielectric layer 900 to each control 800 end surface of grid in the dielectric layer
902.In the specific embodiment, the contact portion 902 through the dielectric layer 900 to 801 surface of diffusion barrier layer, and it is described
It controls grid 800 and forms electrical connection.During forming the contact portion 902, needs to etch the formation of dielectric layer 900 and run through
To the contact hole of dielectric layer 900, then the filling conductive material formation contact portion 902 in contact hole.Due to the control grid 800
Surface is just coated with the dielectric layer 900, therefore when forming contact hole, it is only necessary to etch the dielectric layer 900, can reduce
The difficulty of the contact hole is formed, to improve finally formed contact portion 902 and control the electrical connectivity between grid 800
Energy.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of three-dimensional storage, which is characterized in that including：
Storage stack structure, the storage stack structure include the control grid and insulating layer being alternately stacked；
Channel pore structure runs through the storage stack structure；
The width of the control grid is less than the width of insulating layer, is located at the control grid so that having between adjacent insulating layer
Groove between end and channel pore structure；
Gate dielectric layer is at least filled in the groove.
2. three-dimensional storage according to claim 1, which is characterized in that the gate dielectric layer is only filled in the groove
It is interior, cover the end sidewalls of the control grid.
3. three-dimensional storage according to claim 1, which is characterized in that the gate dielectric layer fills the full groove, and
Side wall of the covering around the insulating layer of channel pore structure.
4. three-dimensional storage according to claim 1, which is characterized in that the material of the gate dielectric layer is high k dielectric material
Material.
5. three-dimensional storage according to claim 1, which is characterized in that the channel pore structure is formed in channel hole,
Including：Cover the electric charge barrier layer of channel hole side wall and gate dielectric layer；The charge for covering the charge barrier layer surface is caught
Obtain the channel layer of layer, the tunnel layer of the covering electric charge capture layer and the covering tunnel layer；Positioned at the channel layer surface
And fill the channel dielectric layer in the full channel hole.
6. three-dimensional storage according to claim 1, which is characterized in that the control grid includes grid and is located at
Diffusion barrier layer between the grid and insulating layer, grid and gate dielectric layer.
7. three-dimensional storage according to claim 1, which is characterized in that the storage stack structure include nucleus and
Around the stepped area of the nucleus, the stepped area exposes the end of each layer of control grid；The stepped region
Dielectric layer is covered on domain.
8. three-dimensional storage according to claim 7, which is characterized in that further include being controlled through the dielectric layer to each layer
The contact portion of grid end surface.
9. three-dimensional storage according to claim 7, which is characterized in that further include the battle array through the storage stack structure
Column common source.
10. three-dimensional storage according to claim 1, which is characterized in that the three-dimensional storage is 3D NAND storage
Device.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643716A (en) * | 2018-11-22 | 2019-04-16 | 长江存储科技有限责任公司 | Three-dimensional storage equipment and its manufacturing method |
| CN109643717A (en) * | 2018-11-22 | 2019-04-16 | 长江存储科技有限责任公司 | Three-dimensional storage part and its manufacturing method |
| CN109786387A (en) * | 2019-01-09 | 2019-05-21 | 长江存储科技有限责任公司 | The selection method of the storage unit of memory and forming method thereof, memory |
| CN109887922A (en) * | 2019-03-15 | 2019-06-14 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN111354730A (en) * | 2020-03-12 | 2020-06-30 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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| CN112885838A (en) * | 2020-03-16 | 2021-06-01 | 长江存储科技有限责任公司 | Memory device and method of forming a memory device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| US20170125436A1 (en) * | 2015-10-28 | 2017-05-04 | Sandisk Technologies Inc. | Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure |
| CN208674119U (en) * | 2018-09-19 | 2019-03-29 | 长江存储科技有限责任公司 | Three-dimensional storage |
-
2018
- 2018-09-19 CN CN201811092868.3A patent/CN108831889A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170125436A1 (en) * | 2015-10-28 | 2017-05-04 | Sandisk Technologies Inc. | Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| CN208674119U (en) * | 2018-09-19 | 2019-03-29 | 长江存储科技有限责任公司 | Three-dimensional storage |
Cited By (15)
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| US11302715B2 (en) | 2018-11-22 | 2022-04-12 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| CN109643717A (en) * | 2018-11-22 | 2019-04-16 | 长江存储科技有限责任公司 | Three-dimensional storage part and its manufacturing method |
| CN109643716A (en) * | 2018-11-22 | 2019-04-16 | 长江存储科技有限责任公司 | Three-dimensional storage equipment and its manufacturing method |
| CN109643716B (en) * | 2018-11-22 | 2019-12-31 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
| US10886294B2 (en) | 2018-11-22 | 2021-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
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| US11706920B2 (en) | 2018-11-22 | 2023-07-18 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| CN109786387A (en) * | 2019-01-09 | 2019-05-21 | 长江存储科技有限责任公司 | The selection method of the storage unit of memory and forming method thereof, memory |
| CN109786387B (en) * | 2019-01-09 | 2023-10-17 | 长江存储科技有限责任公司 | Memory, forming method thereof and memory cell selection method |
| CN109887922A (en) * | 2019-03-15 | 2019-06-14 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN112530873A (en) * | 2019-09-18 | 2021-03-19 | 云谷（固安）科技有限公司 | Display panel, manufacturing method thereof and electronic device |
| CN112530873B (en) * | 2019-09-18 | 2023-09-26 | 云谷（固安）科技有限公司 | Display panel, manufacturing method thereof and electronic equipment |
| WO2021163876A1 (en) * | 2020-02-18 | 2021-08-26 | Yangtze Memory Technologies Co., Ltd. | Staircase structure for three-dimensional memory |
| CN111354730A (en) * | 2020-03-12 | 2020-06-30 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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